drivers/staging/benet/fw/post_codes.h

   1 /*
   2  * Copyright (C) 2005 - 2008 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17 /*
  18  * Autogenerated by srcgen version: 0127
  19  */
  20 #ifndef __post_codes_amap_h__
  21 #define __post_codes_amap_h__
  22
  23 /* --- MGMT_HBA_POST_STAGE_ENUM --- */
  24 #define POST_STAGE_POWER_ON_RESET   (0) /* State after a cold or warm boot. */
  25 #define POST_STAGE_AWAITING_HOST_RDY (1)        /* ARM boot code awaiting a
  26                                                 go-ahed from  the host. */
  27 #define POST_STAGE_HOST_RDY (2) /* Host has given go-ahed to ARM. */
  28 #define POST_STAGE_BE_RESET (3) /* Host wants to reset chip, this is a  chip
  29                                                 workaround  */
  30 #define POST_STAGE_SEEPROM_CS_START (256)       /* SEEPROM checksum
  31                                                 test start. */
  32 #define POST_STAGE_SEEPROM_CS_DONE  (257)       /* SEEPROM checksum test
  33                                                         done. */
  34 #define POST_STAGE_DDR_CONFIG_START (512)       /* DDR configuration start. */
  35 #define POST_STAGE_DDR_CONFIG_DONE  (513)       /* DDR configuration done. */
  36 #define POST_STAGE_DDR_CALIBRATE_START  (768)   /* DDR calibration start. */
  37 #define POST_STAGE_DDR_CALIBRATE_DONE   (769)   /* DDR calibration done. */
  38 #define POST_STAGE_DDR_TEST_START   (1024)      /* DDR memory test start. */
  39 #define POST_STAGE_DDR_TEST_DONE    (1025)      /* DDR memory test done. */
  40 #define POST_STAGE_REDBOOT_INIT_START   (1536)  /* Redboot starts execution. */
  41 #define POST_STAGE_REDBOOT_INIT_DONE (1537)     /* Redboot done execution. */
  42 #define POST_STAGE_FW_IMAGE_LOAD_START (1792)   /* Firmware image load to
  43                                                         DDR start. */
  44 #define POST_STAGE_FW_IMAGE_LOAD_DONE   (1793)  /* Firmware image load
  45                                                         to DDR done. */
  46 #define POST_STAGE_ARMFW_START          (2048)  /* ARMfw runtime code
  47                                                 starts execution. */
  48 #define POST_STAGE_DHCP_QUERY_START     (2304)  /* DHCP server query start. */
  49 #define POST_STAGE_DHCP_QUERY_DONE      (2305)  /* DHCP server query done. */
  50 #define POST_STAGE_BOOT_TARGET_DISCOVERY_START (2560)   /* Boot Target
  51                                                 Discovery Start. */
  52 #define POST_STAGE_BOOT_TARGET_DISCOVERY_DONE (2561)    /* Boot Target
  53                                                 Discovery Done. */
  54 #define POST_STAGE_RC_OPTION_SET        (2816)  /* Remote configuration
  55                                                 option is set in  SEEPROM  */
  56 #define POST_STAGE_SWITCH_LINK          (2817)  /* Wait for link up on switch */
  57 #define POST_STAGE_SEND_ICDS_MESSAGE    (2818)  /* Send the ICDS message
  58                                                 to switch */
  59 #define POST_STAGE_PERFROM_TFTP         (2819)  /* Download xml using TFTP */
  60 #define POST_STAGE_PARSE_XML            (2820)  /* Parse XML file */
  61 #define POST_STAGE_DOWNLOAD_IMAGE       (2821)  /* Download IMAGE from
  62                                                 TFTP server */
  63 #define POST_STAGE_FLASH_IMAGE          (2822)  /* Flash the IMAGE */
  64 #define POST_STAGE_RC_DONE              (2823)  /* Remote configuration
  65                                                 complete */
  66 #define POST_STAGE_REBOOT_SYSTEM        (2824)  /* Upgrade IMAGE done,
  67                                                 reboot required */
  68 #define POST_STAGE_MAC_ADDRESS          (3072)  /* MAC Address Check */
  69 #define POST_STAGE_ARMFW_READY          (49152) /* ARMfw is done with POST
  70                                                 and ready. */
  71 #define POST_STAGE_ARMFW_UE             (61440) /* ARMfw has asserted an
  72                                                 unrecoverable error. The
  73                                                 lower 3 hex digits of the
  74                                                 stage code identify the
  75                                                 unique error code.
  76                                                 */
  77
  78 /* This structure defines the format of the MPU semaphore
  79  * register when used for POST.
  80  */
  81 struct BE_MGMT_HBA_POST_STATUS_STRUCT_AMAP {
  82         u8 stage[16];   /* DWORD 0 */
  83         u8 rsvd0[10];   /* DWORD 0 */
  84         u8 iscsi_driver_loaded; /* DWORD 0 */
  85         u8 option_rom_installed;        /* DWORD 0 */
  86         u8 iscsi_ip_conflict;   /* DWORD 0 */
  87         u8 iscsi_no_ip; /* DWORD 0 */
  88         u8 backup_fw;   /* DWORD 0 */
  89         u8 error;               /* DWORD 0 */
  90 } __packed;
  91 struct MGMT_HBA_POST_STATUS_STRUCT_AMAP {
  92         u32 dw[1];
  93 };
  94
  95 /* --- MGMT_HBA_POST_DUMMY_BITS_ENUM --- */
  96 #define POST_BIT_ISCSI_LOADED           (26)
  97 #define POST_BIT_OPTROM_INST            (27)
  98 #define POST_BIT_BAD_IP_ADDR            (28)
  99 #define POST_BIT_NO_IP_ADDR             (29)
 100 #define POST_BIT_BACKUP_FW              (30)
 101 #define POST_BIT_ERROR                  (31)
 102
 103 /* --- MGMT_HBA_POST_DUMMY_VALUES_ENUM --- */
 104 #define POST_ISCSI_DRIVER_LOADED        (67108864)
 105 #define POST_OPTROM_INSTALLED           (134217728)
 106 #define POST_ISCSI_IP_ADDRESS_CONFLICT  (268435456)
 107 #define POST_ISCSI_NO_IP_ADDRESS        (536870912)
 108 #define POST_BACKUP_FW_LOADED           (1073741824)
 109 #define POST_FATAL_ERROR                (2147483648)
 110
 111 #endif /* __post_codes_amap_h__ */