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[PATCH] skge: gmac register access errors in dual port
[linux-2.6/mini2440.git] / drivers / net / skge.c
blob0208258e7826efabf26f81d889e7d65165272c50
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.0"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
58 #define BLINK_MS 250
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
83 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
100
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
107
108 /* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
110 */
111 #define SKGE_REGS_LEN (29*128)
112
113 static int skge_get_regs_len(struct net_device *dev)
114 {
115 return SKGE_REGS_LEN;
116 }
117
118 /*
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
121 */
122 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
123 void *p)
124 {
125 const struct skge_port *skge = netdev_priv(dev);
126 unsigned long offs;
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
133
134 regs->version = 1;
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
137
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
140 else
141 memset(p + offs, 0, len);
142 }
143 }
144
145 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
146 static int wol_supported(const struct skge_hw *hw)
147 {
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
150 }
151
152 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
153 {
154 struct skge_port *skge = netdev_priv(dev);
155
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
158 }
159
160 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161 {
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
164
165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
166 return -EOPNOTSUPP;
167
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
169 return -EOPNOTSUPP;
170
171 skge->wol = wol->wolopts == WAKE_MAGIC;
172
173 if (skge->wol) {
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
175
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
179 } else
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
181
182 return 0;
183 }
184
185 /* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
187 */
188 static u32 skge_supported_modes(const struct skge_hw *hw)
189 {
190 u32 supported;
191
192 if (hw->copper) {
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
200
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
206
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
209 } else
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
211 | SUPPORTED_Autoneg;
212
213 return supported;
214 }
215
216 static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
218 {
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
221
222 ecmd->transceiver = XCVR_INTERNAL;
223 ecmd->supported = skge_supported_modes(hw);
224
225 if (hw->copper) {
226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
228 } else
229 ecmd->port = PORT_FIBRE;
230
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
235 return 0;
236 }
237
238 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
239 {
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
242 u32 supported = skge_supported_modes(hw);
243
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
245 ecmd->advertising = supported;
246 skge->duplex = -1;
247 skge->speed = -1;
248 } else {
249 u32 setting;
250
251 switch (ecmd->speed) {
252 case SPEED_1000:
253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
257 else
258 return -EINVAL;
259 break;
260 case SPEED_100:
261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
265 else
266 return -EINVAL;
267 break;
268
269 case SPEED_10:
270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
274 else
275 return -EINVAL;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 if ((setting & supported) == 0)
282 return -EINVAL;
283
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
286 }
287
288 skge->autoneg = ecmd->autoneg;
289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296 }
297
298 static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300 {
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307 }
308
309 static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313 } skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338 };
339
340 static int skge_get_stats_count(struct net_device *dev)
341 {
342 return ARRAY_SIZE(skge_stats);
343 }
344
345 static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347 {
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354 }
355
356 /* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360 static struct net_device_stats *skge_get_stats(struct net_device *dev)
361 {
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379 }
380
381 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382 {
383 int i;
384
385 switch (stringset) {
386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392 }
393
394 static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396 {
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408 }
409
410 static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412 {
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428 }
429
430 static u32 skge_get_msglevel(struct net_device *netdev)
431 {
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434 }
435
436 static void skge_set_msglevel(struct net_device *netdev, u32 value)
437 {
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440 }
441
442 static int skge_nway_reset(struct net_device *dev)
443 {
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461 }
462
463 static int skge_set_sg(struct net_device *dev, u32 data)
464 {
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471 }
472
473 static int skge_set_tx_csum(struct net_device *dev, u32 data)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482 }
483
484 static u32 skge_get_rx_csum(struct net_device *dev)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489 }
490
491 /* Only Yukon supports checksum offload. */
492 static int skge_set_rx_csum(struct net_device *dev, u32 data)
493 {
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501 }
502
503 static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505 {
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514 }
515
516 static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518 {
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
524 else if (ecmd->rx_pause && !ecmd->tx_pause)
525 skge->flow_control = FLOW_MODE_REM_SEND;
526 else if (!ecmd->rx_pause && ecmd->tx_pause)
527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536 }
537
538 /* Chip internal frequency for clock calculations */
539 static inline u32 hwkhz(const struct skge_hw *hw)
540 {
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
543 else
544 return 78215; /* or: 78.125 MHz */
545 }
546
547 /* Chip hz to microseconds */
548 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
549 {
550 return (ticks * 1000) / hwkhz(hw);
551 }
552
553 /* Microseconds to chip hz */
554 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
555 {
556 return hwkhz(hw) * usec / 1000;
557 }
558
559 static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561 {
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
568
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
577 }
578
579 return 0;
580 }
581
582 /* Note: interrupt timer is per board, but can turn on/off per port */
583 static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
585 {
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
590 u32 delay = 25;
591
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
596 return -EINVAL;
597 else {
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
600 }
601
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
610 }
611
612 skge_write32(hw, B2_IRQM_MSK, msk);
613 if (msk == 0)
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
615 else {
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
618 }
619 return 0;
620 }
621
622 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
623 static void skge_led(struct skge_port *skge, enum led_mode mode)
624 {
625 struct skge_hw *hw = skge->hw;
626 int port = skge->port;
627
628 spin_lock_bh(&hw->phy_lock);
629 if (hw->chip_id == CHIP_ID_GENESIS) {
630 switch (mode) {
631 case LED_MODE_OFF:
632 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
633 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
634 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
635 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
636 break;
637
638 case LED_MODE_ON:
639 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
640 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
641
642 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
643 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
644
645 break;
646
647 case LED_MODE_TST:
648 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
649 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
650 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
651
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
653 break;
654 }
655 } else {
656 switch (mode) {
657 case LED_MODE_OFF:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
661 PHY_M_LED_MO_10(MO_LED_OFF) |
662 PHY_M_LED_MO_100(MO_LED_OFF) |
663 PHY_M_LED_MO_1000(MO_LED_OFF) |
664 PHY_M_LED_MO_RX(MO_LED_OFF));
665 break;
666 case LED_MODE_ON:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
668 PHY_M_LED_PULS_DUR(PULS_170MS) |
669 PHY_M_LED_BLINK_RT(BLINK_84MS) |
670 PHY_M_LEDC_TX_CTRL |
671 PHY_M_LEDC_DP_CTRL);
672
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_RX(MO_LED_OFF) |
675 (skge->speed == SPEED_100 ?
676 PHY_M_LED_MO_100(MO_LED_ON) : 0));
677 break;
678 case LED_MODE_TST:
679 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
681 PHY_M_LED_MO_DUP(MO_LED_ON) |
682 PHY_M_LED_MO_10(MO_LED_ON) |
683 PHY_M_LED_MO_100(MO_LED_ON) |
684 PHY_M_LED_MO_1000(MO_LED_ON) |
685 PHY_M_LED_MO_RX(MO_LED_ON));
686 }
687 }
688 spin_unlock_bh(&hw->phy_lock);
689 }
690
691 /* blink LED's for finding board */
692 static int skge_phys_id(struct net_device *dev, u32 data)
693 {
694 struct skge_port *skge = netdev_priv(dev);
695 unsigned long ms;
696 enum led_mode mode = LED_MODE_TST;
697
698 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
699 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
700 else
701 ms = data * 1000;
702
703 while (ms > 0) {
704 skge_led(skge, mode);
705 mode ^= LED_MODE_TST;
706
707 if (msleep_interruptible(BLINK_MS))
708 break;
709 ms -= BLINK_MS;
710 }
711
712 /* back to regular LED state */
713 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
714
715 return 0;
716 }
717
718 static struct ethtool_ops skge_ethtool_ops = {
719 .get_settings = skge_get_settings,
720 .set_settings = skge_set_settings,
721 .get_drvinfo = skge_get_drvinfo,
722 .get_regs_len = skge_get_regs_len,
723 .get_regs = skge_get_regs,
724 .get_wol = skge_get_wol,
725 .set_wol = skge_set_wol,
726 .get_msglevel = skge_get_msglevel,
727 .set_msglevel = skge_set_msglevel,
728 .nway_reset = skge_nway_reset,
729 .get_link = ethtool_op_get_link,
730 .get_ringparam = skge_get_ring_param,
731 .set_ringparam = skge_set_ring_param,
732 .get_pauseparam = skge_get_pauseparam,
733 .set_pauseparam = skge_set_pauseparam,
734 .get_coalesce = skge_get_coalesce,
735 .set_coalesce = skge_set_coalesce,
736 .get_sg = ethtool_op_get_sg,
737 .set_sg = skge_set_sg,
738 .get_tx_csum = ethtool_op_get_tx_csum,
739 .set_tx_csum = skge_set_tx_csum,
740 .get_rx_csum = skge_get_rx_csum,
741 .set_rx_csum = skge_set_rx_csum,
742 .get_strings = skge_get_strings,
743 .phys_id = skge_phys_id,
744 .get_stats_count = skge_get_stats_count,
745 .get_ethtool_stats = skge_get_ethtool_stats,
746 };
747
748 /*
749 * Allocate ring elements and chain them together
750 * One-to-one association of board descriptors with ring elements
751 */
752 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
753 {
754 struct skge_tx_desc *d;
755 struct skge_element *e;
756 int i;
757
758 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
759 if (!ring->start)
760 return -ENOMEM;
761
762 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
763 e->desc = d;
764 e->skb = NULL;
765 if (i == ring->count - 1) {
766 e->next = ring->start;
767 d->next_offset = base;
768 } else {
769 e->next = e + 1;
770 d->next_offset = base + (i+1) * sizeof(*d);
771 }
772 }
773 ring->to_use = ring->to_clean = ring->start;
774
775 return 0;
776 }
777
778 static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
779 {
780 struct sk_buff *skb = dev_alloc_skb(size);
781
782 if (likely(skb)) {
783 skb->dev = dev;
784 skb_reserve(skb, NET_IP_ALIGN);
785 }
786 return skb;
787 }
788
789 /* Allocate and setup a new buffer for receiving */
790 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
791 struct sk_buff *skb, unsigned int bufsize)
792 {
793 struct skge_rx_desc *rd = e->desc;
794 u64 map;
795
796 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
797 PCI_DMA_FROMDEVICE);
798
799 rd->dma_lo = map;
800 rd->dma_hi = map >> 32;
801 e->skb = skb;
802 rd->csum1_start = ETH_HLEN;
803 rd->csum2_start = ETH_HLEN;
804 rd->csum1 = 0;
805 rd->csum2 = 0;
806
807 wmb();
808
809 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
810 pci_unmap_addr_set(e, mapaddr, map);
811 pci_unmap_len_set(e, maplen, bufsize);
812 }
813
814 /* Resume receiving using existing skb,
815 * Note: DMA address is not changed by chip.
816 * MTU not changed while receiver active.
817 */
818 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
819 {
820 struct skge_rx_desc *rd = e->desc;
821
822 rd->csum2 = 0;
823 rd->csum2_start = ETH_HLEN;
824
825 wmb();
826
827 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
828 }
829
830
831 /* Free all buffers in receive ring, assumes receiver stopped */
832 static void skge_rx_clean(struct skge_port *skge)
833 {
834 struct skge_hw *hw = skge->hw;
835 struct skge_ring *ring = &skge->rx_ring;
836 struct skge_element *e;
837
838 e = ring->start;
839 do {
840 struct skge_rx_desc *rd = e->desc;
841 rd->control = 0;
842 if (e->skb) {
843 pci_unmap_single(hw->pdev,
844 pci_unmap_addr(e, mapaddr),
845 pci_unmap_len(e, maplen),
846 PCI_DMA_FROMDEVICE);
847 dev_kfree_skb(e->skb);
848 e->skb = NULL;
849 }
850 } while ((e = e->next) != ring->start);
851 }
852
853
854 /* Allocate buffers for receive ring
855 * For receive: to_clean is next received frame.
856 */
857 static int skge_rx_fill(struct skge_port *skge)
858 {
859 struct skge_ring *ring = &skge->rx_ring;
860 struct skge_element *e;
861 unsigned int bufsize = skge->rx_buf_size;
862
863 e = ring->start;
864 do {
865 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
866
867 if (!skb)
868 return -ENOMEM;
869
870 skge_rx_setup(skge, e, skb, bufsize);
871 } while ( (e = e->next) != ring->start);
872
873 ring->to_clean = ring->start;
874 return 0;
875 }
876
877 static void skge_link_up(struct skge_port *skge)
878 {
879 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
880 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
881
882 netif_carrier_on(skge->netdev);
883 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
884 netif_wake_queue(skge->netdev);
885
886 if (netif_msg_link(skge))
887 printk(KERN_INFO PFX
888 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
889 skge->netdev->name, skge->speed,
890 skge->duplex == DUPLEX_FULL ? "full" : "half",
891 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
892 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
893 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
894 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
895 "unknown");
896 }
897
898 static void skge_link_down(struct skge_port *skge)
899 {
900 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
901 netif_carrier_off(skge->netdev);
902 netif_stop_queue(skge->netdev);
903
904 if (netif_msg_link(skge))
905 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
906 }
907
908 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
909 {
910 int i;
911 u16 v;
912
913 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
914 v = xm_read16(hw, port, XM_PHY_DATA);
915
916 /* Need to wait for external PHY */
917 for (i = 0; i < PHY_RETRIES; i++) {
918 udelay(1);
919 if (xm_read16(hw, port, XM_MMU_CMD)
920 & XM_MMU_PHY_RDY)
921 goto ready;
922 }
923
924 printk(KERN_WARNING PFX "%s: phy read timed out\n",
925 hw->dev[port]->name);
926 return 0;
927 ready:
928 v = xm_read16(hw, port, XM_PHY_DATA);
929
930 return v;
931 }
932
933 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
934 {
935 int i;
936
937 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
938 for (i = 0; i < PHY_RETRIES; i++) {
939 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
940 goto ready;
941 udelay(1);
942 }
943 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
944 hw->dev[port]->name);
945
946
947 ready:
948 xm_write16(hw, port, XM_PHY_DATA, val);
949 for (i = 0; i < PHY_RETRIES; i++) {
950 udelay(1);
951 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
952 return;
953 }
954 printk(KERN_WARNING PFX "%s: phy write timed out\n",
955 hw->dev[port]->name);
956 }
957
958 static void genesis_init(struct skge_hw *hw)
959 {
960 /* set blink source counter */
961 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
962 skge_write8(hw, B2_BSC_CTRL, BSC_START);
963
964 /* configure mac arbiter */
965 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
966
967 /* configure mac arbiter timeout values */
968 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
969 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
970 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
971 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
972
973 skge_write8(hw, B3_MA_RCINI_RX1, 0);
974 skge_write8(hw, B3_MA_RCINI_RX2, 0);
975 skge_write8(hw, B3_MA_RCINI_TX1, 0);
976 skge_write8(hw, B3_MA_RCINI_TX2, 0);
977
978 /* configure packet arbiter timeout */
979 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
980 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
981 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
982 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
983 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
984 }
985
986 static void genesis_reset(struct skge_hw *hw, int port)
987 {
988 const u8 zero[8] = { 0 };
989
990 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
991
992 /* reset the statistics module */
993 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
994 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
995 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
996 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
997 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
998
999 /* disable Broadcom PHY IRQ */
1000 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1001
1002 xm_outhash(hw, port, XM_HSM, zero);
1003 }
1004
1005
1006 /* Convert mode to MII values */
1007 static const u16 phy_pause_map[] = {
1008 [FLOW_MODE_NONE] = 0,
1009 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1010 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1011 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1012 };
1013
1014
1015 /* Check status of Broadcom phy link */
1016 static void bcom_check_link(struct skge_hw *hw, int port)
1017 {
1018 struct net_device *dev = hw->dev[port];
1019 struct skge_port *skge = netdev_priv(dev);
1020 u16 status;
1021
1022 /* read twice because of latch */
1023 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1024 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1025
1026 if ((status & PHY_ST_LSYNC) == 0) {
1027 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1028 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1029 xm_write16(hw, port, XM_MMU_CMD, cmd);
1030 /* dummy read to ensure writing */
1031 (void) xm_read16(hw, port, XM_MMU_CMD);
1032
1033 if (netif_carrier_ok(dev))
1034 skge_link_down(skge);
1035 } else {
1036 if (skge->autoneg == AUTONEG_ENABLE &&
1037 (status & PHY_ST_AN_OVER)) {
1038 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1039 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1040
1041 if (lpa & PHY_B_AN_RF) {
1042 printk(KERN_NOTICE PFX "%s: remote fault\n",
1043 dev->name);
1044 return;
1045 }
1046
1047 /* Check Duplex mismatch */
1048 switch (aux & PHY_B_AS_AN_RES_MSK) {
1049 case PHY_B_RES_1000FD:
1050 skge->duplex = DUPLEX_FULL;
1051 break;
1052 case PHY_B_RES_1000HD:
1053 skge->duplex = DUPLEX_HALF;
1054 break;
1055 default:
1056 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1057 dev->name);
1058 return;
1059 }
1060
1061
1062 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1063 switch (aux & PHY_B_AS_PAUSE_MSK) {
1064 case PHY_B_AS_PAUSE_MSK:
1065 skge->flow_control = FLOW_MODE_SYMMETRIC;
1066 break;
1067 case PHY_B_AS_PRR:
1068 skge->flow_control = FLOW_MODE_REM_SEND;
1069 break;
1070 case PHY_B_AS_PRT:
1071 skge->flow_control = FLOW_MODE_LOC_SEND;
1072 break;
1073 default:
1074 skge->flow_control = FLOW_MODE_NONE;
1075 }
1076
1077 skge->speed = SPEED_1000;
1078 }
1079
1080 if (!netif_carrier_ok(dev))
1081 genesis_link_up(skge);
1082 }
1083 }
1084
1085 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1086 * Phy on for 100 or 10Mbit operation
1087 */
1088 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1089 {
1090 struct skge_hw *hw = skge->hw;
1091 int port = skge->port;
1092 int i;
1093 u16 id1, r, ext, ctl;
1094
1095 /* magic workaround patterns for Broadcom */
1096 static const struct {
1097 u16 reg;
1098 u16 val;
1099 } A1hack[] = {
1100 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1101 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1102 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1103 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1104 }, C0hack[] = {
1105 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1106 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1107 };
1108
1109 /* read Id from external PHY (all have the same address) */
1110 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1111
1112 /* Optimize MDIO transfer by suppressing preamble. */
1113 r = xm_read16(hw, port, XM_MMU_CMD);
1114 r |= XM_MMU_NO_PRE;
1115 xm_write16(hw, port, XM_MMU_CMD,r);
1116
1117 switch (id1) {
1118 case PHY_BCOM_ID1_C0:
1119 /*
1120 * Workaround BCOM Errata for the C0 type.
1121 * Write magic patterns to reserved registers.
1122 */
1123 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1124 xm_phy_write(hw, port,
1125 C0hack[i].reg, C0hack[i].val);
1126
1127 break;
1128 case PHY_BCOM_ID1_A1:
1129 /*
1130 * Workaround BCOM Errata for the A1 type.
1131 * Write magic patterns to reserved registers.
1132 */
1133 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1134 xm_phy_write(hw, port,
1135 A1hack[i].reg, A1hack[i].val);
1136 break;
1137 }
1138
1139 /*
1140 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1141 * Disable Power Management after reset.
1142 */
1143 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1144 r |= PHY_B_AC_DIS_PM;
1145 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1146
1147 /* Dummy read */
1148 xm_read16(hw, port, XM_ISRC);
1149
1150 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1151 ctl = PHY_CT_SP1000; /* always 1000mbit */
1152
1153 if (skge->autoneg == AUTONEG_ENABLE) {
1154 /*
1155 * Workaround BCOM Errata #1 for the C5 type.
1156 * 1000Base-T Link Acquisition Failure in Slave Mode
1157 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1158 */
1159 u16 adv = PHY_B_1000C_RD;
1160 if (skge->advertising & ADVERTISED_1000baseT_Half)
1161 adv |= PHY_B_1000C_AHD;
1162 if (skge->advertising & ADVERTISED_1000baseT_Full)
1163 adv |= PHY_B_1000C_AFD;
1164 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1165
1166 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1167 } else {
1168 if (skge->duplex == DUPLEX_FULL)
1169 ctl |= PHY_CT_DUP_MD;
1170 /* Force to slave */
1171 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1172 }
1173
1174 /* Set autonegotiation pause parameters */
1175 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1176 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1177
1178 /* Handle Jumbo frames */
1179 if (jumbo) {
1180 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1181 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1182
1183 ext |= PHY_B_PEC_HIGH_LA;
1184
1185 }
1186
1187 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1188 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1189
1190 /* Use link status change interrrupt */
1191 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1192
1193 bcom_check_link(hw, port);
1194 }
1195
1196 static void genesis_mac_init(struct skge_hw *hw, int port)
1197 {
1198 struct net_device *dev = hw->dev[port];
1199 struct skge_port *skge = netdev_priv(dev);
1200 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1201 int i;
1202 u32 r;
1203 const u8 zero[6] = { 0 };
1204
1205 /* Clear MIB counters */
1206 xm_write16(hw, port, XM_STAT_CMD,
1207 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1208 /* Clear two times according to Errata #3 */
1209 xm_write16(hw, port, XM_STAT_CMD,
1210 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1211
1212 /* Unreset the XMAC. */
1213 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1214
1215 /*
1216 * Perform additional initialization for external PHYs,
1217 * namely for the 1000baseTX cards that use the XMAC's
1218 * GMII mode.
1219 */
1220 /* Take external Phy out of reset */
1221 r = skge_read32(hw, B2_GP_IO);
1222 if (port == 0)
1223 r |= GP_DIR_0|GP_IO_0;
1224 else
1225 r |= GP_DIR_2|GP_IO_2;
1226
1227 skge_write32(hw, B2_GP_IO, r);
1228 skge_read32(hw, B2_GP_IO);
1229
1230 /* Enable GMII interfac */
1231 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1232
1233 bcom_phy_init(skge, jumbo);
1234
1235 /* Set Station Address */
1236 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1237
1238 /* We don't use match addresses so clear */
1239 for (i = 1; i < 16; i++)
1240 xm_outaddr(hw, port, XM_EXM(i), zero);
1241
1242 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1243 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1244
1245 /* We don't need the FCS appended to the packet. */
1246 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1247 if (jumbo)
1248 r |= XM_RX_BIG_PK_OK;
1249
1250 if (skge->duplex == DUPLEX_HALF) {
1251 /*
1252 * If in manual half duplex mode the other side might be in
1253 * full duplex mode, so ignore if a carrier extension is not seen
1254 * on frames received
1255 */
1256 r |= XM_RX_DIS_CEXT;
1257 }
1258 xm_write16(hw, port, XM_RX_CMD, r);
1259
1260
1261 /* We want short frames padded to 60 bytes. */
1262 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1263
1264 /*
1265 * Bump up the transmit threshold. This helps hold off transmit
1266 * underruns when we're blasting traffic from both ports at once.
1267 */
1268 xm_write16(hw, port, XM_TX_THR, 512);
1269
1270 /*
1271 * Enable the reception of all error frames. This is is
1272 * a necessary evil due to the design of the XMAC. The
1273 * XMAC's receive FIFO is only 8K in size, however jumbo
1274 * frames can be up to 9000 bytes in length. When bad
1275 * frame filtering is enabled, the XMAC's RX FIFO operates
1276 * in 'store and forward' mode. For this to work, the
1277 * entire frame has to fit into the FIFO, but that means
1278 * that jumbo frames larger than 8192 bytes will be
1279 * truncated. Disabling all bad frame filtering causes
1280 * the RX FIFO to operate in streaming mode, in which
1281 * case the XMAC will start transfering frames out of the
1282 * RX FIFO as soon as the FIFO threshold is reached.
1283 */
1284 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1285
1286
1287 /*
1288 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1289 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1290 * and 'Octets Rx OK Hi Cnt Ov'.
1291 */
1292 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1293
1294 /*
1295 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1296 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1297 * and 'Octets Tx OK Hi Cnt Ov'.
1298 */
1299 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1300
1301 /* Configure MAC arbiter */
1302 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1303
1304 /* configure timeout values */
1305 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1306 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1307 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1308 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1309
1310 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1311 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1312 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1313 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1314
1315 /* Configure Rx MAC FIFO */
1316 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1317 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1318 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1319
1320 /* Configure Tx MAC FIFO */
1321 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1322 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1323 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1324
1325 if (jumbo) {
1326 /* Enable frame flushing if jumbo frames used */
1327 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1328 } else {
1329 /* enable timeout timers if normal frames */
1330 skge_write16(hw, B3_PA_CTRL,
1331 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1332 }
1333 }
1334
1335 static void genesis_stop(struct skge_port *skge)
1336 {
1337 struct skge_hw *hw = skge->hw;
1338 int port = skge->port;
1339 u32 reg;
1340
1341 genesis_reset(hw, port);
1342
1343 /* Clear Tx packet arbiter timeout IRQ */
1344 skge_write16(hw, B3_PA_CTRL,
1345 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1346
1347 /*
1348 * If the transfer stucks at the MAC the STOP command will not
1349 * terminate if we don't flush the XMAC's transmit FIFO !
1350 */
1351 xm_write32(hw, port, XM_MODE,
1352 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1353
1354
1355 /* Reset the MAC */
1356 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1357
1358 /* For external PHYs there must be special handling */
1359 reg = skge_read32(hw, B2_GP_IO);
1360 if (port == 0) {
1361 reg |= GP_DIR_0;
1362 reg &= ~GP_IO_0;
1363 } else {
1364 reg |= GP_DIR_2;
1365 reg &= ~GP_IO_2;
1366 }
1367 skge_write32(hw, B2_GP_IO, reg);
1368 skge_read32(hw, B2_GP_IO);
1369
1370 xm_write16(hw, port, XM_MMU_CMD,
1371 xm_read16(hw, port, XM_MMU_CMD)
1372 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1373
1374 xm_read16(hw, port, XM_MMU_CMD);
1375 }
1376
1377
1378 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1379 {
1380 struct skge_hw *hw = skge->hw;
1381 int port = skge->port;
1382 int i;
1383 unsigned long timeout = jiffies + HZ;
1384
1385 xm_write16(hw, port,
1386 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1387
1388 /* wait for update to complete */
1389 while (xm_read16(hw, port, XM_STAT_CMD)
1390 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1391 if (time_after(jiffies, timeout))
1392 break;
1393 udelay(10);
1394 }
1395
1396 /* special case for 64 bit octet counter */
1397 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1398 | xm_read32(hw, port, XM_TXO_OK_LO);
1399 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1400 | xm_read32(hw, port, XM_RXO_OK_LO);
1401
1402 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1403 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1404 }
1405
1406 static void genesis_mac_intr(struct skge_hw *hw, int port)
1407 {
1408 struct skge_port *skge = netdev_priv(hw->dev[port]);
1409 u16 status = xm_read16(hw, port, XM_ISRC);
1410
1411 if (netif_msg_intr(skge))
1412 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1413 skge->netdev->name, status);
1414
1415 if (status & XM_IS_TXF_UR) {
1416 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1417 ++skge->net_stats.tx_fifo_errors;
1418 }
1419 if (status & XM_IS_RXF_OV) {
1420 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1421 ++skge->net_stats.rx_fifo_errors;
1422 }
1423 }
1424
1425 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1426 {
1427 int i;
1428
1429 gma_write16(hw, port, GM_SMI_DATA, val);
1430 gma_write16(hw, port, GM_SMI_CTRL,
1431 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1432 for (i = 0; i < PHY_RETRIES; i++) {
1433 udelay(1);
1434
1435 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1436 break;
1437 }
1438 }
1439
1440 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1441 {
1442 int i;
1443
1444 gma_write16(hw, port, GM_SMI_CTRL,
1445 GM_SMI_CT_PHY_AD(hw->phy_addr)
1446 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1447
1448 for (i = 0; i < PHY_RETRIES; i++) {
1449 udelay(1);
1450 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1451 goto ready;
1452 }
1453
1454 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1455 hw->dev[port]->name);
1456 return 0;
1457 ready:
1458 return gma_read16(hw, port, GM_SMI_DATA);
1459 }
1460
1461 static void genesis_link_up(struct skge_port *skge)
1462 {
1463 struct skge_hw *hw = skge->hw;
1464 int port = skge->port;
1465 u16 cmd;
1466 u32 mode, msk;
1467
1468 cmd = xm_read16(hw, port, XM_MMU_CMD);
1469
1470 /*
1471 * enabling pause frame reception is required for 1000BT
1472 * because the XMAC is not reset if the link is going down
1473 */
1474 if (skge->flow_control == FLOW_MODE_NONE ||
1475 skge->flow_control == FLOW_MODE_LOC_SEND)
1476 /* Disable Pause Frame Reception */
1477 cmd |= XM_MMU_IGN_PF;
1478 else
1479 /* Enable Pause Frame Reception */
1480 cmd &= ~XM_MMU_IGN_PF;
1481
1482 xm_write16(hw, port, XM_MMU_CMD, cmd);
1483
1484 mode = xm_read32(hw, port, XM_MODE);
1485 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1486 skge->flow_control == FLOW_MODE_LOC_SEND) {
1487 /*
1488 * Configure Pause Frame Generation
1489 * Use internal and external Pause Frame Generation.
1490 * Sending pause frames is edge triggered.
1491 * Send a Pause frame with the maximum pause time if
1492 * internal oder external FIFO full condition occurs.
1493 * Send a zero pause time frame to re-start transmission.
1494 */
1495 /* XM_PAUSE_DA = '010000C28001' (default) */
1496 /* XM_MAC_PTIME = 0xffff (maximum) */
1497 /* remember this value is defined in big endian (!) */
1498 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1499
1500 mode |= XM_PAUSE_MODE;
1501 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1502 } else {
1503 /*
1504 * disable pause frame generation is required for 1000BT
1505 * because the XMAC is not reset if the link is going down
1506 */
1507 /* Disable Pause Mode in Mode Register */
1508 mode &= ~XM_PAUSE_MODE;
1509
1510 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1511 }
1512
1513 xm_write32(hw, port, XM_MODE, mode);
1514
1515 msk = XM_DEF_MSK;
1516 /* disable GP0 interrupt bit for external Phy */
1517 msk |= XM_IS_INP_ASS;
1518
1519 xm_write16(hw, port, XM_IMSK, msk);
1520 xm_read16(hw, port, XM_ISRC);
1521
1522 /* get MMU Command Reg. */
1523 cmd = xm_read16(hw, port, XM_MMU_CMD);
1524 if (skge->duplex == DUPLEX_FULL)
1525 cmd |= XM_MMU_GMII_FD;
1526
1527 /*
1528 * Workaround BCOM Errata (#10523) for all BCom Phys
1529 * Enable Power Management after link up
1530 */
1531 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1532 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1533 & ~PHY_B_AC_DIS_PM);
1534 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1535
1536 /* enable Rx/Tx */
1537 xm_write16(hw, port, XM_MMU_CMD,
1538 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1539 skge_link_up(skge);
1540 }
1541
1542
1543 static inline void bcom_phy_intr(struct skge_port *skge)
1544 {
1545 struct skge_hw *hw = skge->hw;
1546 int port = skge->port;
1547 u16 isrc;
1548
1549 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1550 if (netif_msg_intr(skge))
1551 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1552 skge->netdev->name, isrc);
1553
1554 if (isrc & PHY_B_IS_PSE)
1555 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1556 hw->dev[port]->name);
1557
1558 /* Workaround BCom Errata:
1559 * enable and disable loopback mode if "NO HCD" occurs.
1560 */
1561 if (isrc & PHY_B_IS_NO_HDCL) {
1562 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1563 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1564 ctrl | PHY_CT_LOOP);
1565 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1566 ctrl & ~PHY_CT_LOOP);
1567 }
1568
1569 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1570 bcom_check_link(hw, port);
1571
1572 }
1573
1574 /* Marvell Phy Initailization */
1575 static void yukon_init(struct skge_hw *hw, int port)
1576 {
1577 struct skge_port *skge = netdev_priv(hw->dev[port]);
1578 u16 ctrl, ct1000, adv;
1579
1580 if (skge->autoneg == AUTONEG_ENABLE) {
1581 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1582
1583 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1584 PHY_M_EC_MAC_S_MSK);
1585 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1586
1587 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1588
1589 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1590 }
1591
1592 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1593 if (skge->autoneg == AUTONEG_DISABLE)
1594 ctrl &= ~PHY_CT_ANE;
1595
1596 ctrl |= PHY_CT_RESET;
1597 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1598
1599 ctrl = 0;
1600 ct1000 = 0;
1601 adv = PHY_AN_CSMA;
1602
1603 if (skge->autoneg == AUTONEG_ENABLE) {
1604 if (hw->copper) {
1605 if (skge->advertising & ADVERTISED_1000baseT_Full)
1606 ct1000 |= PHY_M_1000C_AFD;
1607 if (skge->advertising & ADVERTISED_1000baseT_Half)
1608 ct1000 |= PHY_M_1000C_AHD;
1609 if (skge->advertising & ADVERTISED_100baseT_Full)
1610 adv |= PHY_M_AN_100_FD;
1611 if (skge->advertising & ADVERTISED_100baseT_Half)
1612 adv |= PHY_M_AN_100_HD;
1613 if (skge->advertising & ADVERTISED_10baseT_Full)
1614 adv |= PHY_M_AN_10_FD;
1615 if (skge->advertising & ADVERTISED_10baseT_Half)
1616 adv |= PHY_M_AN_10_HD;
1617 } else /* special defines for FIBER (88E1011S only) */
1618 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1619
1620 /* Set Flow-control capabilities */
1621 adv |= phy_pause_map[skge->flow_control];
1622
1623 /* Restart Auto-negotiation */
1624 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1625 } else {
1626 /* forced speed/duplex settings */
1627 ct1000 = PHY_M_1000C_MSE;
1628
1629 if (skge->duplex == DUPLEX_FULL)
1630 ctrl |= PHY_CT_DUP_MD;
1631
1632 switch (skge->speed) {
1633 case SPEED_1000:
1634 ctrl |= PHY_CT_SP1000;
1635 break;
1636 case SPEED_100:
1637 ctrl |= PHY_CT_SP100;
1638 break;
1639 }
1640
1641 ctrl |= PHY_CT_RESET;
1642 }
1643
1644 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1645
1646 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1647 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1648
1649 /* Enable phy interrupt on autonegotiation complete (or link up) */
1650 if (skge->autoneg == AUTONEG_ENABLE)
1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1652 else
1653 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1654 }
1655
1656 static void yukon_reset(struct skge_hw *hw, int port)
1657 {
1658 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1659 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1660 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1661 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1662 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1663
1664 gma_write16(hw, port, GM_RX_CTRL,
1665 gma_read16(hw, port, GM_RX_CTRL)
1666 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1667 }
1668
1669 static void yukon_mac_init(struct skge_hw *hw, int port)
1670 {
1671 struct skge_port *skge = netdev_priv(hw->dev[port]);
1672 int i;
1673 u32 reg;
1674 const u8 *addr = hw->dev[port]->dev_addr;
1675
1676 /* WA code for COMA mode -- set PHY reset */
1677 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1678 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1679 reg = skge_read32(hw, B2_GP_IO);
1680 reg |= GP_DIR_9 | GP_IO_9;
1681 skge_write32(hw, B2_GP_IO, reg);
1682 }
1683
1684 /* hard reset */
1685 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1686 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1687
1688 /* WA code for COMA mode -- clear PHY reset */
1689 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1690 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1691 reg = skge_read32(hw, B2_GP_IO);
1692 reg |= GP_DIR_9;
1693 reg &= ~GP_IO_9;
1694 skge_write32(hw, B2_GP_IO, reg);
1695 }
1696
1697 /* Set hardware config mode */
1698 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1699 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1700 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1701
1702 /* Clear GMC reset */
1703 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1704 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1705 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1706 if (skge->autoneg == AUTONEG_DISABLE) {
1707 reg = GM_GPCR_AU_ALL_DIS;
1708 gma_write16(hw, port, GM_GP_CTRL,
1709 gma_read16(hw, port, GM_GP_CTRL) | reg);
1710
1711 switch (skge->speed) {
1712 case SPEED_1000:
1713 reg |= GM_GPCR_SPEED_1000;
1714 /* fallthru */
1715 case SPEED_100:
1716 reg |= GM_GPCR_SPEED_100;
1717 }
1718
1719 if (skge->duplex == DUPLEX_FULL)
1720 reg |= GM_GPCR_DUP_FULL;
1721 } else
1722 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1723 switch (skge->flow_control) {
1724 case FLOW_MODE_NONE:
1725 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1726 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1727 break;
1728 case FLOW_MODE_LOC_SEND:
1729 /* disable Rx flow-control */
1730 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1731 }
1732
1733 gma_write16(hw, port, GM_GP_CTRL, reg);
1734 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1735
1736 yukon_init(hw, port);
1737
1738 /* MIB clear */
1739 reg = gma_read16(hw, port, GM_PHY_ADDR);
1740 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1741
1742 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1743 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1744 gma_write16(hw, port, GM_PHY_ADDR, reg);
1745
1746 /* transmit control */
1747 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1748
1749 /* receive control reg: unicast + multicast + no FCS */
1750 gma_write16(hw, port, GM_RX_CTRL,
1751 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1752
1753 /* transmit flow control */
1754 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1755
1756 /* transmit parameter */
1757 gma_write16(hw, port, GM_TX_PARAM,
1758 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1759 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1760 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1761
1762 /* serial mode register */
1763 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1764 if (hw->dev[port]->mtu > 1500)
1765 reg |= GM_SMOD_JUMBO_ENA;
1766
1767 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1768
1769 /* physical address: used for pause frames */
1770 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1771 /* virtual address for data */
1772 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1773
1774 /* enable interrupt mask for counter overflows */
1775 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1776 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1777 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1778
1779 /* Initialize Mac Fifo */
1780
1781 /* Configure Rx MAC FIFO */
1782 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1783 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1784 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1785 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1786 reg &= ~GMF_RX_F_FL_ON;
1787 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1788 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1789 /*
1790 * because Pause Packet Truncation in GMAC is not working
1791 * we have to increase the Flush Threshold to 64 bytes
1792 * in order to flush pause packets in Rx FIFO on Yukon-1
1793 */
1794 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1795
1796 /* Configure Tx MAC FIFO */
1797 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1798 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1799 }
1800
1801 static void yukon_stop(struct skge_port *skge)
1802 {
1803 struct skge_hw *hw = skge->hw;
1804 int port = skge->port;
1805
1806 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1807 yukon_reset(hw, port);
1808
1809 gma_write16(hw, port, GM_GP_CTRL,
1810 gma_read16(hw, port, GM_GP_CTRL)
1811 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1812 gma_read16(hw, port, GM_GP_CTRL);
1813
1814 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1815 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1816 u32 io = skge_read32(hw, B2_GP_IO);
1817
1818 io |= GP_DIR_9 | GP_IO_9;
1819 skge_write32(hw, B2_GP_IO, io);
1820 skge_read32(hw, B2_GP_IO);
1821 }
1822
1823 /* set GPHY Control reset */
1824 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1825 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1826 }
1827
1828 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1829 {
1830 struct skge_hw *hw = skge->hw;
1831 int port = skge->port;
1832 int i;
1833
1834 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1835 | gma_read32(hw, port, GM_TXO_OK_LO);
1836 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1837 | gma_read32(hw, port, GM_RXO_OK_LO);
1838
1839 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1840 data[i] = gma_read32(hw, port,
1841 skge_stats[i].gma_offset);
1842 }
1843
1844 static void yukon_mac_intr(struct skge_hw *hw, int port)
1845 {
1846 struct net_device *dev = hw->dev[port];
1847 struct skge_port *skge = netdev_priv(dev);
1848 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1849
1850 if (netif_msg_intr(skge))
1851 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1852 dev->name, status);
1853
1854 if (status & GM_IS_RX_FF_OR) {
1855 ++skge->net_stats.rx_fifo_errors;
1856 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1857 }
1858
1859 if (status & GM_IS_TX_FF_UR) {
1860 ++skge->net_stats.tx_fifo_errors;
1861 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1862 }
1863
1864 }
1865
1866 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1867 {
1868 switch (aux & PHY_M_PS_SPEED_MSK) {
1869 case PHY_M_PS_SPEED_1000:
1870 return SPEED_1000;
1871 case PHY_M_PS_SPEED_100:
1872 return SPEED_100;
1873 default:
1874 return SPEED_10;
1875 }
1876 }
1877
1878 static void yukon_link_up(struct skge_port *skge)
1879 {
1880 struct skge_hw *hw = skge->hw;
1881 int port = skge->port;
1882 u16 reg;
1883
1884 /* Enable Transmit FIFO Underrun */
1885 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1886
1887 reg = gma_read16(hw, port, GM_GP_CTRL);
1888 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1889 reg |= GM_GPCR_DUP_FULL;
1890
1891 /* enable Rx/Tx */
1892 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1893 gma_write16(hw, port, GM_GP_CTRL, reg);
1894
1895 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1896 skge_link_up(skge);
1897 }
1898
1899 static void yukon_link_down(struct skge_port *skge)
1900 {
1901 struct skge_hw *hw = skge->hw;
1902 int port = skge->port;
1903 u16 ctrl;
1904
1905 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1906
1907 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1908 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1909 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1910
1911 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1912 /* restore Asymmetric Pause bit */
1913 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1914 gm_phy_read(hw, port,
1915 PHY_MARV_AUNE_ADV)
1916 | PHY_M_AN_ASP);
1917
1918 }
1919
1920 yukon_reset(hw, port);
1921 skge_link_down(skge);
1922
1923 yukon_init(hw, port);
1924 }
1925
1926 static void yukon_phy_intr(struct skge_port *skge)
1927 {
1928 struct skge_hw *hw = skge->hw;
1929 int port = skge->port;
1930 const char *reason = NULL;
1931 u16 istatus, phystat;
1932
1933 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1934 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1935
1936 if (netif_msg_intr(skge))
1937 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1938 skge->netdev->name, istatus, phystat);
1939
1940 if (istatus & PHY_M_IS_AN_COMPL) {
1941 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1942 & PHY_M_AN_RF) {
1943 reason = "remote fault";
1944 goto failed;
1945 }
1946
1947 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1948 reason = "master/slave fault";
1949 goto failed;
1950 }
1951
1952 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1953 reason = "speed/duplex";
1954 goto failed;
1955 }
1956
1957 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1958 ? DUPLEX_FULL : DUPLEX_HALF;
1959 skge->speed = yukon_speed(hw, phystat);
1960
1961 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1962 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1963 case PHY_M_PS_PAUSE_MSK:
1964 skge->flow_control = FLOW_MODE_SYMMETRIC;
1965 break;
1966 case PHY_M_PS_RX_P_EN:
1967 skge->flow_control = FLOW_MODE_REM_SEND;
1968 break;
1969 case PHY_M_PS_TX_P_EN:
1970 skge->flow_control = FLOW_MODE_LOC_SEND;
1971 break;
1972 default:
1973 skge->flow_control = FLOW_MODE_NONE;
1974 }
1975
1976 if (skge->flow_control == FLOW_MODE_NONE ||
1977 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1978 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1979 else
1980 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1981 yukon_link_up(skge);
1982 return;
1983 }
1984
1985 if (istatus & PHY_M_IS_LSP_CHANGE)
1986 skge->speed = yukon_speed(hw, phystat);
1987
1988 if (istatus & PHY_M_IS_DUP_CHANGE)
1989 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1990 if (istatus & PHY_M_IS_LST_CHANGE) {
1991 if (phystat & PHY_M_PS_LINK_UP)
1992 yukon_link_up(skge);
1993 else
1994 yukon_link_down(skge);
1995 }
1996 return;
1997 failed:
1998 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1999 skge->netdev->name, reason);
2000
2001 /* XXX restart autonegotiation? */
2002 }
2003
2004 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2005 {
2006 u32 end;
2007
2008 start /= 8;
2009 len /= 8;
2010 end = start + len - 1;
2011
2012 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2013 skge_write32(hw, RB_ADDR(q, RB_START), start);
2014 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2015 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2016 skge_write32(hw, RB_ADDR(q, RB_END), end);
2017
2018 if (q == Q_R1 || q == Q_R2) {
2019 /* Set thresholds on receive queue's */
2020 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2021 start + (2*len)/3);
2022 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2023 start + (len/3));
2024 } else {
2025 /* Enable store & forward on Tx queue's because
2026 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2027 */
2028 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2029 }
2030
2031 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2032 }
2033
2034 /* Setup Bus Memory Interface */
2035 static void skge_qset(struct skge_port *skge, u16 q,
2036 const struct skge_element *e)
2037 {
2038 struct skge_hw *hw = skge->hw;
2039 u32 watermark = 0x600;
2040 u64 base = skge->dma + (e->desc - skge->mem);
2041
2042 /* optimization to reduce window on 32bit/33mhz */
2043 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2044 watermark /= 2;
2045
2046 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2047 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2048 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2049 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2050 }
2051
2052 static int skge_up(struct net_device *dev)
2053 {
2054 struct skge_port *skge = netdev_priv(dev);
2055 struct skge_hw *hw = skge->hw;
2056 int port = skge->port;
2057 u32 chunk, ram_addr;
2058 size_t rx_size, tx_size;
2059 int err;
2060
2061 if (netif_msg_ifup(skge))
2062 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2063
2064 if (dev->mtu > RX_BUF_SIZE)
2065 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2066 else
2067 skge->rx_buf_size = RX_BUF_SIZE;
2068
2069
2070 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2071 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2072 skge->mem_size = tx_size + rx_size;
2073 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2074 if (!skge->mem)
2075 return -ENOMEM;
2076
2077 memset(skge->mem, 0, skge->mem_size);
2078
2079 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2080 goto free_pci_mem;
2081
2082 err = skge_rx_fill(skge);
2083 if (err)
2084 goto free_rx_ring;
2085
2086 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2087 skge->dma + rx_size)))
2088 goto free_rx_ring;
2089
2090 skge->tx_avail = skge->tx_ring.count - 1;
2091
2092 /* Enable IRQ from port */
2093 hw->intr_mask |= portirqmask[port];
2094 skge_write32(hw, B0_IMSK, hw->intr_mask);
2095
2096 /* Initialze MAC */
2097 spin_lock_bh(&hw->phy_lock);
2098 if (hw->chip_id == CHIP_ID_GENESIS)
2099 genesis_mac_init(hw, port);
2100 else
2101 yukon_mac_init(hw, port);
2102 spin_unlock_bh(&hw->phy_lock);
2103
2104 /* Configure RAMbuffers */
2105 chunk = hw->ram_size / ((hw->ports + 1)*2);
2106 ram_addr = hw->ram_offset + 2 * chunk * port;
2107
2108 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2109 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2110
2111 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2112 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2113 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2114
2115 /* Start receiver BMU */
2116 wmb();
2117 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2118 skge_led(skge, LED_MODE_ON);
2119
2120 return 0;
2121
2122 free_rx_ring:
2123 skge_rx_clean(skge);
2124 kfree(skge->rx_ring.start);
2125 free_pci_mem:
2126 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2127
2128 return err;
2129 }
2130
2131 static int skge_down(struct net_device *dev)
2132 {
2133 struct skge_port *skge = netdev_priv(dev);
2134 struct skge_hw *hw = skge->hw;
2135 int port = skge->port;
2136
2137 if (netif_msg_ifdown(skge))
2138 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2139
2140 netif_stop_queue(dev);
2141
2142 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2143 if (hw->chip_id == CHIP_ID_GENESIS)
2144 genesis_stop(skge);
2145 else
2146 yukon_stop(skge);
2147
2148 hw->intr_mask &= ~portirqmask[skge->port];
2149 skge_write32(hw, B0_IMSK, hw->intr_mask);
2150
2151 /* Stop transmitter */
2152 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2153 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2154 RB_RST_SET|RB_DIS_OP_MD);
2155
2156
2157 /* Disable Force Sync bit and Enable Alloc bit */
2158 skge_write8(hw, SK_REG(port, TXA_CTRL),
2159 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2160
2161 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2162 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2163 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2164
2165 /* Reset PCI FIFO */
2166 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2167 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2168
2169 /* Reset the RAM Buffer async Tx queue */
2170 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2171 /* stop receiver */
2172 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2173 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2174 RB_RST_SET|RB_DIS_OP_MD);
2175 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2176
2177 if (hw->chip_id == CHIP_ID_GENESIS) {
2178 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2179 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2180 } else {
2181 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2182 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2183 }
2184
2185 skge_led(skge, LED_MODE_OFF);
2186
2187 skge_tx_clean(skge);
2188 skge_rx_clean(skge);
2189
2190 kfree(skge->rx_ring.start);
2191 kfree(skge->tx_ring.start);
2192 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2193 return 0;
2194 }
2195
2196 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2197 {
2198 struct skge_port *skge = netdev_priv(dev);
2199 struct skge_hw *hw = skge->hw;
2200 struct skge_ring *ring = &skge->tx_ring;
2201 struct skge_element *e;
2202 struct skge_tx_desc *td;
2203 int i;
2204 u32 control, len;
2205 u64 map;
2206 unsigned long flags;
2207
2208 skb = skb_padto(skb, ETH_ZLEN);
2209 if (!skb)
2210 return NETDEV_TX_OK;
2211
2212 local_irq_save(flags);
2213 if (!spin_trylock(&skge->tx_lock)) {
2214 /* Collision - tell upper layer to requeue */
2215 local_irq_restore(flags);
2216 return NETDEV_TX_LOCKED;
2217 }
2218
2219 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2220 netif_stop_queue(dev);
2221 spin_unlock_irqrestore(&skge->tx_lock, flags);
2222
2223 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2224 dev->name);
2225 return NETDEV_TX_BUSY;
2226 }
2227
2228 e = ring->to_use;
2229 td = e->desc;
2230 e->skb = skb;
2231 len = skb_headlen(skb);
2232 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2233 pci_unmap_addr_set(e, mapaddr, map);
2234 pci_unmap_len_set(e, maplen, len);
2235
2236 td->dma_lo = map;
2237 td->dma_hi = map >> 32;
2238
2239 if (skb->ip_summed == CHECKSUM_HW) {
2240 const struct iphdr *ip
2241 = (const struct iphdr *) (skb->data + ETH_HLEN);
2242 int offset = skb->h.raw - skb->data;
2243
2244 /* This seems backwards, but it is what the sk98lin
2245 * does. Looks like hardware is wrong?
2246 */
2247 if (ip->protocol == IPPROTO_UDP
2248 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2249 control = BMU_TCP_CHECK;
2250 else
2251 control = BMU_UDP_CHECK;
2252
2253 td->csum_offs = 0;
2254 td->csum_start = offset;
2255 td->csum_write = offset + skb->csum;
2256 } else
2257 control = BMU_CHECK;
2258
2259 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2260 control |= BMU_EOF| BMU_IRQ_EOF;
2261 else {
2262 struct skge_tx_desc *tf = td;
2263
2264 control |= BMU_STFWD;
2265 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2266 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2267
2268 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2269 frag->size, PCI_DMA_TODEVICE);
2270
2271 e = e->next;
2272 e->skb = NULL;
2273 tf = e->desc;
2274 tf->dma_lo = map;
2275 tf->dma_hi = (u64) map >> 32;
2276 pci_unmap_addr_set(e, mapaddr, map);
2277 pci_unmap_len_set(e, maplen, frag->size);
2278
2279 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2280 }
2281 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2282 }
2283 /* Make sure all the descriptors written */
2284 wmb();
2285 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2286 wmb();
2287
2288 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2289
2290 if (netif_msg_tx_queued(skge))
2291 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2292 dev->name, e - ring->start, skb->len);
2293
2294 ring->to_use = e->next;
2295 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2296 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2297 pr_debug("%s: transmit queue full\n", dev->name);
2298 netif_stop_queue(dev);
2299 }
2300
2301 dev->trans_start = jiffies;
2302 spin_unlock_irqrestore(&skge->tx_lock, flags);
2303
2304 return NETDEV_TX_OK;
2305 }
2306
2307 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2308 {
2309 /* This ring element can be skb or fragment */
2310 if (e->skb) {
2311 pci_unmap_single(hw->pdev,
2312 pci_unmap_addr(e, mapaddr),
2313 pci_unmap_len(e, maplen),
2314 PCI_DMA_TODEVICE);
2315 dev_kfree_skb_any(e->skb);
2316 e->skb = NULL;
2317 } else {
2318 pci_unmap_page(hw->pdev,
2319 pci_unmap_addr(e, mapaddr),
2320 pci_unmap_len(e, maplen),
2321 PCI_DMA_TODEVICE);
2322 }
2323 }
2324
2325 static void skge_tx_clean(struct skge_port *skge)
2326 {
2327 struct skge_ring *ring = &skge->tx_ring;
2328 struct skge_element *e;
2329 unsigned long flags;
2330
2331 spin_lock_irqsave(&skge->tx_lock, flags);
2332 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2333 ++skge->tx_avail;
2334 skge_tx_free(skge->hw, e);
2335 }
2336 ring->to_clean = e;
2337 spin_unlock_irqrestore(&skge->tx_lock, flags);
2338 }
2339
2340 static void skge_tx_timeout(struct net_device *dev)
2341 {
2342 struct skge_port *skge = netdev_priv(dev);
2343
2344 if (netif_msg_timer(skge))
2345 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2346
2347 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2348 skge_tx_clean(skge);
2349 }
2350
2351 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2352 {
2353 int err = 0;
2354 int running = netif_running(dev);
2355
2356 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2357 return -EINVAL;
2358
2359
2360 if (running)
2361 skge_down(dev);
2362 dev->mtu = new_mtu;
2363 if (running)
2364 skge_up(dev);
2365
2366 return err;
2367 }
2368
2369 static void genesis_set_multicast(struct net_device *dev)
2370 {
2371 struct skge_port *skge = netdev_priv(dev);
2372 struct skge_hw *hw = skge->hw;
2373 int port = skge->port;
2374 int i, count = dev->mc_count;
2375 struct dev_mc_list *list = dev->mc_list;
2376 u32 mode;
2377 u8 filter[8];
2378
2379 mode = xm_read32(hw, port, XM_MODE);
2380 mode |= XM_MD_ENA_HASH;
2381 if (dev->flags & IFF_PROMISC)
2382 mode |= XM_MD_ENA_PROM;
2383 else
2384 mode &= ~XM_MD_ENA_PROM;
2385
2386 if (dev->flags & IFF_ALLMULTI)
2387 memset(filter, 0xff, sizeof(filter));
2388 else {
2389 memset(filter, 0, sizeof(filter));
2390 for (i = 0; list && i < count; i++, list = list->next) {
2391 u32 crc, bit;
2392 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2393 bit = ~crc & 0x3f;
2394 filter[bit/8] |= 1 << (bit%8);
2395 }
2396 }
2397
2398 xm_write32(hw, port, XM_MODE, mode);
2399 xm_outhash(hw, port, XM_HSM, filter);
2400 }
2401
2402 static void yukon_set_multicast(struct net_device *dev)
2403 {
2404 struct skge_port *skge = netdev_priv(dev);
2405 struct skge_hw *hw = skge->hw;
2406 int port = skge->port;
2407 struct dev_mc_list *list = dev->mc_list;
2408 u16 reg;
2409 u8 filter[8];
2410
2411 memset(filter, 0, sizeof(filter));
2412
2413 reg = gma_read16(hw, port, GM_RX_CTRL);
2414 reg |= GM_RXCR_UCF_ENA;
2415
2416 if (dev->flags & IFF_PROMISC) /* promiscious */
2417 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2418 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2419 memset(filter, 0xff, sizeof(filter));
2420 else if (dev->mc_count == 0) /* no multicast */
2421 reg &= ~GM_RXCR_MCF_ENA;
2422 else {
2423 int i;
2424 reg |= GM_RXCR_MCF_ENA;
2425
2426 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2427 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2428 filter[bit/8] |= 1 << (bit%8);
2429 }
2430 }
2431
2432
2433 gma_write16(hw, port, GM_MC_ADDR_H1,
2434 (u16)filter[0] | ((u16)filter[1] << 8));
2435 gma_write16(hw, port, GM_MC_ADDR_H2,
2436 (u16)filter[2] | ((u16)filter[3] << 8));
2437 gma_write16(hw, port, GM_MC_ADDR_H3,
2438 (u16)filter[4] | ((u16)filter[5] << 8));
2439 gma_write16(hw, port, GM_MC_ADDR_H4,
2440 (u16)filter[6] | ((u16)filter[7] << 8));
2441
2442 gma_write16(hw, port, GM_RX_CTRL, reg);
2443 }
2444
2445 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2446 {
2447 if (hw->chip_id == CHIP_ID_GENESIS)
2448 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2449 else
2450 return (status & GMR_FS_ANY_ERR) ||
2451 (status & GMR_FS_RX_OK) == 0;
2452 }
2453
2454 static void skge_rx_error(struct skge_port *skge, int slot,
2455 u32 control, u32 status)
2456 {
2457 if (netif_msg_rx_err(skge))
2458 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2459 skge->netdev->name, slot, control, status);
2460
2461 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2462 skge->net_stats.rx_length_errors++;
2463 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2464 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2465 skge->net_stats.rx_length_errors++;
2466 if (status & XMR_FS_FRA_ERR)
2467 skge->net_stats.rx_frame_errors++;
2468 if (status & XMR_FS_FCS_ERR)
2469 skge->net_stats.rx_crc_errors++;
2470 } else {
2471 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2472 skge->net_stats.rx_length_errors++;
2473 if (status & GMR_FS_FRAGMENT)
2474 skge->net_stats.rx_frame_errors++;
2475 if (status & GMR_FS_CRC_ERR)
2476 skge->net_stats.rx_crc_errors++;
2477 }
2478 }
2479
2480 /* Get receive buffer from descriptor.
2481 * Handles copy of small buffers and reallocation failures
2482 */
2483 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2484 struct skge_element *e,
2485 unsigned int len)
2486 {
2487 struct sk_buff *nskb, *skb;
2488
2489 if (len < RX_COPY_THRESHOLD) {
2490 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2491 if (unlikely(!nskb))
2492 return NULL;
2493
2494 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2495 pci_unmap_addr(e, mapaddr),
2496 len, PCI_DMA_FROMDEVICE);
2497 memcpy(nskb->data, e->skb->data, len);
2498 pci_dma_sync_single_for_device(skge->hw->pdev,
2499 pci_unmap_addr(e, mapaddr),
2500 len, PCI_DMA_FROMDEVICE);
2501
2502 if (skge->rx_csum) {
2503 struct skge_rx_desc *rd = e->desc;
2504 nskb->csum = le16_to_cpu(rd->csum2);
2505 nskb->ip_summed = CHECKSUM_HW;
2506 }
2507 skge_rx_reuse(e, skge->rx_buf_size);
2508 return nskb;
2509 } else {
2510 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2511 if (unlikely(!nskb))
2512 return NULL;
2513
2514 pci_unmap_single(skge->hw->pdev,
2515 pci_unmap_addr(e, mapaddr),
2516 pci_unmap_len(e, maplen),
2517 PCI_DMA_FROMDEVICE);
2518 skb = e->skb;
2519 if (skge->rx_csum) {
2520 struct skge_rx_desc *rd = e->desc;
2521 skb->csum = le16_to_cpu(rd->csum2);
2522 skb->ip_summed = CHECKSUM_HW;
2523 }
2524
2525 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2526 return skb;
2527 }
2528 }
2529
2530
2531 static int skge_poll(struct net_device *dev, int *budget)
2532 {
2533 struct skge_port *skge = netdev_priv(dev);
2534 struct skge_hw *hw = skge->hw;
2535 struct skge_ring *ring = &skge->rx_ring;
2536 struct skge_element *e;
2537 unsigned int to_do = min(dev->quota, *budget);
2538 unsigned int work_done = 0;
2539
2540 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2541 struct skge_rx_desc *rd = e->desc;
2542 struct sk_buff *skb;
2543 u32 control, len, status;
2544
2545 rmb();
2546 control = rd->control;
2547 if (control & BMU_OWN)
2548 break;
2549
2550 len = control & BMU_BBC;
2551 status = rd->status;
2552
2553 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2554 || bad_phy_status(hw, status))) {
2555 skge_rx_error(skge, e - ring->start, control, status);
2556 skge_rx_reuse(e, skge->rx_buf_size);
2557 continue;
2558 }
2559
2560 if (netif_msg_rx_status(skge))
2561 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2562 dev->name, e - ring->start, rd->status, len);
2563
2564 skb = skge_rx_get(skge, e, len);
2565 if (likely(skb)) {
2566 skb_put(skb, len);
2567 skb->protocol = eth_type_trans(skb, dev);
2568
2569 dev->last_rx = jiffies;
2570 netif_receive_skb(skb);
2571
2572 ++work_done;
2573 } else
2574 skge_rx_reuse(e, skge->rx_buf_size);
2575 }
2576 ring->to_clean = e;
2577
2578 /* restart receiver */
2579 wmb();
2580 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2581 CSR_START | CSR_IRQ_CL_F);
2582
2583 *budget -= work_done;
2584 dev->quota -= work_done;
2585
2586 if (work_done >= to_do)
2587 return 1; /* not done */
2588
2589 local_irq_disable();
2590 __netif_rx_complete(dev);
2591 hw->intr_mask |= portirqmask[skge->port];
2592 skge_write32(hw, B0_IMSK, hw->intr_mask);
2593 local_irq_enable();
2594 return 0;
2595 }
2596
2597 static inline void skge_tx_intr(struct net_device *dev)
2598 {
2599 struct skge_port *skge = netdev_priv(dev);
2600 struct skge_hw *hw = skge->hw;
2601 struct skge_ring *ring = &skge->tx_ring;
2602 struct skge_element *e;
2603
2604 spin_lock(&skge->tx_lock);
2605 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2606 struct skge_tx_desc *td = e->desc;
2607 u32 control;
2608
2609 rmb();
2610 control = td->control;
2611 if (control & BMU_OWN)
2612 break;
2613
2614 if (unlikely(netif_msg_tx_done(skge)))
2615 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2616 dev->name, e - ring->start, td->status);
2617
2618 skge_tx_free(hw, e);
2619 e->skb = NULL;
2620 ++skge->tx_avail;
2621 }
2622 ring->to_clean = e;
2623 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2624
2625 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2626 netif_wake_queue(dev);
2627
2628 spin_unlock(&skge->tx_lock);
2629 }
2630
2631 /* Parity errors seem to happen when Genesis is connected to a switch
2632 * with no other ports present. Heartbeat error??
2633 */
2634 static void skge_mac_parity(struct skge_hw *hw, int port)
2635 {
2636 struct net_device *dev = hw->dev[port];
2637
2638 if (dev) {
2639 struct skge_port *skge = netdev_priv(dev);
2640 ++skge->net_stats.tx_heartbeat_errors;
2641 }
2642
2643 if (hw->chip_id == CHIP_ID_GENESIS)
2644 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2645 MFF_CLR_PERR);
2646 else
2647 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2648 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2649 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2650 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2651 }
2652
2653 static void skge_pci_clear(struct skge_hw *hw)
2654 {
2655 u16 status;
2656
2657 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2658 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2659 pci_write_config_word(hw->pdev, PCI_STATUS,
2660 status | PCI_STATUS_ERROR_BITS);
2661 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2662 }
2663
2664 static void skge_mac_intr(struct skge_hw *hw, int port)
2665 {
2666 if (hw->chip_id == CHIP_ID_GENESIS)
2667 genesis_mac_intr(hw, port);
2668 else
2669 yukon_mac_intr(hw, port);
2670 }
2671
2672 /* Handle device specific framing and timeout interrupts */
2673 static void skge_error_irq(struct skge_hw *hw)
2674 {
2675 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2676
2677 if (hw->chip_id == CHIP_ID_GENESIS) {
2678 /* clear xmac errors */
2679 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2680 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2681 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2682 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2683 } else {
2684 /* Timestamp (unused) overflow */
2685 if (hwstatus & IS_IRQ_TIST_OV)
2686 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2687 }
2688
2689 if (hwstatus & IS_RAM_RD_PAR) {
2690 printk(KERN_ERR PFX "Ram read data parity error\n");
2691 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2692 }
2693
2694 if (hwstatus & IS_RAM_WR_PAR) {
2695 printk(KERN_ERR PFX "Ram write data parity error\n");
2696 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2697 }
2698
2699 if (hwstatus & IS_M1_PAR_ERR)
2700 skge_mac_parity(hw, 0);
2701
2702 if (hwstatus & IS_M2_PAR_ERR)
2703 skge_mac_parity(hw, 1);
2704
2705 if (hwstatus & IS_R1_PAR_ERR)
2706 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2707
2708 if (hwstatus & IS_R2_PAR_ERR)
2709 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2710
2711 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2712 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2713 hwstatus);
2714
2715 skge_pci_clear(hw);
2716
2717 /* if error still set then just ignore it */
2718 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2719 if (hwstatus & IS_IRQ_STAT) {
2720 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2721 hwstatus);
2722 hw->intr_mask &= ~IS_HW_ERR;
2723 }
2724 }
2725 }
2726
2727 /*
2728 * Interrrupt from PHY are handled in tasklet (soft irq)
2729 * because accessing phy registers requires spin wait which might
2730 * cause excess interrupt latency.
2731 */
2732 static void skge_extirq(unsigned long data)
2733 {
2734 struct skge_hw *hw = (struct skge_hw *) data;
2735 int port;
2736
2737 spin_lock(&hw->phy_lock);
2738 for (port = 0; port < 2; port++) {
2739 struct net_device *dev = hw->dev[port];
2740
2741 if (dev && netif_running(dev)) {
2742 struct skge_port *skge = netdev_priv(dev);
2743
2744 if (hw->chip_id != CHIP_ID_GENESIS)
2745 yukon_phy_intr(skge);
2746 else
2747 bcom_phy_intr(skge);
2748 }
2749 }
2750 spin_unlock(&hw->phy_lock);
2751
2752 local_irq_disable();
2753 hw->intr_mask |= IS_EXT_REG;
2754 skge_write32(hw, B0_IMSK, hw->intr_mask);
2755 local_irq_enable();
2756 }
2757
2758 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2759 {
2760 struct skge_hw *hw = dev_id;
2761 u32 status = skge_read32(hw, B0_SP_ISRC);
2762
2763 if (status == 0 || status == ~0) /* hotplug or shared irq */
2764 return IRQ_NONE;
2765
2766 status &= hw->intr_mask;
2767 if (status & IS_R1_F) {
2768 hw->intr_mask &= ~IS_R1_F;
2769 netif_rx_schedule(hw->dev[0]);
2770 }
2771
2772 if (status & IS_R2_F) {
2773 hw->intr_mask &= ~IS_R2_F;
2774 netif_rx_schedule(hw->dev[1]);
2775 }
2776
2777 if (status & IS_XA1_F)
2778 skge_tx_intr(hw->dev[0]);
2779
2780 if (status & IS_XA2_F)
2781 skge_tx_intr(hw->dev[1]);
2782
2783 if (status & IS_PA_TO_RX1) {
2784 struct skge_port *skge = netdev_priv(hw->dev[0]);
2785 ++skge->net_stats.rx_over_errors;
2786 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2787 }
2788
2789 if (status & IS_PA_TO_RX2) {
2790 struct skge_port *skge = netdev_priv(hw->dev[1]);
2791 ++skge->net_stats.rx_over_errors;
2792 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2793 }
2794
2795 if (status & IS_PA_TO_TX1)
2796 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2797
2798 if (status & IS_PA_TO_TX2)
2799 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2800
2801 if (status & IS_MAC1)
2802 skge_mac_intr(hw, 0);
2803
2804 if (status & IS_MAC2)
2805 skge_mac_intr(hw, 1);
2806
2807 if (status & IS_HW_ERR)
2808 skge_error_irq(hw);
2809
2810 if (status & IS_EXT_REG) {
2811 hw->intr_mask &= ~IS_EXT_REG;
2812 tasklet_schedule(&hw->ext_tasklet);
2813 }
2814
2815 skge_write32(hw, B0_IMSK, hw->intr_mask);
2816
2817 return IRQ_HANDLED;
2818 }
2819
2820 #ifdef CONFIG_NET_POLL_CONTROLLER
2821 static void skge_netpoll(struct net_device *dev)
2822 {
2823 struct skge_port *skge = netdev_priv(dev);
2824
2825 disable_irq(dev->irq);
2826 skge_intr(dev->irq, skge->hw, NULL);
2827 enable_irq(dev->irq);
2828 }
2829 #endif
2830
2831 static int skge_set_mac_address(struct net_device *dev, void *p)
2832 {
2833 struct skge_port *skge = netdev_priv(dev);
2834 struct sockaddr *addr = p;
2835 int err = 0;
2836
2837 if (!is_valid_ether_addr(addr->sa_data))
2838 return -EADDRNOTAVAIL;
2839
2840 skge_down(dev);
2841 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2842 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2843 dev->dev_addr, ETH_ALEN);
2844 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2845 dev->dev_addr, ETH_ALEN);
2846 if (dev->flags & IFF_UP)
2847 err = skge_up(dev);
2848 return err;
2849 }
2850
2851 static const struct {
2852 u8 id;
2853 const char *name;
2854 } skge_chips[] = {
2855 { CHIP_ID_GENESIS, "Genesis" },
2856 { CHIP_ID_YUKON, "Yukon" },
2857 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2858 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2859 };
2860
2861 static const char *skge_board_name(const struct skge_hw *hw)
2862 {
2863 int i;
2864 static char buf[16];
2865
2866 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2867 if (skge_chips[i].id == hw->chip_id)
2868 return skge_chips[i].name;
2869
2870 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2871 return buf;
2872 }
2873
2874
2875 /*
2876 * Setup the board data structure, but don't bring up
2877 * the port(s)
2878 */
2879 static int skge_reset(struct skge_hw *hw)
2880 {
2881 u16 ctst;
2882 u8 t8, mac_cfg, pmd_type, phy_type;
2883 int i;
2884
2885 ctst = skge_read16(hw, B0_CTST);
2886
2887 /* do a SW reset */
2888 skge_write8(hw, B0_CTST, CS_RST_SET);
2889 skge_write8(hw, B0_CTST, CS_RST_CLR);
2890
2891 /* clear PCI errors, if any */
2892 skge_pci_clear(hw);
2893
2894 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2895
2896 /* restore CLK_RUN bits (for Yukon-Lite) */
2897 skge_write16(hw, B0_CTST,
2898 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2899
2900 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2901 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2902 pmd_type = skge_read8(hw, B2_PMD_TYP);
2903 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2904
2905 switch (hw->chip_id) {
2906 case CHIP_ID_GENESIS:
2907 switch (phy_type) {
2908 case SK_PHY_BCOM:
2909 hw->phy_addr = PHY_ADDR_BCOM;
2910 break;
2911 default:
2912 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2913 pci_name(hw->pdev), phy_type);
2914 return -EOPNOTSUPP;
2915 }
2916 break;
2917
2918 case CHIP_ID_YUKON:
2919 case CHIP_ID_YUKON_LITE:
2920 case CHIP_ID_YUKON_LP:
2921 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2922 hw->copper = 1;
2923
2924 hw->phy_addr = PHY_ADDR_MARV;
2925 break;
2926
2927 default:
2928 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2929 pci_name(hw->pdev), hw->chip_id);
2930 return -EOPNOTSUPP;
2931 }
2932
2933 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2934 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2935 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2936
2937 /* read the adapters RAM size */
2938 t8 = skge_read8(hw, B2_E_0);
2939 if (hw->chip_id == CHIP_ID_GENESIS) {
2940 if (t8 == 3) {
2941 /* special case: 4 x 64k x 36, offset = 0x80000 */
2942 hw->ram_size = 0x100000;
2943 hw->ram_offset = 0x80000;
2944 } else
2945 hw->ram_size = t8 * 512;
2946 }
2947 else if (t8 == 0)
2948 hw->ram_size = 0x20000;
2949 else
2950 hw->ram_size = t8 * 4096;
2951
2952 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2953 if (hw->chip_id == CHIP_ID_GENESIS)
2954 genesis_init(hw);
2955 else {
2956 /* switch power to VCC (WA for VAUX problem) */
2957 skge_write8(hw, B0_POWER_CTRL,
2958 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2959 /* avoid boards with stuck Hardware error bits */
2960 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2961 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2962 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2963 hw->intr_mask &= ~IS_HW_ERR;
2964 }
2965
2966 for (i = 0; i < hw->ports; i++) {
2967 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2968 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2969 }
2970 }
2971
2972 /* turn off hardware timer (unused) */
2973 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2974 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2975 skge_write8(hw, B0_LED, LED_STAT_ON);
2976
2977 /* enable the Tx Arbiters */
2978 for (i = 0; i < hw->ports; i++)
2979 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2980
2981 /* Initialize ram interface */
2982 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2983
2984 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2985 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2986 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2987 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2988 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2989 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2990 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2991 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2992 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2993 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2994 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2995 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2996
2997 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2998
2999 /* Set interrupt moderation for Transmit only
3000 * Receive interrupts avoided by NAPI
3001 */
3002 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3003 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3004 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3005
3006 skge_write32(hw, B0_IMSK, hw->intr_mask);
3007
3008 spin_lock_bh(&hw->phy_lock);
3009 for (i = 0; i < hw->ports; i++) {
3010 if (hw->chip_id == CHIP_ID_GENESIS)
3011 genesis_reset(hw, i);
3012 else
3013 yukon_reset(hw, i);
3014 }
3015 spin_unlock_bh(&hw->phy_lock);
3016
3017 return 0;
3018 }
3019
3020 /* Initialize network device */
3021 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3022 int highmem)
3023 {
3024 struct skge_port *skge;
3025 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3026
3027 if (!dev) {
3028 printk(KERN_ERR "skge etherdev alloc failed");
3029 return NULL;
3030 }
3031
3032 SET_MODULE_OWNER(dev);
3033 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3034 dev->open = skge_up;
3035 dev->stop = skge_down;
3036 dev->hard_start_xmit = skge_xmit_frame;
3037 dev->get_stats = skge_get_stats;
3038 if (hw->chip_id == CHIP_ID_GENESIS)
3039 dev->set_multicast_list = genesis_set_multicast;
3040 else
3041 dev->set_multicast_list = yukon_set_multicast;
3042
3043 dev->set_mac_address = skge_set_mac_address;
3044 dev->change_mtu = skge_change_mtu;
3045 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3046 dev->tx_timeout = skge_tx_timeout;
3047 dev->watchdog_timeo = TX_WATCHDOG;
3048 dev->poll = skge_poll;
3049 dev->weight = NAPI_WEIGHT;
3050 #ifdef CONFIG_NET_POLL_CONTROLLER
3051 dev->poll_controller = skge_netpoll;
3052 #endif
3053 dev->irq = hw->pdev->irq;
3054 dev->features = NETIF_F_LLTX;
3055 if (highmem)
3056 dev->features |= NETIF_F_HIGHDMA;
3057
3058 skge = netdev_priv(dev);
3059 skge->netdev = dev;
3060 skge->hw = hw;
3061 skge->msg_enable = netif_msg_init(debug, default_msg);
3062 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3063 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3064
3065 /* Auto speed and flow control */
3066 skge->autoneg = AUTONEG_ENABLE;
3067 skge->flow_control = FLOW_MODE_SYMMETRIC;
3068 skge->duplex = -1;
3069 skge->speed = -1;
3070 skge->advertising = skge_supported_modes(hw);
3071
3072 hw->dev[port] = dev;
3073
3074 skge->port = port;
3075
3076 spin_lock_init(&skge->tx_lock);
3077
3078 if (hw->chip_id != CHIP_ID_GENESIS) {
3079 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3080 skge->rx_csum = 1;
3081 }
3082
3083 /* read the mac address */
3084 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3085
3086 /* device is off until link detection */
3087 netif_carrier_off(dev);
3088 netif_stop_queue(dev);
3089
3090 return dev;
3091 }
3092
3093 static void __devinit skge_show_addr(struct net_device *dev)
3094 {
3095 const struct skge_port *skge = netdev_priv(dev);
3096
3097 if (netif_msg_probe(skge))
3098 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3099 dev->name,
3100 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3101 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3102 }
3103
3104 static int __devinit skge_probe(struct pci_dev *pdev,
3105 const struct pci_device_id *ent)
3106 {
3107 struct net_device *dev, *dev1;
3108 struct skge_hw *hw;
3109 int err, using_dac = 0;
3110
3111 if ((err = pci_enable_device(pdev))) {
3112 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3113 pci_name(pdev));
3114 goto err_out;
3115 }
3116
3117 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3118 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3119 pci_name(pdev));
3120 goto err_out_disable_pdev;
3121 }
3122
3123 pci_set_master(pdev);
3124
3125 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3126 using_dac = 1;
3127 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3128 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3129 pci_name(pdev));
3130 goto err_out_free_regions;
3131 }
3132
3133 #ifdef __BIG_ENDIAN
3134 /* byte swap decriptors in hardware */
3135 {
3136 u32 reg;
3137
3138 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3139 reg |= PCI_REV_DESC;
3140 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3141 }
3142 #endif
3143
3144 err = -ENOMEM;
3145 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3146 if (!hw) {
3147 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3148 pci_name(pdev));
3149 goto err_out_free_regions;
3150 }
3151
3152 memset(hw, 0, sizeof(*hw));
3153 hw->pdev = pdev;
3154 spin_lock_init(&hw->phy_lock);
3155 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3156
3157 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3158 if (!hw->regs) {
3159 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3160 pci_name(pdev));
3161 goto err_out_free_hw;
3162 }
3163
3164 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3165 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3166 pci_name(pdev), pdev->irq);
3167 goto err_out_iounmap;
3168 }
3169 pci_set_drvdata(pdev, hw);
3170
3171 err = skge_reset(hw);
3172 if (err)
3173 goto err_out_free_irq;
3174
3175 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3176 pci_resource_start(pdev, 0), pdev->irq,
3177 skge_board_name(hw), hw->chip_rev);
3178
3179 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3180 goto err_out_led_off;
3181
3182 if ((err = register_netdev(dev))) {
3183 printk(KERN_ERR PFX "%s: cannot register net device\n",
3184 pci_name(pdev));
3185 goto err_out_free_netdev;
3186 }
3187
3188 skge_show_addr(dev);
3189
3190 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3191 if (register_netdev(dev1) == 0)
3192 skge_show_addr(dev1);
3193 else {
3194 /* Failure to register second port need not be fatal */
3195 printk(KERN_WARNING PFX "register of second port failed\n");
3196 hw->dev[1] = NULL;
3197 free_netdev(dev1);
3198 }
3199 }
3200
3201 return 0;
3202
3203 err_out_free_netdev:
3204 free_netdev(dev);
3205 err_out_led_off:
3206 skge_write16(hw, B0_LED, LED_STAT_OFF);
3207 err_out_free_irq:
3208 free_irq(pdev->irq, hw);
3209 err_out_iounmap:
3210 iounmap(hw->regs);
3211 err_out_free_hw:
3212 kfree(hw);
3213 err_out_free_regions:
3214 pci_release_regions(pdev);
3215 err_out_disable_pdev:
3216 pci_disable_device(pdev);
3217 pci_set_drvdata(pdev, NULL);
3218 err_out:
3219 return err;
3220 }
3221
3222 static void __devexit skge_remove(struct pci_dev *pdev)
3223 {
3224 struct skge_hw *hw = pci_get_drvdata(pdev);
3225 struct net_device *dev0, *dev1;
3226
3227 if (!hw)
3228 return;
3229
3230 if ((dev1 = hw->dev[1]))
3231 unregister_netdev(dev1);
3232 dev0 = hw->dev[0];
3233 unregister_netdev(dev0);
3234
3235 skge_write32(hw, B0_IMSK, 0);
3236 skge_write16(hw, B0_LED, LED_STAT_OFF);
3237 skge_pci_clear(hw);
3238 skge_write8(hw, B0_CTST, CS_RST_SET);
3239
3240 tasklet_kill(&hw->ext_tasklet);
3241
3242 free_irq(pdev->irq, hw);
3243 pci_release_regions(pdev);
3244 pci_disable_device(pdev);
3245 if (dev1)
3246 free_netdev(dev1);
3247 free_netdev(dev0);
3248
3249 iounmap(hw->regs);
3250 kfree(hw);
3251 pci_set_drvdata(pdev, NULL);
3252 }
3253
3254 #ifdef CONFIG_PM
3255 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3256 {
3257 struct skge_hw *hw = pci_get_drvdata(pdev);
3258 int i, wol = 0;
3259
3260 for (i = 0; i < 2; i++) {
3261 struct net_device *dev = hw->dev[i];
3262
3263 if (dev) {
3264 struct skge_port *skge = netdev_priv(dev);
3265 if (netif_running(dev)) {
3266 netif_carrier_off(dev);
3267 if (skge->wol)
3268 netif_stop_queue(dev);
3269 else
3270 skge_down(dev);
3271 }
3272 netif_device_detach(dev);
3273 wol |= skge->wol;
3274 }
3275 }
3276
3277 pci_save_state(pdev);
3278 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3279 pci_disable_device(pdev);
3280 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3281
3282 return 0;
3283 }
3284
3285 static int skge_resume(struct pci_dev *pdev)
3286 {
3287 struct skge_hw *hw = pci_get_drvdata(pdev);
3288 int i;
3289
3290 pci_set_power_state(pdev, PCI_D0);
3291 pci_restore_state(pdev);
3292 pci_enable_wake(pdev, PCI_D0, 0);
3293
3294 skge_reset(hw);
3295
3296 for (i = 0; i < 2; i++) {
3297 struct net_device *dev = hw->dev[i];
3298 if (dev) {
3299 netif_device_attach(dev);
3300 if (netif_running(dev))
3301 skge_up(dev);
3302 }
3303 }
3304 return 0;
3305 }
3306 #endif
3307
3308 static struct pci_driver skge_driver = {
3309 .name = DRV_NAME,
3310 .id_table = skge_id_table,
3311 .probe = skge_probe,
3312 .remove = __devexit_p(skge_remove),
3313 #ifdef CONFIG_PM
3314 .suspend = skge_suspend,
3315 .resume = skge_resume,
3316 #endif
3317 };
3318
3319 static int __init skge_init_module(void)
3320 {
3321 return pci_module_init(&skge_driver);
3322 }
3323
3324 static void __exit skge_cleanup_module(void)
3325 {
3326 pci_unregister_driver(&skge_driver);
3327 }
3328
3329 module_init(skge_init_module);
3330 module_exit(skge_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards