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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6
[linux-2.6/mini2440.git] / drivers / net / ucc_geth.h
blob2f8ee7c87efe944e6e788e861ee407ce97018a59
1 /*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 *
6 * Description:
7 * Internal header file for UCC Gigabit Ethernet unit routines.
8 *
9 * Changelog:
10 * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
11 * - Rearrange code and style fixes
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18 #ifndef __UCC_GETH_H__
19 #define __UCC_GETH_H__
20
21 #include <linux/kernel.h>
22 #include <linux/list.h>
23
24 #include <asm/immap_qe.h>
25 #include <asm/qe.h>
26
27 #include <asm/ucc.h>
28 #include <asm/ucc_fast.h>
29
30 #define DRV_DESC "QE UCC Gigabit Ethernet Controller"
31 #define DRV_NAME "ucc_geth"
32 #define DRV_VERSION "1.1"
33
34 #define NUM_TX_QUEUES 8
35 #define NUM_RX_QUEUES 8
36 #define NUM_BDS_IN_PREFETCHED_BDS 4
37 #define TX_IP_OFFSET_ENTRY_MAX 8
38 #define NUM_OF_PADDRS 4
39 #define ENET_INIT_PARAM_MAX_ENTRIES_RX 9
40 #define ENET_INIT_PARAM_MAX_ENTRIES_TX 8
41
42 struct ucc_geth {
43 struct ucc_fast uccf;
44 u8 res0[0x100 - sizeof(struct ucc_fast)];
45
46 u32 maccfg1; /* mac configuration reg. 1 */
47 u32 maccfg2; /* mac configuration reg. 2 */
48 u32 ipgifg; /* interframe gap reg. */
49 u32 hafdup; /* half-duplex reg. */
50 u8 res1[0x10];
51 u8 miimng[0x18]; /* MII management structure moved to _mii.h */
52 u32 ifctl; /* interface control reg */
53 u32 ifstat; /* interface statux reg */
54 u32 macstnaddr1; /* mac station address part 1 reg */
55 u32 macstnaddr2; /* mac station address part 2 reg */
56 u8 res2[0x8];
57 u32 uempr; /* UCC Ethernet Mac parameter reg */
58 u32 utbipar; /* UCC tbi address reg */
59 u16 uescr; /* UCC Ethernet statistics control reg */
60 u8 res3[0x180 - 0x15A];
61 u32 tx64; /* Total number of frames (including bad
62 frames) transmitted that were exactly of the
63 minimal length (64 for un tagged, 68 for
64 tagged, or with length exactly equal to the
65 parameter MINLength */
66 u32 tx127; /* Total number of frames (including bad
67 frames) transmitted that were between
68 MINLength (Including FCS length==4) and 127
69 octets */
70 u32 tx255; /* Total number of frames (including bad
71 frames) transmitted that were between 128
72 (Including FCS length==4) and 255 octets */
73 u32 rx64; /* Total number of frames received including
74 bad frames that were exactly of the mninimal
75 length (64 bytes) */
76 u32 rx127; /* Total number of frames (including bad
77 frames) received that were between MINLength
78 (Including FCS length==4) and 127 octets */
79 u32 rx255; /* Total number of frames (including bad
80 frames) received that were between 128
81 (Including FCS length==4) and 255 octets */
82 u32 txok; /* Total number of octets residing in frames
83 that where involved in succesfull
84 transmission */
85 u16 txcf; /* Total number of PAUSE control frames
86 transmitted by this MAC */
87 u8 res4[0x2];
88 u32 tmca; /* Total number of frames that were transmitted
89 succesfully with the group address bit set
90 that are not broadcast frames */
91 u32 tbca; /* Total number of frames transmitted
92 succesfully that had destination address
93 field equal to the broadcast address */
94 u32 rxfok; /* Total number of frames received OK */
95 u32 rxbok; /* Total number of octets received OK */
96 u32 rbyt; /* Total number of octets received including
97 octets in bad frames. Must be implemented in
98 HW because it includes octets in frames that
99 never even reach the UCC */
100 u32 rmca; /* Total number of frames that were received
101 succesfully with the group address bit set
102 that are not broadcast frames */
103 u32 rbca; /* Total number of frames received succesfully
104 that had destination address equal to the
105 broadcast address */
106 u32 scar; /* Statistics carry register */
107 u32 scam; /* Statistics caryy mask register */
108 u8 res5[0x200 - 0x1c4];
109 } __attribute__ ((packed));
110
111 /* UCC GETH TEMODR Register */
112 #define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics
113 */
114 #define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */
115 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4
116 checksums */
117 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance
118 optimization
119 enhancement (mode1) */
120 #define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics
121 */
122 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
123 shift */
124
125 /* UCC GETH TEMODR Register */
126 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx
127 statistics */
128 #define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable
129 extended
130 features */
131 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation
132 tagged << shift */
133 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
134 tagged << shift */
135 #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift
136 */
137 #define REMODER_RMON_STATISTICS 0x00001000 /* enable rx
138 statistics */
139 #define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended
140 filtering
141 vs.
142 mpc82xx-like
143 filtering */
144 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<
145 shift */
146 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable
147 dynamic max
148 frame length
149 */
150 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable
151 dynamic min
152 frame length
153 */
154 #define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4
155 checksums */
156 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip
157 address to
158 4-byte
159 boundary */
160
161 /* UCC GETH Event Register */
162 #define UCCE_TXB (UCC_GETH_UCCE_TXB7 | UCC_GETH_UCCE_TXB6 | \
163 UCC_GETH_UCCE_TXB5 | UCC_GETH_UCCE_TXB4 | \
164 UCC_GETH_UCCE_TXB3 | UCC_GETH_UCCE_TXB2 | \
165 UCC_GETH_UCCE_TXB1 | UCC_GETH_UCCE_TXB0)
166
167 #define UCCE_RXB (UCC_GETH_UCCE_RXB7 | UCC_GETH_UCCE_RXB6 | \
168 UCC_GETH_UCCE_RXB5 | UCC_GETH_UCCE_RXB4 | \
169 UCC_GETH_UCCE_RXB3 | UCC_GETH_UCCE_RXB2 | \
170 UCC_GETH_UCCE_RXB1 | UCC_GETH_UCCE_RXB0)
171
172 #define UCCE_RXF (UCC_GETH_UCCE_RXF7 | UCC_GETH_UCCE_RXF6 | \
173 UCC_GETH_UCCE_RXF5 | UCC_GETH_UCCE_RXF4 | \
174 UCC_GETH_UCCE_RXF3 | UCC_GETH_UCCE_RXF2 | \
175 UCC_GETH_UCCE_RXF1 | UCC_GETH_UCCE_RXF0)
176
177 #define UCCE_OTHER (UCC_GETH_UCCE_SCAR | UCC_GETH_UCCE_GRA | \
178 UCC_GETH_UCCE_CBPR | UCC_GETH_UCCE_BSY | \
179 UCC_GETH_UCCE_RXC | UCC_GETH_UCCE_TXC | UCC_GETH_UCCE_TXE)
180
181 #define UCCE_RX_EVENTS (UCCE_RXF | UCC_GETH_UCCE_BSY)
182 #define UCCE_TX_EVENTS (UCCE_TXB | UCC_GETH_UCCE_TXE)
183
184 /* TBI defines */
185 #define ENET_TBI_MII_CR 0x00 /* Control */
186 #define ENET_TBI_MII_SR 0x01 /* Status */
187 #define ENET_TBI_MII_ANA 0x04 /* AN advertisement */
188 #define ENET_TBI_MII_ANLPBPA 0x05 /* AN link partner base page ability */
189 #define ENET_TBI_MII_ANEX 0x06 /* AN expansion */
190 #define ENET_TBI_MII_ANNPT 0x07 /* AN next page transmit */
191 #define ENET_TBI_MII_ANLPANP 0x08 /* AN link partner ability next page */
192 #define ENET_TBI_MII_EXST 0x0F /* Extended status */
193 #define ENET_TBI_MII_JD 0x10 /* Jitter diagnostics */
194 #define ENET_TBI_MII_TBICON 0x11 /* TBI control */
195
196 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
197 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
198 Rx */
199 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control
200 Tx */
201 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable
202 synchronized
203 to Rx stream
204 */
205 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
206 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable
207 synchronized
208 to Tx stream
209 */
210 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
211
212 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
213 #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble
214 Length <<
215 shift */
216 #define MACCFG2_PREL_MASK 0x0000f000 /* Preamble
217 Length mask */
218 #define MACCFG2_SRP 0x00000080 /* Soft Receive
219 Preamble */
220 #define MACCFG2_STP 0x00000040 /* Soft
221 Transmit
222 Preamble */
223 #define MACCFG2_RESERVED_1 0x00000020 /* Reserved -
224 must be set
225 to 1 */
226 #define MACCFG2_LC 0x00000010 /* Length Check
227 */
228 #define MACCFG2_MPE 0x00000008 /* Magic packet
229 detect */
230 #define MACCFG2_FDX 0x00000001 /* Full Duplex */
231 #define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex
232 mask */
233 #define MACCFG2_PAD_CRC 0x00000004
234 #define MACCFG2_CRC_EN 0x00000002
235 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither
236 Padding
237 short frames
238 nor CRC */
239 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC
240 only */
241 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
242 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode
243 (MII/RMII/RGMII
244 10/100bps) */
245 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode
246 (GMII/TBI/RTB/RGMII
247 1000bps ) */
248 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask
249 covering all
250 relevant
251 bits */
252
253 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
254 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non
255 back-to-back
256 inter frame
257 gap part 1.
258 << shift */
259 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non
260 back-to-back
261 inter frame
262 gap part 2.
263 << shift */
264 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG
265 Enforcement
266 << shift */
267 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back
268 inter frame
269 gap << shift
270 */
271 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back
272 inter frame gap part
273 1. max val */
274 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back
275 inter frame gap part
276 2. max val */
277 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG
278 Enforcement max val */
279 #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter
280 frame gap max val */
281 #define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000
282 #define IPGIFG_NBTB_IPG_MASK 0x007F0000
283 #define IPGIFG_MIN_IFG_MASK 0x0000FF00
284 #define IPGIFG_BTB_IPG_MASK 0x0000007F
285
286 /* UCC GETH HAFDUP (Half Duplex Register) */
287 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate
288 Binary
289 Exponential
290 Backoff
291 Truncation
292 << shift */
293 #define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary
294 Exponential Backoff
295 Truncation max val */
296 #define HALFDUP_ALT_BEB 0x00080000 /* Alternate
297 Binary
298 Exponential
299 Backoff */
300 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back
301 pressure no
302 backoff */
303 #define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */
304 #define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive
305 Defer */
306 #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum
307 Retransmission
308 << shift */
309 #define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum
310 Retransmission max
311 val */
312 #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision
313 Window <<
314 shift */
315 #define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max
316 val */
317 #define HALFDUP_ALT_BEB_TR_MASK 0x00F00000
318 #define HALFDUP_RETRANS_MASK 0x0000F000
319 #define HALFDUP_COL_WINDOW_MASK 0x0000003F
320
321 /* UCC GETH UCCS (Ethernet Status Register) */
322 #define UCCS_BPR 0x02 /* Back pressure (in
323 half duplex mode) */
324 #define UCCS_PAU 0x02 /* Pause state (in full
325 duplex mode) */
326 #define UCCS_MPD 0x01 /* Magic Packet
327 Detected */
328
329 /* UCC GETH IFSTAT (Interface Status Register) */
330 #define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive
331 transmission
332 defer */
333
334 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
335 #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station
336 address 6th
337 octet <<
338 shift */
339 #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station
340 address 5th
341 octet <<
342 shift */
343 #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station
344 address 4th
345 octet <<
346 shift */
347 #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station
348 address 3rd
349 octet <<
350 shift */
351
352 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
353 #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station
354 address 2nd
355 octet <<
356 shift */
357 #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station
358 address 1st
359 octet <<
360 shift */
361
362 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
363 #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time
364 value <<
365 shift */
366 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended
367 pause time
368 value <<
369 shift */
370
371 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
372 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address
373 << shift */
374 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address
375 mask */
376
377 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
378 #define UESCR_AUTOZ 0x8000 /* Automatically zero
379 addressed
380 statistical counter
381 values */
382 #define UESCR_CLRCNT 0x4000 /* Clear all statistics
383 counters */
384 #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max
385 Coalescing
386 Value <<
387 shift */
388 #define UESCR_SCOV_SHIFT (15 - 15) /* Status
389 Coalescing
390 Value <<
391 shift */
392
393 /* UCC GETH UDSR (Data Synchronization Register) */
394 #define UDSR_MAGIC 0x067E
395
396 struct ucc_geth_thread_data_tx {
397 u8 res0[104];
398 } __attribute__ ((packed));
399
400 struct ucc_geth_thread_data_rx {
401 u8 res0[40];
402 } __attribute__ ((packed));
403
404 /* Send Queue Queue-Descriptor */
405 struct ucc_geth_send_queue_qd {
406 u32 bd_ring_base; /* pointer to BD ring base address */
407 u8 res0[0x8];
408 u32 last_bd_completed_address;/* initialize to last entry in BD ring */
409 u8 res1[0x30];
410 } __attribute__ ((packed));
411
412 struct ucc_geth_send_queue_mem_region {
413 struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
414 } __attribute__ ((packed));
415
416 struct ucc_geth_thread_tx_pram {
417 u8 res0[64];
418 } __attribute__ ((packed));
419
420 struct ucc_geth_thread_rx_pram {
421 u8 res0[128];
422 } __attribute__ ((packed));
423
424 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64
425 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64
426 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96
427
428 struct ucc_geth_scheduler {
429 u16 cpucount0; /* CPU packet counter */
430 u16 cpucount1; /* CPU packet counter */
431 u16 cecount0; /* QE packet counter */
432 u16 cecount1; /* QE packet counter */
433 u16 cpucount2; /* CPU packet counter */
434 u16 cpucount3; /* CPU packet counter */
435 u16 cecount2; /* QE packet counter */
436 u16 cecount3; /* QE packet counter */
437 u16 cpucount4; /* CPU packet counter */
438 u16 cpucount5; /* CPU packet counter */
439 u16 cecount4; /* QE packet counter */
440 u16 cecount5; /* QE packet counter */
441 u16 cpucount6; /* CPU packet counter */
442 u16 cpucount7; /* CPU packet counter */
443 u16 cecount6; /* QE packet counter */
444 u16 cecount7; /* QE packet counter */
445 u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */
446 u32 rtsrshadow; /* temporary variable handled by QE */
447 u32 time; /* temporary variable handled by QE */
448 u32 ttl; /* temporary variable handled by QE */
449 u32 mblinterval; /* max burst length interval */
450 u16 nortsrbytetime; /* normalized value of byte time in tsr units */
451 u8 fracsiz; /* radix 2 log value of denom. of
452 NorTSRByteTime */
453 u8 res0[1];
454 u8 strictpriorityq; /* Strict Priority Mask register */
455 u8 txasap; /* Transmit ASAP register */
456 u8 extrabw; /* Extra BandWidth register */
457 u8 oldwfqmask; /* temporary variable handled by QE */
458 u8 weightfactor[NUM_TX_QUEUES];
459 /**< weight factor for queues */
460 u32 minw; /* temporary variable handled by QE */
461 u8 res1[0x70 - 0x64];
462 } __attribute__ ((packed));
463
464 struct ucc_geth_tx_firmware_statistics_pram {
465 u32 sicoltx; /* single collision */
466 u32 mulcoltx; /* multiple collision */
467 u32 latecoltxfr; /* late collision */
468 u32 frabortduecol; /* frames aborted due to transmit collision */
469 u32 frlostinmactxer; /* frames lost due to internal MAC error
470 transmission that are not counted on any
471 other counter */
472 u32 carriersenseertx; /* carrier sense error */
473 u32 frtxok; /* frames transmitted OK */
474 u32 txfrexcessivedefer; /* frames with defferal time greater than
475 specified threshold */
476 u32 txpkts256; /* total packets (including bad) between 256
477 and 511 octets */
478 u32 txpkts512; /* total packets (including bad) between 512
479 and 1023 octets */
480 u32 txpkts1024; /* total packets (including bad) between 1024
481 and 1518 octets */
482 u32 txpktsjumbo; /* total packets (including bad) between 1024
483 and MAXLength octets */
484 } __attribute__ ((packed));
485
486 struct ucc_geth_rx_firmware_statistics_pram {
487 u32 frrxfcser; /* frames with crc error */
488 u32 fraligner; /* frames with alignment error */
489 u32 inrangelenrxer; /* in range length error */
490 u32 outrangelenrxer; /* out of range length error */
491 u32 frtoolong; /* frame too long */
492 u32 runt; /* runt */
493 u32 verylongevent; /* very long event */
494 u32 symbolerror; /* symbol error */
495 u32 dropbsy; /* drop because of BD not ready */
496 u8 res0[0x8];
497 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
498 or type mismatch) */
499 u32 underpkts; /* total frames less than 64 octets */
500 u32 pkts256; /* total frames (including bad) between 256 and
501 511 octets */
502 u32 pkts512; /* total frames (including bad) between 512 and
503 1023 octets */
504 u32 pkts1024; /* total frames (including bad) between 1024
505 and 1518 octets */
506 u32 pktsjumbo; /* total frames (including bad) between 1024
507 and MAXLength octets */
508 u32 frlossinmacer; /* frames lost because of internal MAC error
509 that is not counted in any other counter */
510 u32 pausefr; /* pause frames */
511 u8 res1[0x4];
512 u32 removevlan; /* total frames that had their VLAN tag removed
513 */
514 u32 replacevlan; /* total frames that had their VLAN tag
515 replaced */
516 u32 insertvlan; /* total frames that had their VLAN tag
517 inserted */
518 } __attribute__ ((packed));
519
520 struct ucc_geth_rx_interrupt_coalescing_entry {
521 u32 interruptcoalescingmaxvalue; /* interrupt coalescing max
522 value */
523 u32 interruptcoalescingcounter; /* interrupt coalescing counter,
524 initialize to
525 interruptcoalescingmaxvalue */
526 } __attribute__ ((packed));
527
528 struct ucc_geth_rx_interrupt_coalescing_table {
529 struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
530 /**< interrupt coalescing entry */
531 } __attribute__ ((packed));
532
533 struct ucc_geth_rx_prefetched_bds {
534 struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
535 } __attribute__ ((packed));
536
537 struct ucc_geth_rx_bd_queues_entry {
538 u32 bdbaseptr; /* BD base pointer */
539 u32 bdptr; /* BD pointer */
540 u32 externalbdbaseptr; /* external BD base pointer */
541 u32 externalbdptr; /* external BD pointer */
542 } __attribute__ ((packed));
543
544 struct ucc_geth_tx_global_pram {
545 u16 temoder;
546 u8 res0[0x38 - 0x02];
547 u32 sqptr; /* a base pointer to send queue memory region */
548 u32 schedulerbasepointer; /* a base pointer to scheduler memory
549 region */
550 u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */
551 u32 tstate; /* tx internal state. High byte contains
552 function code */
553 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
554 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
555 u32 tqptr; /* a base pointer to the Tx Queues Memory
556 Region */
557 u8 res2[0x80 - 0x74];
558 } __attribute__ ((packed));
559
560 /* structure representing Extended Filtering Global Parameters in PRAM */
561 struct ucc_geth_exf_global_pram {
562 u32 l2pcdptr; /* individual address filter, high */
563 u8 res0[0x10 - 0x04];
564 } __attribute__ ((packed));
565
566 struct ucc_geth_rx_global_pram {
567 u32 remoder; /* ethernet mode reg. */
568 u32 rqptr; /* base pointer to the Rx Queues Memory Region*/
569 u32 res0[0x1];
570 u8 res1[0x20 - 0xC];
571 u16 typeorlen; /* cutoff point less than which, type/len field
572 is considered length */
573 u8 res2[0x1];
574 u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/
575 u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */
576 u8 res3[0x30 - 0x28];
577 u32 intcoalescingptr; /* Interrupt coalescing table pointer */
578 u8 res4[0x36 - 0x34];
579 u8 rstate; /* rx internal state. High byte contains
580 function code */
581 u8 res5[0x46 - 0x37];
582 u16 mrblr; /* max receive buffer length reg. */
583 u32 rbdqptr; /* base pointer to RxBD parameter table
584 description */
585 u16 mflr; /* max frame length reg. */
586 u16 minflr; /* min frame length reg. */
587 u16 maxd1; /* max dma1 length reg. */
588 u16 maxd2; /* max dma2 length reg. */
589 u32 ecamptr; /* external CAM address */
590 u32 l2qt; /* VLAN priority mapping table. */
591 u32 l3qt[0x8]; /* IP priority mapping table. */
592 u16 vlantype; /* vlan type */
593 u16 vlantci; /* default vlan tci */
594 u8 addressfiltering[64]; /* address filtering data structure */
595 u32 exfGlobalParam; /* base address for extended filtering global
596 parameters */
597 u8 res6[0x100 - 0xC4]; /* Initialize to zero */
598 } __attribute__ ((packed));
599
600 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
601
602 /* structure representing InitEnet command */
603 struct ucc_geth_init_pram {
604 u8 resinit1;
605 u8 resinit2;
606 u8 resinit3;
607 u8 resinit4;
608 u16 resinit5;
609 u8 res1[0x1];
610 u8 largestexternallookupkeysize;
611 u32 rgftgfrxglobal;
612 u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */
613 u8 res2[0x38 - 0x30];
614 u32 txglobal; /* tx global */
615 u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */
616 u8 res3[0x1];
617 } __attribute__ ((packed));
618
619 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
620 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
621
622 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f
623 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
624 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000
625 #define ENET_INIT_PARAM_SNUM_SHIFT 24
626
627 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06
628 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30
629 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff
630 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00
631 #define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400
632
633 /* structure representing 82xx Address Filtering Enet Address in PRAM */
634 struct ucc_geth_82xx_enet_address {
635 u8 res1[0x2];
636 u16 h; /* address (MSB) */
637 u16 m; /* address */
638 u16 l; /* address (LSB) */
639 } __attribute__ ((packed));
640
641 /* structure representing 82xx Address Filtering PRAM */
642 struct ucc_geth_82xx_address_filtering_pram {
643 u32 iaddr_h; /* individual address filter, high */
644 u32 iaddr_l; /* individual address filter, low */
645 u32 gaddr_h; /* group address filter, high */
646 u32 gaddr_l; /* group address filter, low */
647 struct ucc_geth_82xx_enet_address __iomem taddr;
648 struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
649 u8 res0[0x40 - 0x38];
650 } __attribute__ ((packed));
651
652 /* GETH Tx firmware statistics structure, used when calling
653 UCC_GETH_GetStatistics. */
654 struct ucc_geth_tx_firmware_statistics {
655 u32 sicoltx; /* single collision */
656 u32 mulcoltx; /* multiple collision */
657 u32 latecoltxfr; /* late collision */
658 u32 frabortduecol; /* frames aborted due to transmit collision */
659 u32 frlostinmactxer; /* frames lost due to internal MAC error
660 transmission that are not counted on any
661 other counter */
662 u32 carriersenseertx; /* carrier sense error */
663 u32 frtxok; /* frames transmitted OK */
664 u32 txfrexcessivedefer; /* frames with defferal time greater than
665 specified threshold */
666 u32 txpkts256; /* total packets (including bad) between 256
667 and 511 octets */
668 u32 txpkts512; /* total packets (including bad) between 512
669 and 1023 octets */
670 u32 txpkts1024; /* total packets (including bad) between 1024
671 and 1518 octets */
672 u32 txpktsjumbo; /* total packets (including bad) between 1024
673 and MAXLength octets */
674 } __attribute__ ((packed));
675
676 /* GETH Rx firmware statistics structure, used when calling
677 UCC_GETH_GetStatistics. */
678 struct ucc_geth_rx_firmware_statistics {
679 u32 frrxfcser; /* frames with crc error */
680 u32 fraligner; /* frames with alignment error */
681 u32 inrangelenrxer; /* in range length error */
682 u32 outrangelenrxer; /* out of range length error */
683 u32 frtoolong; /* frame too long */
684 u32 runt; /* runt */
685 u32 verylongevent; /* very long event */
686 u32 symbolerror; /* symbol error */
687 u32 dropbsy; /* drop because of BD not ready */
688 u8 res0[0x8];
689 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
690 or type mismatch) */
691 u32 underpkts; /* total frames less than 64 octets */
692 u32 pkts256; /* total frames (including bad) between 256 and
693 511 octets */
694 u32 pkts512; /* total frames (including bad) between 512 and
695 1023 octets */
696 u32 pkts1024; /* total frames (including bad) between 1024
697 and 1518 octets */
698 u32 pktsjumbo; /* total frames (including bad) between 1024
699 and MAXLength octets */
700 u32 frlossinmacer; /* frames lost because of internal MAC error
701 that is not counted in any other counter */
702 u32 pausefr; /* pause frames */
703 u8 res1[0x4];
704 u32 removevlan; /* total frames that had their VLAN tag removed
705 */
706 u32 replacevlan; /* total frames that had their VLAN tag
707 replaced */
708 u32 insertvlan; /* total frames that had their VLAN tag
709 inserted */
710 } __attribute__ ((packed));
711
712 /* GETH hardware statistics structure, used when calling
713 UCC_GETH_GetStatistics. */
714 struct ucc_geth_hardware_statistics {
715 u32 tx64; /* Total number of frames (including bad
716 frames) transmitted that were exactly of the
717 minimal length (64 for un tagged, 68 for
718 tagged, or with length exactly equal to the
719 parameter MINLength */
720 u32 tx127; /* Total number of frames (including bad
721 frames) transmitted that were between
722 MINLength (Including FCS length==4) and 127
723 octets */
724 u32 tx255; /* Total number of frames (including bad
725 frames) transmitted that were between 128
726 (Including FCS length==4) and 255 octets */
727 u32 rx64; /* Total number of frames received including
728 bad frames that were exactly of the mninimal
729 length (64 bytes) */
730 u32 rx127; /* Total number of frames (including bad
731 frames) received that were between MINLength
732 (Including FCS length==4) and 127 octets */
733 u32 rx255; /* Total number of frames (including bad
734 frames) received that were between 128
735 (Including FCS length==4) and 255 octets */
736 u32 txok; /* Total number of octets residing in frames
737 that where involved in succesfull
738 transmission */
739 u16 txcf; /* Total number of PAUSE control frames
740 transmitted by this MAC */
741 u32 tmca; /* Total number of frames that were transmitted
742 succesfully with the group address bit set
743 that are not broadcast frames */
744 u32 tbca; /* Total number of frames transmitted
745 succesfully that had destination address
746 field equal to the broadcast address */
747 u32 rxfok; /* Total number of frames received OK */
748 u32 rxbok; /* Total number of octets received OK */
749 u32 rbyt; /* Total number of octets received including
750 octets in bad frames. Must be implemented in
751 HW because it includes octets in frames that
752 never even reach the UCC */
753 u32 rmca; /* Total number of frames that were received
754 succesfully with the group address bit set
755 that are not broadcast frames */
756 u32 rbca; /* Total number of frames received succesfully
757 that had destination address equal to the
758 broadcast address */
759 } __attribute__ ((packed));
760
761 /* UCC GETH Tx errors returned via TxConf callback */
762 #define TX_ERRORS_DEF 0x0200
763 #define TX_ERRORS_EXDEF 0x0100
764 #define TX_ERRORS_LC 0x0080
765 #define TX_ERRORS_RL 0x0040
766 #define TX_ERRORS_RC_MASK 0x003C
767 #define TX_ERRORS_RC_SHIFT 2
768 #define TX_ERRORS_UN 0x0002
769 #define TX_ERRORS_CSL 0x0001
770
771 /* UCC GETH Rx errors returned via RxStore callback */
772 #define RX_ERRORS_CMR 0x0200
773 #define RX_ERRORS_M 0x0100
774 #define RX_ERRORS_BC 0x0080
775 #define RX_ERRORS_MC 0x0040
776
777 /* Transmit BD. These are in addition to values defined in uccf. */
778 #define T_VID 0x003c0000 /* insert VLAN id index mask. */
779 #define T_DEF (((u32) TX_ERRORS_DEF ) << 16)
780 #define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16)
781 #define T_LC (((u32) TX_ERRORS_LC ) << 16)
782 #define T_RL (((u32) TX_ERRORS_RL ) << 16)
783 #define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16)
784 #define T_UN (((u32) TX_ERRORS_UN ) << 16)
785 #define T_CSL (((u32) TX_ERRORS_CSL ) << 16)
786 #define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
787 | T_UN | T_CSL) /* transmit errors to report */
788
789 /* Receive BD. These are in addition to values defined in uccf. */
790 #define R_LG 0x00200000 /* Frame length violation. */
791 #define R_NO 0x00100000 /* Non-octet aligned frame. */
792 #define R_SH 0x00080000 /* Short frame. */
793 #define R_CR 0x00040000 /* CRC error. */
794 #define R_OV 0x00020000 /* Overrun. */
795 #define R_IPCH 0x00010000 /* IP checksum check failed. */
796 #define R_CMR (((u32) RX_ERRORS_CMR ) << 16)
797 #define R_M (((u32) RX_ERRORS_M ) << 16)
798 #define R_BC (((u32) RX_ERRORS_BC ) << 16)
799 #define R_MC (((u32) RX_ERRORS_MC ) << 16)
800 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to
801 report */
802 #define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
803 R_OV | R_IPCH) /* receive errors to discard */
804
805 /* Alignments */
806 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256
807 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128
808 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128
809 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64
810 #define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values
811 based on num of
812 threads, but always
813 using the maximum is
814 easier */
815 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
816 #define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */
817 #define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
818 #define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
819 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
820 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
821 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
822 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This
823 is a
824 guess
825 */
826 #define UCC_GETH_RX_BD_RING_ALIGNMENT 32
827 #define UCC_GETH_TX_BD_RING_ALIGNMENT 32
828 #define UCC_GETH_MRBLR_ALIGNMENT 128
829 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4
830 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
831 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64
832
833 #define UCC_GETH_TAD_EF 0x80
834 #define UCC_GETH_TAD_V 0x40
835 #define UCC_GETH_TAD_REJ 0x20
836 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2
837 #define UCC_GETH_TAD_VTAG_OP_SHIFT 6
838 #define UCC_GETH_TAD_V_NON_VTAG_OP 0x20
839 #define UCC_GETH_TAD_RQOS_SHIFT 0
840 #define UCC_GETH_TAD_V_PRIORITY_SHIFT 5
841 #define UCC_GETH_TAD_CFI 0x10
842
843 #define UCC_GETH_VLAN_PRIORITY_MAX 8
844 #define UCC_GETH_IP_PRIORITY_MAX 64
845 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8
846 #define UCC_GETH_RX_BD_RING_SIZE_MIN 8
847 #define UCC_GETH_TX_BD_RING_SIZE_MIN 2
848 #define UCC_GETH_BD_RING_SIZE_MAX 0xffff
849
850 #define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD
851
852 /* Driver definitions */
853 #define TX_BD_RING_LEN 0x10
854 #define RX_BD_RING_LEN 0x10
855 #define UCC_GETH_DEV_WEIGHT TX_BD_RING_LEN
856
857 #define TX_RING_MOD_MASK(size) (size-1)
858 #define RX_RING_MOD_MASK(size) (size-1)
859
860 #define ENET_NUM_OCTETS_PER_ADDRESS 6
861 #define ENET_GROUP_ADDR 0x01 /* Group address mask
862 for ethernet
863 addresses */
864
865 #define TX_TIMEOUT (1*HZ)
866 #define SKB_ALLOC_TIMEOUT 100000
867 #define PHY_INIT_TIMEOUT 100000
868 #define PHY_CHANGE_TIME 2
869
870 /* Fast Ethernet (10/100 Mbps) */
871 #define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size
872 */
873 #define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */
874 #define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */
875 #define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size
876 */
877 #define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
878 #define UCC_GETH_UTFTT_INIT 128
879 /* Gigabit Ethernet (1000 Mbps) */
880 #define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual
881 FIFO size */
882 #define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
883 #define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
884 #define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual
885 FIFO size */
886 #define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */
887 #define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */
888
889 #define UCC_GETH_REMODER_INIT 0 /* bits that must be
890 set */
891 #define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */
892
893 /* Initial value for UPSMR */
894 #define UCC_GETH_UPSMR_INIT UCC_GETH_UPSMR_RES1
895
896 #define UCC_GETH_MACCFG1_INIT 0
897 #define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)
898
899 /* Ethernet Address Type. */
900 enum enet_addr_type {
901 ENET_ADDR_TYPE_INDIVIDUAL,
902 ENET_ADDR_TYPE_GROUP,
903 ENET_ADDR_TYPE_BROADCAST
904 };
905
906 /* UCC GETH 82xx Ethernet Address Recognition Location */
907 enum ucc_geth_enet_address_recognition_location {
908 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
909 address */
910 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
911 station
912 address
913 paddr1 */
914 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional
915 station
916 address
917 paddr2 */
918 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional
919 station
920 address
921 paddr3 */
922 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional
923 station
924 address
925 paddr4 */
926 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */
927 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
928 hash */
929 };
930
931 /* UCC GETH vlan operation tagged */
932 enum ucc_geth_vlan_operation_tagged {
933 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
934 UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
935 = 0x1, /* Tagged - replace vid portion of q tag */
936 UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
937 = 0x2, /* Tagged - if vid0 replace vid with default value */
938 UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
939 = 0x3 /* Tagged - extract q tag from frame */
940 };
941
942 /* UCC GETH vlan operation non-tagged */
943 enum ucc_geth_vlan_operation_non_tagged {
944 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
945 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
946 q tag insert
947 */
948 };
949
950 /* UCC GETH Rx Quality of Service Mode */
951 enum ucc_geth_qos_mode {
952 UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */
953 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue
954 determined
955 by L2
956 criteria */
957 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue
958 determined
959 by L3
960 criteria */
961 };
962
963 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
964 for combined functionality */
965 enum ucc_geth_statistics_gathering_mode {
966 UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No
967 statistics
968 gathering */
969 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
970 hardware
971 statistics
972 gathering
973 */
974 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
975 firmware
976 tx
977 statistics
978 gathering
979 */
980 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
981 firmware
982 rx
983 statistics
984 gathering
985 */
986 };
987
988 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
989 enum ucc_geth_maccfg2_pad_and_crc_mode {
990 UCC_GETH_PAD_AND_CRC_MODE_NONE
991 = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding
992 short frames
993 nor CRC */
994 UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
995 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append
996 CRC only */
997 UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
998 MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
999 };
1000
1001 /* UCC GETH upsmr Flow Control Mode */
1002 enum ucc_geth_flow_control_mode {
1003 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic
1004 flow control
1005 */
1006 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1007 = 0x00004000 /* Send pause frame when RxFIFO reaches its
1008 emergency threshold */
1009 };
1010
1011 /* UCC GETH number of threads */
1012 enum ucc_geth_num_of_threads {
1013 UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */
1014 UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */
1015 UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */
1016 UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */
1017 UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1018 };
1019
1020 /* UCC GETH number of station addresses */
1021 enum ucc_geth_num_of_station_addresses {
1022 UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */
1023 UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */
1024 };
1025
1026 /* UCC GETH 82xx Ethernet Address Container */
1027 struct enet_addr_container {
1028 u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
1029 enum ucc_geth_enet_address_recognition_location location; /* location in
1030 82xx address
1031 recognition
1032 hardware */
1033 struct list_head node;
1034 };
1035
1036 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1037
1038 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1039 struct ucc_geth_tad_params {
1040 int rx_non_dynamic_extended_features_mode;
1041 int reject_frame;
1042 enum ucc_geth_vlan_operation_tagged vtag_op;
1043 enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1044 enum ucc_geth_qos_mode rqos;
1045 u8 vpri;
1046 u16 vid;
1047 };
1048
1049 /* GETH protocol initialization structure */
1050 struct ucc_geth_info {
1051 struct ucc_fast_info uf_info;
1052 u8 numQueuesTx;
1053 u8 numQueuesRx;
1054 int ipCheckSumCheck;
1055 int ipCheckSumGenerate;
1056 int rxExtendedFiltering;
1057 u32 extendedFilteringChainPointer;
1058 u16 typeorlen;
1059 int dynamicMaxFrameLength;
1060 int dynamicMinFrameLength;
1061 u8 nonBackToBackIfgPart1;
1062 u8 nonBackToBackIfgPart2;
1063 u8 miminumInterFrameGapEnforcement;
1064 u8 backToBackInterFrameGap;
1065 int ipAddressAlignment;
1066 int lengthCheckRx;
1067 u32 mblinterval;
1068 u16 nortsrbytetime;
1069 u8 fracsiz;
1070 u8 strictpriorityq;
1071 u8 txasap;
1072 u8 extrabw;
1073 int miiPreambleSupress;
1074 u8 altBebTruncation;
1075 int altBeb;
1076 int backPressureNoBackoff;
1077 int noBackoff;
1078 int excessDefer;
1079 u8 maxRetransmission;
1080 u8 collisionWindow;
1081 int pro;
1082 int cap;
1083 int rsh;
1084 int rlpb;
1085 int cam;
1086 int bro;
1087 int ecm;
1088 int receiveFlowControl;
1089 int transmitFlowControl;
1090 u8 maxGroupAddrInHash;
1091 u8 maxIndAddrInHash;
1092 u8 prel;
1093 u16 maxFrameLength;
1094 u16 minFrameLength;
1095 u16 maxD1Length;
1096 u16 maxD2Length;
1097 u16 vlantype;
1098 u16 vlantci;
1099 u32 ecamptr;
1100 u32 eventRegMask;
1101 u16 pausePeriod;
1102 u16 extensionField;
1103 char phy_bus_id[BUS_ID_SIZE];
1104 u8 weightfactor[NUM_TX_QUEUES];
1105 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1106 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1107 u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1108 u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1109 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1110 u16 bdRingLenTx[NUM_TX_QUEUES];
1111 u16 bdRingLenRx[NUM_RX_QUEUES];
1112 enum ucc_geth_num_of_station_addresses numStationAddresses;
1113 enum qe_fltr_largest_external_tbl_lookup_key_size
1114 largestexternallookupkeysize;
1115 enum ucc_geth_statistics_gathering_mode statisticsMode;
1116 enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1117 enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1118 enum ucc_geth_qos_mode rxQoSMode;
1119 enum ucc_geth_flow_control_mode aufc;
1120 enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1121 enum ucc_geth_num_of_threads numThreadsTx;
1122 enum ucc_geth_num_of_threads numThreadsRx;
1123 enum qe_risc_allocation riscTx;
1124 enum qe_risc_allocation riscRx;
1125 };
1126
1127 /* structure representing UCC GETH */
1128 struct ucc_geth_private {
1129 struct ucc_geth_info *ug_info;
1130 struct ucc_fast_private *uccf;
1131 struct device *dev;
1132 struct net_device *ndev;
1133 struct napi_struct napi;
1134 struct work_struct timeout_work;
1135 struct ucc_geth __iomem *ug_regs;
1136 struct ucc_geth_init_pram *p_init_enet_param_shadow;
1137 struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1138 u32 exf_glbl_param_offset;
1139 struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1140 u32 rx_glbl_pram_offset;
1141 struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1142 u32 tx_glbl_pram_offset;
1143 struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1144 u32 send_q_mem_reg_offset;
1145 struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1146 u32 thread_dat_tx_offset;
1147 struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1148 u32 thread_dat_rx_offset;
1149 struct ucc_geth_scheduler __iomem *p_scheduler;
1150 u32 scheduler_offset;
1151 struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1152 u32 tx_fw_statistics_pram_offset;
1153 struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1154 u32 rx_fw_statistics_pram_offset;
1155 struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1156 u32 rx_irq_coalescing_tbl_offset;
1157 struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1158 u32 rx_bd_qs_tbl_offset;
1159 u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1160 u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1161 u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1162 u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1163 u8 __iomem *confBd[NUM_TX_QUEUES];
1164 u8 __iomem *txBd[NUM_TX_QUEUES];
1165 u8 __iomem *rxBd[NUM_RX_QUEUES];
1166 int badFrame[NUM_RX_QUEUES];
1167 u16 cpucount[NUM_TX_QUEUES];
1168 u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1169 int indAddrRegUsed[NUM_OF_PADDRS];
1170 u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
1171 u8 numGroupAddrInHash;
1172 u8 numIndAddrInHash;
1173 u8 numIndAddrInReg;
1174 int rx_extended_features;
1175 int rx_non_dynamic_extended_features;
1176 struct list_head conf_skbs;
1177 struct list_head group_hash_q;
1178 struct list_head ind_hash_q;
1179 u32 saved_uccm;
1180 spinlock_t lock;
1181 /* pointers to arrays of skbuffs for tx and rx */
1182 struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1183 struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1184 /* indices pointing to the next free sbk in skb arrays */
1185 u16 skb_curtx[NUM_TX_QUEUES];
1186 u16 skb_currx[NUM_RX_QUEUES];
1187 /* index of the first skb which hasn't been transmitted yet. */
1188 u16 skb_dirtytx[NUM_TX_QUEUES];
1189
1190 struct ugeth_mii_info *mii_info;
1191 struct phy_device *phydev;
1192 phy_interface_t phy_interface;
1193 int max_speed;
1194 uint32_t msg_enable;
1195 int oldspeed;
1196 int oldduplex;
1197 int oldlink;
1198
1199 struct device_node *node;
1200 };
1201
1202 void uec_set_ethtool_ops(struct net_device *netdev);
1203 int init_flow_control_params(u32 automatic_flow_control_mode,
1204 int rx_flow_control_enable, int tx_flow_control_enable,
1205 u16 pause_period, u16 extension_field,
1206 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1207 u32 __iomem *maccfg1_register);
1208
1209
1210 #endif /* __UCC_GETH_H__ */
Support for the Chinese Samsung S3C2440 based development boards