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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6
[linux-2.6/mini2440.git] / drivers / net / smc91x.h
blob329f890e2903075c23cea798acbb5f79e3f12196
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37 #include <linux/smc91x.h>
38
39 /*
40 * Define your architecture specific bus configuration parameters here.
41 */
42
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE) ||\
46 defined(CONFIG_MACH_LITTLETON) ||\
47 defined(CONFIG_MACH_ZYLONITE2) ||\
48 defined(CONFIG_ARCH_VIPER)
49
50 #include <asm/mach-types.h>
51
52 /* Now the bus width is specified in the platform data
53 * pretend here to support all I/O access types
54 */
55 #define SMC_CAN_USE_8BIT 1
56 #define SMC_CAN_USE_16BIT 1
57 #define SMC_CAN_USE_32BIT 1
58 #define SMC_NOWAIT 1
59
60 #define SMC_IO_SHIFT (lp->io_shift)
61
62 #define SMC_inb(a, r) readb((a) + (r))
63 #define SMC_inw(a, r) readw((a) + (r))
64 #define SMC_inl(a, r) readl((a) + (r))
65 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
66 #define SMC_outl(v, a, r) writel(v, (a) + (r))
67 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
68 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
69 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
70 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
71 #define SMC_IRQ_FLAGS (-1) /* from resource */
72
73 /* We actually can't write halfwords properly if not word aligned */
74 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
75 {
76 if (machine_is_mainstone() && reg & 2) {
77 unsigned int v = val << 16;
78 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
79 writel(v, ioaddr + (reg & ~2));
80 } else {
81 writew(val, ioaddr + reg);
82 }
83 }
84
85 #elif defined(CONFIG_BLACKFIN)
86
87 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
88 #define RPC_LSA_DEFAULT RPC_LED_100_10
89 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
90
91 #define SMC_CAN_USE_8BIT 0
92 #define SMC_CAN_USE_16BIT 1
93 # if defined(CONFIG_BF561)
94 #define SMC_CAN_USE_32BIT 1
95 # else
96 #define SMC_CAN_USE_32BIT 0
97 # endif
98 #define SMC_IO_SHIFT 0
99 #define SMC_NOWAIT 1
100 #define SMC_USE_BFIN_DMA 0
101
102 #define SMC_inw(a, r) readw((a) + (r))
103 #define SMC_outw(v, a, r) writew(v, (a) + (r))
104 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
105 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
106 # if SMC_CAN_USE_32BIT
107 #define SMC_inl(a, r) readl((a) + (r))
108 #define SMC_outl(v, a, r) writel(v, (a) + (r))
109 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
110 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
111 # endif
112
113 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
114
115 /* We can only do 16-bit reads and writes in the static memory space. */
116 #define SMC_CAN_USE_8BIT 0
117 #define SMC_CAN_USE_16BIT 1
118 #define SMC_CAN_USE_32BIT 0
119 #define SMC_NOWAIT 1
120
121 #define SMC_IO_SHIFT 0
122
123 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
124 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
125 #define SMC_insw(a, r, p, l) \
126 do { \
127 unsigned long __port = (a) + (r); \
128 u16 *__p = (u16 *)(p); \
129 int __l = (l); \
130 insw(__port, __p, __l); \
131 while (__l > 0) { \
132 *__p = swab16(*__p); \
133 __p++; \
134 __l--; \
135 } \
136 } while (0)
137 #define SMC_outsw(a, r, p, l) \
138 do { \
139 unsigned long __port = (a) + (r); \
140 u16 *__p = (u16 *)(p); \
141 int __l = (l); \
142 while (__l > 0) { \
143 /* Believe it or not, the swab isn't needed. */ \
144 outw( /* swab16 */ (*__p++), __port); \
145 __l--; \
146 } \
147 } while (0)
148 #define SMC_IRQ_FLAGS (0)
149
150 #elif defined(CONFIG_SA1100_PLEB)
151 /* We can only do 16-bit reads and writes in the static memory space. */
152 #define SMC_CAN_USE_8BIT 1
153 #define SMC_CAN_USE_16BIT 1
154 #define SMC_CAN_USE_32BIT 0
155 #define SMC_IO_SHIFT 0
156 #define SMC_NOWAIT 1
157
158 #define SMC_inb(a, r) readb((a) + (r))
159 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
160 #define SMC_inw(a, r) readw((a) + (r))
161 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
162 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
163 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
164 #define SMC_outw(v, a, r) writew(v, (a) + (r))
165 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
166
167 #define SMC_IRQ_FLAGS (-1)
168
169 #elif defined(CONFIG_SA1100_ASSABET)
170
171 #include <mach/neponset.h>
172
173 /* We can only do 8-bit reads and writes in the static memory space. */
174 #define SMC_CAN_USE_8BIT 1
175 #define SMC_CAN_USE_16BIT 0
176 #define SMC_CAN_USE_32BIT 0
177 #define SMC_NOWAIT 1
178
179 /* The first two address lines aren't connected... */
180 #define SMC_IO_SHIFT 2
181
182 #define SMC_inb(a, r) readb((a) + (r))
183 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
184 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
185 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
186 #define SMC_IRQ_FLAGS (-1) /* from resource */
187
188 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
189
190 #define SMC_CAN_USE_8BIT 0
191 #define SMC_CAN_USE_16BIT 1
192 #define SMC_CAN_USE_32BIT 0
193 #define SMC_IO_SHIFT 0
194 #define SMC_NOWAIT 1
195
196 #define SMC_inw(a, r) readw((a) + (r))
197 #define SMC_outw(v, a, r) writew(v, (a) + (r))
198 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
199 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
200
201 #elif defined(CONFIG_ARCH_INNOKOM) || \
202 defined(CONFIG_ARCH_PXA_IDP) || \
203 defined(CONFIG_ARCH_RAMSES) || \
204 defined(CONFIG_ARCH_PCM027)
205
206 #define SMC_CAN_USE_8BIT 1
207 #define SMC_CAN_USE_16BIT 1
208 #define SMC_CAN_USE_32BIT 1
209 #define SMC_IO_SHIFT 0
210 #define SMC_NOWAIT 1
211 #define SMC_USE_PXA_DMA 1
212
213 #define SMC_inb(a, r) readb((a) + (r))
214 #define SMC_inw(a, r) readw((a) + (r))
215 #define SMC_inl(a, r) readl((a) + (r))
216 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
217 #define SMC_outl(v, a, r) writel(v, (a) + (r))
218 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
219 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
220 #define SMC_IRQ_FLAGS (-1) /* from resource */
221
222 /* We actually can't write halfwords properly if not word aligned */
223 static inline void
224 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
225 {
226 if (reg & 2) {
227 unsigned int v = val << 16;
228 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
229 writel(v, ioaddr + (reg & ~2));
230 } else {
231 writew(val, ioaddr + reg);
232 }
233 }
234
235 #elif defined(CONFIG_ARCH_OMAP)
236
237 /* We can only do 16-bit reads and writes in the static memory space. */
238 #define SMC_CAN_USE_8BIT 0
239 #define SMC_CAN_USE_16BIT 1
240 #define SMC_CAN_USE_32BIT 0
241 #define SMC_IO_SHIFT 0
242 #define SMC_NOWAIT 1
243
244 #define SMC_inw(a, r) readw((a) + (r))
245 #define SMC_outw(v, a, r) writew(v, (a) + (r))
246 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
247 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
248 #define SMC_IRQ_FLAGS (-1) /* from resource */
249
250 #elif defined(CONFIG_SH_SH4202_MICRODEV)
251
252 #define SMC_CAN_USE_8BIT 0
253 #define SMC_CAN_USE_16BIT 1
254 #define SMC_CAN_USE_32BIT 0
255
256 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
257 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
258 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
259 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
260 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
261 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
262 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
263 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
264 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
265 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
266
267 #define SMC_IRQ_FLAGS (0)
268
269 #elif defined(CONFIG_M32R)
270
271 #define SMC_CAN_USE_8BIT 0
272 #define SMC_CAN_USE_16BIT 1
273 #define SMC_CAN_USE_32BIT 0
274
275 #define SMC_inb(a, r) inb(((u32)a) + (r))
276 #define SMC_inw(a, r) inw(((u32)a) + (r))
277 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
278 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
279 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
280 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
281
282 #define SMC_IRQ_FLAGS (0)
283
284 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
285 #define RPC_LSB_DEFAULT RPC_LED_100_10
286
287 #elif defined(CONFIG_MACH_LPD79520) \
288 || defined(CONFIG_MACH_LPD7A400) \
289 || defined(CONFIG_MACH_LPD7A404)
290
291 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
292 * way that the CPU handles chip selects and the way that the SMC chip
293 * expects the chip select to operate. Refer to
294 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
295 * IOBARRIER is a byte, in order that we read the least-common
296 * denominator. It would be wasteful to read 32 bits from an 8-bit
297 * accessible region.
298 *
299 * There is no explicit protection against interrupts intervening
300 * between the writew and the IOBARRIER. In SMC ISR there is a
301 * preamble that performs an IOBARRIER in the extremely unlikely event
302 * that the driver interrupts itself between a writew to the chip an
303 * the IOBARRIER that follows *and* the cache is large enough that the
304 * first off-chip access while handing the interrupt is to the SMC
305 * chip. Other devices in the same address space as the SMC chip must
306 * be aware of the potential for trouble and perform a similar
307 * IOBARRIER on entry to their ISR.
308 */
309
310 #include <mach/constants.h> /* IOBARRIER_VIRT */
311
312 #define SMC_CAN_USE_8BIT 0
313 #define SMC_CAN_USE_16BIT 1
314 #define SMC_CAN_USE_32BIT 0
315 #define SMC_NOWAIT 0
316 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
317
318 #define SMC_inw(a,r)\
319 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
320 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
321
322 #define SMC_insw LPD7_SMC_insw
323 static inline void LPD7_SMC_insw (unsigned char* a, int r,
324 unsigned char* p, int l)
325 {
326 unsigned short* ps = (unsigned short*) p;
327 while (l-- > 0) {
328 *ps++ = readw (a + r);
329 LPD7X_IOBARRIER;
330 }
331 }
332
333 #define SMC_outsw LPD7_SMC_outsw
334 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
335 unsigned char* p, int l)
336 {
337 unsigned short* ps = (unsigned short*) p;
338 while (l-- > 0) {
339 writew (*ps++, a + r);
340 LPD7X_IOBARRIER;
341 }
342 }
343
344 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
345
346 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
347 #define RPC_LSB_DEFAULT RPC_LED_100_10
348
349 #elif defined(CONFIG_ARCH_VERSATILE)
350
351 #define SMC_CAN_USE_8BIT 1
352 #define SMC_CAN_USE_16BIT 1
353 #define SMC_CAN_USE_32BIT 1
354 #define SMC_NOWAIT 1
355
356 #define SMC_inb(a, r) readb((a) + (r))
357 #define SMC_inw(a, r) readw((a) + (r))
358 #define SMC_inl(a, r) readl((a) + (r))
359 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
360 #define SMC_outw(v, a, r) writew(v, (a) + (r))
361 #define SMC_outl(v, a, r) writel(v, (a) + (r))
362 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
363 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
364 #define SMC_IRQ_FLAGS (-1) /* from resource */
365
366 #elif defined(CONFIG_MN10300)
367
368 /*
369 * MN10300/AM33 configuration
370 */
371
372 #include <unit/smc91111.h>
373
374 #else
375
376 /*
377 * Default configuration
378 */
379
380 #define SMC_CAN_USE_8BIT 1
381 #define SMC_CAN_USE_16BIT 1
382 #define SMC_CAN_USE_32BIT 1
383 #define SMC_NOWAIT 1
384
385 #define SMC_IO_SHIFT (lp->io_shift)
386
387 #define SMC_inb(a, r) readb((a) + (r))
388 #define SMC_inw(a, r) readw((a) + (r))
389 #define SMC_inl(a, r) readl((a) + (r))
390 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
391 #define SMC_outw(v, a, r) writew(v, (a) + (r))
392 #define SMC_outl(v, a, r) writel(v, (a) + (r))
393 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
394 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
395 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
396 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
397
398 #define RPC_LSA_DEFAULT RPC_LED_100_10
399 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
400
401 #endif
402
403
404 /* store this information for the driver.. */
405 struct smc_local {
406 /*
407 * If I have to wait until memory is available to send a
408 * packet, I will store the skbuff here, until I get the
409 * desired memory. Then, I'll send it out and free it.
410 */
411 struct sk_buff *pending_tx_skb;
412 struct tasklet_struct tx_task;
413
414 /* version/revision of the SMC91x chip */
415 int version;
416
417 /* Contains the current active transmission mode */
418 int tcr_cur_mode;
419
420 /* Contains the current active receive mode */
421 int rcr_cur_mode;
422
423 /* Contains the current active receive/phy mode */
424 int rpc_cur_mode;
425 int ctl_rfduplx;
426 int ctl_rspeed;
427
428 u32 msg_enable;
429 u32 phy_type;
430 struct mii_if_info mii;
431
432 /* work queue */
433 struct work_struct phy_configure;
434 struct net_device *dev;
435 int work_pending;
436
437 spinlock_t lock;
438
439 #ifdef CONFIG_ARCH_PXA
440 /* DMA needs the physical address of the chip */
441 u_long physaddr;
442 struct device *device;
443 #endif
444 void __iomem *base;
445 void __iomem *datacs;
446
447 /* the low address lines on some platforms aren't connected... */
448 int io_shift;
449
450 struct smc91x_platdata cfg;
451 };
452
453 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
454 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
455 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
456
457 #ifdef CONFIG_ARCH_PXA
458 /*
459 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
460 * always happening in irq context so no need to worry about races. TX is
461 * different and probably not worth it for that reason, and not as critical
462 * as RX which can overrun memory and lose packets.
463 */
464 #include <linux/dma-mapping.h>
465 #include <mach/dma.h>
466
467 #ifdef SMC_insl
468 #undef SMC_insl
469 #define SMC_insl(a, r, p, l) \
470 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
471 static inline void
472 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
473 u_char *buf, int len)
474 {
475 u_long physaddr = lp->physaddr;
476 dma_addr_t dmabuf;
477
478 /* fallback if no DMA available */
479 if (dma == (unsigned char)-1) {
480 readsl(ioaddr + reg, buf, len);
481 return;
482 }
483
484 /* 64 bit alignment is required for memory to memory DMA */
485 if ((long)buf & 4) {
486 *((u32 *)buf) = SMC_inl(ioaddr, reg);
487 buf += 4;
488 len--;
489 }
490
491 len *= 4;
492 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
493 DCSR(dma) = DCSR_NODESC;
494 DTADR(dma) = dmabuf;
495 DSADR(dma) = physaddr + reg;
496 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
497 DCMD_WIDTH4 | (DCMD_LENGTH & len));
498 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
499 while (!(DCSR(dma) & DCSR_STOPSTATE))
500 cpu_relax();
501 DCSR(dma) = 0;
502 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
503 }
504 #endif
505
506 #ifdef SMC_insw
507 #undef SMC_insw
508 #define SMC_insw(a, r, p, l) \
509 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
510 static inline void
511 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
512 u_char *buf, int len)
513 {
514 u_long physaddr = lp->physaddr;
515 dma_addr_t dmabuf;
516
517 /* fallback if no DMA available */
518 if (dma == (unsigned char)-1) {
519 readsw(ioaddr + reg, buf, len);
520 return;
521 }
522
523 /* 64 bit alignment is required for memory to memory DMA */
524 while ((long)buf & 6) {
525 *((u16 *)buf) = SMC_inw(ioaddr, reg);
526 buf += 2;
527 len--;
528 }
529
530 len *= 2;
531 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
532 DCSR(dma) = DCSR_NODESC;
533 DTADR(dma) = dmabuf;
534 DSADR(dma) = physaddr + reg;
535 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
536 DCMD_WIDTH2 | (DCMD_LENGTH & len));
537 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
538 while (!(DCSR(dma) & DCSR_STOPSTATE))
539 cpu_relax();
540 DCSR(dma) = 0;
541 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
542 }
543 #endif
544
545 static void
546 smc_pxa_dma_irq(int dma, void *dummy)
547 {
548 DCSR(dma) = 0;
549 }
550 #endif /* CONFIG_ARCH_PXA */
551
552
553 /*
554 * Everything a particular hardware setup needs should have been defined
555 * at this point. Add stubs for the undefined cases, mainly to avoid
556 * compilation warnings since they'll be optimized away, or to prevent buggy
557 * use of them.
558 */
559
560 #if ! SMC_CAN_USE_32BIT
561 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
562 #define SMC_outl(x, ioaddr, reg) BUG()
563 #define SMC_insl(a, r, p, l) BUG()
564 #define SMC_outsl(a, r, p, l) BUG()
565 #endif
566
567 #if !defined(SMC_insl) || !defined(SMC_outsl)
568 #define SMC_insl(a, r, p, l) BUG()
569 #define SMC_outsl(a, r, p, l) BUG()
570 #endif
571
572 #if ! SMC_CAN_USE_16BIT
573
574 /*
575 * Any 16-bit access is performed with two 8-bit accesses if the hardware
576 * can't do it directly. Most registers are 16-bit so those are mandatory.
577 */
578 #define SMC_outw(x, ioaddr, reg) \
579 do { \
580 unsigned int __val16 = (x); \
581 SMC_outb( __val16, ioaddr, reg ); \
582 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
583 } while (0)
584 #define SMC_inw(ioaddr, reg) \
585 ({ \
586 unsigned int __val16; \
587 __val16 = SMC_inb( ioaddr, reg ); \
588 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
589 __val16; \
590 })
591
592 #define SMC_insw(a, r, p, l) BUG()
593 #define SMC_outsw(a, r, p, l) BUG()
594
595 #endif
596
597 #if !defined(SMC_insw) || !defined(SMC_outsw)
598 #define SMC_insw(a, r, p, l) BUG()
599 #define SMC_outsw(a, r, p, l) BUG()
600 #endif
601
602 #if ! SMC_CAN_USE_8BIT
603 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
604 #define SMC_outb(x, ioaddr, reg) BUG()
605 #define SMC_insb(a, r, p, l) BUG()
606 #define SMC_outsb(a, r, p, l) BUG()
607 #endif
608
609 #if !defined(SMC_insb) || !defined(SMC_outsb)
610 #define SMC_insb(a, r, p, l) BUG()
611 #define SMC_outsb(a, r, p, l) BUG()
612 #endif
613
614 #ifndef SMC_CAN_USE_DATACS
615 #define SMC_CAN_USE_DATACS 0
616 #endif
617
618 #ifndef SMC_IO_SHIFT
619 #define SMC_IO_SHIFT 0
620 #endif
621
622 #ifndef SMC_IRQ_FLAGS
623 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
624 #endif
625
626 #ifndef SMC_INTERRUPT_PREAMBLE
627 #define SMC_INTERRUPT_PREAMBLE
628 #endif
629
630
631 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
632 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
633 #define SMC_DATA_EXTENT (4)
634
635 /*
636 . Bank Select Register:
637 .
638 . yyyy yyyy 0000 00xx
639 . xx = bank number
640 . yyyy yyyy = 0x33, for identification purposes.
641 */
642 #define BANK_SELECT (14 << SMC_IO_SHIFT)
643
644
645 // Transmit Control Register
646 /* BANK 0 */
647 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
648 #define TCR_ENABLE 0x0001 // When 1 we can transmit
649 #define TCR_LOOP 0x0002 // Controls output pin LBK
650 #define TCR_FORCOL 0x0004 // When 1 will force a collision
651 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
652 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
653 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
654 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
655 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
656 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
657 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
658
659 #define TCR_CLEAR 0 /* do NOTHING */
660 /* the default settings for the TCR register : */
661 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
662
663
664 // EPH Status Register
665 /* BANK 0 */
666 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
667 #define ES_TX_SUC 0x0001 // Last TX was successful
668 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
669 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
670 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
671 #define ES_16COL 0x0010 // 16 Collisions Reached
672 #define ES_SQET 0x0020 // Signal Quality Error Test
673 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
674 #define ES_TXDEFR 0x0080 // Transmit Deferred
675 #define ES_LATCOL 0x0200 // Late collision detected on last tx
676 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
677 #define ES_EXC_DEF 0x0800 // Excessive Deferral
678 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
679 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
680 #define ES_TXUNRN 0x8000 // Tx Underrun
681
682
683 // Receive Control Register
684 /* BANK 0 */
685 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
686 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
687 #define RCR_PRMS 0x0002 // Enable promiscuous mode
688 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
689 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
690 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
691 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
692 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
693 #define RCR_SOFTRST 0x8000 // resets the chip
694
695 /* the normal settings for the RCR register : */
696 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
697 #define RCR_CLEAR 0x0 // set it to a base state
698
699
700 // Counter Register
701 /* BANK 0 */
702 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
703
704
705 // Memory Information Register
706 /* BANK 0 */
707 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
708
709
710 // Receive/Phy Control Register
711 /* BANK 0 */
712 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
713 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
714 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
715 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
716 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
717 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
718
719 #ifndef RPC_LSA_DEFAULT
720 #define RPC_LSA_DEFAULT RPC_LED_100
721 #endif
722 #ifndef RPC_LSB_DEFAULT
723 #define RPC_LSB_DEFAULT RPC_LED_FD
724 #endif
725
726 #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX)
727
728
729 /* Bank 0 0x0C is reserved */
730
731 // Bank Select Register
732 /* All Banks */
733 #define BSR_REG 0x000E
734
735
736 // Configuration Reg
737 /* BANK 1 */
738 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
739 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
740 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
741 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
742 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
743
744 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
745 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
746
747
748 // Base Address Register
749 /* BANK 1 */
750 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
751
752
753 // Individual Address Registers
754 /* BANK 1 */
755 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
756 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
757 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
758
759
760 // General Purpose Register
761 /* BANK 1 */
762 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
763
764
765 // Control Register
766 /* BANK 1 */
767 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
768 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
769 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
770 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
771 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
772 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
773 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
774 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
775 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
776
777
778 // MMU Command Register
779 /* BANK 2 */
780 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
781 #define MC_BUSY 1 // When 1 the last release has not completed
782 #define MC_NOP (0<<5) // No Op
783 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
784 #define MC_RESET (2<<5) // Reset MMU to initial state
785 #define MC_REMOVE (3<<5) // Remove the current rx packet
786 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
787 #define MC_FREEPKT (5<<5) // Release packet in PNR register
788 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
789 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
790
791
792 // Packet Number Register
793 /* BANK 2 */
794 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
795
796
797 // Allocation Result Register
798 /* BANK 2 */
799 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
800 #define AR_FAILED 0x80 // Alocation Failed
801
802
803 // TX FIFO Ports Register
804 /* BANK 2 */
805 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
806 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
807
808 // RX FIFO Ports Register
809 /* BANK 2 */
810 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
811 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
812
813 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
814
815 // Pointer Register
816 /* BANK 2 */
817 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
818 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
819 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
820 #define PTR_READ 0x2000 // When 1 the operation is a read
821
822
823 // Data Register
824 /* BANK 2 */
825 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
826
827
828 // Interrupt Status/Acknowledge Register
829 /* BANK 2 */
830 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
831
832
833 // Interrupt Mask Register
834 /* BANK 2 */
835 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
836 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
837 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
838 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
839 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
840 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
841 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
842 #define IM_TX_INT 0x02 // Transmit Interrupt
843 #define IM_RCV_INT 0x01 // Receive Interrupt
844
845
846 // Multicast Table Registers
847 /* BANK 3 */
848 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
849 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
850 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
851 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
852
853
854 // Management Interface Register (MII)
855 /* BANK 3 */
856 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
857 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
858 #define MII_MDOE 0x0008 // MII Output Enable
859 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
860 #define MII_MDI 0x0002 // MII Input, pin MDI
861 #define MII_MDO 0x0001 // MII Output, pin MDO
862
863
864 // Revision Register
865 /* BANK 3 */
866 /* ( hi: chip id low: rev # ) */
867 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
868
869
870 // Early RCV Register
871 /* BANK 3 */
872 /* this is NOT on SMC9192 */
873 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
874 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
875 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
876
877
878 // External Register
879 /* BANK 7 */
880 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
881
882
883 #define CHIP_9192 3
884 #define CHIP_9194 4
885 #define CHIP_9195 5
886 #define CHIP_9196 6
887 #define CHIP_91100 7
888 #define CHIP_91100FD 8
889 #define CHIP_91111FD 9
890
891 static const char * chip_ids[ 16 ] = {
892 NULL, NULL, NULL,
893 /* 3 */ "SMC91C90/91C92",
894 /* 4 */ "SMC91C94",
895 /* 5 */ "SMC91C95",
896 /* 6 */ "SMC91C96",
897 /* 7 */ "SMC91C100",
898 /* 8 */ "SMC91C100FD",
899 /* 9 */ "SMC91C11xFD",
900 NULL, NULL, NULL,
901 NULL, NULL, NULL};
902
903
904 /*
905 . Receive status bits
906 */
907 #define RS_ALGNERR 0x8000
908 #define RS_BRODCAST 0x4000
909 #define RS_BADCRC 0x2000
910 #define RS_ODDFRAME 0x1000
911 #define RS_TOOLONG 0x0800
912 #define RS_TOOSHORT 0x0400
913 #define RS_MULTICAST 0x0001
914 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
915
916
917 /*
918 * PHY IDs
919 * LAN83C183 == LAN91C111 Internal PHY
920 */
921 #define PHY_LAN83C183 0x0016f840
922 #define PHY_LAN83C180 0x02821c50
923
924 /*
925 * PHY Register Addresses (LAN91C111 Internal PHY)
926 *
927 * Generic PHY registers can be found in <linux/mii.h>
928 *
929 * These phy registers are specific to our on-board phy.
930 */
931
932 // PHY Configuration Register 1
933 #define PHY_CFG1_REG 0x10
934 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
935 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
936 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
937 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
938 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
939 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
940 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
941 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
942 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
943 #define PHY_CFG1_TLVL_MASK 0x003C
944 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
945
946
947 // PHY Configuration Register 2
948 #define PHY_CFG2_REG 0x11
949 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
950 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
951 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
952 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
953
954 // PHY Status Output (and Interrupt status) Register
955 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
956 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
957 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
958 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
959 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
960 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
961 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
962 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
963 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
964 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
965 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
966
967 // PHY Interrupt/Status Mask Register
968 #define PHY_MASK_REG 0x13 // Interrupt Mask
969 // Uses the same bit definitions as PHY_INT_REG
970
971
972 /*
973 * SMC91C96 ethernet config and status registers.
974 * These are in the "attribute" space.
975 */
976 #define ECOR 0x8000
977 #define ECOR_RESET 0x80
978 #define ECOR_LEVEL_IRQ 0x40
979 #define ECOR_WR_ATTRIB 0x04
980 #define ECOR_ENABLE 0x01
981
982 #define ECSR 0x8002
983 #define ECSR_IOIS8 0x20
984 #define ECSR_PWRDWN 0x04
985 #define ECSR_INT 0x02
986
987 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
988
989
990 /*
991 * Macros to abstract register access according to the data bus
992 * capabilities. Please use those and not the in/out primitives.
993 * Note: the following macros do *not* select the bank -- this must
994 * be done separately as needed in the main code. The SMC_REG() macro
995 * only uses the bank argument for debugging purposes (when enabled).
996 *
997 * Note: despite inline functions being safer, everything leading to this
998 * should preferably be macros to let BUG() display the line number in
999 * the core source code since we're interested in the top call site
1000 * not in any inline function location.
1001 */
1002
1003 #if SMC_DEBUG > 0
1004 #define SMC_REG(lp, reg, bank) \
1005 ({ \
1006 int __b = SMC_CURRENT_BANK(lp); \
1007 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1008 printk( "%s: bank reg screwed (0x%04x)\n", \
1009 CARDNAME, __b ); \
1010 BUG(); \
1011 } \
1012 reg<<SMC_IO_SHIFT; \
1013 })
1014 #else
1015 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1016 #endif
1017
1018 /*
1019 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1020 * aligned to a 32 bit boundary. I tell you that does exist!
1021 * Fortunately the affected register accesses can be easily worked around
1022 * since we can write zeroes to the preceeding 16 bits without adverse
1023 * effects and use a 32-bit access.
1024 *
1025 * Enforce it on any 32-bit capable setup for now.
1026 */
1027 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1028
1029 #define SMC_GET_PN(lp) \
1030 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1031 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1032
1033 #define SMC_SET_PN(lp, x) \
1034 do { \
1035 if (SMC_MUST_ALIGN_WRITE(lp)) \
1036 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1037 else if (SMC_8BIT(lp)) \
1038 SMC_outb(x, ioaddr, PN_REG(lp)); \
1039 else \
1040 SMC_outw(x, ioaddr, PN_REG(lp)); \
1041 } while (0)
1042
1043 #define SMC_GET_AR(lp) \
1044 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1045 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1046
1047 #define SMC_GET_TXFIFO(lp) \
1048 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1049 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1050
1051 #define SMC_GET_RXFIFO(lp) \
1052 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1053 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1054
1055 #define SMC_GET_INT(lp) \
1056 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1057 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1058
1059 #define SMC_ACK_INT(lp, x) \
1060 do { \
1061 if (SMC_8BIT(lp)) \
1062 SMC_outb(x, ioaddr, INT_REG(lp)); \
1063 else { \
1064 unsigned long __flags; \
1065 int __mask; \
1066 local_irq_save(__flags); \
1067 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1068 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1069 local_irq_restore(__flags); \
1070 } \
1071 } while (0)
1072
1073 #define SMC_GET_INT_MASK(lp) \
1074 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1075 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1076
1077 #define SMC_SET_INT_MASK(lp, x) \
1078 do { \
1079 if (SMC_8BIT(lp)) \
1080 SMC_outb(x, ioaddr, IM_REG(lp)); \
1081 else \
1082 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1083 } while (0)
1084
1085 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1086
1087 #define SMC_SELECT_BANK(lp, x) \
1088 do { \
1089 if (SMC_MUST_ALIGN_WRITE(lp)) \
1090 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1091 else \
1092 SMC_outw(x, ioaddr, BANK_SELECT); \
1093 } while (0)
1094
1095 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1096
1097 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1098
1099 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1100
1101 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1102
1103 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1104
1105 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1106
1107 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1108
1109 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1110
1111 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
1112
1113 #define SMC_SET_GP(lp, x) \
1114 do { \
1115 if (SMC_MUST_ALIGN_WRITE(lp)) \
1116 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
1117 else \
1118 SMC_outw(x, ioaddr, GP_REG(lp)); \
1119 } while (0)
1120
1121 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1122
1123 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1124
1125 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1126
1127 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1128
1129 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1130
1131 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1132
1133 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1134
1135 #define SMC_SET_PTR(lp, x) \
1136 do { \
1137 if (SMC_MUST_ALIGN_WRITE(lp)) \
1138 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1139 else \
1140 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1141 } while (0)
1142
1143 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1144
1145 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1146
1147 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1148
1149 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1150
1151 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1152
1153 #define SMC_SET_RPC(lp, x) \
1154 do { \
1155 if (SMC_MUST_ALIGN_WRITE(lp)) \
1156 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1157 else \
1158 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1159 } while (0)
1160
1161 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1162
1163 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1164
1165 #ifndef SMC_GET_MAC_ADDR
1166 #define SMC_GET_MAC_ADDR(lp, addr) \
1167 do { \
1168 unsigned int __v; \
1169 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1170 addr[0] = __v; addr[1] = __v >> 8; \
1171 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1172 addr[2] = __v; addr[3] = __v >> 8; \
1173 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1174 addr[4] = __v; addr[5] = __v >> 8; \
1175 } while (0)
1176 #endif
1177
1178 #define SMC_SET_MAC_ADDR(lp, addr) \
1179 do { \
1180 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1181 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1182 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1183 } while (0)
1184
1185 #define SMC_SET_MCAST(lp, x) \
1186 do { \
1187 const unsigned char *mt = (x); \
1188 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1189 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1190 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1191 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1192 } while (0)
1193
1194 #define SMC_PUT_PKT_HDR(lp, status, length) \
1195 do { \
1196 if (SMC_32BIT(lp)) \
1197 SMC_outl((status) | (length)<<16, ioaddr, \
1198 DATA_REG(lp)); \
1199 else { \
1200 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1201 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1202 } \
1203 } while (0)
1204
1205 #define SMC_GET_PKT_HDR(lp, status, length) \
1206 do { \
1207 if (SMC_32BIT(lp)) { \
1208 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1209 (status) = __val & 0xffff; \
1210 (length) = __val >> 16; \
1211 } else { \
1212 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1213 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1214 } \
1215 } while (0)
1216
1217 #define SMC_PUSH_DATA(lp, p, l) \
1218 do { \
1219 if (SMC_32BIT(lp)) { \
1220 void *__ptr = (p); \
1221 int __len = (l); \
1222 void __iomem *__ioaddr = ioaddr; \
1223 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1224 __len -= 2; \
1225 SMC_outw(*(u16 *)__ptr, ioaddr, \
1226 DATA_REG(lp)); \
1227 __ptr += 2; \
1228 } \
1229 if (SMC_CAN_USE_DATACS && lp->datacs) \
1230 __ioaddr = lp->datacs; \
1231 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1232 if (__len & 2) { \
1233 __ptr += (__len & ~3); \
1234 SMC_outw(*((u16 *)__ptr), ioaddr, \
1235 DATA_REG(lp)); \
1236 } \
1237 } else if (SMC_16BIT(lp)) \
1238 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1239 else if (SMC_8BIT(lp)) \
1240 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1241 } while (0)
1242
1243 #define SMC_PULL_DATA(lp, p, l) \
1244 do { \
1245 if (SMC_32BIT(lp)) { \
1246 void *__ptr = (p); \
1247 int __len = (l); \
1248 void __iomem *__ioaddr = ioaddr; \
1249 if ((unsigned long)__ptr & 2) { \
1250 /* \
1251 * We want 32bit alignment here. \
1252 * Since some buses perform a full \
1253 * 32bit fetch even for 16bit data \
1254 * we can't use SMC_inw() here. \
1255 * Back both source (on-chip) and \
1256 * destination pointers of 2 bytes. \
1257 * This is possible since the call to \
1258 * SMC_GET_PKT_HDR() already advanced \
1259 * the source pointer of 4 bytes, and \
1260 * the skb_reserve(skb, 2) advanced \
1261 * the destination pointer of 2 bytes. \
1262 */ \
1263 __ptr -= 2; \
1264 __len += 2; \
1265 SMC_SET_PTR(lp, \
1266 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1267 } \
1268 if (SMC_CAN_USE_DATACS && lp->datacs) \
1269 __ioaddr = lp->datacs; \
1270 __len += 2; \
1271 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1272 } else if (SMC_16BIT(lp)) \
1273 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1274 else if (SMC_8BIT(lp)) \
1275 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1276 } while (0)
1277
1278 #endif /* _SMC91X_H_ */
Support for the Chinese Samsung S3C2440 based development boards