2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.10"
53 #define PFX DRV_NAME " "
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81 static const u32 default_msg
=
82 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
83 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
86 static int debug
= -1; /* defaults above */
87 module_param(debug
, int, 0);
88 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly
= 128;
91 module_param(copybreak
, int, 0);
92 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
94 static int disable_msi
= 0;
95 module_param(disable_msi
, int, 0);
96 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
98 static int idle_timeout
= 0;
99 module_param(idle_timeout
, int, 0);
100 MODULE_PARM_DESC(idle_timeout
, "Watchdog timer for lost interrupts (ms)");
102 static const struct pci_device_id sky2_id_table
[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
132 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
134 /* Avoid conditionals by using array */
135 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
136 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
137 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
139 /* This driver supports yukon2 chipset only */
140 static const char *yukon2_name
[] = {
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
148 /* Access to external PHY */
149 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
153 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
154 gma_write16(hw
, port
, GM_SMI_CTRL
,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
157 for (i
= 0; i
< PHY_RETRIES
; i
++) {
158 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
163 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
167 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
171 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
172 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
174 for (i
= 0; i
< PHY_RETRIES
; i
++) {
175 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
176 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
186 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
190 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
191 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
195 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
200 pr_debug("sky2_set_power_state %d\n", state
);
201 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
203 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
204 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
205 (power_control
& PCI_PM_CAP_PME_D3cold
);
207 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
209 power_control
|= PCI_PM_CTRL_PME_STATUS
;
210 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw
, B0_POWER_CTRL
,
216 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
218 /* disable Core Clock Division, */
219 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
221 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
222 /* enable bits are inverted */
223 sky2_write8(hw
, B2_Y2_CLK_GATE
,
224 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
225 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
226 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
228 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
230 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
233 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
234 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
235 reg1
&= P_ASPM_CONTROL_MSK
;
236 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
237 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
244 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
245 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
247 /* enable bits are inverted */
248 sky2_write8(hw
, B2_Y2_CLK_GATE
,
249 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
250 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
251 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
253 /* switch power to VAUX */
254 if (vaux
&& state
!= PCI_D3cold
)
255 sky2_write8(hw
, B0_POWER_CTRL
,
256 (PC_VAUX_ENA
| PC_VCC_ENA
|
257 PC_VAUX_ON
| PC_VCC_OFF
));
260 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
263 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
264 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
267 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
276 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
277 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
278 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
279 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
281 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
282 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
283 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
286 /* flow control to advertise bits */
287 static const u16 copper_fc_adv
[] = {
289 [FC_TX
] = PHY_M_AN_ASP
,
290 [FC_RX
] = PHY_M_AN_PC
,
291 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
294 /* flow control to advertise bits when using 1000BaseX */
295 static const u16 fiber_fc_adv
[] = {
296 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
297 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
298 [FC_RX
] = PHY_M_P_SYM_MD_X
,
299 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
302 /* flow control to GMA disable bits */
303 static const u16 gm_fc_disable
[] = {
304 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
305 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
306 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
311 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
313 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
314 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
316 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
317 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
318 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
320 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
322 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
324 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
325 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
327 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
329 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
332 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
333 if (sky2_is_copper(hw
)) {
334 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
335 /* enable automatic crossover */
336 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
338 /* disable energy detect */
339 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
341 /* enable automatic crossover */
342 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
344 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
345 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
346 ctrl
&= ~PHY_M_PC_DSC_MSK
;
347 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
351 /* workaround for deviation #4.88 (CRC errors) */
352 /* disable Automatic Crossover */
354 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
357 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
359 /* special setup for PHY 88E1112 Fiber */
360 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
361 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
363 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
364 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
365 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
366 ctrl
&= ~PHY_M_MAC_MD_MSK
;
367 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
368 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
370 if (hw
->pmd_type
== 'P') {
371 /* select page 1 to access Fiber registers */
372 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
374 /* for SFP-module set SIGDET polarity to low */
375 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
376 ctrl
|= PHY_M_FIB_SIGD_POL
;
377 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
380 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
388 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
389 if (sky2_is_copper(hw
)) {
390 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
391 ct1000
|= PHY_M_1000C_AFD
;
392 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
393 ct1000
|= PHY_M_1000C_AHD
;
394 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
395 adv
|= PHY_M_AN_100_FD
;
396 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
397 adv
|= PHY_M_AN_100_HD
;
398 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
399 adv
|= PHY_M_AN_10_FD
;
400 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
401 adv
|= PHY_M_AN_10_HD
;
403 adv
|= copper_fc_adv
[sky2
->flow_mode
];
404 } else { /* special defines for FIBER (88E1040S only) */
405 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
406 adv
|= PHY_M_AN_1000X_AFD
;
407 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
408 adv
|= PHY_M_AN_1000X_AHD
;
410 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
413 /* Restart Auto-negotiation */
414 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
416 /* forced speed/duplex settings */
417 ct1000
= PHY_M_1000C_MSE
;
419 /* Disable auto update for duplex flow control and speed */
420 reg
|= GM_GPCR_AU_ALL_DIS
;
422 switch (sky2
->speed
) {
424 ctrl
|= PHY_CT_SP1000
;
425 reg
|= GM_GPCR_SPEED_1000
;
428 ctrl
|= PHY_CT_SP100
;
429 reg
|= GM_GPCR_SPEED_100
;
433 if (sky2
->duplex
== DUPLEX_FULL
) {
434 reg
|= GM_GPCR_DUP_FULL
;
435 ctrl
|= PHY_CT_DUP_MD
;
436 } else if (sky2
->speed
< SPEED_1000
)
437 sky2
->flow_mode
= FC_NONE
;
440 reg
|= gm_fc_disable
[sky2
->flow_mode
];
442 /* Forward pause packets to GMAC? */
443 if (sky2
->flow_mode
& FC_RX
)
444 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
446 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
449 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
451 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
452 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
454 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
455 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
457 /* Setup Phy LED's */
458 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
461 switch (hw
->chip_id
) {
462 case CHIP_ID_YUKON_FE
:
463 /* on 88E3082 these bits are at 11..9 (shifted left) */
464 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
466 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
468 /* delete ACT LED control bits */
469 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
470 /* change ACT LED control to blink mode */
471 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
472 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
475 case CHIP_ID_YUKON_XL
:
476 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
481 /* set LED Function Control register */
482 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
488 /* set Polarity Control register */
489 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
490 (PHY_M_POLC_LS1_P_MIX(4) |
491 PHY_M_POLC_IS0_P_MIX(4) |
492 PHY_M_POLC_LOS_CTRL(2) |
493 PHY_M_POLC_INIT_CTRL(2) |
494 PHY_M_POLC_STA1_CTRL(2) |
495 PHY_M_POLC_STA0_CTRL(2)));
497 /* restore page register */
498 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
500 case CHIP_ID_YUKON_EC_U
:
501 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
503 /* select page 3 to access LED control register */
504 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
506 /* set LED Function Control register */
507 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
508 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
509 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
510 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
511 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
513 /* set Blink Rate in LED Timer Control Register */
514 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
515 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
516 /* restore page register */
517 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
521 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
522 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
523 /* turn off the Rx LED (LED_RX) */
524 ledover
&= ~PHY_M_LED_MO_RX
;
527 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
528 /* apply fixes in PHY AFE */
529 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
530 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
532 /* increase differential signal amplitude in 10BASE-T */
533 gm_phy_write(hw
, port
, 0x18, 0xaa99);
534 gm_phy_write(hw
, port
, 0x17, 0x2011);
536 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
537 gm_phy_write(hw
, port
, 0x18, 0xa204);
538 gm_phy_write(hw
, port
, 0x17, 0x2002);
540 /* set page register to 0 */
541 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
543 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
545 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
546 /* turn on 100 Mbps LED (LED_LINK100) */
547 ledover
|= PHY_M_LED_MO_100
;
551 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
555 /* Enable phy interrupt on auto-negotiation complete (or link up) */
556 if (sky2
->autoneg
== AUTONEG_ENABLE
)
557 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
559 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
562 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
565 static const u32 phy_power
[]
566 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
568 /* looks like this XL is back asswards .. */
569 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
572 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
575 /* Turn off phy power saving */
576 reg1
&= ~phy_power
[port
];
578 reg1
|= phy_power
[port
];
580 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
581 sky2_pci_read32(hw
, PCI_DEV_REG1
);
585 /* Force a renegotiation */
586 static void sky2_phy_reinit(struct sky2_port
*sky2
)
588 spin_lock_bh(&sky2
->phy_lock
);
589 sky2_phy_init(sky2
->hw
, sky2
->port
);
590 spin_unlock_bh(&sky2
->phy_lock
);
593 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
595 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
598 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
600 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
601 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
603 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
605 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
606 /* WA DEV_472 -- looks like crossed wires on port 2 */
607 /* clear GMAC 1 Control reset */
608 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
610 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
611 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
612 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
613 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
614 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
617 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
619 /* Enable Transmit FIFO Underrun */
620 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
622 spin_lock_bh(&sky2
->phy_lock
);
623 sky2_phy_init(hw
, port
);
624 spin_unlock_bh(&sky2
->phy_lock
);
627 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
628 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
630 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
631 gma_read16(hw
, port
, i
);
632 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
634 /* transmit control */
635 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
637 /* receive control reg: unicast + multicast + no FCS */
638 gma_write16(hw
, port
, GM_RX_CTRL
,
639 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
641 /* transmit flow control */
642 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
644 /* transmit parameter */
645 gma_write16(hw
, port
, GM_TX_PARAM
,
646 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
647 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
648 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
649 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
651 /* serial mode register */
652 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
653 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
655 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
656 reg
|= GM_SMOD_JUMBO_ENA
;
658 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
660 /* virtual address for data */
661 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
663 /* physical address: used for pause frames */
664 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
666 /* ignore counter overflows */
667 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
668 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
669 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
671 /* Configure Rx MAC FIFO */
672 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
673 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
674 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
676 /* Flush Rx MAC FIFO on any flow control or error */
677 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
679 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
680 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
+1);
682 /* Configure Tx MAC FIFO */
683 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
684 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
686 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
687 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768/8);
688 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
689 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
690 /* set Tx GMAC FIFO Almost Empty Threshold */
691 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
692 /* Disable Store & Forward mode for TX */
693 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
699 /* Assign Ram Buffer allocation to queue */
700 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
704 /* convert from K bytes to qwords used for hw register */
707 end
= start
+ space
- 1;
709 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
710 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
711 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
712 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
713 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
715 if (q
== Q_R1
|| q
== Q_R2
) {
716 u32 tp
= space
- space
/4;
718 /* On receive queue's set the thresholds
719 * give receiver priority when > 3/4 full
720 * send pause when down to 2K
722 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
723 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
726 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
727 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
729 /* Enable store & forward on Tx queue's because
730 * Tx FIFO is only 1K on Yukon
732 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
735 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
736 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
739 /* Setup Bus Memory Interface */
740 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
742 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
743 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
744 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
745 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
748 /* Setup prefetch unit registers. This is the interface between
749 * hardware and driver list elements
751 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
754 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
755 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
756 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
757 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
758 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
759 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
761 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
764 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
766 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
768 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
773 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
774 struct sky2_tx_le
*le
)
776 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
779 /* Update chip's next pointer */
780 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
782 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
784 sky2_write16(hw
, q
, idx
);
789 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
791 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
792 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
797 /* Return high part of DMA address (could be 32 or 64 bit) */
798 static inline u32
high32(dma_addr_t a
)
800 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
803 /* Build description to hardware for one receive segment */
804 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
805 dma_addr_t map
, unsigned len
)
807 struct sky2_rx_le
*le
;
808 u32 hi
= high32(map
);
810 if (sky2
->rx_addr64
!= hi
) {
811 le
= sky2_next_rx(sky2
);
812 le
->addr
= cpu_to_le32(hi
);
813 le
->opcode
= OP_ADDR64
| HW_OWNER
;
814 sky2
->rx_addr64
= high32(map
+ len
);
817 le
= sky2_next_rx(sky2
);
818 le
->addr
= cpu_to_le32((u32
) map
);
819 le
->length
= cpu_to_le16(len
);
820 le
->opcode
= op
| HW_OWNER
;
823 /* Build description to hardware for one possibly fragmented skb */
824 static void sky2_rx_submit(struct sky2_port
*sky2
,
825 const struct rx_ring_info
*re
)
829 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
831 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
832 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
836 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
839 struct sk_buff
*skb
= re
->skb
;
842 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
843 pci_unmap_len_set(re
, data_size
, size
);
845 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
846 re
->frag_addr
[i
] = pci_map_page(pdev
,
847 skb_shinfo(skb
)->frags
[i
].page
,
848 skb_shinfo(skb
)->frags
[i
].page_offset
,
849 skb_shinfo(skb
)->frags
[i
].size
,
853 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
855 struct sk_buff
*skb
= re
->skb
;
858 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
861 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
862 pci_unmap_page(pdev
, re
->frag_addr
[i
],
863 skb_shinfo(skb
)->frags
[i
].size
,
867 /* Tell chip where to start receive checksum.
868 * Actually has two checksums, but set both same to avoid possible byte
871 static void rx_set_checksum(struct sky2_port
*sky2
)
873 struct sky2_rx_le
*le
;
875 le
= sky2_next_rx(sky2
);
876 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
878 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
880 sky2_write32(sky2
->hw
,
881 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
882 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
887 * The RX Stop command will not work for Yukon-2 if the BMU does not
888 * reach the end of packet and since we can't make sure that we have
889 * incoming data, we must reset the BMU while it is not doing a DMA
890 * transfer. Since it is possible that the RX path is still active,
891 * the RX RAM buffer will be stopped first, so any possible incoming
892 * data will not trigger a DMA. After the RAM buffer is stopped, the
893 * BMU is polled until any DMA in progress is ended and only then it
896 static void sky2_rx_stop(struct sky2_port
*sky2
)
898 struct sky2_hw
*hw
= sky2
->hw
;
899 unsigned rxq
= rxqaddr
[sky2
->port
];
902 /* disable the RAM Buffer receive queue */
903 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
905 for (i
= 0; i
< 0xffff; i
++)
906 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
907 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
910 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
913 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
915 /* reset the Rx prefetch unit */
916 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
919 /* Clean out receive buffer area, assumes receiver hardware stopped */
920 static void sky2_rx_clean(struct sky2_port
*sky2
)
924 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
925 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
926 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
929 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
936 /* Basic MII support */
937 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
939 struct mii_ioctl_data
*data
= if_mii(ifr
);
940 struct sky2_port
*sky2
= netdev_priv(dev
);
941 struct sky2_hw
*hw
= sky2
->hw
;
942 int err
= -EOPNOTSUPP
;
944 if (!netif_running(dev
))
945 return -ENODEV
; /* Phy still in reset */
949 data
->phy_id
= PHY_ADDR_MARV
;
955 spin_lock_bh(&sky2
->phy_lock
);
956 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
957 spin_unlock_bh(&sky2
->phy_lock
);
964 if (!capable(CAP_NET_ADMIN
))
967 spin_lock_bh(&sky2
->phy_lock
);
968 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
970 spin_unlock_bh(&sky2
->phy_lock
);
976 #ifdef SKY2_VLAN_TAG_USED
977 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
979 struct sky2_port
*sky2
= netdev_priv(dev
);
980 struct sky2_hw
*hw
= sky2
->hw
;
981 u16 port
= sky2
->port
;
983 netif_tx_lock_bh(dev
);
985 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
986 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
989 netif_tx_unlock_bh(dev
);
992 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
994 struct sky2_port
*sky2
= netdev_priv(dev
);
995 struct sky2_hw
*hw
= sky2
->hw
;
996 u16 port
= sky2
->port
;
998 netif_tx_lock_bh(dev
);
1000 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
1001 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
1003 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
1005 netif_tx_unlock_bh(dev
);
1010 * Allocate an skb for receiving. If the MTU is large enough
1011 * make the skb non-linear with a fragment list of pages.
1013 * It appears the hardware has a bug in the FIFO logic that
1014 * cause it to hang if the FIFO gets overrun and the receive buffer
1015 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1016 * aligned except if slab debugging is enabled.
1018 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1020 struct sk_buff
*skb
;
1024 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1028 p
= (unsigned long) skb
->data
;
1029 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1031 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1032 struct page
*page
= alloc_page(GFP_ATOMIC
);
1036 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1047 * Allocate and setup receiver buffer pool.
1048 * Normal case this ends up creating one list element for skb
1049 * in the receive ring. Worst case if using large MTU and each
1050 * allocation falls on a different 64 bit region, that results
1051 * in 6 list elements per ring entry.
1052 * One element is used for checksum enable/disable, and one
1053 * extra to avoid wrap.
1055 static int sky2_rx_start(struct sky2_port
*sky2
)
1057 struct sky2_hw
*hw
= sky2
->hw
;
1058 struct rx_ring_info
*re
;
1059 unsigned rxq
= rxqaddr
[sky2
->port
];
1060 unsigned i
, size
, space
, thresh
;
1062 sky2
->rx_put
= sky2
->rx_next
= 0;
1065 /* On PCI express lowering the watermark gives better performance */
1066 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1067 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1069 /* These chips have no ram buffer?
1070 * MAC Rx RAM Read is controlled by hardware */
1071 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1072 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
1073 || hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1074 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1076 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1078 rx_set_checksum(sky2
);
1080 /* Space needed for frame data + headers rounded up */
1081 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1084 /* Stopping point for hardware truncation */
1085 thresh
= (size
- 8) / sizeof(u32
);
1087 /* Account for overhead of skb - to avoid order > 0 allocation */
1088 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1089 + sizeof(struct skb_shared_info
);
1091 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1092 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1094 if (sky2
->rx_nfrags
!= 0) {
1095 /* Compute residue after pages */
1096 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1103 /* Optimize to handle small packets and headers */
1104 if (size
< copybreak
)
1106 if (size
< ETH_HLEN
)
1109 sky2
->rx_data_size
= size
;
1112 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1113 re
= sky2
->rx_ring
+ i
;
1115 re
->skb
= sky2_rx_alloc(sky2
);
1119 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1120 sky2_rx_submit(sky2
, re
);
1124 * The receiver hangs if it receives frames larger than the
1125 * packet buffer. As a workaround, truncate oversize frames, but
1126 * the register is limited to 9 bits, so if you do frames > 2052
1127 * you better get the MTU right!
1130 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1132 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1133 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1136 /* Tell chip about available buffers */
1137 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1140 sky2_rx_clean(sky2
);
1144 /* Bring up network interface. */
1145 static int sky2_up(struct net_device
*dev
)
1147 struct sky2_port
*sky2
= netdev_priv(dev
);
1148 struct sky2_hw
*hw
= sky2
->hw
;
1149 unsigned port
= sky2
->port
;
1151 int cap
, err
= -ENOMEM
;
1152 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1155 * On dual port PCI-X card, there is an problem where status
1156 * can be received out of order due to split transactions
1158 if (otherdev
&& netif_running(otherdev
) &&
1159 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1160 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1163 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1164 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1165 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1171 if (netif_msg_ifup(sky2
))
1172 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1174 /* must be power of 2 */
1175 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1177 sizeof(struct sky2_tx_le
),
1182 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1186 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1188 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1192 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1194 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1199 sky2_phy_power(hw
, port
, 1);
1201 sky2_mac_init(hw
, port
);
1203 /* Register is number of 4K blocks on internal RAM buffer. */
1204 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1205 printk(KERN_INFO PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1211 rxspace
= ramsize
/ 2;
1213 rxspace
= 8 + (2*(ramsize
- 16))/3;
1215 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1216 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1218 /* Make sure SyncQ is disabled */
1219 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1223 sky2_qset(hw
, txqaddr
[port
]);
1225 /* Set almost empty threshold */
1226 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1227 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1228 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1230 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1233 err
= sky2_rx_start(sky2
);
1237 /* Enable interrupts from phy/mac for port */
1238 imask
= sky2_read32(hw
, B0_IMSK
);
1239 imask
|= portirq_msk
[port
];
1240 sky2_write32(hw
, B0_IMSK
, imask
);
1246 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1247 sky2
->rx_le
, sky2
->rx_le_map
);
1251 pci_free_consistent(hw
->pdev
,
1252 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1253 sky2
->tx_le
, sky2
->tx_le_map
);
1256 kfree(sky2
->tx_ring
);
1257 kfree(sky2
->rx_ring
);
1259 sky2
->tx_ring
= NULL
;
1260 sky2
->rx_ring
= NULL
;
1264 /* Modular subtraction in ring */
1265 static inline int tx_dist(unsigned tail
, unsigned head
)
1267 return (head
- tail
) & (TX_RING_SIZE
- 1);
1270 /* Number of list elements available for next tx */
1271 static inline int tx_avail(const struct sky2_port
*sky2
)
1273 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1276 /* Estimate of number of transmit list elements required */
1277 static unsigned tx_le_req(const struct sk_buff
*skb
)
1281 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1282 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1284 if (skb_is_gso(skb
))
1287 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1294 * Put one packet in ring for transmit.
1295 * A single packet can generate multiple list elements, and
1296 * the number of ring elements will probably be less than the number
1297 * of list elements used.
1299 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1301 struct sky2_port
*sky2
= netdev_priv(dev
);
1302 struct sky2_hw
*hw
= sky2
->hw
;
1303 struct sky2_tx_le
*le
= NULL
;
1304 struct tx_ring_info
*re
;
1311 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1312 return NETDEV_TX_BUSY
;
1314 if (unlikely(netif_msg_tx_queued(sky2
)))
1315 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1316 dev
->name
, sky2
->tx_prod
, skb
->len
);
1318 len
= skb_headlen(skb
);
1319 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1320 addr64
= high32(mapping
);
1322 /* Send high bits if changed or crosses boundary */
1323 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1324 le
= get_tx_le(sky2
);
1325 le
->addr
= cpu_to_le32(addr64
);
1326 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1327 sky2
->tx_addr64
= high32(mapping
+ len
);
1330 /* Check for TCP Segmentation Offload */
1331 mss
= skb_shinfo(skb
)->gso_size
;
1333 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1334 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1337 if (mss
!= sky2
->tx_last_mss
) {
1338 le
= get_tx_le(sky2
);
1339 le
->addr
= cpu_to_le32(mss
);
1340 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1341 sky2
->tx_last_mss
= mss
;
1346 #ifdef SKY2_VLAN_TAG_USED
1347 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1348 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1350 le
= get_tx_le(sky2
);
1352 le
->opcode
= OP_VLAN
|HW_OWNER
;
1354 le
->opcode
|= OP_VLAN
;
1355 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1360 /* Handle TCP checksum offload */
1361 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1362 unsigned offset
= skb
->h
.raw
- skb
->data
;
1365 tcpsum
= offset
<< 16; /* sum start */
1366 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1368 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1369 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1372 if (tcpsum
!= sky2
->tx_tcpsum
) {
1373 sky2
->tx_tcpsum
= tcpsum
;
1375 le
= get_tx_le(sky2
);
1376 le
->addr
= cpu_to_le32(tcpsum
);
1377 le
->length
= 0; /* initial checksum value */
1378 le
->ctrl
= 1; /* one packet */
1379 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1383 le
= get_tx_le(sky2
);
1384 le
->addr
= cpu_to_le32((u32
) mapping
);
1385 le
->length
= cpu_to_le16(len
);
1387 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1389 re
= tx_le_re(sky2
, le
);
1391 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1392 pci_unmap_len_set(re
, maplen
, len
);
1394 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1395 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1397 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1398 frag
->size
, PCI_DMA_TODEVICE
);
1399 addr64
= high32(mapping
);
1400 if (addr64
!= sky2
->tx_addr64
) {
1401 le
= get_tx_le(sky2
);
1402 le
->addr
= cpu_to_le32(addr64
);
1404 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1405 sky2
->tx_addr64
= addr64
;
1408 le
= get_tx_le(sky2
);
1409 le
->addr
= cpu_to_le32((u32
) mapping
);
1410 le
->length
= cpu_to_le16(frag
->size
);
1412 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1414 re
= tx_le_re(sky2
, le
);
1416 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1417 pci_unmap_len_set(re
, maplen
, frag
->size
);
1422 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1423 netif_stop_queue(dev
);
1425 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1427 dev
->trans_start
= jiffies
;
1428 return NETDEV_TX_OK
;
1432 * Free ring elements from starting at tx_cons until "done"
1434 * NB: the hardware will tell us about partial completion of multi-part
1435 * buffers so make sure not to free skb to early.
1437 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1439 struct net_device
*dev
= sky2
->netdev
;
1440 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1443 BUG_ON(done
>= TX_RING_SIZE
);
1445 for (idx
= sky2
->tx_cons
; idx
!= done
;
1446 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1447 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1448 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1450 switch(le
->opcode
& ~HW_OWNER
) {
1453 pci_unmap_single(pdev
,
1454 pci_unmap_addr(re
, mapaddr
),
1455 pci_unmap_len(re
, maplen
),
1459 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1460 pci_unmap_len(re
, maplen
),
1465 if (le
->ctrl
& EOP
) {
1466 if (unlikely(netif_msg_tx_done(sky2
)))
1467 printk(KERN_DEBUG
"%s: tx done %u\n",
1469 dev_kfree_skb_any(re
->skb
);
1472 le
->opcode
= 0; /* paranoia */
1475 sky2
->tx_cons
= idx
;
1476 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1477 netif_wake_queue(dev
);
1480 /* Cleanup all untransmitted buffers, assume transmitter not running */
1481 static void sky2_tx_clean(struct net_device
*dev
)
1483 struct sky2_port
*sky2
= netdev_priv(dev
);
1485 netif_tx_lock_bh(dev
);
1486 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1487 netif_tx_unlock_bh(dev
);
1490 /* Network shutdown */
1491 static int sky2_down(struct net_device
*dev
)
1493 struct sky2_port
*sky2
= netdev_priv(dev
);
1494 struct sky2_hw
*hw
= sky2
->hw
;
1495 unsigned port
= sky2
->port
;
1499 /* Never really got started! */
1503 if (netif_msg_ifdown(sky2
))
1504 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1506 /* Stop more packets from being queued */
1507 netif_stop_queue(dev
);
1509 /* Disable port IRQ */
1510 imask
= sky2_read32(hw
, B0_IMSK
);
1511 imask
&= ~portirq_msk
[port
];
1512 sky2_write32(hw
, B0_IMSK
, imask
);
1515 * Both ports share the NAPI poll on port 0, so if necessary undo the
1516 * the disable that is done in dev_close.
1518 if (sky2
->port
== 0 && hw
->ports
> 1)
1519 netif_poll_enable(dev
);
1521 sky2_gmac_reset(hw
, port
);
1523 /* Stop transmitter */
1524 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1525 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1527 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1528 RB_RST_SET
| RB_DIS_OP_MD
);
1530 /* WA for dev. #4.209 */
1531 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1532 && (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
|| hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1533 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1534 sky2
->speed
!= SPEED_1000
?
1535 TX_STFW_ENA
: TX_STFW_DIS
);
1537 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1538 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1539 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1541 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1543 /* Workaround shared GMAC reset */
1544 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1545 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1546 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1548 /* Disable Force Sync bit and Enable Alloc bit */
1549 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1550 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1552 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1553 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1554 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1556 /* Reset the PCI FIFO of the async Tx queue */
1557 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1558 BMU_RST_SET
| BMU_FIFO_RST
);
1560 /* Reset the Tx prefetch units */
1561 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1564 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1568 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1569 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1571 sky2_phy_power(hw
, port
, 0);
1573 /* turn off LED's */
1574 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1576 synchronize_irq(hw
->pdev
->irq
);
1579 sky2_rx_clean(sky2
);
1581 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1582 sky2
->rx_le
, sky2
->rx_le_map
);
1583 kfree(sky2
->rx_ring
);
1585 pci_free_consistent(hw
->pdev
,
1586 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1587 sky2
->tx_le
, sky2
->tx_le_map
);
1588 kfree(sky2
->tx_ring
);
1593 sky2
->rx_ring
= NULL
;
1594 sky2
->tx_ring
= NULL
;
1599 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1601 if (!sky2_is_copper(hw
))
1604 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1605 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1607 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1608 case PHY_M_PS_SPEED_1000
:
1610 case PHY_M_PS_SPEED_100
:
1617 static void sky2_link_up(struct sky2_port
*sky2
)
1619 struct sky2_hw
*hw
= sky2
->hw
;
1620 unsigned port
= sky2
->port
;
1622 static const char *fc_name
[] = {
1630 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1631 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1632 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1634 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1636 netif_carrier_on(sky2
->netdev
);
1637 netif_wake_queue(sky2
->netdev
);
1639 /* Turn on link LED */
1640 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1641 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1643 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1644 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1645 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1647 switch(sky2
->speed
) {
1649 led
|= PHY_M_LEDC_INIT_CTRL(7);
1653 led
|= PHY_M_LEDC_STA1_CTRL(7);
1657 led
|= PHY_M_LEDC_STA0_CTRL(7);
1661 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1662 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1663 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1666 if (netif_msg_link(sky2
))
1667 printk(KERN_INFO PFX
1668 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1669 sky2
->netdev
->name
, sky2
->speed
,
1670 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1671 fc_name
[sky2
->flow_status
]);
1674 static void sky2_link_down(struct sky2_port
*sky2
)
1676 struct sky2_hw
*hw
= sky2
->hw
;
1677 unsigned port
= sky2
->port
;
1680 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1682 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1683 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1684 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1686 if (sky2
->flow_status
== FC_RX
) {
1687 /* restore Asymmetric Pause bit */
1688 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1689 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1693 netif_carrier_off(sky2
->netdev
);
1694 netif_stop_queue(sky2
->netdev
);
1696 /* Turn on link LED */
1697 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1699 if (netif_msg_link(sky2
))
1700 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1702 sky2_phy_init(hw
, port
);
1705 static enum flow_control
sky2_flow(int rx
, int tx
)
1708 return tx
? FC_BOTH
: FC_RX
;
1710 return tx
? FC_TX
: FC_NONE
;
1713 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1715 struct sky2_hw
*hw
= sky2
->hw
;
1716 unsigned port
= sky2
->port
;
1719 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1721 if (lpa
& PHY_M_AN_RF
) {
1722 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1726 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1727 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1728 sky2
->netdev
->name
);
1732 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1733 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1735 /* Pause bits are offset (9..8) */
1736 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1739 sky2
->flow_status
= sky2_flow(aux
& PHY_M_PS_RX_P_EN
,
1740 aux
& PHY_M_PS_TX_P_EN
);
1742 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
1743 && hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
1744 sky2
->flow_status
= FC_NONE
;
1746 if (aux
& PHY_M_PS_RX_P_EN
)
1747 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1749 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1754 /* Interrupt from PHY */
1755 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1757 struct net_device
*dev
= hw
->dev
[port
];
1758 struct sky2_port
*sky2
= netdev_priv(dev
);
1759 u16 istatus
, phystat
;
1761 if (!netif_running(dev
))
1764 spin_lock(&sky2
->phy_lock
);
1765 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1766 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1768 if (netif_msg_intr(sky2
))
1769 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1770 sky2
->netdev
->name
, istatus
, phystat
);
1772 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1773 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1778 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1779 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1781 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1783 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1785 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1786 if (phystat
& PHY_M_PS_LINK_UP
)
1789 sky2_link_down(sky2
);
1792 spin_unlock(&sky2
->phy_lock
);
1796 /* Transmit timeout is only called if we are running, carries is up
1797 * and tx queue is full (stopped).
1799 static void sky2_tx_timeout(struct net_device
*dev
)
1801 struct sky2_port
*sky2
= netdev_priv(dev
);
1802 struct sky2_hw
*hw
= sky2
->hw
;
1803 unsigned txq
= txqaddr
[sky2
->port
];
1806 if (netif_msg_timer(sky2
))
1807 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1809 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1810 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1812 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1814 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1816 if (report
!= done
) {
1817 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1819 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1820 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1821 } else if (report
!= sky2
->tx_cons
) {
1822 printk(KERN_INFO PFX
"status report lost?\n");
1824 netif_tx_lock_bh(dev
);
1825 sky2_tx_complete(sky2
, report
);
1826 netif_tx_unlock_bh(dev
);
1828 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1830 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1831 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1836 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1840 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1842 struct sky2_port
*sky2
= netdev_priv(dev
);
1843 struct sky2_hw
*hw
= sky2
->hw
;
1848 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1851 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1854 if (!netif_running(dev
)) {
1859 imask
= sky2_read32(hw
, B0_IMSK
);
1860 sky2_write32(hw
, B0_IMSK
, 0);
1862 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1863 netif_stop_queue(dev
);
1864 netif_poll_disable(hw
->dev
[0]);
1866 synchronize_irq(hw
->pdev
->irq
);
1868 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1869 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1871 sky2_rx_clean(sky2
);
1875 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1876 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1878 if (dev
->mtu
> ETH_DATA_LEN
)
1879 mode
|= GM_SMOD_JUMBO_ENA
;
1881 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1883 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1885 err
= sky2_rx_start(sky2
);
1886 sky2_write32(hw
, B0_IMSK
, imask
);
1891 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1893 netif_poll_enable(hw
->dev
[0]);
1894 netif_wake_queue(dev
);
1900 /* For small just reuse existing skb for next receive */
1901 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1902 const struct rx_ring_info
*re
,
1905 struct sk_buff
*skb
;
1907 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1909 skb_reserve(skb
, 2);
1910 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1911 length
, PCI_DMA_FROMDEVICE
);
1912 memcpy(skb
->data
, re
->skb
->data
, length
);
1913 skb
->ip_summed
= re
->skb
->ip_summed
;
1914 skb
->csum
= re
->skb
->csum
;
1915 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1916 length
, PCI_DMA_FROMDEVICE
);
1917 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1918 skb_put(skb
, length
);
1923 /* Adjust length of skb with fragments to match received data */
1924 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1925 unsigned int length
)
1930 /* put header into skb */
1931 size
= min(length
, hdr_space
);
1936 num_frags
= skb_shinfo(skb
)->nr_frags
;
1937 for (i
= 0; i
< num_frags
; i
++) {
1938 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1941 /* don't need this page */
1942 __free_page(frag
->page
);
1943 --skb_shinfo(skb
)->nr_frags
;
1945 size
= min(length
, (unsigned) PAGE_SIZE
);
1948 skb
->data_len
+= size
;
1949 skb
->truesize
+= size
;
1956 /* Normal packet - take skb from ring element and put in a new one */
1957 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
1958 struct rx_ring_info
*re
,
1959 unsigned int length
)
1961 struct sk_buff
*skb
, *nskb
;
1962 unsigned hdr_space
= sky2
->rx_data_size
;
1964 pr_debug(PFX
"receive new length=%d\n", length
);
1966 /* Don't be tricky about reusing pages (yet) */
1967 nskb
= sky2_rx_alloc(sky2
);
1968 if (unlikely(!nskb
))
1972 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1974 prefetch(skb
->data
);
1976 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
1978 if (skb_shinfo(skb
)->nr_frags
)
1979 skb_put_frags(skb
, hdr_space
, length
);
1981 skb_put(skb
, length
);
1986 * Receive one packet.
1987 * For larger packets, get new buffer.
1989 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
1990 u16 length
, u32 status
)
1992 struct sky2_port
*sky2
= netdev_priv(dev
);
1993 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1994 struct sk_buff
*skb
= NULL
;
1996 if (unlikely(netif_msg_rx_status(sky2
)))
1997 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1998 dev
->name
, sky2
->rx_next
, status
, length
);
2000 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2001 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2003 if (status
& GMR_FS_ANY_ERR
)
2006 if (!(status
& GMR_FS_RX_OK
))
2009 if (length
> dev
->mtu
+ ETH_HLEN
)
2012 if (length
< copybreak
)
2013 skb
= receive_copy(sky2
, re
, length
);
2015 skb
= receive_new(sky2
, re
, length
);
2017 sky2_rx_submit(sky2
, re
);
2022 ++sky2
->net_stats
.rx_over_errors
;
2026 ++sky2
->net_stats
.rx_errors
;
2027 if (status
& GMR_FS_RX_FF_OV
) {
2028 sky2
->net_stats
.rx_fifo_errors
++;
2032 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2033 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2034 dev
->name
, status
, length
);
2036 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2037 sky2
->net_stats
.rx_length_errors
++;
2038 if (status
& GMR_FS_FRAGMENT
)
2039 sky2
->net_stats
.rx_frame_errors
++;
2040 if (status
& GMR_FS_CRC_ERR
)
2041 sky2
->net_stats
.rx_crc_errors
++;
2046 /* Transmit complete */
2047 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2049 struct sky2_port
*sky2
= netdev_priv(dev
);
2051 if (netif_running(dev
)) {
2053 sky2_tx_complete(sky2
, last
);
2054 netif_tx_unlock(dev
);
2058 /* Process status response ring */
2059 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2061 struct sky2_port
*sky2
;
2063 unsigned buf_write
[2] = { 0, 0 };
2064 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2068 while (hw
->st_idx
!= hwidx
) {
2069 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2070 struct net_device
*dev
;
2071 struct sk_buff
*skb
;
2075 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2077 BUG_ON(le
->link
>= 2);
2078 dev
= hw
->dev
[le
->link
];
2080 sky2
= netdev_priv(dev
);
2081 length
= le16_to_cpu(le
->length
);
2082 status
= le32_to_cpu(le
->status
);
2084 switch (le
->opcode
& ~HW_OWNER
) {
2086 skb
= sky2_receive(dev
, length
, status
);
2090 skb
->protocol
= eth_type_trans(skb
, dev
);
2091 dev
->last_rx
= jiffies
;
2093 #ifdef SKY2_VLAN_TAG_USED
2094 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2095 vlan_hwaccel_receive_skb(skb
,
2097 be16_to_cpu(sky2
->rx_tag
));
2100 netif_receive_skb(skb
);
2102 /* Update receiver after 16 frames */
2103 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2105 sky2_put_idx(hw
, rxqaddr
[le
->link
], sky2
->rx_put
);
2106 buf_write
[le
->link
] = 0;
2109 /* Stop after net poll weight */
2110 if (++work_done
>= to_do
)
2114 #ifdef SKY2_VLAN_TAG_USED
2116 sky2
->rx_tag
= length
;
2120 sky2
->rx_tag
= length
;
2124 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2125 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2126 skb
->csum
= status
& 0xffff;
2130 /* TX index reports status for both ports */
2131 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2132 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2134 sky2_tx_done(hw
->dev
[1],
2135 ((status
>> 24) & 0xff)
2136 | (u16
)(length
& 0xf) << 8);
2140 if (net_ratelimit())
2141 printk(KERN_WARNING PFX
2142 "unknown status opcode 0x%x\n", le
->opcode
);
2147 /* Fully processed status ring so clear irq */
2148 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2152 sky2
= netdev_priv(hw
->dev
[0]);
2153 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2157 sky2
= netdev_priv(hw
->dev
[1]);
2158 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2164 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2166 struct net_device
*dev
= hw
->dev
[port
];
2168 if (net_ratelimit())
2169 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2172 if (status
& Y2_IS_PAR_RD1
) {
2173 if (net_ratelimit())
2174 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2177 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2180 if (status
& Y2_IS_PAR_WR1
) {
2181 if (net_ratelimit())
2182 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2185 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2188 if (status
& Y2_IS_PAR_MAC1
) {
2189 if (net_ratelimit())
2190 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2191 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2194 if (status
& Y2_IS_PAR_RX1
) {
2195 if (net_ratelimit())
2196 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2197 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2200 if (status
& Y2_IS_TCP_TXA1
) {
2201 if (net_ratelimit())
2202 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2204 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2208 static void sky2_hw_intr(struct sky2_hw
*hw
)
2210 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2212 if (status
& Y2_IS_TIST_OV
)
2213 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2215 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2218 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2219 if (net_ratelimit())
2220 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2221 pci_name(hw
->pdev
), pci_err
);
2223 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2224 sky2_pci_write16(hw
, PCI_STATUS
,
2225 pci_err
| PCI_STATUS_ERROR_BITS
);
2226 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2229 if (status
& Y2_IS_PCI_EXP
) {
2230 /* PCI-Express uncorrectable Error occurred */
2233 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2235 if (net_ratelimit())
2236 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2237 pci_name(hw
->pdev
), pex_err
);
2239 /* clear the interrupt */
2240 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2241 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2243 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2245 if (pex_err
& PEX_FATAL_ERRORS
) {
2246 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2247 hwmsk
&= ~Y2_IS_PCI_EXP
;
2248 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2252 if (status
& Y2_HWE_L1_MASK
)
2253 sky2_hw_error(hw
, 0, status
);
2255 if (status
& Y2_HWE_L1_MASK
)
2256 sky2_hw_error(hw
, 1, status
);
2259 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2261 struct net_device
*dev
= hw
->dev
[port
];
2262 struct sky2_port
*sky2
= netdev_priv(dev
);
2263 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2265 if (netif_msg_intr(sky2
))
2266 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2269 if (status
& GM_IS_RX_FF_OR
) {
2270 ++sky2
->net_stats
.rx_fifo_errors
;
2271 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2274 if (status
& GM_IS_TX_FF_UR
) {
2275 ++sky2
->net_stats
.tx_fifo_errors
;
2276 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2280 /* This should never happen it is a fatal situation */
2281 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2282 const char *rxtx
, u32 mask
)
2284 struct net_device
*dev
= hw
->dev
[port
];
2285 struct sky2_port
*sky2
= netdev_priv(dev
);
2288 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2289 dev
? dev
->name
: "<not registered>", rxtx
);
2291 imask
= sky2_read32(hw
, B0_IMSK
);
2293 sky2_write32(hw
, B0_IMSK
, imask
);
2296 spin_lock(&sky2
->phy_lock
);
2297 sky2_link_down(sky2
);
2298 spin_unlock(&sky2
->phy_lock
);
2302 /* If idle then force a fake soft NAPI poll once a second
2303 * to work around cases where sharing an edge triggered interrupt.
2305 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2307 if (idle_timeout
> 0)
2308 mod_timer(&hw
->idle_timer
,
2309 jiffies
+ msecs_to_jiffies(idle_timeout
));
2312 static void sky2_idle(unsigned long arg
)
2314 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2315 struct net_device
*dev
= hw
->dev
[0];
2317 if (__netif_rx_schedule_prep(dev
))
2318 __netif_rx_schedule(dev
);
2320 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2324 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2326 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2327 int work_limit
= min(dev0
->quota
, *budget
);
2329 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2331 if (status
& Y2_IS_HW_ERR
)
2334 if (status
& Y2_IS_IRQ_PHY1
)
2335 sky2_phy_intr(hw
, 0);
2337 if (status
& Y2_IS_IRQ_PHY2
)
2338 sky2_phy_intr(hw
, 1);
2340 if (status
& Y2_IS_IRQ_MAC1
)
2341 sky2_mac_intr(hw
, 0);
2343 if (status
& Y2_IS_IRQ_MAC2
)
2344 sky2_mac_intr(hw
, 1);
2346 if (status
& Y2_IS_CHK_RX1
)
2347 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2349 if (status
& Y2_IS_CHK_RX2
)
2350 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2352 if (status
& Y2_IS_CHK_TXA1
)
2353 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2355 if (status
& Y2_IS_CHK_TXA2
)
2356 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2358 work_done
= sky2_status_intr(hw
, work_limit
);
2359 if (work_done
< work_limit
) {
2360 netif_rx_complete(dev0
);
2362 sky2_read32(hw
, B0_Y2_SP_LISR
);
2365 *budget
-= work_done
;
2366 dev0
->quota
-= work_done
;
2371 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2373 struct sky2_hw
*hw
= dev_id
;
2374 struct net_device
*dev0
= hw
->dev
[0];
2377 /* Reading this mask interrupts as side effect */
2378 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2379 if (status
== 0 || status
== ~0)
2382 prefetch(&hw
->st_le
[hw
->st_idx
]);
2383 if (likely(__netif_rx_schedule_prep(dev0
)))
2384 __netif_rx_schedule(dev0
);
2389 #ifdef CONFIG_NET_POLL_CONTROLLER
2390 static void sky2_netpoll(struct net_device
*dev
)
2392 struct sky2_port
*sky2
= netdev_priv(dev
);
2393 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2395 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2396 __netif_rx_schedule(dev0
);
2400 /* Chip internal frequency for clock calculations */
2401 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2403 switch (hw
->chip_id
) {
2404 case CHIP_ID_YUKON_EC
:
2405 case CHIP_ID_YUKON_EC_U
:
2406 return 125; /* 125 Mhz */
2407 case CHIP_ID_YUKON_FE
:
2408 return 100; /* 100 Mhz */
2409 default: /* YUKON_XL */
2410 return 156; /* 156 Mhz */
2414 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2416 return sky2_mhz(hw
) * us
;
2419 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2421 return clk
/ sky2_mhz(hw
);
2425 static int sky2_reset(struct sky2_hw
*hw
)
2431 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2433 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2434 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2435 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2436 pci_name(hw
->pdev
), hw
->chip_id
);
2440 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2442 /* This rev is really old, and requires untested workarounds */
2443 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2444 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2445 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2446 hw
->chip_id
, hw
->chip_rev
);
2451 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2452 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2453 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2457 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2458 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2460 /* clear PCI errors, if any */
2461 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2463 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2464 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2467 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2469 /* clear any PEX errors */
2470 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2471 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2474 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2476 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2477 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2478 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2482 sky2_set_power_state(hw
, PCI_D0
);
2484 for (i
= 0; i
< hw
->ports
; i
++) {
2485 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2486 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2489 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2491 /* Clear I2C IRQ noise */
2492 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2494 /* turn off hardware timer (unused) */
2495 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2496 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2498 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2500 /* Turn off descriptor polling */
2501 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2503 /* Turn off receive timestamp */
2504 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2505 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2507 /* enable the Tx Arbiters */
2508 for (i
= 0; i
< hw
->ports
; i
++)
2509 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2511 /* Initialize ram interface */
2512 for (i
= 0; i
< hw
->ports
; i
++) {
2513 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2515 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2516 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2517 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2518 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2519 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2520 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2521 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2522 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2523 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2524 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2525 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2526 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2529 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2531 for (i
= 0; i
< hw
->ports
; i
++)
2532 sky2_gmac_reset(hw
, i
);
2534 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2537 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2538 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2540 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2541 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2543 /* Set the list last index */
2544 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2546 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2547 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2549 /* set Status-FIFO ISR watermark */
2550 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2551 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2553 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2555 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2556 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2557 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2559 /* enable status unit */
2560 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2562 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2563 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2564 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2569 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2571 if (sky2_is_copper(hw
)) {
2572 u32 modes
= SUPPORTED_10baseT_Half
2573 | SUPPORTED_10baseT_Full
2574 | SUPPORTED_100baseT_Half
2575 | SUPPORTED_100baseT_Full
2576 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2578 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2579 modes
|= SUPPORTED_1000baseT_Half
2580 | SUPPORTED_1000baseT_Full
;
2583 return SUPPORTED_1000baseT_Half
2584 | SUPPORTED_1000baseT_Full
2589 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2591 struct sky2_port
*sky2
= netdev_priv(dev
);
2592 struct sky2_hw
*hw
= sky2
->hw
;
2594 ecmd
->transceiver
= XCVR_INTERNAL
;
2595 ecmd
->supported
= sky2_supported_modes(hw
);
2596 ecmd
->phy_address
= PHY_ADDR_MARV
;
2597 if (sky2_is_copper(hw
)) {
2598 ecmd
->supported
= SUPPORTED_10baseT_Half
2599 | SUPPORTED_10baseT_Full
2600 | SUPPORTED_100baseT_Half
2601 | SUPPORTED_100baseT_Full
2602 | SUPPORTED_1000baseT_Half
2603 | SUPPORTED_1000baseT_Full
2604 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2605 ecmd
->port
= PORT_TP
;
2606 ecmd
->speed
= sky2
->speed
;
2608 ecmd
->speed
= SPEED_1000
;
2609 ecmd
->port
= PORT_FIBRE
;
2612 ecmd
->advertising
= sky2
->advertising
;
2613 ecmd
->autoneg
= sky2
->autoneg
;
2614 ecmd
->duplex
= sky2
->duplex
;
2618 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2620 struct sky2_port
*sky2
= netdev_priv(dev
);
2621 const struct sky2_hw
*hw
= sky2
->hw
;
2622 u32 supported
= sky2_supported_modes(hw
);
2624 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2625 ecmd
->advertising
= supported
;
2631 switch (ecmd
->speed
) {
2633 if (ecmd
->duplex
== DUPLEX_FULL
)
2634 setting
= SUPPORTED_1000baseT_Full
;
2635 else if (ecmd
->duplex
== DUPLEX_HALF
)
2636 setting
= SUPPORTED_1000baseT_Half
;
2641 if (ecmd
->duplex
== DUPLEX_FULL
)
2642 setting
= SUPPORTED_100baseT_Full
;
2643 else if (ecmd
->duplex
== DUPLEX_HALF
)
2644 setting
= SUPPORTED_100baseT_Half
;
2650 if (ecmd
->duplex
== DUPLEX_FULL
)
2651 setting
= SUPPORTED_10baseT_Full
;
2652 else if (ecmd
->duplex
== DUPLEX_HALF
)
2653 setting
= SUPPORTED_10baseT_Half
;
2661 if ((setting
& supported
) == 0)
2664 sky2
->speed
= ecmd
->speed
;
2665 sky2
->duplex
= ecmd
->duplex
;
2668 sky2
->autoneg
= ecmd
->autoneg
;
2669 sky2
->advertising
= ecmd
->advertising
;
2671 if (netif_running(dev
))
2672 sky2_phy_reinit(sky2
);
2677 static void sky2_get_drvinfo(struct net_device
*dev
,
2678 struct ethtool_drvinfo
*info
)
2680 struct sky2_port
*sky2
= netdev_priv(dev
);
2682 strcpy(info
->driver
, DRV_NAME
);
2683 strcpy(info
->version
, DRV_VERSION
);
2684 strcpy(info
->fw_version
, "N/A");
2685 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2688 static const struct sky2_stat
{
2689 char name
[ETH_GSTRING_LEN
];
2692 { "tx_bytes", GM_TXO_OK_HI
},
2693 { "rx_bytes", GM_RXO_OK_HI
},
2694 { "tx_broadcast", GM_TXF_BC_OK
},
2695 { "rx_broadcast", GM_RXF_BC_OK
},
2696 { "tx_multicast", GM_TXF_MC_OK
},
2697 { "rx_multicast", GM_RXF_MC_OK
},
2698 { "tx_unicast", GM_TXF_UC_OK
},
2699 { "rx_unicast", GM_RXF_UC_OK
},
2700 { "tx_mac_pause", GM_TXF_MPAUSE
},
2701 { "rx_mac_pause", GM_RXF_MPAUSE
},
2702 { "collisions", GM_TXF_COL
},
2703 { "late_collision",GM_TXF_LAT_COL
},
2704 { "aborted", GM_TXF_ABO_COL
},
2705 { "single_collisions", GM_TXF_SNG_COL
},
2706 { "multi_collisions", GM_TXF_MUL_COL
},
2708 { "rx_short", GM_RXF_SHT
},
2709 { "rx_runt", GM_RXE_FRAG
},
2710 { "rx_64_byte_packets", GM_RXF_64B
},
2711 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2712 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2713 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2714 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2715 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2716 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2717 { "rx_too_long", GM_RXF_LNG_ERR
},
2718 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2719 { "rx_jabber", GM_RXF_JAB_PKT
},
2720 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2722 { "tx_64_byte_packets", GM_TXF_64B
},
2723 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2724 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2725 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2726 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2727 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2728 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2729 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2732 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2734 struct sky2_port
*sky2
= netdev_priv(dev
);
2736 return sky2
->rx_csum
;
2739 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2741 struct sky2_port
*sky2
= netdev_priv(dev
);
2743 sky2
->rx_csum
= data
;
2745 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2746 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2751 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2753 struct sky2_port
*sky2
= netdev_priv(netdev
);
2754 return sky2
->msg_enable
;
2757 static int sky2_nway_reset(struct net_device
*dev
)
2759 struct sky2_port
*sky2
= netdev_priv(dev
);
2761 if (!netif_running(dev
) || sky2
->autoneg
!= AUTONEG_ENABLE
)
2764 sky2_phy_reinit(sky2
);
2769 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2771 struct sky2_hw
*hw
= sky2
->hw
;
2772 unsigned port
= sky2
->port
;
2775 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2776 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2777 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2778 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2780 for (i
= 2; i
< count
; i
++)
2781 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2784 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2786 struct sky2_port
*sky2
= netdev_priv(netdev
);
2787 sky2
->msg_enable
= value
;
2790 static int sky2_get_stats_count(struct net_device
*dev
)
2792 return ARRAY_SIZE(sky2_stats
);
2795 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2796 struct ethtool_stats
*stats
, u64
* data
)
2798 struct sky2_port
*sky2
= netdev_priv(dev
);
2800 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2803 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2807 switch (stringset
) {
2809 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2810 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2811 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2816 /* Use hardware MIB variables for critical path statistics and
2817 * transmit feedback not reported at interrupt.
2818 * Other errors are accounted for in interrupt handler.
2820 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2822 struct sky2_port
*sky2
= netdev_priv(dev
);
2825 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2827 sky2
->net_stats
.tx_bytes
= data
[0];
2828 sky2
->net_stats
.rx_bytes
= data
[1];
2829 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2830 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2831 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2832 sky2
->net_stats
.collisions
= data
[10];
2833 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2835 return &sky2
->net_stats
;
2838 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2840 struct sky2_port
*sky2
= netdev_priv(dev
);
2841 struct sky2_hw
*hw
= sky2
->hw
;
2842 unsigned port
= sky2
->port
;
2843 const struct sockaddr
*addr
= p
;
2845 if (!is_valid_ether_addr(addr
->sa_data
))
2846 return -EADDRNOTAVAIL
;
2848 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2849 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2850 dev
->dev_addr
, ETH_ALEN
);
2851 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2852 dev
->dev_addr
, ETH_ALEN
);
2854 /* virtual address for data */
2855 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2857 /* physical address: used for pause frames */
2858 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2863 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
2867 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
2868 filter
[bit
>> 3] |= 1 << (bit
& 7);
2871 static void sky2_set_multicast(struct net_device
*dev
)
2873 struct sky2_port
*sky2
= netdev_priv(dev
);
2874 struct sky2_hw
*hw
= sky2
->hw
;
2875 unsigned port
= sky2
->port
;
2876 struct dev_mc_list
*list
= dev
->mc_list
;
2880 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2882 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
2883 memset(filter
, 0, sizeof(filter
));
2885 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2886 reg
|= GM_RXCR_UCF_ENA
;
2888 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2889 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2890 else if (dev
->flags
& IFF_ALLMULTI
)
2891 memset(filter
, 0xff, sizeof(filter
));
2892 else if (dev
->mc_count
== 0 && !rx_pause
)
2893 reg
&= ~GM_RXCR_MCF_ENA
;
2896 reg
|= GM_RXCR_MCF_ENA
;
2899 sky2_add_filter(filter
, pause_mc_addr
);
2901 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
2902 sky2_add_filter(filter
, list
->dmi_addr
);
2905 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2906 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2907 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2908 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2909 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2910 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2911 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2912 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2914 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2917 /* Can have one global because blinking is controlled by
2918 * ethtool and that is always under RTNL mutex
2920 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2924 switch (hw
->chip_id
) {
2925 case CHIP_ID_YUKON_XL
:
2926 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2927 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2928 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2929 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2930 PHY_M_LEDC_INIT_CTRL(7) |
2931 PHY_M_LEDC_STA1_CTRL(7) |
2932 PHY_M_LEDC_STA0_CTRL(7))
2935 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2939 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2940 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2941 on
? PHY_M_LED_ALL
: 0);
2945 /* blink LED's for finding board */
2946 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2948 struct sky2_port
*sky2
= netdev_priv(dev
);
2949 struct sky2_hw
*hw
= sky2
->hw
;
2950 unsigned port
= sky2
->port
;
2951 u16 ledctrl
, ledover
= 0;
2956 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2957 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2961 /* save initial values */
2962 spin_lock_bh(&sky2
->phy_lock
);
2963 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2964 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2965 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2966 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2967 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2969 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2970 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2974 while (!interrupted
&& ms
> 0) {
2975 sky2_led(hw
, port
, onoff
);
2978 spin_unlock_bh(&sky2
->phy_lock
);
2979 interrupted
= msleep_interruptible(250);
2980 spin_lock_bh(&sky2
->phy_lock
);
2985 /* resume regularly scheduled programming */
2986 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2987 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2988 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2989 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2990 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2992 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2993 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2995 spin_unlock_bh(&sky2
->phy_lock
);
3000 static void sky2_get_pauseparam(struct net_device
*dev
,
3001 struct ethtool_pauseparam
*ecmd
)
3003 struct sky2_port
*sky2
= netdev_priv(dev
);
3005 switch (sky2
->flow_mode
) {
3007 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3010 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3013 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3016 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3019 ecmd
->autoneg
= sky2
->autoneg
;
3022 static int sky2_set_pauseparam(struct net_device
*dev
,
3023 struct ethtool_pauseparam
*ecmd
)
3025 struct sky2_port
*sky2
= netdev_priv(dev
);
3027 sky2
->autoneg
= ecmd
->autoneg
;
3028 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3030 if (netif_running(dev
))
3031 sky2_phy_reinit(sky2
);
3036 static int sky2_get_coalesce(struct net_device
*dev
,
3037 struct ethtool_coalesce
*ecmd
)
3039 struct sky2_port
*sky2
= netdev_priv(dev
);
3040 struct sky2_hw
*hw
= sky2
->hw
;
3042 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3043 ecmd
->tx_coalesce_usecs
= 0;
3045 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3046 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3048 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3050 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3051 ecmd
->rx_coalesce_usecs
= 0;
3053 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3054 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3056 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3058 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3059 ecmd
->rx_coalesce_usecs_irq
= 0;
3061 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3062 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3065 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3070 /* Note: this affect both ports */
3071 static int sky2_set_coalesce(struct net_device
*dev
,
3072 struct ethtool_coalesce
*ecmd
)
3074 struct sky2_port
*sky2
= netdev_priv(dev
);
3075 struct sky2_hw
*hw
= sky2
->hw
;
3076 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3078 if (ecmd
->tx_coalesce_usecs
> tmax
||
3079 ecmd
->rx_coalesce_usecs
> tmax
||
3080 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3083 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3085 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3087 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3090 if (ecmd
->tx_coalesce_usecs
== 0)
3091 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3093 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3094 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3095 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3097 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3099 if (ecmd
->rx_coalesce_usecs
== 0)
3100 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3102 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3103 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3104 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3106 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3108 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3109 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3111 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3112 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3113 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3115 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3119 static void sky2_get_ringparam(struct net_device
*dev
,
3120 struct ethtool_ringparam
*ering
)
3122 struct sky2_port
*sky2
= netdev_priv(dev
);
3124 ering
->rx_max_pending
= RX_MAX_PENDING
;
3125 ering
->rx_mini_max_pending
= 0;
3126 ering
->rx_jumbo_max_pending
= 0;
3127 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3129 ering
->rx_pending
= sky2
->rx_pending
;
3130 ering
->rx_mini_pending
= 0;
3131 ering
->rx_jumbo_pending
= 0;
3132 ering
->tx_pending
= sky2
->tx_pending
;
3135 static int sky2_set_ringparam(struct net_device
*dev
,
3136 struct ethtool_ringparam
*ering
)
3138 struct sky2_port
*sky2
= netdev_priv(dev
);
3141 if (ering
->rx_pending
> RX_MAX_PENDING
||
3142 ering
->rx_pending
< 8 ||
3143 ering
->tx_pending
< MAX_SKB_TX_LE
||
3144 ering
->tx_pending
> TX_RING_SIZE
- 1)
3147 if (netif_running(dev
))
3150 sky2
->rx_pending
= ering
->rx_pending
;
3151 sky2
->tx_pending
= ering
->tx_pending
;
3153 if (netif_running(dev
)) {
3158 sky2_set_multicast(dev
);
3164 static int sky2_get_regs_len(struct net_device
*dev
)
3170 * Returns copy of control register region
3171 * Note: access to the RAM address register set will cause timeouts.
3173 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3176 const struct sky2_port
*sky2
= netdev_priv(dev
);
3177 const void __iomem
*io
= sky2
->hw
->regs
;
3179 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3181 memset(p
, 0, regs
->len
);
3183 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3185 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3187 regs
->len
- B3_RI_WTO_R1
);
3190 static const struct ethtool_ops sky2_ethtool_ops
= {
3191 .get_settings
= sky2_get_settings
,
3192 .set_settings
= sky2_set_settings
,
3193 .get_drvinfo
= sky2_get_drvinfo
,
3194 .get_msglevel
= sky2_get_msglevel
,
3195 .set_msglevel
= sky2_set_msglevel
,
3196 .nway_reset
= sky2_nway_reset
,
3197 .get_regs_len
= sky2_get_regs_len
,
3198 .get_regs
= sky2_get_regs
,
3199 .get_link
= ethtool_op_get_link
,
3200 .get_sg
= ethtool_op_get_sg
,
3201 .set_sg
= ethtool_op_set_sg
,
3202 .get_tx_csum
= ethtool_op_get_tx_csum
,
3203 .set_tx_csum
= ethtool_op_set_tx_csum
,
3204 .get_tso
= ethtool_op_get_tso
,
3205 .set_tso
= ethtool_op_set_tso
,
3206 .get_rx_csum
= sky2_get_rx_csum
,
3207 .set_rx_csum
= sky2_set_rx_csum
,
3208 .get_strings
= sky2_get_strings
,
3209 .get_coalesce
= sky2_get_coalesce
,
3210 .set_coalesce
= sky2_set_coalesce
,
3211 .get_ringparam
= sky2_get_ringparam
,
3212 .set_ringparam
= sky2_set_ringparam
,
3213 .get_pauseparam
= sky2_get_pauseparam
,
3214 .set_pauseparam
= sky2_set_pauseparam
,
3215 .phys_id
= sky2_phys_id
,
3216 .get_stats_count
= sky2_get_stats_count
,
3217 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3218 .get_perm_addr
= ethtool_op_get_perm_addr
,
3221 /* Initialize network device */
3222 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3223 unsigned port
, int highmem
)
3225 struct sky2_port
*sky2
;
3226 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3229 printk(KERN_ERR
"sky2 etherdev alloc failed");
3233 SET_MODULE_OWNER(dev
);
3234 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3235 dev
->irq
= hw
->pdev
->irq
;
3236 dev
->open
= sky2_up
;
3237 dev
->stop
= sky2_down
;
3238 dev
->do_ioctl
= sky2_ioctl
;
3239 dev
->hard_start_xmit
= sky2_xmit_frame
;
3240 dev
->get_stats
= sky2_get_stats
;
3241 dev
->set_multicast_list
= sky2_set_multicast
;
3242 dev
->set_mac_address
= sky2_set_mac_address
;
3243 dev
->change_mtu
= sky2_change_mtu
;
3244 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3245 dev
->tx_timeout
= sky2_tx_timeout
;
3246 dev
->watchdog_timeo
= TX_WATCHDOG
;
3248 dev
->poll
= sky2_poll
;
3249 dev
->weight
= NAPI_WEIGHT
;
3250 #ifdef CONFIG_NET_POLL_CONTROLLER
3251 /* Network console (only works on port 0)
3252 * because netpoll makes assumptions about NAPI
3255 dev
->poll_controller
= sky2_netpoll
;
3258 sky2
= netdev_priv(dev
);
3261 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3263 /* Auto speed and flow control */
3264 sky2
->autoneg
= AUTONEG_ENABLE
;
3265 sky2
->flow_mode
= FC_BOTH
;
3269 sky2
->advertising
= sky2_supported_modes(hw
);
3272 spin_lock_init(&sky2
->phy_lock
);
3273 sky2
->tx_pending
= TX_DEF_PENDING
;
3274 sky2
->rx_pending
= RX_DEF_PENDING
;
3276 hw
->dev
[port
] = dev
;
3280 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3281 dev
->features
|= NETIF_F_TSO
;
3283 dev
->features
|= NETIF_F_HIGHDMA
;
3284 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3286 #ifdef SKY2_VLAN_TAG_USED
3287 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3288 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3289 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3292 /* read the mac address */
3293 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3294 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3296 /* device is off until link detection */
3297 netif_carrier_off(dev
);
3298 netif_stop_queue(dev
);
3303 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3305 const struct sky2_port
*sky2
= netdev_priv(dev
);
3307 if (netif_msg_probe(sky2
))
3308 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3310 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3311 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3314 /* Handle software interrupt used during MSI test */
3315 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3317 struct sky2_hw
*hw
= dev_id
;
3318 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3323 if (status
& Y2_IS_IRQ_SW
) {
3325 wake_up(&hw
->msi_wait
);
3326 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3328 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3333 /* Test interrupt path by forcing a a software IRQ */
3334 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3336 struct pci_dev
*pdev
= hw
->pdev
;
3339 init_waitqueue_head (&hw
->msi_wait
);
3341 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3343 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
3345 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3346 pci_name(pdev
), pdev
->irq
);
3350 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3351 sky2_read8(hw
, B0_CTST
);
3353 wait_event_timeout(hw
->msi_wait
, hw
->msi
, HZ
/10);
3356 /* MSI test failed, go back to INTx mode */
3357 printk(KERN_INFO PFX
"%s: No interrupt generated using MSI, "
3358 "switching to INTx mode.\n",
3362 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3365 sky2_write32(hw
, B0_IMSK
, 0);
3366 sky2_read32(hw
, B0_IMSK
);
3368 free_irq(pdev
->irq
, hw
);
3373 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3374 const struct pci_device_id
*ent
)
3376 struct net_device
*dev
, *dev1
= NULL
;
3378 int err
, pm_cap
, using_dac
= 0;
3380 err
= pci_enable_device(pdev
);
3382 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3387 err
= pci_request_regions(pdev
, DRV_NAME
);
3389 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3394 pci_set_master(pdev
);
3396 /* Find power-management capability. */
3397 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3399 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3402 goto err_out_free_regions
;
3405 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3406 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3408 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3410 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3411 "for consistent allocations\n", pci_name(pdev
));
3412 goto err_out_free_regions
;
3416 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3418 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3420 goto err_out_free_regions
;
3425 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3427 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3429 goto err_out_free_regions
;
3434 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3436 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3438 goto err_out_free_hw
;
3440 hw
->pm_cap
= pm_cap
;
3443 /* The sk98lin vendor driver uses hardware byte swapping but
3444 * this driver uses software swapping.
3448 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3449 reg
&= ~PCI_REV_DESC
;
3450 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3454 /* ring for status responses */
3455 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3458 goto err_out_iounmap
;
3460 err
= sky2_reset(hw
);
3462 goto err_out_iounmap
;
3464 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3465 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3466 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3467 hw
->chip_id
, hw
->chip_rev
);
3469 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3471 goto err_out_free_pci
;
3473 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3474 err
= sky2_test_msi(hw
);
3475 if (err
== -EOPNOTSUPP
)
3476 pci_disable_msi(pdev
);
3478 goto err_out_free_netdev
;
3481 err
= register_netdev(dev
);
3483 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3485 goto err_out_free_netdev
;
3488 err
= request_irq(pdev
->irq
, sky2_intr
, hw
->msi
? 0 : IRQF_SHARED
,
3491 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3492 pci_name(pdev
), pdev
->irq
);
3493 goto err_out_unregister
;
3495 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3497 sky2_show_addr(dev
);
3499 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3500 if (register_netdev(dev1
) == 0)
3501 sky2_show_addr(dev1
);
3503 /* Failure to register second port need not be fatal */
3504 printk(KERN_WARNING PFX
3505 "register of second port failed\n");
3511 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3512 sky2_idle_start(hw
);
3514 pci_set_drvdata(pdev
, hw
);
3520 pci_disable_msi(pdev
);
3521 unregister_netdev(dev
);
3522 err_out_free_netdev
:
3525 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3526 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3531 err_out_free_regions
:
3532 pci_release_regions(pdev
);
3533 pci_disable_device(pdev
);
3538 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3540 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3541 struct net_device
*dev0
, *dev1
;
3546 del_timer_sync(&hw
->idle_timer
);
3548 sky2_write32(hw
, B0_IMSK
, 0);
3549 synchronize_irq(hw
->pdev
->irq
);
3554 unregister_netdev(dev1
);
3555 unregister_netdev(dev0
);
3557 sky2_set_power_state(hw
, PCI_D3hot
);
3558 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3559 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3560 sky2_read8(hw
, B0_CTST
);
3562 free_irq(pdev
->irq
, hw
);
3564 pci_disable_msi(pdev
);
3565 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3566 pci_release_regions(pdev
);
3567 pci_disable_device(pdev
);
3575 pci_set_drvdata(pdev
, NULL
);
3579 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3581 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3583 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3585 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3588 del_timer_sync(&hw
->idle_timer
);
3589 netif_poll_disable(hw
->dev
[0]);
3591 for (i
= 0; i
< hw
->ports
; i
++) {
3592 struct net_device
*dev
= hw
->dev
[i
];
3594 if (netif_running(dev
)) {
3596 netif_device_detach(dev
);
3600 sky2_write32(hw
, B0_IMSK
, 0);
3601 pci_save_state(pdev
);
3602 sky2_set_power_state(hw
, pstate
);
3606 static int sky2_resume(struct pci_dev
*pdev
)
3608 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3611 pci_restore_state(pdev
);
3612 pci_enable_wake(pdev
, PCI_D0
, 0);
3613 sky2_set_power_state(hw
, PCI_D0
);
3615 err
= sky2_reset(hw
);
3619 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3621 for (i
= 0; i
< hw
->ports
; i
++) {
3622 struct net_device
*dev
= hw
->dev
[i
];
3623 if (netif_running(dev
)) {
3624 netif_device_attach(dev
);
3628 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3636 netif_poll_enable(hw
->dev
[0]);
3637 sky2_idle_start(hw
);
3642 /* BIOS resume runs after device (it's a bug in PM)
3643 * as a temporary workaround on suspend/resume leave MSI disabled
3645 static int sky2_suspend_late(struct pci_dev
*pdev
, pm_message_t state
)
3647 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3649 free_irq(pdev
->irq
, hw
);
3651 pci_disable_msi(pdev
);
3657 static int sky2_resume_early(struct pci_dev
*pdev
)
3659 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3660 struct net_device
*dev
= hw
->dev
[0];
3662 return request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, dev
->name
, hw
);
3666 static struct pci_driver sky2_driver
= {
3668 .id_table
= sky2_id_table
,
3669 .probe
= sky2_probe
,
3670 .remove
= __devexit_p(sky2_remove
),
3672 .suspend
= sky2_suspend
,
3673 .resume
= sky2_resume
,
3674 .suspend_late
= sky2_suspend_late
,
3675 .resume_early
= sky2_resume_early
,
3679 static int __init
sky2_init_module(void)
3681 return pci_register_driver(&sky2_driver
);
3684 static void __exit
sky2_cleanup_module(void)
3686 pci_unregister_driver(&sky2_driver
);
3689 module_init(sky2_init_module
);
3690 module_exit(sky2_cleanup_module
);
3692 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3693 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3694 MODULE_LICENSE("GPL");
3695 MODULE_VERSION(DRV_VERSION
);