drivers/ata/sata_vsc.c

   1 /*
   2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
   3  *
   4  *  Maintained by:  Jeremy Higdon @ SGI
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 SGI
   9  *
  10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  11  *
  12  *
  13  *  This program is free software; you can redistribute it and/or modify
  14  *  it under the terms of the GNU General Public License as published by
  15  *  the Free Software Foundation; either version 2, or (at your option)
  16  *  any later version.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  *  libata documentation is available via 'make {ps|pdf}docs',
  29  *  as Documentation/DocBook/libata.*
  30  *
  31  *  Vitesse hardware documentation presumably available under NDA.
  32  *  Intel 31244 (same hardware interface) documentation presumably
  33  *  available from http://developer.intel.com/
  34  *
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/init.h>
  41 #include <linux/blkdev.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/device.h>
  46 #include <scsi/scsi_host.h>
  47 #include <linux/libata.h>
  48
  49 #define DRV_NAME        "sata_vsc"
  50 #define DRV_VERSION     "2.1"
  51
  52 enum {
  53         VSC_MMIO_BAR                    = 0,
  54
  55         /* Interrupt register offsets (from chip base address) */
  56         VSC_SATA_INT_STAT_OFFSET        = 0x00,
  57         VSC_SATA_INT_MASK_OFFSET        = 0x04,
  58
  59         /* Taskfile registers offsets */
  60         VSC_SATA_TF_CMD_OFFSET          = 0x00,
  61         VSC_SATA_TF_DATA_OFFSET         = 0x00,
  62         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
  63         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
  64         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
  65         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
  66         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
  67         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
  68         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
  69         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
  70         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
  71         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
  72         VSC_SATA_TF_CTL_OFFSET          = 0x29,
  73
  74         /* DMA base */
  75         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
  76         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
  77         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
  78
  79         /* SCRs base */
  80         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
  81         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
  82         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
  83
  84         /* Port stride */
  85         VSC_SATA_PORT_OFFSET            = 0x200,
  86
  87         /* Error interrupt status bit offsets */
  88         VSC_SATA_INT_ERROR_CRC          = 0x40,
  89         VSC_SATA_INT_ERROR_T            = 0x20,
  90         VSC_SATA_INT_ERROR_P            = 0x10,
  91         VSC_SATA_INT_ERROR_R            = 0x8,
  92         VSC_SATA_INT_ERROR_E            = 0x4,
  93         VSC_SATA_INT_ERROR_M            = 0x2,
  94         VSC_SATA_INT_PHY_CHANGE         = 0x1,
  95         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
  96                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
  97                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
  98                               VSC_SATA_INT_PHY_CHANGE),
  99 };
 100
 101 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
 102 {
 103         if (sc_reg > SCR_CONTROL)
 104                 return 0xffffffffU;
 105         return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
 106 }
 107
 108
 109 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
 110                                u32 val)
 111 {
 112         if (sc_reg > SCR_CONTROL)
 113                 return;
 114         writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
 115 }
 116
 117
 118 static void vsc_freeze(struct ata_port *ap)
 119 {
 120         void __iomem *mask_addr;
 121
 122         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
 123                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 124
 125         writeb(0, mask_addr);
 126 }
 127
 128
 129 static void vsc_thaw(struct ata_port *ap)
 130 {
 131         void __iomem *mask_addr;
 132
 133         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
 134                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 135
 136         writeb(0xff, mask_addr);
 137 }
 138
 139
 140 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
 141 {
 142         void __iomem *mask_addr;
 143         u8 mask;
 144
 145         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
 146                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 147         mask = readb(mask_addr);
 148         if (ctl & ATA_NIEN)
 149                 mask |= 0x80;
 150         else
 151                 mask &= 0x7F;
 152         writeb(mask, mask_addr);
 153 }
 154
 155
 156 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 157 {
 158         struct ata_ioports *ioaddr = &ap->ioaddr;
 159         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 160
 161         /*
 162          * The only thing the ctl register is used for is SRST.
 163          * That is not enabled or disabled via tf_load.
 164          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
 165          */
 166         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
 167                 ap->last_ctl = tf->ctl;
 168                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
 169         }
 170         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 171                 writew(tf->feature | (((u16)tf->hob_feature) << 8),
 172                        ioaddr->feature_addr);
 173                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
 174                        ioaddr->nsect_addr);
 175                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
 176                        ioaddr->lbal_addr);
 177                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
 178                        ioaddr->lbam_addr);
 179                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
 180                        ioaddr->lbah_addr);
 181         } else if (is_addr) {
 182                 writew(tf->feature, ioaddr->feature_addr);
 183                 writew(tf->nsect, ioaddr->nsect_addr);
 184                 writew(tf->lbal, ioaddr->lbal_addr);
 185                 writew(tf->lbam, ioaddr->lbam_addr);
 186                 writew(tf->lbah, ioaddr->lbah_addr);
 187         }
 188
 189         if (tf->flags & ATA_TFLAG_DEVICE)
 190                 writeb(tf->device, ioaddr->device_addr);
 191
 192         ata_wait_idle(ap);
 193 }
 194
 195
 196 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 197 {
 198         struct ata_ioports *ioaddr = &ap->ioaddr;
 199         u16 nsect, lbal, lbam, lbah, feature;
 200
 201         tf->command = ata_check_status(ap);
 202         tf->device = readw(ioaddr->device_addr);
 203         feature = readw(ioaddr->error_addr);
 204         nsect = readw(ioaddr->nsect_addr);
 205         lbal = readw(ioaddr->lbal_addr);
 206         lbam = readw(ioaddr->lbam_addr);
 207         lbah = readw(ioaddr->lbah_addr);
 208
 209         tf->feature = feature;
 210         tf->nsect = nsect;
 211         tf->lbal = lbal;
 212         tf->lbam = lbam;
 213         tf->lbah = lbah;
 214
 215         if (tf->flags & ATA_TFLAG_LBA48) {
 216                 tf->hob_feature = feature >> 8;
 217                 tf->hob_nsect = nsect >> 8;
 218                 tf->hob_lbal = lbal >> 8;
 219                 tf->hob_lbam = lbam >> 8;
 220                 tf->hob_lbah = lbah >> 8;
 221         }
 222 }
 223
 224 static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
 225 {
 226         if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
 227                 ata_port_freeze(ap);
 228         else
 229                 ata_port_abort(ap);
 230 }
 231
 232 static void vsc_port_intr(u8 port_status, struct ata_port *ap)
 233 {
 234         struct ata_queued_cmd *qc;
 235         int handled = 0;
 236
 237         if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
 238                 vsc_error_intr(port_status, ap);
 239                 return;
 240         }
 241
 242         qc = ata_qc_from_tag(ap, ap->active_tag);
 243         if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
 244                 handled = ata_host_intr(ap, qc);
 245
 246         /* We received an interrupt during a polled command,
 247          * or some other spurious condition.  Interrupt reporting
 248          * with this hardware is fairly reliable so it is safe to
 249          * simply clear the interrupt
 250          */
 251         if (unlikely(!handled))
 252                 ata_chk_status(ap);
 253 }
 254
 255 /*
 256  * vsc_sata_interrupt
 257  *
 258  * Read the interrupt register and process for the devices that have them pending.
 259  */
 260 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
 261 {
 262         struct ata_host *host = dev_instance;
 263         unsigned int i;
 264         unsigned int handled = 0;
 265         u32 status;
 266
 267         status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
 268
 269         if (unlikely(status == 0xffffffff || status == 0)) {
 270                 if (status)
 271                         dev_printk(KERN_ERR, host->dev,
 272                                 ": IRQ status == 0xffffffff, "
 273                                 "PCI fault or device removal?\n");
 274                 goto out;
 275         }
 276
 277         spin_lock(&host->lock);
 278
 279         for (i = 0; i < host->n_ports; i++) {
 280                 u8 port_status = (status >> (8 * i)) & 0xff;
 281                 if (port_status) {
 282                         struct ata_port *ap = host->ports[i];
 283
 284                         if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
 285                                 vsc_port_intr(port_status, ap);
 286                                 handled++;
 287                         } else
 288                                 dev_printk(KERN_ERR, host->dev,
 289                                         ": interrupt from disabled port %d\n", i);
 290                 }
 291         }
 292
 293         spin_unlock(&host->lock);
 294 out:
 295         return IRQ_RETVAL(handled);
 296 }
 297
 298
 299 static struct scsi_host_template vsc_sata_sht = {
 300         .module                 = THIS_MODULE,
 301         .name                   = DRV_NAME,
 302         .ioctl                  = ata_scsi_ioctl,
 303         .queuecommand           = ata_scsi_queuecmd,
 304         .can_queue              = ATA_DEF_QUEUE,
 305         .this_id                = ATA_SHT_THIS_ID,
 306         .sg_tablesize           = LIBATA_MAX_PRD,
 307         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 308         .emulated               = ATA_SHT_EMULATED,
 309         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 310         .proc_name              = DRV_NAME,
 311         .dma_boundary           = ATA_DMA_BOUNDARY,
 312         .slave_configure        = ata_scsi_slave_config,
 313         .slave_destroy          = ata_scsi_slave_destroy,
 314         .bios_param             = ata_std_bios_param,
 315 };
 316
 317
 318 static const struct ata_port_operations vsc_sata_ops = {
 319         .port_disable           = ata_port_disable,
 320         .tf_load                = vsc_sata_tf_load,
 321         .tf_read                = vsc_sata_tf_read,
 322         .exec_command           = ata_exec_command,
 323         .check_status           = ata_check_status,
 324         .dev_select             = ata_std_dev_select,
 325         .bmdma_setup            = ata_bmdma_setup,
 326         .bmdma_start            = ata_bmdma_start,
 327         .bmdma_stop             = ata_bmdma_stop,
 328         .bmdma_status           = ata_bmdma_status,
 329         .qc_prep                = ata_qc_prep,
 330         .qc_issue               = ata_qc_issue_prot,
 331         .data_xfer              = ata_data_xfer,
 332         .freeze                 = vsc_freeze,
 333         .thaw                   = vsc_thaw,
 334         .error_handler          = ata_bmdma_error_handler,
 335         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
 336         .irq_clear              = ata_bmdma_irq_clear,
 337         .irq_on                 = ata_irq_on,
 338         .irq_ack                = ata_irq_ack,
 339         .scr_read               = vsc_sata_scr_read,
 340         .scr_write              = vsc_sata_scr_write,
 341         .port_start             = ata_port_start,
 342 };
 343
 344 static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
 345                                           void __iomem *base)
 346 {
 347         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
 348         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
 349         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
 350         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
 351         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
 352         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
 353         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
 354         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
 355         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
 356         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
 357         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
 358         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
 359         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
 360         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
 361         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
 362         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
 363         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
 364 }
 365
 366
 367 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 368 {
 369         static const struct ata_port_info pi = {
 370                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 371                                   ATA_FLAG_MMIO,
 372                 .pio_mask       = 0x1f,
 373                 .mwdma_mask     = 0x07,
 374                 .udma_mask      = 0x7f,
 375                 .port_ops       = &vsc_sata_ops,
 376         };
 377         const struct ata_port_info *ppi[] = { &pi, NULL };
 378         static int printed_version;
 379         struct ata_host *host;
 380         void __iomem *mmio_base;
 381         int i, rc;
 382         u8 cls;
 383
 384         if (!printed_version++)
 385                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 386
 387         /* allocate host */
 388         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
 389         if (!host)
 390                 return -ENOMEM;
 391
 392         rc = pcim_enable_device(pdev);
 393         if (rc)
 394                 return rc;
 395
 396         /* check if we have needed resource mapped */
 397         if (pci_resource_len(pdev, 0) == 0)
 398                 return -ENODEV;
 399
 400         /* map IO regions and intialize host accordingly */
 401         rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
 402         if (rc == -EBUSY)
 403                 pcim_pin_device(pdev);
 404         if (rc)
 405                 return rc;
 406         host->iomap = pcim_iomap_table(pdev);
 407
 408         mmio_base = host->iomap[VSC_MMIO_BAR];
 409
 410         for (i = 0; i < host->n_ports; i++)
 411                 vsc_sata_setup_port(&host->ports[i]->ioaddr,
 412                                     mmio_base + (i + 1) * VSC_SATA_PORT_OFFSET);
 413
 414         /*
 415          * Use 32 bit DMA mask, because 64 bit address support is poor.
 416          */
 417         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 418         if (rc)
 419                 return rc;
 420         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 421         if (rc)
 422                 return rc;
 423
 424         /*
 425          * Due to a bug in the chip, the default cache line size can't be
 426          * used (unless the default is non-zero).
 427          */
 428         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
 429         if (cls == 0x00)
 430                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 431
 432         if (pci_enable_msi(pdev) == 0)
 433                 pci_intx(pdev, 0);
 434
 435         /*
 436          * Config offset 0x98 is "Extended Control and Status Register 0"
 437          * Default value is (1 << 28).  All bits except bit 28 are reserved in
 438          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
 439          * If bit 28 is clear, each port has its own LED.
 440          */
 441         pci_write_config_dword(pdev, 0x98, 0);
 442
 443         pci_set_master(pdev);
 444         return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
 445                                  IRQF_SHARED, &vsc_sata_sht);
 446 }
 447
 448 static const struct pci_device_id vsc_sata_pci_tbl[] = {
 449         { PCI_VENDOR_ID_VITESSE, 0x7174,
 450           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 451         { PCI_VENDOR_ID_INTEL, 0x3200,
 452           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 453
 454         { }     /* terminate list */
 455 };
 456
 457 static struct pci_driver vsc_sata_pci_driver = {
 458         .name                   = DRV_NAME,
 459         .id_table               = vsc_sata_pci_tbl,
 460         .probe                  = vsc_sata_init_one,
 461         .remove                 = ata_pci_remove_one,
 462 };
 463
 464 static int __init vsc_sata_init(void)
 465 {
 466         return pci_register_driver(&vsc_sata_pci_driver);
 467 }
 468
 469 static void __exit vsc_sata_exit(void)
 470 {
 471         pci_unregister_driver(&vsc_sata_pci_driver);
 472 }
 473
 474 MODULE_AUTHOR("Jeremy Higdon");
 475 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
 476 MODULE_LICENSE("GPL");
 477 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
 478 MODULE_VERSION(DRV_VERSION);
 479
 480 module_init(vsc_sata_init);
 481 module_exit(vsc_sata_exit);