2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
4 * Copyright (C) 2003 SAN People (Pty) Ltd
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/mii.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ethtool.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
32 #include <asm/uaccess.h>
33 #include <asm/mach-types.h>
35 #include <asm/arch/at91rm9200_emac.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/board.h>
39 #include "at91_ether.h"
41 #define DRV_NAME "at91_ether"
42 #define DRV_VERSION "1.0"
44 #define LINK_POLL_INTERVAL (HZ)
46 /* ..................................................................... */
49 * Read from a EMAC register.
51 static inline unsigned long at91_emac_read(unsigned int reg
)
53 void __iomem
*emac_base
= (void __iomem
*)AT91_VA_BASE_EMAC
;
55 return __raw_readl(emac_base
+ reg
);
59 * Write to a EMAC register.
61 static inline void at91_emac_write(unsigned int reg
, unsigned long value
)
63 void __iomem
*emac_base
= (void __iomem
*)AT91_VA_BASE_EMAC
;
65 __raw_writel(value
, emac_base
+ reg
);
68 /* ........................... PHY INTERFACE ........................... */
71 * Enable the MDIO bit in MAC control register
72 * When not called from an interrupt-handler, access to the PHY must be
73 * protected by a spinlock.
75 static void enable_mdi(void)
79 ctl
= at91_emac_read(AT91_EMAC_CTL
);
80 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_MPE
); /* enable management port */
84 * Disable the MDIO bit in the MAC control register
86 static void disable_mdi(void)
90 ctl
= at91_emac_read(AT91_EMAC_CTL
);
91 at91_emac_write(AT91_EMAC_CTL
, ctl
& ~AT91_EMAC_MPE
); /* disable management port */
95 * Wait until the PHY operation is complete.
97 static inline void at91_phy_wait(void) {
98 unsigned long timeout
= jiffies
+ 2;
100 while (!(at91_emac_read(AT91_EMAC_SR
) & AT91_EMAC_SR_IDLE
)) {
101 if (time_after(jiffies
, timeout
)) {
102 printk("at91_ether: MIO timeout\n");
110 * Write value to the a PHY register
111 * Note: MDI interface is assumed to already have been enabled.
113 static void write_phy(unsigned char phy_addr
, unsigned char address
, unsigned int value
)
115 at91_emac_write(AT91_EMAC_MAN
, AT91_EMAC_MAN_802_3
| AT91_EMAC_RW_W
116 | ((phy_addr
& 0x1f) << 23) | (address
<< 18) | (value
& AT91_EMAC_DATA
));
118 /* Wait until IDLE bit in Network Status register is cleared */
123 * Read value stored in a PHY register.
124 * Note: MDI interface is assumed to already have been enabled.
126 static void read_phy(unsigned char phy_addr
, unsigned char address
, unsigned int *value
)
128 at91_emac_write(AT91_EMAC_MAN
, AT91_EMAC_MAN_802_3
| AT91_EMAC_RW_R
129 | ((phy_addr
& 0x1f) << 23) | (address
<< 18));
131 /* Wait until IDLE bit in Network Status register is cleared */
134 *value
= at91_emac_read(AT91_EMAC_MAN
) & AT91_EMAC_DATA
;
137 /* ........................... PHY MANAGEMENT .......................... */
140 * Access the PHY to determine the current link speed and mode, and update the
142 * If no link or auto-negotiation is busy, then no changes are made.
144 static void update_linkspeed(struct net_device
*dev
, int silent
)
146 struct at91_private
*lp
= netdev_priv(dev
);
147 unsigned int bmsr
, bmcr
, lpa
, mac_cfg
;
148 unsigned int speed
, duplex
;
150 if (!mii_link_ok(&lp
->mii
)) { /* no link */
151 netif_carrier_off(dev
);
153 printk(KERN_INFO
"%s: Link down.\n", dev
->name
);
157 /* Link up, or auto-negotiation still in progress */
158 read_phy(lp
->phy_address
, MII_BMSR
, &bmsr
);
159 read_phy(lp
->phy_address
, MII_BMCR
, &bmcr
);
160 if (bmcr
& BMCR_ANENABLE
) { /* AutoNegotiation is enabled */
161 if (!(bmsr
& BMSR_ANEGCOMPLETE
))
162 return; /* Do nothing - another interrupt generated when negotiation complete */
164 read_phy(lp
->phy_address
, MII_LPA
, &lpa
);
165 if ((lpa
& LPA_100FULL
) || (lpa
& LPA_100HALF
)) speed
= SPEED_100
;
166 else speed
= SPEED_10
;
167 if ((lpa
& LPA_100FULL
) || (lpa
& LPA_10FULL
)) duplex
= DUPLEX_FULL
;
168 else duplex
= DUPLEX_HALF
;
170 speed
= (bmcr
& BMCR_SPEED100
) ? SPEED_100
: SPEED_10
;
171 duplex
= (bmcr
& BMCR_FULLDPLX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
175 mac_cfg
= at91_emac_read(AT91_EMAC_CFG
) & ~(AT91_EMAC_SPD
| AT91_EMAC_FD
);
176 if (speed
== SPEED_100
) {
177 if (duplex
== DUPLEX_FULL
) /* 100 Full Duplex */
178 mac_cfg
|= AT91_EMAC_SPD
| AT91_EMAC_FD
;
179 else /* 100 Half Duplex */
180 mac_cfg
|= AT91_EMAC_SPD
;
182 if (duplex
== DUPLEX_FULL
) /* 10 Full Duplex */
183 mac_cfg
|= AT91_EMAC_FD
;
184 else {} /* 10 Half Duplex */
186 at91_emac_write(AT91_EMAC_CFG
, mac_cfg
);
189 printk(KERN_INFO
"%s: Link now %i-%s\n", dev
->name
, speed
, (duplex
== DUPLEX_FULL
) ? "FullDuplex" : "HalfDuplex");
190 netif_carrier_on(dev
);
194 * Handle interrupts from the PHY
196 static irqreturn_t
at91ether_phy_interrupt(int irq
, void *dev_id
)
198 struct net_device
*dev
= (struct net_device
*) dev_id
;
199 struct at91_private
*lp
= netdev_priv(dev
);
203 * This hander is triggered on both edges, but the PHY chips expect
204 * level-triggering. We therefore have to check if the PHY actually has
208 if ((lp
->phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) {
209 read_phy(lp
->phy_address
, MII_DSINTR_REG
, &phy
); /* ack interrupt in Davicom PHY */
210 if (!(phy
& (1 << 0)))
213 else if (lp
->phy_type
== MII_LXT971A_ID
) {
214 read_phy(lp
->phy_address
, MII_ISINTS_REG
, &phy
); /* ack interrupt in Intel PHY */
215 if (!(phy
& (1 << 2)))
218 else if (lp
->phy_type
== MII_BCM5221_ID
) {
219 read_phy(lp
->phy_address
, MII_BCMINTR_REG
, &phy
); /* ack interrupt in Broadcom PHY */
220 if (!(phy
& (1 << 0)))
223 else if (lp
->phy_type
== MII_KS8721_ID
) {
224 read_phy(lp
->phy_address
, MII_TPISTATUS
, &phy
); /* ack interrupt in Micrel PHY */
225 if (!(phy
& ((1 << 2) | 1)))
229 update_linkspeed(dev
, 0);
238 * Initialize and enable the PHY interrupt for link-state changes
240 static void enable_phyirq(struct net_device
*dev
)
242 struct at91_private
*lp
= netdev_priv(dev
);
243 unsigned int dsintr
, irq_number
;
246 irq_number
= lp
->board_data
.phy_irq_pin
;
249 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
250 * or board does not have it connected.
252 mod_timer(&lp
->check_timer
, jiffies
+ LINK_POLL_INTERVAL
);
256 status
= request_irq(irq_number
, at91ether_phy_interrupt
, 0, dev
->name
, dev
);
258 printk(KERN_ERR
"at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number
, status
);
262 spin_lock_irq(&lp
->lock
);
265 if ((lp
->phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) { /* for Davicom PHY */
266 read_phy(lp
->phy_address
, MII_DSINTR_REG
, &dsintr
);
267 dsintr
= dsintr
& ~0xf00; /* clear bits 8..11 */
268 write_phy(lp
->phy_address
, MII_DSINTR_REG
, dsintr
);
270 else if (lp
->phy_type
== MII_LXT971A_ID
) { /* for Intel PHY */
271 read_phy(lp
->phy_address
, MII_ISINTE_REG
, &dsintr
);
272 dsintr
= dsintr
| 0xf2; /* set bits 1, 4..7 */
273 write_phy(lp
->phy_address
, MII_ISINTE_REG
, dsintr
);
275 else if (lp
->phy_type
== MII_BCM5221_ID
) { /* for Broadcom PHY */
276 dsintr
= (1 << 15) | ( 1 << 14);
277 write_phy(lp
->phy_address
, MII_BCMINTR_REG
, dsintr
);
279 else if (lp
->phy_type
== MII_KS8721_ID
) { /* for Micrel PHY */
280 dsintr
= (1 << 10) | ( 1 << 8);
281 write_phy(lp
->phy_address
, MII_TPISTATUS
, dsintr
);
285 spin_unlock_irq(&lp
->lock
);
289 * Disable the PHY interrupt
291 static void disable_phyirq(struct net_device
*dev
)
293 struct at91_private
*lp
= netdev_priv(dev
);
295 unsigned int irq_number
;
297 irq_number
= lp
->board_data
.phy_irq_pin
;
299 del_timer_sync(&lp
->check_timer
);
303 spin_lock_irq(&lp
->lock
);
306 if ((lp
->phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) { /* for Davicom PHY */
307 read_phy(lp
->phy_address
, MII_DSINTR_REG
, &dsintr
);
308 dsintr
= dsintr
| 0xf00; /* set bits 8..11 */
309 write_phy(lp
->phy_address
, MII_DSINTR_REG
, dsintr
);
311 else if (lp
->phy_type
== MII_LXT971A_ID
) { /* for Intel PHY */
312 read_phy(lp
->phy_address
, MII_ISINTE_REG
, &dsintr
);
313 dsintr
= dsintr
& ~0xf2; /* clear bits 1, 4..7 */
314 write_phy(lp
->phy_address
, MII_ISINTE_REG
, dsintr
);
316 else if (lp
->phy_type
== MII_BCM5221_ID
) { /* for Broadcom PHY */
317 read_phy(lp
->phy_address
, MII_BCMINTR_REG
, &dsintr
);
319 write_phy(lp
->phy_address
, MII_BCMINTR_REG
, dsintr
);
321 else if (lp
->phy_type
== MII_KS8721_ID
) { /* for Micrel PHY */
322 read_phy(lp
->phy_address
, MII_TPISTATUS
, &dsintr
);
323 dsintr
= ~((1 << 10) | (1 << 8));
324 write_phy(lp
->phy_address
, MII_TPISTATUS
, dsintr
);
328 spin_unlock_irq(&lp
->lock
);
330 free_irq(irq_number
, dev
); /* Free interrupt handler */
334 * Perform a software reset of the PHY.
337 static void reset_phy(struct net_device
*dev
)
339 struct at91_private
*lp
= netdev_priv(dev
);
342 spin_lock_irq(&lp
->lock
);
345 /* Perform PHY reset */
346 write_phy(lp
->phy_address
, MII_BMCR
, BMCR_RESET
);
348 /* Wait until PHY reset is complete */
350 read_phy(lp
->phy_address
, MII_BMCR
, &bmcr
);
351 } while (!(bmcr
&& BMCR_RESET
));
354 spin_unlock_irq(&lp
->lock
);
358 static void at91ether_check_link(unsigned long dev_id
)
360 struct net_device
*dev
= (struct net_device
*) dev_id
;
361 struct at91_private
*lp
= netdev_priv(dev
);
364 update_linkspeed(dev
, 1);
367 mod_timer(&lp
->check_timer
, jiffies
+ LINK_POLL_INTERVAL
);
370 /* ......................... ADDRESS MANAGEMENT ........................ */
373 * NOTE: Your bootloader must always set the MAC address correctly before
374 * booting into Linux.
376 * - It must always set the MAC address after reset, even if it doesn't
377 * happen to access the Ethernet while it's booting. Some versions of
378 * U-Boot on the AT91RM9200-DK do not do this.
380 * - Likewise it must store the addresses in the correct byte order.
381 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
382 * continues to do so, for bug-compatibility).
385 static short __init
unpack_mac_address(struct net_device
*dev
, unsigned int hi
, unsigned int lo
)
389 if (machine_is_csb337()) {
390 addr
[5] = (lo
& 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
391 addr
[4] = (lo
& 0xff00) >> 8;
392 addr
[3] = (lo
& 0xff0000) >> 16;
393 addr
[2] = (lo
& 0xff000000) >> 24;
394 addr
[1] = (hi
& 0xff);
395 addr
[0] = (hi
& 0xff00) >> 8;
398 addr
[0] = (lo
& 0xff);
399 addr
[1] = (lo
& 0xff00) >> 8;
400 addr
[2] = (lo
& 0xff0000) >> 16;
401 addr
[3] = (lo
& 0xff000000) >> 24;
402 addr
[4] = (hi
& 0xff);
403 addr
[5] = (hi
& 0xff00) >> 8;
406 if (is_valid_ether_addr(addr
)) {
407 memcpy(dev
->dev_addr
, &addr
, 6);
414 * Set the ethernet MAC address in dev->dev_addr
416 static void __init
get_mac_address(struct net_device
*dev
)
418 /* Check Specific-Address 1 */
419 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA1H
), at91_emac_read(AT91_EMAC_SA1L
)))
421 /* Check Specific-Address 2 */
422 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA2H
), at91_emac_read(AT91_EMAC_SA2L
)))
424 /* Check Specific-Address 3 */
425 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA3H
), at91_emac_read(AT91_EMAC_SA3L
)))
427 /* Check Specific-Address 4 */
428 if (unpack_mac_address(dev
, at91_emac_read(AT91_EMAC_SA4H
), at91_emac_read(AT91_EMAC_SA4L
)))
431 printk(KERN_ERR
"at91_ether: Your bootloader did not configure a MAC address.\n");
435 * Program the hardware MAC address from dev->dev_addr.
437 static void update_mac_address(struct net_device
*dev
)
439 at91_emac_write(AT91_EMAC_SA1L
, (dev
->dev_addr
[3] << 24) | (dev
->dev_addr
[2] << 16) | (dev
->dev_addr
[1] << 8) | (dev
->dev_addr
[0]));
440 at91_emac_write(AT91_EMAC_SA1H
, (dev
->dev_addr
[5] << 8) | (dev
->dev_addr
[4]));
442 at91_emac_write(AT91_EMAC_SA2L
, 0);
443 at91_emac_write(AT91_EMAC_SA2H
, 0);
447 * Store the new hardware address in dev->dev_addr, and update the MAC.
449 static int set_mac_address(struct net_device
*dev
, void* addr
)
451 struct sockaddr
*address
= addr
;
453 if (!is_valid_ether_addr(address
->sa_data
))
454 return -EADDRNOTAVAIL
;
456 memcpy(dev
->dev_addr
, address
->sa_data
, dev
->addr_len
);
457 update_mac_address(dev
);
459 printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev
->name
,
460 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
461 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
466 static int inline hash_bit_value(int bitnr
, __u8
*addr
)
468 if (addr
[bitnr
/ 8] & (1 << (bitnr
% 8)))
474 * The hash address register is 64 bits long and takes up two locations in the memory map.
475 * The least significant bits are stored in EMAC_HSL and the most significant
478 * The unicast hash enable and the multicast hash enable bits in the network configuration
479 * register enable the reception of hash matched frames. The destination address is
480 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
481 * The hash function is an exclusive or of every sixth bit of the destination address.
482 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
483 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
484 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
485 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
486 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
487 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
488 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
489 * unicast indicator, and da[47] represents the most significant bit of the last byte
491 * If the hash index points to a bit that is set in the hash register then the frame will be
492 * matched according to whether the frame is multicast or unicast.
493 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
494 * the hash index points to a bit set in the hash register.
495 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
496 * hash index points to a bit set in the hash register.
497 * To receive all multicast frames, the hash register should be set with all ones and the
498 * multicast hash enable bit should be set in the network configuration register.
502 * Return the hash index value for the specified address.
504 static int hash_get_index(__u8
*addr
)
509 for (j
= 0; j
< 6; j
++) {
510 for (i
= 0, bitval
= 0; i
< 8; i
++)
511 bitval
^= hash_bit_value(i
*6 + j
, addr
);
513 hash_index
|= (bitval
<< j
);
520 * Add multicast addresses to the internal multicast-hash table.
522 static void at91ether_sethashtable(struct net_device
*dev
)
524 struct dev_mc_list
*curr
;
525 unsigned long mc_filter
[2];
526 unsigned int i
, bitnr
;
528 mc_filter
[0] = mc_filter
[1] = 0;
531 for (i
= 0; i
< dev
->mc_count
; i
++, curr
= curr
->next
) {
532 if (!curr
) break; /* unexpected end of list */
534 bitnr
= hash_get_index(curr
->dmi_addr
);
535 mc_filter
[bitnr
>> 5] |= 1 << (bitnr
& 31);
538 at91_emac_write(AT91_EMAC_HSH
, mc_filter
[0]);
539 at91_emac_write(AT91_EMAC_HSL
, mc_filter
[1]);
543 * Enable/Disable promiscuous and multicast modes.
545 static void at91ether_set_rx_mode(struct net_device
*dev
)
549 cfg
= at91_emac_read(AT91_EMAC_CFG
);
551 if (dev
->flags
& IFF_PROMISC
) /* Enable promiscuous mode */
552 cfg
|= AT91_EMAC_CAF
;
553 else if (dev
->flags
& (~IFF_PROMISC
)) /* Disable promiscuous mode */
554 cfg
&= ~AT91_EMAC_CAF
;
556 if (dev
->flags
& IFF_ALLMULTI
) { /* Enable all multicast mode */
557 at91_emac_write(AT91_EMAC_HSH
, -1);
558 at91_emac_write(AT91_EMAC_HSL
, -1);
559 cfg
|= AT91_EMAC_MTI
;
560 } else if (dev
->mc_count
> 0) { /* Enable specific multicasts */
561 at91ether_sethashtable(dev
);
562 cfg
|= AT91_EMAC_MTI
;
563 } else if (dev
->flags
& (~IFF_ALLMULTI
)) { /* Disable all multicast mode */
564 at91_emac_write(AT91_EMAC_HSH
, 0);
565 at91_emac_write(AT91_EMAC_HSL
, 0);
566 cfg
&= ~AT91_EMAC_MTI
;
569 at91_emac_write(AT91_EMAC_CFG
, cfg
);
572 /* ......................... ETHTOOL SUPPORT ........................... */
574 static int mdio_read(struct net_device
*dev
, int phy_id
, int location
)
578 read_phy(phy_id
, location
, &value
);
582 static void mdio_write(struct net_device
*dev
, int phy_id
, int location
, int value
)
584 write_phy(phy_id
, location
, value
);
587 static int at91ether_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
589 struct at91_private
*lp
= netdev_priv(dev
);
592 spin_lock_irq(&lp
->lock
);
595 ret
= mii_ethtool_gset(&lp
->mii
, cmd
);
598 spin_unlock_irq(&lp
->lock
);
600 if (lp
->phy_media
== PORT_FIBRE
) { /* override media type since mii.c doesn't know */
601 cmd
->supported
= SUPPORTED_FIBRE
;
602 cmd
->port
= PORT_FIBRE
;
608 static int at91ether_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
610 struct at91_private
*lp
= netdev_priv(dev
);
613 spin_lock_irq(&lp
->lock
);
616 ret
= mii_ethtool_sset(&lp
->mii
, cmd
);
619 spin_unlock_irq(&lp
->lock
);
624 static int at91ether_nwayreset(struct net_device
*dev
)
626 struct at91_private
*lp
= netdev_priv(dev
);
629 spin_lock_irq(&lp
->lock
);
632 ret
= mii_nway_restart(&lp
->mii
);
635 spin_unlock_irq(&lp
->lock
);
640 static void at91ether_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
642 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
643 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
644 strlcpy(info
->bus_info
, dev
->dev
.parent
->bus_id
, sizeof(info
->bus_info
));
647 static const struct ethtool_ops at91ether_ethtool_ops
= {
648 .get_settings
= at91ether_get_settings
,
649 .set_settings
= at91ether_set_settings
,
650 .get_drvinfo
= at91ether_get_drvinfo
,
651 .nway_reset
= at91ether_nwayreset
,
652 .get_link
= ethtool_op_get_link
,
655 static int at91ether_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
657 struct at91_private
*lp
= netdev_priv(dev
);
660 if (!netif_running(dev
))
663 spin_lock_irq(&lp
->lock
);
665 res
= generic_mii_ioctl(&lp
->mii
, if_mii(rq
), cmd
, NULL
);
667 spin_unlock_irq(&lp
->lock
);
672 /* ................................ MAC ................................ */
675 * Initialize and start the Receiver and Transmit subsystems
677 static void at91ether_start(struct net_device
*dev
)
679 struct at91_private
*lp
= netdev_priv(dev
);
680 struct recv_desc_bufs
*dlist
, *dlist_phys
;
685 dlist_phys
= lp
->dlist_phys
;
687 for (i
= 0; i
< MAX_RX_DESCR
; i
++) {
688 dlist
->descriptors
[i
].addr
= (unsigned int) &dlist_phys
->recv_buf
[i
][0];
689 dlist
->descriptors
[i
].size
= 0;
692 /* Set the Wrap bit on the last descriptor */
693 dlist
->descriptors
[i
-1].addr
|= EMAC_DESC_WRAP
;
695 /* Reset buffer index */
698 /* Program address of descriptor list in Rx Buffer Queue register */
699 at91_emac_write(AT91_EMAC_RBQP
, (unsigned long) dlist_phys
);
701 /* Enable Receive and Transmit */
702 ctl
= at91_emac_read(AT91_EMAC_CTL
);
703 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_RE
| AT91_EMAC_TE
);
707 * Open the ethernet interface
709 static int at91ether_open(struct net_device
*dev
)
711 struct at91_private
*lp
= netdev_priv(dev
);
714 if (!is_valid_ether_addr(dev
->dev_addr
))
715 return -EADDRNOTAVAIL
;
717 clk_enable(lp
->ether_clk
); /* Re-enable Peripheral clock */
719 /* Clear internal statistics */
720 ctl
= at91_emac_read(AT91_EMAC_CTL
);
721 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_CSR
);
723 /* Update the MAC address (incase user has changed it) */
724 update_mac_address(dev
);
726 /* Enable PHY interrupt */
729 /* Enable MAC interrupts */
730 at91_emac_write(AT91_EMAC_IER
, AT91_EMAC_RCOM
| AT91_EMAC_RBNA
731 | AT91_EMAC_TUND
| AT91_EMAC_RTRY
| AT91_EMAC_TCOM
732 | AT91_EMAC_ROVR
| AT91_EMAC_ABT
);
734 /* Determine current link speed */
735 spin_lock_irq(&lp
->lock
);
737 update_linkspeed(dev
, 0);
739 spin_unlock_irq(&lp
->lock
);
741 at91ether_start(dev
);
742 netif_start_queue(dev
);
747 * Close the interface
749 static int at91ether_close(struct net_device
*dev
)
751 struct at91_private
*lp
= netdev_priv(dev
);
754 /* Disable Receiver and Transmitter */
755 ctl
= at91_emac_read(AT91_EMAC_CTL
);
756 at91_emac_write(AT91_EMAC_CTL
, ctl
& ~(AT91_EMAC_TE
| AT91_EMAC_RE
));
758 /* Disable PHY interrupt */
761 /* Disable MAC interrupts */
762 at91_emac_write(AT91_EMAC_IDR
, AT91_EMAC_RCOM
| AT91_EMAC_RBNA
763 | AT91_EMAC_TUND
| AT91_EMAC_RTRY
| AT91_EMAC_TCOM
764 | AT91_EMAC_ROVR
| AT91_EMAC_ABT
);
766 netif_stop_queue(dev
);
768 clk_disable(lp
->ether_clk
); /* Disable Peripheral clock */
776 static int at91ether_tx(struct sk_buff
*skb
, struct net_device
*dev
)
778 struct at91_private
*lp
= netdev_priv(dev
);
780 if (at91_emac_read(AT91_EMAC_TSR
) & AT91_EMAC_TSR_BNQ
) {
781 netif_stop_queue(dev
);
783 /* Store packet information (to free when Tx completed) */
785 lp
->skb_length
= skb
->len
;
786 lp
->skb_physaddr
= dma_map_single(NULL
, skb
->data
, skb
->len
, DMA_TO_DEVICE
);
787 lp
->stats
.tx_bytes
+= skb
->len
;
789 /* Set address of the data in the Transmit Address register */
790 at91_emac_write(AT91_EMAC_TAR
, lp
->skb_physaddr
);
791 /* Set length of the packet in the Transmit Control register */
792 at91_emac_write(AT91_EMAC_TCR
, skb
->len
);
794 dev
->trans_start
= jiffies
;
796 printk(KERN_ERR
"at91_ether.c: at91ether_tx() called, but device is busy!\n");
797 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
798 on this skb, he also reports -ENETDOWN and printk's, so either
799 we free and return(0) or don't free and return 1 */
806 * Update the current statistics from the internal statistics registers.
808 static struct net_device_stats
*at91ether_stats(struct net_device
*dev
)
810 struct at91_private
*lp
= netdev_priv(dev
);
811 int ale
, lenerr
, seqe
, lcol
, ecol
;
813 if (netif_running(dev
)) {
814 lp
->stats
.rx_packets
+= at91_emac_read(AT91_EMAC_OK
); /* Good frames received */
815 ale
= at91_emac_read(AT91_EMAC_ALE
);
816 lp
->stats
.rx_frame_errors
+= ale
; /* Alignment errors */
817 lenerr
= at91_emac_read(AT91_EMAC_ELR
) + at91_emac_read(AT91_EMAC_USF
);
818 lp
->stats
.rx_length_errors
+= lenerr
; /* Excessive Length or Undersize Frame error */
819 seqe
= at91_emac_read(AT91_EMAC_SEQE
);
820 lp
->stats
.rx_crc_errors
+= seqe
; /* CRC error */
821 lp
->stats
.rx_fifo_errors
+= at91_emac_read(AT91_EMAC_DRFC
); /* Receive buffer not available */
822 lp
->stats
.rx_errors
+= (ale
+ lenerr
+ seqe
823 + at91_emac_read(AT91_EMAC_CDE
) + at91_emac_read(AT91_EMAC_RJB
));
825 lp
->stats
.tx_packets
+= at91_emac_read(AT91_EMAC_FRA
); /* Frames successfully transmitted */
826 lp
->stats
.tx_fifo_errors
+= at91_emac_read(AT91_EMAC_TUE
); /* Transmit FIFO underruns */
827 lp
->stats
.tx_carrier_errors
+= at91_emac_read(AT91_EMAC_CSE
); /* Carrier Sense errors */
828 lp
->stats
.tx_heartbeat_errors
+= at91_emac_read(AT91_EMAC_SQEE
);/* Heartbeat error */
830 lcol
= at91_emac_read(AT91_EMAC_LCOL
);
831 ecol
= at91_emac_read(AT91_EMAC_ECOL
);
832 lp
->stats
.tx_window_errors
+= lcol
; /* Late collisions */
833 lp
->stats
.tx_aborted_errors
+= ecol
; /* 16 collisions */
835 lp
->stats
.collisions
+= (at91_emac_read(AT91_EMAC_SCOL
) + at91_emac_read(AT91_EMAC_MCOL
) + lcol
+ ecol
);
841 * Extract received frame from buffer descriptors and sent to upper layers.
842 * (Called from interrupt context)
844 static void at91ether_rx(struct net_device
*dev
)
846 struct at91_private
*lp
= netdev_priv(dev
);
847 struct recv_desc_bufs
*dlist
;
848 unsigned char *p_recv
;
853 while (dlist
->descriptors
[lp
->rxBuffIndex
].addr
& EMAC_DESC_DONE
) {
854 p_recv
= dlist
->recv_buf
[lp
->rxBuffIndex
];
855 pktlen
= dlist
->descriptors
[lp
->rxBuffIndex
].size
& 0x7ff; /* Length of frame including FCS */
856 skb
= dev_alloc_skb(pktlen
+ 2);
859 memcpy(skb_put(skb
, pktlen
), p_recv
, pktlen
);
862 skb
->protocol
= eth_type_trans(skb
, dev
);
863 dev
->last_rx
= jiffies
;
864 lp
->stats
.rx_bytes
+= pktlen
;
868 lp
->stats
.rx_dropped
+= 1;
869 printk(KERN_NOTICE
"%s: Memory squeeze, dropping packet.\n", dev
->name
);
872 if (dlist
->descriptors
[lp
->rxBuffIndex
].size
& EMAC_MULTICAST
)
873 lp
->stats
.multicast
++;
875 dlist
->descriptors
[lp
->rxBuffIndex
].addr
&= ~EMAC_DESC_DONE
; /* reset ownership bit */
876 if (lp
->rxBuffIndex
== MAX_RX_DESCR
-1) /* wrap after last buffer */
884 * MAC interrupt handler
886 static irqreturn_t
at91ether_interrupt(int irq
, void *dev_id
)
888 struct net_device
*dev
= (struct net_device
*) dev_id
;
889 struct at91_private
*lp
= netdev_priv(dev
);
890 unsigned long intstatus
, ctl
;
892 /* MAC Interrupt Status register indicates what interrupts are pending.
893 It is automatically cleared once read. */
894 intstatus
= at91_emac_read(AT91_EMAC_ISR
);
896 if (intstatus
& AT91_EMAC_RCOM
) /* Receive complete */
899 if (intstatus
& AT91_EMAC_TCOM
) { /* Transmit complete */
900 /* The TCOM bit is set even if the transmission failed. */
901 if (intstatus
& (AT91_EMAC_TUND
| AT91_EMAC_RTRY
))
902 lp
->stats
.tx_errors
+= 1;
905 dev_kfree_skb_irq(lp
->skb
);
907 dma_unmap_single(NULL
, lp
->skb_physaddr
, lp
->skb_length
, DMA_TO_DEVICE
);
909 netif_wake_queue(dev
);
912 /* Work-around for Errata #11 */
913 if (intstatus
& AT91_EMAC_RBNA
) {
914 ctl
= at91_emac_read(AT91_EMAC_CTL
);
915 at91_emac_write(AT91_EMAC_CTL
, ctl
& ~AT91_EMAC_RE
);
916 at91_emac_write(AT91_EMAC_CTL
, ctl
| AT91_EMAC_RE
);
919 if (intstatus
& AT91_EMAC_ROVR
)
920 printk("%s: ROVR error\n", dev
->name
);
925 #ifdef CONFIG_NET_POLL_CONTROLLER
926 static void at91ether_poll_controller(struct net_device
*dev
)
930 local_irq_save(flags
);
931 at91ether_interrupt(dev
->irq
, dev
);
932 local_irq_restore(flags
);
937 * Initialize the ethernet interface
939 static int __init
at91ether_setup(unsigned long phy_type
, unsigned short phy_address
,
940 struct platform_device
*pdev
, struct clk
*ether_clk
)
942 struct at91_eth_data
*board_data
= pdev
->dev
.platform_data
;
943 struct net_device
*dev
;
944 struct at91_private
*lp
;
948 dev
= alloc_etherdev(sizeof(struct at91_private
));
952 dev
->base_addr
= AT91_VA_BASE_EMAC
;
953 dev
->irq
= AT91RM9200_ID_EMAC
;
954 SET_MODULE_OWNER(dev
);
956 /* Install the interrupt handler */
957 if (request_irq(dev
->irq
, at91ether_interrupt
, 0, dev
->name
, dev
)) {
962 /* Allocate memory for DMA Receive descriptors */
963 lp
= netdev_priv(dev
);
964 lp
->dlist
= (struct recv_desc_bufs
*) dma_alloc_coherent(NULL
, sizeof(struct recv_desc_bufs
), (dma_addr_t
*) &lp
->dlist_phys
, GFP_KERNEL
);
965 if (lp
->dlist
== NULL
) {
966 free_irq(dev
->irq
, dev
);
970 lp
->board_data
= *board_data
;
971 lp
->ether_clk
= ether_clk
;
972 platform_set_drvdata(pdev
, dev
);
974 spin_lock_init(&lp
->lock
);
977 dev
->open
= at91ether_open
;
978 dev
->stop
= at91ether_close
;
979 dev
->hard_start_xmit
= at91ether_tx
;
980 dev
->get_stats
= at91ether_stats
;
981 dev
->set_multicast_list
= at91ether_set_rx_mode
;
982 dev
->set_mac_address
= set_mac_address
;
983 dev
->ethtool_ops
= &at91ether_ethtool_ops
;
984 dev
->do_ioctl
= at91ether_ioctl
;
985 #ifdef CONFIG_NET_POLL_CONTROLLER
986 dev
->poll_controller
= at91ether_poll_controller
;
989 SET_NETDEV_DEV(dev
, &pdev
->dev
);
991 get_mac_address(dev
); /* Get ethernet address and store it in dev->dev_addr */
992 update_mac_address(dev
); /* Program ethernet address into MAC */
994 at91_emac_write(AT91_EMAC_CTL
, 0);
996 if (lp
->board_data
.is_rmii
)
997 at91_emac_write(AT91_EMAC_CFG
, AT91_EMAC_CLK_DIV32
| AT91_EMAC_BIG
| AT91_EMAC_RMII
);
999 at91_emac_write(AT91_EMAC_CFG
, AT91_EMAC_CLK_DIV32
| AT91_EMAC_BIG
);
1001 /* Perform PHY-specific initialization */
1002 spin_lock_irq(&lp
->lock
);
1004 if ((phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
)) {
1005 read_phy(phy_address
, MII_DSCR_REG
, &val
);
1006 if ((val
& (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1007 lp
->phy_media
= PORT_FIBRE
;
1008 } else if (machine_is_csb337()) {
1009 /* mix link activity status into LED2 link state */
1010 write_phy(phy_address
, MII_LEDCTRL_REG
, 0x0d22);
1013 spin_unlock_irq(&lp
->lock
);
1015 lp
->mii
.dev
= dev
; /* Support for ethtool */
1016 lp
->mii
.mdio_read
= mdio_read
;
1017 lp
->mii
.mdio_write
= mdio_write
;
1018 lp
->mii
.phy_id
= phy_address
;
1019 lp
->mii
.phy_id_mask
= 0x1f;
1020 lp
->mii
.reg_num_mask
= 0x1f;
1022 lp
->phy_type
= phy_type
; /* Type of PHY connected */
1023 lp
->phy_address
= phy_address
; /* MDI address of PHY */
1025 /* Register the network interface */
1026 res
= register_netdev(dev
);
1028 free_irq(dev
->irq
, dev
);
1030 dma_free_coherent(NULL
, sizeof(struct recv_desc_bufs
), lp
->dlist
, (dma_addr_t
)lp
->dlist_phys
);
1034 /* Determine current link speed */
1035 spin_lock_irq(&lp
->lock
);
1037 update_linkspeed(dev
, 0);
1039 spin_unlock_irq(&lp
->lock
);
1040 netif_carrier_off(dev
); /* will be enabled in open() */
1042 /* If board has no PHY IRQ, use a timer to poll the PHY */
1043 if (!lp
->board_data
.phy_irq_pin
) {
1044 init_timer(&lp
->check_timer
);
1045 lp
->check_timer
.data
= (unsigned long)dev
;
1046 lp
->check_timer
.function
= at91ether_check_link
;
1049 /* Display ethernet banner */
1050 printk(KERN_INFO
"%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n",
1051 dev
->name
, (uint
) dev
->base_addr
, dev
->irq
,
1052 at91_emac_read(AT91_EMAC_CFG
) & AT91_EMAC_SPD
? "100-" : "10-",
1053 at91_emac_read(AT91_EMAC_CFG
) & AT91_EMAC_FD
? "FullDuplex" : "HalfDuplex",
1054 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
1055 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
1056 if ((phy_type
== MII_DM9161_ID
) || (lp
->phy_type
== MII_DM9161A_ID
))
1057 printk(KERN_INFO
"%s: Davicom 9161 PHY %s\n", dev
->name
, (lp
->phy_media
== PORT_FIBRE
) ? "(Fiber)" : "(Copper)");
1058 else if (phy_type
== MII_LXT971A_ID
)
1059 printk(KERN_INFO
"%s: Intel LXT971A PHY\n", dev
->name
);
1060 else if (phy_type
== MII_RTL8201_ID
)
1061 printk(KERN_INFO
"%s: Realtek RTL8201(B)L PHY\n", dev
->name
);
1062 else if (phy_type
== MII_BCM5221_ID
)
1063 printk(KERN_INFO
"%s: Broadcom BCM5221 PHY\n", dev
->name
);
1064 else if (phy_type
== MII_DP83847_ID
)
1065 printk(KERN_INFO
"%s: National Semiconductor DP83847 PHY\n", dev
->name
);
1066 else if (phy_type
== MII_AC101L_ID
)
1067 printk(KERN_INFO
"%s: Altima AC101L PHY\n", dev
->name
);
1068 else if (phy_type
== MII_KS8721_ID
)
1069 printk(KERN_INFO
"%s: Micrel KS8721 PHY\n", dev
->name
);
1075 * Detect MAC and PHY and perform initialization
1077 static int __init
at91ether_probe(struct platform_device
*pdev
)
1079 unsigned int phyid1
, phyid2
;
1081 unsigned long phy_id
;
1082 unsigned short phy_address
= 0;
1083 struct clk
*ether_clk
;
1085 ether_clk
= clk_get(&pdev
->dev
, "ether_clk");
1086 if (IS_ERR(ether_clk
)) {
1087 printk(KERN_ERR
"at91_ether: no clock defined\n");
1090 clk_enable(ether_clk
); /* Enable Peripheral clock */
1092 while ((detected
!= 0) && (phy_address
< 32)) {
1093 /* Read the PHY ID registers */
1095 read_phy(phy_address
, MII_PHYSID1
, &phyid1
);
1096 read_phy(phy_address
, MII_PHYSID2
, &phyid2
);
1099 phy_id
= (phyid1
<< 16) | (phyid2
& 0xfff0);
1101 case MII_DM9161_ID
: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1102 case MII_DM9161A_ID
: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1103 case MII_LXT971A_ID
: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1104 case MII_RTL8201_ID
: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1105 case MII_BCM5221_ID
: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1106 case MII_DP83847_ID
: /* National Semiconductor DP83847: */
1107 case MII_AC101L_ID
: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1108 case MII_KS8721_ID
: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1109 detected
= at91ether_setup(phy_id
, phy_address
, pdev
, ether_clk
);
1116 clk_disable(ether_clk
); /* Disable Peripheral clock */
1121 static int __devexit
at91ether_remove(struct platform_device
*pdev
)
1123 struct net_device
*dev
= platform_get_drvdata(pdev
);
1124 struct at91_private
*lp
= netdev_priv(dev
);
1126 unregister_netdev(dev
);
1127 free_irq(dev
->irq
, dev
);
1128 dma_free_coherent(NULL
, sizeof(struct recv_desc_bufs
), lp
->dlist
, (dma_addr_t
)lp
->dlist_phys
);
1129 clk_put(lp
->ether_clk
);
1131 platform_set_drvdata(pdev
, NULL
);
1138 static int at91ether_suspend(struct platform_device
*pdev
, pm_message_t mesg
)
1140 struct net_device
*net_dev
= platform_get_drvdata(pdev
);
1141 struct at91_private
*lp
= netdev_priv(net_dev
);
1142 int phy_irq
= lp
->board_data
.phy_irq_pin
;
1144 if (netif_running(net_dev
)) {
1146 disable_irq(phy_irq
);
1148 netif_stop_queue(net_dev
);
1149 netif_device_detach(net_dev
);
1151 clk_disable(lp
->ether_clk
);
1156 static int at91ether_resume(struct platform_device
*pdev
)
1158 struct net_device
*net_dev
= platform_get_drvdata(pdev
);
1159 struct at91_private
*lp
= netdev_priv(net_dev
);
1160 int phy_irq
= lp
->board_data
.phy_irq_pin
;
1162 if (netif_running(net_dev
)) {
1163 clk_enable(lp
->ether_clk
);
1165 netif_device_attach(net_dev
);
1166 netif_start_queue(net_dev
);
1169 enable_irq(phy_irq
);
1175 #define at91ether_suspend NULL
1176 #define at91ether_resume NULL
1179 static struct platform_driver at91ether_driver
= {
1180 .probe
= at91ether_probe
,
1181 .remove
= __devexit_p(at91ether_remove
),
1182 .suspend
= at91ether_suspend
,
1183 .resume
= at91ether_resume
,
1186 .owner
= THIS_MODULE
,
1190 static int __init
at91ether_init(void)
1192 return platform_driver_register(&at91ether_driver
);
1195 static void __exit
at91ether_exit(void)
1197 platform_driver_unregister(&at91ether_driver
);
1200 module_init(at91ether_init
)
1201 module_exit(at91ether_exit
)
1203 MODULE_LICENSE("GPL");
1204 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1205 MODULE_AUTHOR("Andrew Victor");