drivers/staging/rtl8192su/r8192S_hw.h

   1 /*****************************************************************************
   2  *      Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
   3  *
   4  * Module:      __INC_HAL8192SEREG_H
   5  *
   6  *
   7  * Note:        1. Define Mac register address and corresponding bit mask map
   8  *                      2. CCX register
   9  *                      3. Backward compatible register with useless address.
  10  *                      4. Define 92SU required register address and definition.
  11  *
  12  *
  13  * Export:      Constants, macro, functions(API), global variables(None).
  14  *
  15  * Abbrev:
  16  *
  17  * History:
  18  *              Data            Who             Remark
  19  *      08/07/2007  MHC         1. Porting from 9x series PHYCFG.h.
  20  *                                                      2. Reorganize code architecture.
  21  *
  22  *****************************************************************************/
  23 #ifndef R8192S_HW
  24 #define R8192S_HW
  25
  26 typedef enum _VERSION_8192S{
  27         VERSION_8192S_ACUT,
  28         VERSION_8192S_BCUT,
  29         VERSION_8192S_CCUT
  30 }VERSION_8192S,*PVERSION_8192S;
  31
  32 //#ifdef RTL8192SU
  33 typedef enum _VERSION_8192SUsb{
  34         VERSION_8192SU_A, //A-Cut
  35         VERSION_8192SU_B, //B-Cut
  36         VERSION_8192SU_C, //C-Cut
  37 }VERSION_8192SUsb, *PVERSION_8192SUsb;
  38 //#else
  39 typedef enum _VERSION_819xU{
  40         VERSION_819xU_A, // A-cut
  41         VERSION_819xU_B, // B-cut
  42         VERSION_819xU_C,// C-cut
  43 }VERSION_819xU,*PVERSION_819xU;
  44 //#endif
  45
  46 /* 2007/11/15 MH Define different RF type. */
  47 typedef enum _RT_RF_TYPE_DEFINITION
  48 {
  49         RF_1T2R = 0,
  50         RF_2T4R,
  51         RF_2T2R,
  52         RF_1T1R,
  53         RF_2T2R_GREEN,
  54         //RF_3T3R,
  55         //RF_3T4R,
  56         //RF_4T4R,
  57         RF_819X_MAX_TYPE
  58 }RT_RF_TYPE_DEF_E;
  59
  60 typedef enum _BaseBand_Config_Type{
  61         BaseBand_Config_PHY_REG = 0,                    //Radio Path A
  62         BaseBand_Config_AGC_TAB = 1,                    //Radio Path B
  63 }BaseBand_Config_Type, *PBaseBand_Config_Type;
  64
  65 #define RTL8187_REQT_READ               0xc0
  66 #define RTL8187_REQT_WRITE      0x40
  67 #define RTL8187_REQ_GET_REGS    0x05
  68 #define RTL8187_REQ_SET_REGS    0x05
  69
  70 #define MAX_TX_URB 5
  71 #define MAX_RX_URB 16
  72
  73 #define R8180_MAX_RETRY 255
  74 //#define MAX_RX_NORMAL_URB 3
  75 //#define MAX_RX_COMMAND_URB 2
  76 #define RX_URB_SIZE             9100
  77
  78 #define BB_ANTATTEN_CHAN14      0x0c
  79 #define BB_ANTENNA_B            0x40
  80
  81 #define BB_HOST_BANG            (1<<30)
  82 #define BB_HOST_BANG_EN         (1<<2)
  83 #define BB_HOST_BANG_CLK        (1<<1)
  84 #define BB_HOST_BANG_RW         (1<<3)
  85 #define BB_HOST_BANG_DATA       1
  86
  87
  88 //============================================================
  89 //       8192S Regsiter bit
  90 //============================================================
  91 #define BB_GLOBAL_RESET_BIT     0x1
  92
  93 #define CR_RST                  0x10
  94 #define CR_RE                   0x08
  95 #define CR_TE                   0x04
  96 #define CR_MulRW                        0x01
  97
  98 #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
  99                 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
 100
 101 #define RX_FIFO_THRESHOLD_MASK  ((1<<13) | (1<<14) | (1<<15))
 102 #define RX_FIFO_THRESHOLD_SHIFT         13
 103 #define RX_FIFO_THRESHOLD_128           3
 104 #define RX_FIFO_THRESHOLD_256           4
 105 #define RX_FIFO_THRESHOLD_512           5
 106 #define RX_FIFO_THRESHOLD_1024          6
 107 #define RX_FIFO_THRESHOLD_NONE  7
 108
 109 #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
 110
 111 //----------------------------------------------------------------------------
 112 //       8190 CPU General Register              (offset 0x100, 4 byte)
 113 //----------------------------------------------------------------------------
 114 #define CPU_CCK_LOOPBACK                        0x00030000
 115 #define CPU_GEN_SYSTEM_RESET            0x00000001
 116 #define CPU_GEN_FIRMWARE_RESET  0x00000008
 117 #define CPU_GEN_BOOT_RDY                        0x00000010
 118 #define CPU_GEN_FIRM_RDY                        0x00000020
 119 #define CPU_GEN_PUT_CODE_OK             0x00000080
 120 #define CPU_GEN_BB_RST                          0x00000100
 121 #define CPU_GEN_PWR_STB_CPU             0x00000004
 122 #define         CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
 123 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
 124 //----------------------------------------------------------------------------
 125 ////
 126 ////       8190 AcmHwCtrl bits                                    (offset 0x171, 1 byte)
 127 ////----------------------------------------------------------------------------
 128 #define MSR_LINK_MASK           ((1<<0)|(1<<1))
 129 #define MSR_LINK_MANAGED        2
 130 #define MSR_LINK_NONE           0
 131 #define MSR_LINK_SHIFT          0
 132 #define MSR_LINK_ADHOC          1
 133 #define MSR_LINK_MASTER         3
 134 #define MSR_LINK_ENEDCA         (1<<4)
 135
 136
 137 //#define Cmd9346CR_9356SEL     (1<<4)
 138 #define EPROM_CMD_RESERVED_MASK                         (1<<5)
 139 #define EPROM_CMD_OPERATING_MODE_SHIFT  6
 140 #define EPROM_CMD_OPERATING_MODE_MASK   ((1<<7)|(1<<6))
 141 #define EPROM_CMD_CONFIG                0x3
 142 #define EPROM_CMD_NORMAL                0
 143 #define EPROM_CMD_LOAD                  1
 144 #define EPROM_CMD_PROGRAM               2
 145 #define EPROM_CS_SHIFT                  3
 146 #define EPROM_CK_SHIFT                  2
 147 #define EPROM_W_SHIFT                   1
 148 #define EPROM_R_SHIFT                   0
 149
 150 //#define       MAC0                     0x000,
 151 //#define       MAC1                     0x001,
 152 //#define       MAC2                     0x002,
 153 //#define       MAC3                     0x003,
 154 //#define       MAC4                     0x004,
 155 //#define       MAC5                     0x005,
 156
 157 //============================================================
 158 //       8192S Regsiter offset definition
 159 //============================================================
 160
 161 //
 162 // MAC register 0x0 - 0x5xx
 163 // 1. System configuration registers.
 164 // 2. Command Control Registers
 165 // 3. MACID Setting Registers
 166 // 4. Timing Control Registers
 167 // 5. FIFO Control Registers
 168 // 6. Adaptive Control Registers
 169 // 7. EDCA Setting Registers
 170 // 8. WMAC, BA and CCX related Register.
 171 // 9. Security Control Registers
 172 // 10. Power Save Control Registers
 173 // 11. General Purpose Registers
 174 // 12. Host Interrupt Status Registers
 175 // 13. Test Mode and Debug Control Registers
 176 // 14. PCIE config register
 177 //
 178
 179
 180 //
 181 // 1. System Configuration Registers     (Offset: 0x0000 - 0x003F)
 182 //
 183 #define         SYS_ISO_CTRL            0x0000  // System Isolation Interface Control.
 184 #define         SYS_FUNC_EN             0x0002  // System Function Enable.
 185 #define         PMC_FSM                 0x0004  // Power Sequence Control.
 186 #define         SYS_CLKR                        0x0008  // System Clock.
 187 #define         EPROM_CMD                       0x000A  // 93C46/93C56 Command Register. (win CR93C46)
 188 #define         EE_VPD                          0x000C  // EEPROM VPD Data.
 189 #define         AFE_MISC                        0x0010  // AFE Misc.
 190 #define         SPS0_CTRL                       0x0011  // Switching Power Supply 0 Control.
 191 #define         SPS1_CTRL                       0x0018  // Switching Power Supply 1 Control.
 192 #define         RF_CTRL                         0x001F  // RF Block Control.
 193 #define         LDOA15_CTRL             0x0020  // V15 Digital LDO Control.
 194 #define         LDOV12D_CTRL            0x0021  // V12 Digital LDO Control.
 195 #define         LDOHCI12_CTRL           0x0022  // V12 Digital LDO Control.
 196 #define         LDO_USB_SDIO            0x0023  // LDO USB Control.
 197 #define         LPLDO_CTRL                      0x0024  // Low Power LDO Control.
 198 #define         AFE_XTAL_CTRL           0x0026  // AFE Crystal Control.
 199 #define         AFE_PLL_CTRL            0x0028  // System Function Enable.
 200 #define         EFUSE_CTRL                      0x0030  // E-Fuse Control.
 201 #define         EFUSE_TEST                      0x0034  // E-Fuse Test.
 202 #define         PWR_DATA                        0x0038  // Power on date.
 203 #define         DBG_PORT                        0x003A  // MAC debug port select
 204 #define         DPS_TIMER                       0x003C  // Deep Power Save Timer Register.
 205 #define         RCLK_MON                        0x003E  // Retention Clock Monitor.
 206
 207 //
 208 // 2. Command Control Registers  (Offset: 0x0040 - 0x004F)
 209 //
 210 #define         CMDR                            0x0040  // MAC Command Register.
 211 #define         TXPAUSE                         0x0042  // Transmission Pause Register.
 212 #define         LBKMD_SEL                       0x0043  // Loopback Mode Select Register.
 213 #define         TCR                                     0x0044  // Transmit Configuration Register
 214 #define         RCR                                     0x0048  // Receive Configuration Register
 215 #define         MSR                                     0x004C  // Media Status register
 216 #define         SYSF_CFG                        0x004D  // System Function Configuration.
 217 #define         RX_PKY_LIMIT            0x004E  // RX packet length limit
 218 #define         MBIDCTRL                        0x004F  // MBSSID Control.
 219
 220 //
 221 // 3. MACID Setting Registers   (Offset: 0x0050 - 0x007F)
 222 //
 223 #define         MACIDR                          0x0050  // MAC ID Register, Offset 0x0050-0x0055
 224 #define         MACIDR0                         0x0050  // MAC ID Register, Offset 0x0050-0x0053
 225 #define         MACIDR4                         0x0054  // MAC ID Register, Offset 0x0054-0x0055
 226 #define         BSSIDR                          0x0058  // BSSID Register, Offset 0x0058-0x005D
 227 #define         HWVID                           0x005E  // HW Version ID.
 228 #define         MAR                                     0x0060  // Multicase Address.
 229 #define         MBIDCAMCONTENT  0x0068  // MBSSID CAM Content.
 230 #define         MBIDCAMCFG                      0x0070  // MBSSID CAM Configuration.
 231 #define         BUILDTIME                       0x0074  // Build Time Register.
 232 #define         BUILDUSER                       0x0078  // Build User Register.
 233
 234 // Redifine MACID register, to compatible prior ICs.
 235 #define         IDR0                            MACIDR0
 236 #define         IDR4                            MACIDR4
 237
 238 //
 239 // 4. Timing Control Registers  (Offset: 0x0080 - 0x009F)
 240 //
 241 #define         TSFR                            0x0080  // Timing Sync Function Timer Register.
 242 #define         SLOT_TIME                       0x0089  // Slot Time Register, in us.
 243 #define         USTIME                          0x008A  // EDCA/TSF clock unit time us unit.
 244 #define         SIFS_CCK                        0x008C  // SIFS for CCK, in us.
 245 #define         SIFS_OFDM                       0x008E  // SIFS for OFDM, in us.
 246 #define         PIFS_TIME                       0x0090  // PIFS time register.
 247 #define         ACK_TIMEOUT             0x0091  // Ack Timeout Register
 248 #define         EIFSTR                          0x0092  // EIFS time regiser.
 249 #define         BCN_INTERVAL            0x0094  // Beacon Interval, in TU.
 250 #define         ATIMWND                 0x0096  // ATIM Window width, in TU.
 251 #define         BCN_DRV_EARLY_INT       0x0098  // Driver Early Interrupt.
 252 #define         BCN_DMATIME             0x009A  // Beacon DMA and ATIM INT Time.
 253 #define         BCN_ERR_THRESH          0x009C  // Beacon Error Threshold.
 254 #define         MLT                                     0x009D  // MSDU Lifetime.
 255 #define         RSVD_MAC_TUNE_US        0x009E  // MAC Internal USE.
 256
 257 //
 258 // 5. FIFO Control Registers     (Offset: 0x00A0 - 0x015F)
 259 //
 260 #define         RQPN                            0x00A0
 261 #define RQPN1                           0x00A0  // Reserved Queue Page Number for BK
 262 #define RQPN2                           0x00A1  // Reserved Queue Page Number for BE
 263 #define RQPN3                           0x00A2  // Reserved Queue Page Number for VI
 264 #define RQPN4                           0x00A3  // Reserved Queue Page Number for VO
 265 #define RQPN5                           0x00A4  // Reserved Queue Page Number for HCCA
 266 #define RQPN6                           0x00A5  // Reserved Queue Page Number for CMD
 267 #define RQPN7                           0x00A6  // Reserved Queue Page Number for MGNT
 268 #define RQPN8                           0x00A7  // Reserved Queue Page Number for HIGH
 269 #define RQPN9                           0x00A8  // Reserved Queue Page Number for Beacon
 270 #define RQPN10                          0x00A9  // Reserved Queue Page Number for Public
 271 #define         LD_RQPN                         0x00AB  //
 272 #define         RXFF_BNDY                       0x00AC  //
 273 #define         RXRPT_BNDY                      0x00B0  //
 274 #define         TXPKTBUF_PGBNDY         0x00B4  //
 275 #define         PBP                                     0x00B5  //
 276 #define         RXDRVINFO_SZ            0x00B6  //
 277 #define         TXFF_STATUS                     0x00B7  //
 278 #define         RXFF_STATUS                     0x00B8  //
 279 #define         TXFF_EMPTY_TH           0x00B9  //
 280 #define         SDIO_RX_BLKSZ           0x00BC  //
 281 #define         RXDMA                           0x00BD  //
 282 #define         RXPKT_NUM                       0x00BE  //
 283 #define         C2HCMD_UDT_SIZE         0x00C0  //
 284 #define         C2HCMD_UDT_ADDR         0x00C2  //
 285 #define         FIFOPAGE1                       0x00C4  // Available public queue page number
 286 #define         FIFOPAGE2                       0x00C8  //
 287 #define         FIFOPAGE3                       0x00CC  //
 288 #define         FIFOPAGE4                       0x00D0  //
 289 #define         FIFOPAGE5                       0x00D4  //
 290 #define         FW_RSVD_PG_CRTL         0x00D8  //
 291 #define         RXDMA_AGG_PG_TH         0x00D9  //
 292 #define         TXRPTFF_RDPTR           0x00E0  //
 293 #define         TXRPTFF_WTPTR           0x00E4  //
 294 #define         C2HFF_RDPTR                     0x00E8  //FIFO Read pointer register.
 295 #define         C2HFF_WTPTR                     0x00EC  //FIFO Write pointer register.
 296 #define         RXFF0_RDPTR                     0x00F0  //
 297 #define         RXFF0_WTPTR                     0x00F4  //
 298 #define         RXFF1_RDPTR                     0x00F8  //
 299 #define         RXFF1_WTPTR                     0x00FC  //
 300 #define         RXRPT0_RDPTR            0x0100  //
 301 #define         RXRPT0_WTPTR            0x0104  //
 302 #define         RXRPT1_RDPTR            0x0108  //
 303 #define         RXRPT1_WTPTR            0x010C  //
 304 #define         RX0_UDT_SIZE            0x0110  //
 305 #define         RX1PKTNUM                       0x0114  //
 306 #define         RXFILTERMAP                     0x0116  //
 307 #define         RXFILTERMAP_GP1         0x0118  //
 308 #define         RXFILTERMAP_GP2         0x011A  //
 309 #define         RXFILTERMAP_GP3         0x011C  //
 310 #define         BCNQ_CTRL                       0x0120  //
 311 #define         MGTQ_CTRL                       0x0124  //
 312 #define         HIQ_CTRL                        0x0128  //
 313 #define         VOTID7_CTRL                     0x012c  //
 314 #define         VOTID6_CTRL                     0x0130  //
 315 #define         VITID5_CTRL                     0x0134  //
 316 #define         VITID4_CTRL                     0x0138  //
 317 #define         BETID3_CTRL                     0x013c  //
 318 #define         BETID0_CTRL                     0x0140  //
 319 #define         BKTID2_CTRL                     0x0144  //
 320 #define         BKTID1_CTRL                     0x0148  //
 321 #define         CMDQ_CTRL                       0x014c  //
 322 #define         TXPKT_NUM_CTRL          0x0150  //
 323 #define         TXQ_PGADD                       0x0152  //
 324 #define         TXFF_PG_NUM                     0x0154  //
 325 #define         TRXDMA_STATUS           0x0156  //
 326
 327 //
 328 // 6. Adaptive Control Registers  (Offset: 0x0160 - 0x01CF)
 329 //
 330 #define         INIMCS_SEL                      0x0160  // Init MCSrate for 32 MACID 0x160-17f
 331 #define         TX_RATE_REG             INIMCS_SEL //Current Tx rate register
 332 #define         INIRTSMCS_SEL           0x0180  // Init RTSMCSrate
 333 #define         RRSR                            0x0181  // Response rate setting.
 334 #define         ARFR0                           0x0184  // Auto Rate Fallback 0 Register.
 335 #define         ARFR1                           0x0188  //
 336 #define         ARFR2                           0x018C  //
 337 #define         ARFR3                           0x0190  //
 338 #define         ARFR4                           0x0194  //
 339 #define         ARFR5                           0x0198  //
 340 #define         ARFR6                           0x019C  //
 341 #define         ARFR7                           0x01A0  //
 342 #define         AGGLEN_LMT_H            0x01A7  // Aggregation Length Limit for High-MCS
 343 #define         AGGLEN_LMT_L            0x01A8  // Aggregation Length Limit for Low-MCS.
 344 #define         DARFRC                          0x01B0  // Data Auto Rate Fallback Retry Count.
 345 #define         RARFRC                          0x01B8  // Response Auto Rate Fallback Count.
 346 #define         MCS_TXAGC                       0x01C0
 347 #define         CCK_TXAGC                       0x01C8
 348
 349 //
 350 // 7. EDCA Setting Registers     (Offset: 0x01D0 - 0x01FF)
 351 //
 352 #define         EDCAPARA_VO             0x01D0  // EDCA Parameter Register for VO queue.
 353 #define         EDCAPARA_VI                     0x01D4  // EDCA Parameter Register for VI queue.
 354 #define         EDCAPARA_BE                     0x01D8  // EDCA Parameter Register for BE queue.
 355 #define         EDCAPARA_BK                     0x01DC  // EDCA Parameter Register for BK queue.
 356 #define         BCNTCFG                         0x01E0  // Beacon Time Configuration Register.
 357 #define         CWRR                            0x01E2  // Contention Window Report Register.
 358 #define         ACMAVG                          0x01E4  // ACM Average Register.
 359 #define         AcmHwCtrl                       0x01E7
 360 #define         VO_ADMTM                        0x01E8  // Admission Time Register.
 361 #define         VI_ADMTM                        0x01EC
 362 #define         BE_ADMTM                        0x01F0
 363 #define         RETRY_LIMIT                     0x01F4  // Retry Limit Registers[15:8]-short, [7:0]-long
 364 #define         SG_RATE                         0x01F6  // Max MCS Rate Available Register, which we Set the hightst SG rate.
 365
 366 //
 367 // 8. WMAC, BA and CCX related Register.         (Offset: 0x0200 - 0x023F)
 368 //
 369 #define         NAV_CTRL                        0x0200
 370 #define         BW_OPMODE                       0x0203
 371 #define         BACAMCMD                        0x0204
 372 #define         BACAMCONTENT            0x0208  // Block ACK CAM R/W Register.
 373
 374 // Roger had defined the 0x2xx register WMAC definition
 375 #define         LBDLY                           0x0210  // Loopback Delay Register.
 376 #define         FWDLY                           0x0211  // FW Delay Register.
 377 #define         HWPC_RX_CTRL            0x0218  // HW Packet Conversion RX Control Reg
 378 #define         MQIR                            0x0220  // Mesh Qos Type Indication Register.
 379 #define         MAIR                            0x0222  // Mesh ACK.
 380 #define         MSIR                            0x0224  // Mesh HW Security Requirement Indication Reg
 381 #define         CLM_RESULT                      0x0227  // CCA Busy Fraction(Channel Load)
 382 #define         NHM_RPI_CNT                     0x0228  // Noise Histogram Measurement (NHM) RPI Report.
 383 #define         RXERR_RPT                       0x0230  // Rx Error Report.
 384 #define         NAV_PROT_LEN            0x0234  // NAV Protection Length.
 385 #define         CFEND_TH                        0x0236  // CF-End Threshold.
 386 #define         AMPDU_MIN_SPACE         0x0237  // AMPDU Min Space.
 387 #define         TXOP_STALL_CTRL         0x0238
 388
 389 //
 390 // 9. Security Control Registers        (Offset: 0x0240 - 0x025F)
 391 //
 392 #define         RWCAM                           0x0240  //IN 8190 Data Sheet is called CAMcmd
 393 #define         WCAMI                           0x0244  // Software write CAM input content
 394 #define         RCAMO                           0x0248  // Software read/write CAM config
 395 #define         CAMDBG                          0x024C
 396 #define         SECR                            0x0250  //Security Configuration Register
 397
 398 //
 399 // 10. Power Save Control Registers      (Offset: 0x0260 - 0x02DF)
 400 //
 401 #define         WOW_CTRL                        0x0260  //Wake On WLAN Control.
 402 #define         PSSTATUS                        0x0261  // Power Save Status.
 403 #define         PSSWITCH                        0x0262  // Power Save Switch.
 404 #define         MIMOPS_WAIT_PERIOD      0x0263
 405 #define         LPNAV_CTRL                      0x0264
 406 #define         WFM0                            0x0270  // Wakeup Frame Mask.
 407 #define         WFM1                            0x0280  //
 408 #define         WFM2                            0x0290  //
 409 #define         WFM3                            0x02A0  //
 410 #define         WFM4                            0x02B0  //
 411 #define         WFM5                            0x02C0  // FW Control register.
 412 #define         WFCRC                           0x02D0  // Wakeup Frame CRC.
 413 #define         RPWM                            0x02DC  // Host Request Power Mode.
 414 #define         CPWM                            0x02DD  // Current Power Mode.
 415 #define         FW_RPT_REG                      0x02c4
 416
 417 //
 418 // 11. General Purpose Registers        (Offset: 0x02E0 - 0x02FF)
 419 //
 420 #define         PSTIME                          0x02E0  // Power Save Timer Register
 421 #define         TIMER0                          0x02E4  //
 422 #define         TIMER1                          0x02E8  //
 423 #define         GPIO_CTRL                       0x02EC  // GPIO Control Register
 424 #define         GPIO_IN                         0x02EC  // GPIO pins input value
 425 #define         GPIO_OUT                        0x02ED  // GPIO pins output value
 426 #define         GPIO_IO_SEL                     0x02EE  // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured.
 427 #define         GPIO_MOD                        0x02EF  //
 428 #define         GPIO_INTCTRL            0x02F0  // GPIO Interrupt Control Register[7:0]
 429 #define         MAC_PINMUX_CFG          0x02F1  // MAC PINMUX Configuration Reg[7:0]
 430 #define         LEDCFG                          0x02F2  // System PINMUX Configuration Reg[7:0]
 431 #define         PHY_REG                         0x02F3  // RPT: PHY REG Access Report Reg[7:0]
 432 #define         PHY_REG_DATA            0x02F4  // PHY REG Read DATA Register [31:0]
 433 #define         EFUSE_CLK                       0x02F8  // CTRL: E-FUSE Clock Control Reg[7:0]
 434 //#define               GPIO_INTCTRL            0x02F9  // GPIO Interrupt Control Register[7:0]
 435
 436 //
 437 // 12. Host Interrupt Status Registers   (Offset: 0x0300 - 0x030F)
 438 //
 439 #define         IMR                                     0x0300  // Interrupt Mask Register
 440 #define         ISR                                     0x0308  // Interrupt Status Register
 441
 442 //
 443 // 13. Test Mode and Debug Control Registers    (Offset: 0x0310 - 0x034F)
 444 //
 445 #define         DBG_PORT_SWITCH         0x003A
 446 #define         BIST                            0x0310  // Bist reg definition
 447 #define         DBS                                     0x0314  // Debug Select ???
 448 #define         CPUINST                         0x0318  // CPU Instruction Read Register
 449 #define         CPUCAUSE                        0x031C  // CPU Cause Register
 450 #define         LBUS_ERR_ADDR           0x0320  // Lexra Bus Error Address Register
 451 #define         LBUS_ERR_CMD            0x0324  // Lexra Bus Error Command Register
 452 #define         LBUS_ERR_DATA_L         0x0328  // Lexra Bus Error Data Low DW Register
 453 #define         LBUS_ERR_DATA_H         0x032C  //
 454 #define         LX_EXCEPTION_ADDR       0x0330  // Lexra Bus Exception Address Register
 455 #define         WDG_CTRL                        0x0334  // Watch Dog Control Register
 456 #define         INTMTU                          0x0338  // Interrupt Mitigation Time Unit Reg
 457 #define         INTM                            0x033A  // Interrupt Mitigation Register
 458 #define         FDLOCKTURN0                     0x033C  // FW/DRV Lock Turn 0 Register
 459 #define         FDLOCKTURN1                     0x033D  // FW/DRV Lock Turn 1 Register
 460 #define         TRXPKTBUF_DBG_DATA      0x0340  // TRX Packet Buffer Debug Data Register
 461 #define         TRXPKTBUF_DBG_CTRL      0x0348  // TRX Packet Buffer Debug Control Reg
 462 #define         DPLL                            0x034A  // DPLL Monitor Register [15:0]
 463 #define         CBUS_ERR_ADDR           0x0350  // CPU Bus Error Address Register
 464 #define         CBUS_ERR_CMD            0x0354  // CPU Bus Error Command Register
 465 #define         CBUS_ERR_DATA_L         0x0358  // CPU Bus Error Data Low DW Register
 466 #define         CBUS_ERR_DATA_H         0x035C  //
 467 #define         USB_SIE_INTF_ADDR       0x0360  // USB SIE Access Interface Address Reg
 468 #define         USB_SIE_INTF_WD         0x0361  // USB SIE Access Interface WData Reg
 469 #define         USB_SIE_INTF_RD         0x0362  // USB SIE Access Interface RData Reg
 470 #define         USB_SIE_INTF_CTRL       0x0363  // USB SIE Access Interface Control Reg
 471
 472 // Boundary is 0x37F
 473
 474 //
 475 // 14. PCIE config register     (Offset 0x500-)
 476 //
 477 #define         TPPoll                          0x0500  // Transmit Polling
 478 #define         PM_CTRL                         0x0502  // PCIE power management control Register
 479 #define         PCIF                            0x0503  // PCI Function Register 0x0009h~0x000bh
 480
 481 #define         THPDA                           0x0514  // Transmit High Priority Desc Addr
 482 #define         TMDA                            0x0518  // Transmit Management Desc Addr
 483 #define         TCDA                            0x051C  // Transmit Command Desc Addr
 484 #define         HDA                             0x0520  // HCCA Desc Addr
 485 #define         TVODA                           0x0524  // Transmit VO Desc Addr
 486 #define         TVIDA                           0x0528  // Transmit VI Desc Addr
 487 #define         TBEDA                           0x052C  // Transmit BE Desc Addr
 488 #define         TBKDA                           0x0530  // Transmit BK Desc Addr
 489 #define         TBDA                            0x0534  // Transmit Beacon Desc Addr
 490 #define         RCDA                            0x0538  // Receive Command Desc Addr
 491 #define         RDSA                            0x053C  // Receive Desc Starting Addr
 492 #define         DBI_WDATA                       0x0540  // DBI write data Register
 493 #define         DBI_RDATA                       0x0544  // DBI read data Register
 494 #define         DBI_CTRL                        0x0548  // PCIE DBI control Register
 495 #define         MDIO_DATA                       0x0550  // PCIE MDIO data Register
 496 #define         MDIO_CTRL                       0x0554  // PCIE MDIO control Register
 497 #define         PCI_RPWM                        0x0561  // PCIE RPWM register
 498 #define         PCI_CPWM                                0x0563  // Current Power Mode.
 499
 500 //
 501 // Config register   (Offset 0x800-)
 502 //
 503 #define         PHY_CCA                         0x803   // CCA related register
 504
 505 //============================================================================
 506 //       8192S USB specific Regsiter Offset and Content definition,
 507 //       2008.08.28, added by Roger.
 508 //============================================================================
 509 // Rx Aggregation time-out reg.
 510 #define USB_RX_AGG_TIMEOUT      0xFE5B
 511
 512 // Firware reserved Tx page control.
 513 #define FW_OFFLOAD_EN           BIT7
 514
 515 // Min Spacing related settings.
 516 #define MAX_MSS_DENSITY                         0x13
 517 #define MAX_MSS_DENSITY_2T              0x13
 518 #define MAX_MSS_DENSITY_1T              0x0A
 519
 520 // Rx DMA Control related settings
 521 #define RXDMA_AGG_EN            BIT7
 522
 523 // USB Rx Aggregation TimeOut settings
 524 #define RXDMA_AGG_TIMEOUT_DISABLE               0x00
 525 #define RXDMA_AGG_TIMEOUT_17MS                          0x01
 526 #define RXDMA_AGG_TIMEOUT_17_2_MS               0x02
 527 #define RXDMA_AGG_TIMEOUT_17_4_MS               0x04
 528 #define RXDMA_AGG_TIMEOUT_17_10_MS              0x0A
 529 // USB RPWM register
 530 #define USB_RPWM                        0xFE58
 531
 532 //FIXLZM SVN_BRACH NOT MOD HERE, IF MOD RX IS LITTLE LOW
 533 //#if ((HAL_CODE_BASE == RTL8192_S) &&  (DEV_BUS_TYPE==PCI_INTERFACE))
 534 //#define       RPWM            PCI_RPWM
 535 //#elif ((HAL_CODE_BASE == RTL8192_S) &&  (DEV_BUS_TYPE==USB_INTERFACE))
 536 //#define       RPWM            USB_RPWM
 537 //#endif
 538
 539
 540 //============================================================================
 541 //       8190 Regsiter offset definition
 542 //============================================================================
 543 #if 1   // Delete the register later
 544 #define         AFR                                     0x010   // AutoLoad Function Register
 545 #define         BCN_TCFG                        0x062   // Beacon Time Configuration
 546 #define         RATR0                           0x320   // Rate Adaptive Table register1
 547 #endif
 548 // TODO: Remove unused register, We must declare backward compatiable
 549 //Undefined register set in 8192S. 0x320/350 DW is useless
 550 #define         UnusedRegister          0x0320
 551 #define         PSR                                     UnusedRegister  // Page Select Register
 552 //Security Related
 553 #define         DCAM                            UnusedRegister  // Debug CAM Interface
 554 //PHY Configuration related
 555 #define         BBAddr                          UnusedRegister  // Phy register address register
 556 #define         PhyDataR                        UnusedRegister  // Phy register data read
 557 #define         UFWP                            UnusedRegister
 558
 559
 560 //============================================================================
 561 //       8192S Regsiter Bit and Content definition
 562 //============================================================================
 563
 564 //
 565 // 1. System Configuration Registers     (Offset: 0x0000 - 0x003F)
 566 //
 567 //----------------------------------------------------------------------------
 568 //       8192S SYS_ISO_CTRL bits                                        (Offset 0x0, 16bit)
 569 //----------------------------------------------------------------------------
 570 #define         ISO_MD2PP                       BIT0    // MACTOP/BB/PCIe Digital to Power On.
 571 #define         ISO_PA2PCIE                     BIT3    // PCIe Analog 1.2V to PCIe 3.3V
 572 #define         ISO_PLL2MD                      BIT4    // AFE PLL to MACTOP/BB/PCIe Digital.
 573 #define         ISO_PWC_DV2RP           BIT11   // Digital Vdd to Retention Path
 574 #define         ISO_PWC_RV2RP           BIT12   // LPLDOR12 to Retenrion Path, 1: isolation, 0: attach.
 575
 576 //----------------------------------------------------------------------------
 577 //       8192S SYS_FUNC_EN bits                                 (Offset 0x2, 16bit)
 578 //----------------------------------------------------------------------------
 579 #define         FEN_MREGEN                      BIT15   // MAC I/O Registers Enable.
 580 #define         FEN_DCORE                       BIT11   // Enable Core Digital.
 581 #define         FEN_CPUEN                       BIT10   // Enable CPU Core Digital.
 582 //       8192S PMC_FSM bits                                     (Offset 0x4, 32bit)
 583 //----------------------------------------------------------------------------
 584 #define         PAD_HWPD_IDN            BIT22   // HWPDN PAD status Indicator
 585
 586 //----------------------------------------------------------------------------
 587
 588 //----------------------------------------------------------------------------
 589 //       8192S SYS_CLKR bits                                    (Offset 0x8, 16bit)
 590 //----------------------------------------------------------------------------
 591 #define         SYS_CLKSEL_80M          BIT0    // System Clock 80MHz
 592 #define         SYS_PS_CLKSEL           BIT1     //System power save clock select.
 593 #define         SYS_CPU_CLKSEL          BIT2    // System Clock select, 1: AFE source, 0: System clock(L-Bus)
 594 #define         SYS_MAC_CLK_EN          BIT11   // MAC Clock Enable.
 595 #define         SYS_SWHW_SEL            BIT14   // Load done, control path seitch.
 596 #define         SYS_FWHW_SEL            BIT15   // Sleep exit, control path swith.
 597
 598
 599 //----------------------------------------------------------------------------
 600 //       8192S Cmd9346CR bits                                   (Offset 0xA, 16bit)
 601 //----------------------------------------------------------------------------
 602 #define         CmdEEPROM_En                                            BIT5     // EEPROM enable when set 1
 603 #define         CmdEERPOMSEL                                            BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346
 604 #define         Cmd9346CR_9356SEL                                       BIT4
 605 #define         AutoLoadEEPROM                                          (CmdEEPROM_En|CmdEERPOMSEL)
 606 #define         AutoLoadEFUSE                                           CmdEEPROM_En
 607
 608
 609 //----------------------------------------------------------------------------
 610 //       8192S AFE_MISC bits            AFE Misc                        (Offset 0x10, 8bits)
 611 //----------------------------------------------------------------------------
 612 #define         AFE_MBEN                        BIT1    // Enable AFE Macro Block's Mbias.
 613 #define         AFE_BGEN                        BIT0    // Enable AFE Macro Block's Bandgap.
 614
 615 //----------------------------------------------------------------------------
 616 //       8192S SPS1_CTRL bits                                   (Offset 0x18-1E, 56bits)
 617 //----------------------------------------------------------------------------
 618 #define         SPS1_SWEN                       BIT1    // Enable vsps18 SW Macro Block.
 619 #define         SPS1_LDEN                       BIT0    // Enable VSPS12 LDO Macro block.
 620
 621 //----------------------------------------------------------------------------
 622 //       8192S RF_CTRL bits                                     (Offset 0x1F, 8bits)
 623 //----------------------------------------------------------------------------
 624 #define         RF_EN                           BIT0 // Enable RF module.
 625 #define         RF_RSTB                 BIT1 // Reset RF module.
 626 #define         RF_SDMRSTB                      BIT2 // Reset RF SDM module.
 627
 628 //----------------------------------------------------------------------------
 629 //       8192S LDOA15_CTRL bits                                 (Offset 0x20, 8bits)
 630 //----------------------------------------------------------------------------
 631 #define         LDA15_EN                        BIT0    // Enable LDOA15 Macro Block
 632
 633 //----------------------------------------------------------------------------
 634 //       8192S LDOV12D_CTRL bits                                        (Offset 0x21, 8bits)
 635 //----------------------------------------------------------------------------
 636 #define         LDV12_EN                        BIT0    // Enable LDOVD12 Macro Block
 637 #define         LDV12_SDBY                      BIT1    // LDOVD12 standby mode
 638
 639 //----------------------------------------------------------------------------
 640 //       8192S AFE_XTAL_CTRL bits       AFE Crystal Control.    (Offset 0x26,16bits)
 641 //----------------------------------------------------------------------------
 642 #define         XTAL_GATE_AFE           BIT10
 643 // Gated Control. 1: AFE Clock source gated, 0: Clock enable.
 644
 645 //----------------------------------------------------------------------------
 646 //       8192S AFE_PLL_CTRL bits        System Function Enable  (Offset 0x28,64bits)
 647 //----------------------------------------------------------------------------
 648 #define         APLL_EN                         BIT0    // Enable AFE PLL Macro Block.
 649
 650 // Find which card bus type
 651 #define         AFR_CardBEn                     BIT0
 652 #define         AFR_CLKRUN_SEL          BIT1
 653 #define         AFR_FuncRegEn           BIT2
 654
 655 //
 656 // 2. Command Control Registers  (Offset: 0x0040 - 0x004F)
 657 //
 658 //----------------------------------------------------------------------------
 659 //       8192S (CMD) command register bits              (Offset 0x40, 16 bits)
 660 //----------------------------------------------------------------------------
 661 #define         APSDOFF_STATUS          BIT15   //
 662 #define         APSDOFF                         BIT14   //
 663 #define         BBRSTn                          BIT13   //Enable OFDM/CCK
 664 #define         BB_GLB_RSTn                     BIT12   //Enable BB
 665 #define         SCHEDULE_EN                     BIT10   //Enable MAC scheduler
 666 #define         MACRXEN                         BIT9    //
 667 #define         MACTXEN                         BIT8    //
 668 #define         DDMA_EN                         BIT7    //FW off load function enable
 669 #define         FW2HW_EN                        BIT6    //MAC every module reset as below
 670 #define         RXDMA_EN                        BIT5    //
 671 #define         TXDMA_EN                        BIT4    //
 672 #define         HCI_RXDMA_EN            BIT3    //
 673 #define         HCI_TXDMA_EN            BIT2    //
 674
 675 //----------------------------------------------------------------------------
 676 //       8192S (TXPAUSE) transmission pause             (Offset 0x42, 8 bits)
 677 //----------------------------------------------------------------------------
 678 #define         StopHCCA                        BIT6
 679 #define         StopHigh                        BIT5
 680 #define         StopMgt                         BIT4
 681 #define         StopVO                          BIT3
 682 #define         StopVI                          BIT2
 683 #define         StopBE                          BIT1
 684 #define         StopBK                          BIT0
 685
 686 //----------------------------------------------------------------------------
 687 //       8192S (LBKMD) LoopBack Mode Select             (Offset 0x43, 8 bits)
 688 //----------------------------------------------------------------------------
 689 //
 690 //      [3] no buffer, 1: no delay, 0: delay; [2] dmalbk, [1] no_txphy, [0] diglbk.
 691 //      0000: Normal
 692 //      1011: MAC loopback (involving CPU)
 693 //      0011: MAC Delay Loopback
 694 //      0001: PHY loopback (not yet implemented)
 695 //      0111: DMA loopback (only uses TxPktBuffer and DMA engine)
 696 //      All other combinations are reserved.
 697 //      Default: 0000b.
 698 //
 699 #define         LBK_NORMAL              0x00
 700 #define         LBK_MAC_LB              (BIT0|BIT1|BIT3)
 701 #define         LBK_MAC_DLB             (BIT0|BIT1)
 702 #define         LBK_DMA_LB              (BIT0|BIT1|BIT2)
 703
 704 //----------------------------------------------------------------------------
 705 //       8192S (TCR) transmission Configuration Register (Offset 0x44, 32 bits)
 706 //----------------------------------------------------------------------------
 707 #define         TCP_OFDL_EN                             BIT25   //For CE packet conversion
 708 #define         HWPC_TX_EN                              BIT24   //""
 709 #define         TXDMAPRE2FULL                   BIT23   //TXDMA enable pre2full sync
 710 #define         DISCW                                   BIT20   //CW disable
 711 #define         TCRICV                                  BIT19   //Append ICV or not
 712 #define         CfendForm                               BIT17   //AP mode
 713 #define         TCRCRC                                  BIT16   //Append CRC32
 714 #define         FAKE_IMEM_EN                    BIT15   //
 715 #define         TSFRST                                  BIT9    //
 716 #define         TSFEN                                   BIT8    //
 717 // For TCR FW download ready --> write by FW  Bit0-7 must all one
 718 #define         FWALLRDY                                (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7)
 719 #define         FWRDY                                   BIT7
 720 #define         BASECHG                                 BIT6
 721 #define         IMEM                                    BIT5
 722 #define         DMEM_CODE_DONE                  BIT4
 723 #define         EXT_IMEM_CHK_RPT                BIT3
 724 #define         EXT_IMEM_CODE_DONE              BIT2
 725 #define         IMEM_CHK_RPT                    BIT1
 726 #define         IMEM_CODE_DONE                  BIT0
 727 // Copy fomr 92SU definition
 728 #define         IMEM_CODE_DONE          BIT0
 729 #define         IMEM_CHK_RPT            BIT1
 730 #define         EMEM_CODE_DONE          BIT2
 731 #define         EMEM_CHK_RPT            BIT3
 732 #define         DMEM_CODE_DONE          BIT4
 733 #define         IMEM_RDY                        BIT5
 734 #define         BASECHG                 BIT6
 735 #define         FWRDY                           BIT7
 736 #define         LOAD_FW_READY           (IMEM_CODE_DONE|IMEM_CHK_RPT|EMEM_CODE_DONE|\
 737                                         EMEM_CHK_RPT|DMEM_CODE_DONE|IMEM_RDY|BASECHG|\
 738                                         FWRDY)
 739 #define         TCR_TSFEN                       BIT8            // TSF function on or off.
 740 #define         TCR_TSFRST                      BIT9            // Reset TSF function to zero.
 741 #define         TCR_FAKE_IMEM_EN        BIT15
 742 #define         TCR_CRC                         BIT16
 743 #define         TCR_ICV                         BIT19   // Integrity Check Value.
 744 #define         TCR_DISCW                       BIT20   // Disable Contention Windows Backoff.
 745 #define         TCR_HWPC_TX_EN  BIT24
 746 #define         TCR_TCP_OFDL_EN BIT25
 747 #define         TXDMA_INIT_VALUE        (IMEM_CHK_RPT|EXT_IMEM_CHK_RPT)
 748 //----------------------------------------------------------------------------
 749 //       8192S (RCR) Receive Configuration Register     (Offset 0x48, 32 bits)
 750 //----------------------------------------------------------------------------
 751 #define         RCR_APPFCS                              BIT31           //WMAC append FCS after pauload
 752 #define         RCR_DIS_ENC_2BYTE               BIT30       //HW encrypt 2 or 1 byte mode
 753 #define         RCR_DIS_AES_2BYTE               BIT29       //
 754 #define         RCR_HTC_LOC_CTRL                BIT28       //MFC<--HTC=1 MFC-->HTC=0
 755 #define         RCR_ENMBID                              BIT27           //Enable Multiple BssId.
 756 #define         RCR_RX_TCPOFDL_EN               BIT26           //
 757 #define         RCR_APP_PHYST_RXFF      BIT25       //
 758 #define         RCR_APP_PHYST_STAFF     BIT24       //
 759 #define         RCR_CBSSID                              BIT23           //Accept BSSID match packet
 760 #define         RCR_APWRMGT                     BIT22           //Accept power management packet
 761 #define         RCR_ADD3                                BIT21           //Accept address 3 match packet
 762 #define         RCR_AMF                         BIT20           //Accept management type frame
 763 #define         RCR_ACF                                 BIT19           //Accept control type frame
 764 #define         RCR_ADF                                 BIT18           //Accept data type frame
 765 #define         RCR_APP_MIC                     BIT17           //
 766 #define         RCR_APP_ICV                     BIT16       //
 767 #define         RCR_RXFTH                               BIT13           //Rx FIFO Threshold Bot 13 - 15
 768 #define         RCR_AICV                                BIT12           //Accept ICV error packet
 769 #define         RCR_RXDESC_LK_EN                BIT11           //Accept to update rx desc length
 770 #define         RCR_APP_BA_SSN                  BIT6            //Accept BA SSN
 771 #define         RCR_ACRC32                              BIT5            //Accept CRC32 error packet
 772 #define         RCR_RXSHFT_EN                   BIT4            //Accept broadcast packet
 773 #define         RCR_AB                                  BIT3            //Accept broadcast packet
 774 #define         RCR_AM                                  BIT2            //Accept multicast packet
 775 #define         RCR_APM                         BIT1            //Accept physical match packet
 776 #define         RCR_AAP                                 BIT0            //Accept all unicast packet
 777 #define         RCR_MXDMA_OFFSET                8
 778 #define         RCR_FIFO_OFFSET         13
 779
 780 //in 92U FIXLZM
 781 //#ifdef RTL8192U
 782 #define RCR_ONLYERLPKT          BIT31                   // Early Receiving based on Packet Size.
 783 #define RCR_ENCS2                       BIT30                   // Enable Carrier Sense Detection Method 2
 784 #define RCR_ENCS1                       BIT29                   // Enable Carrier Sense Detection Method 1
 785 #define RCR_ACKTXBW                     (BIT24|BIT25)           // TXBW Setting of ACK frames
 786 //#endif
 787 //----------------------------------------------------------------------------
 788 //       8192S (MSR) Media Status Register      (Offset 0x4C, 8 bits)
 789 //----------------------------------------------------------------------------
 790 /*
 791 Network Type
 792 00: No link
 793 01: Link in ad hoc network
 794 10: Link in infrastructure network
 795 11: AP mode
 796 Default: 00b.
 797 */
 798 #define         MSR_NOLINK                              0x00
 799 #define         MSR_ADHOC                               0x01
 800 #define         MSR_INFRA                               0x02
 801 #define         MSR_AP                                  0x03
 802
 803 //----------------------------------------------------------------------------
 804 //       8192S (SYSF_CFG) system Fucntion Config Reg    (Offset 0x4D, 8 bits)
 805 //----------------------------------------------------------------------------
 806 #define         ENUART                                  BIT7
 807 #define         ENJTAG                                  BIT3
 808 #define         BTMODE                                  (BIT2|BIT1)
 809 #define         ENBT                                    BIT0
 810
 811 //----------------------------------------------------------------------------
 812 //       8192S (MBIDCTRL) MBSSID Control Register       (Offset 0x4F, 8 bits)
 813 //----------------------------------------------------------------------------
 814 #define         ENMBID                                  BIT7
 815 #define         BCNUM                                   (BIT6|BIT5|BIT4)
 816
 817 //
 818 // 3. MACID Setting Registers   (Offset: 0x0050 - 0x007F)
 819 //
 820
 821 //
 822 // 4. Timing Control Registers  (Offset: 0x0080 - 0x009F)
 823 //
 824 //----------------------------------------------------------------------------
 825 //       8192S (USTIME) US Time Tunning Register        (Offset 0x8A, 16 bits)
 826 //----------------------------------------------------------------------------
 827 #define         USTIME_EDCA                             0xFF00
 828 #define         USTIME_TSF                              0x00FF
 829
 830 //----------------------------------------------------------------------------
 831 //       8192S (SIFS_CCK/OFDM) US Time Tunning Register (Offset 0x8C/8E,16 bits)
 832 //----------------------------------------------------------------------------
 833 #define         SIFS_TRX                                0xFF00
 834 #define         SIFS_CTX                                0x00FF
 835
 836 //----------------------------------------------------------------------------
 837 //       8192S (DRVERLYINT)     Driver Early Interrupt Reg              (Offset 0x98, 16bit)
 838 //----------------------------------------------------------------------------
 839 #define         ENSWBCN                                 BIT15
 840 #define         DRVERLY_TU                              0x0FF0
 841 #define         DRVERLY_US                              0x000F
 842 #define         BCN_TCFG_CW_SHIFT               8
 843 #define         BCN_TCFG_IFS                    0
 844
 845 //
 846 // 5. FIFO Control Registers     (Offset: 0x00A0 - 0x015F)
 847 //
 848
 849 //
 850 // 6. Adaptive Control Registers  (Offset: 0x0160 - 0x01CF)
 851 //
 852 //----------------------------------------------------------------------------
 853 //       8192S Response Rate Set Register       (offset 0x181, 24bits)
 854 //----------------------------------------------------------------------------
 855 #define         RRSR_RSC_OFFSET                 21
 856 #define         RRSR_SHORT_OFFSET               23
 857 #define         RRSR_RSC_BW_40M         0x600000
 858 #define         RRSR_RSC_UPSUBCHNL              0x400000
 859 #define         RRSR_RSC_LOWSUBCHNL             0x200000
 860 #define         RRSR_SHORT                              0x800000
 861 #define         RRSR_1M                                 BIT0
 862 #define         RRSR_2M                                 BIT1
 863 #define         RRSR_5_5M                               BIT2
 864 #define         RRSR_11M                                BIT3
 865 #define         RRSR_6M                                 BIT4
 866 #define         RRSR_9M                                 BIT5
 867 #define         RRSR_12M                                BIT6
 868 #define         RRSR_18M                                BIT7
 869 #define         RRSR_24M                                BIT8
 870 #define         RRSR_36M                                BIT9
 871 #define         RRSR_48M                                BIT10
 872 #define         RRSR_54M                                BIT11
 873 #define         RRSR_MCS0                               BIT12
 874 #define         RRSR_MCS1                               BIT13
 875 #define         RRSR_MCS2                               BIT14
 876 #define         RRSR_MCS3                               BIT15
 877 #define         RRSR_MCS4                               BIT16
 878 #define         RRSR_MCS5                               BIT17
 879 #define         RRSR_MCS6                               BIT18
 880 #define         RRSR_MCS7                               BIT19
 881 #define         BRSR_AckShortPmb                BIT23
 882
 883 #define                 RRSR_RSC_UPSUBCHANL     0x200000
 884 // CCK ACK: use Short Preamble or not
 885
 886 //----------------------------------------------------------------------------
 887 //       8192S Rate Definition
 888 //----------------------------------------------------------------------------
 889 //CCK
 890 #define         RATR_1M                                 0x00000001
 891 #define         RATR_2M                                 0x00000002
 892 #define         RATR_55M                                0x00000004
 893 #define         RATR_11M                                0x00000008
 894 //OFDM
 895 #define         RATR_6M                                 0x00000010
 896 #define         RATR_9M                                 0x00000020
 897 #define         RATR_12M                                0x00000040
 898 #define         RATR_18M                                0x00000080
 899 #define         RATR_24M                                0x00000100
 900 #define         RATR_36M                                0x00000200
 901 #define         RATR_48M                                0x00000400
 902 #define         RATR_54M                                0x00000800
 903 //MCS 1 Spatial Stream
 904 #define         RATR_MCS0                               0x00001000
 905 #define         RATR_MCS1                               0x00002000
 906 #define         RATR_MCS2                               0x00004000
 907 #define         RATR_MCS3                               0x00008000
 908 #define         RATR_MCS4                               0x00010000
 909 #define         RATR_MCS5                               0x00020000
 910 #define         RATR_MCS6                               0x00040000
 911 #define         RATR_MCS7                               0x00080000
 912 //MCS 2 Spatial Stream
 913 #define         RATR_MCS8                               0x00100000
 914 #define         RATR_MCS9                               0x00200000
 915 #define         RATR_MCS10                              0x00400000
 916 #define         RATR_MCS11                              0x00800000
 917 #define         RATR_MCS12                              0x01000000
 918 #define         RATR_MCS13                              0x02000000
 919 #define         RATR_MCS14                              0x04000000
 920 #define         RATR_MCS15                              0x08000000
 921 // ALL CCK Rate
 922 #define RATE_ALL_CCK                            RATR_1M|RATR_2M|RATR_55M|RATR_11M
 923 #define RATE_ALL_OFDM_AG                        RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\
 924                                                                         RATR_36M|RATR_48M|RATR_54M
 925 #define RATE_ALL_OFDM_1SS                       RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\
 926                                                                         RATR_MCS4|RATR_MCS5|RATR_MCS6   |RATR_MCS7
 927 #define RATE_ALL_OFDM_2SS                       RATR_MCS8|RATR_MCS9     |RATR_MCS10|RATR_MCS11|\
 928                                                                         RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
 929
 930 //
 931 // 7. EDCA Setting Registers     (Offset: 0x01D0 - 0x01FF)
 932 //
 933 //----------------------------------------------------------------------------
 934 //       8192S EDCA Setting     (offset 0x1D0-1DF, 4DW VO/VI/BE/BK)
 935 //----------------------------------------------------------------------------
 936 #define         AC_PARAM_TXOP_LIMIT_OFFSET              16
 937 #define         AC_PARAM_ECW_MAX_OFFSET                 12
 938 #define         AC_PARAM_ECW_MIN_OFFSET                 8
 939 #define         AC_PARAM_AIFS_OFFSET                    0
 940
 941 //----------------------------------------------------------------------------
 942 //       8192S AcmHwCtrl bits                                   (offset 0x1E7, 1 byte)
 943 //----------------------------------------------------------------------------
 944 #define         AcmHw_HwEn                              BIT0
 945 #define         AcmHw_BeqEn                             BIT1
 946 #define         AcmHw_ViqEn                             BIT2
 947 #define         AcmHw_VoqEn                             BIT3
 948 #define         AcmHw_BeqStatus                 BIT4
 949 #define         AcmHw_ViqStatus                 BIT5
 950 #define         AcmHw_VoqStatus                 BIT6
 951
 952 //----------------------------------------------------------------------------
 953 //       8192S Retry Limit                                      (Offset 0x1F4, 16bit)
 954 //----------------------------------------------------------------------------
 955 #define         RETRY_LIMIT_SHORT_SHIFT 8
 956 #define         RETRY_LIMIT_LONG_SHIFT  0
 957
 958 //
 959 // 8. WMAC, BA and CCX related Register.         (Offset: 0x0200 - 0x023F)
 960 //
 961 //----------------------------------------------------------------------------
 962 //       8192S NAV_CTRL bits                                    (Offset 0x200, 24bit)
 963 //----------------------------------------------------------------------------
 964 #define         NAV_UPPER_EN                    BIT16
 965 #define         NAV_UPPER                               0xFF00
 966 #define         NAV_RTSRST                              0xFF
 967 //----------------------------------------------------------------------------
 968 //       8192S BW_OPMODE bits                                   (Offset 0x203, 8bit)
 969 //----------------------------------------------------------------------------
 970 #define         BW_OPMODE_20MHZ                 BIT2
 971 #define         BW_OPMODE_5G                    BIT1
 972 #define         BW_OPMODE_11J                   BIT0
 973 //----------------------------------------------------------------------------
 974 //       8192S BW_OPMODE bits                                   (Offset 0x230, 4 Byte)
 975 //----------------------------------------------------------------------------
 976 #define         RXERR_RPT_RST                   BIT27 // Write "one" to set the counter to zero.
 977 // RXERR_RPT_SEL
 978 #define         RXERR_OFDM_PPDU                 0
 979 #define         RXERR_OFDM_FALSE_ALARM  1
 980 #define         RXERR_OFDM_MPDU_OK              2
 981 #define         RXERR_OFDM_MPDU_FAIL    3
 982 #define         RXERR_CCK_PPDU                  4
 983 #define         RXERR_CCK_FALSE_ALARM   5
 984 #define         RXERR_CCK_MPDU_OK               6
 985 #define         RXERR_CCK_MPDU_FAIL             7
 986 #define         RXERR_HT_PPDU                   8
 987 #define         RXERR_HT_FALSE_ALARM    9
 988 #define         RXERR_HT_MPDU_TOTAL             10
 989 #define         RXERR_HT_MPDU_OK                11
 990 #define         RXERR_HT_MPDU_FAIL              12
 991 #define         RXERR_RX_FULL_DROP              15
 992
 993 //
 994 // 9. Security Control Registers        (Offset: 0x0240 - 0x025F)
 995 //
 996 //----------------------------------------------------------------------------
 997 //       8192S RWCAM CAM Command Register               (offset 0x240, 4 byte)
 998 //----------------------------------------------------------------------------
 999 #define         CAM_CM_SecCAMPolling    BIT31           //Security CAM Polling
1000 #define         CAM_CM_SecCAMClr                BIT30           //Clear all bits in CAM
1001 #define         CAM_CM_SecCAMWE                 BIT16           //Security CAM enable
1002 #define         CAM_ADDR                                0xFF            //CAM Address Offset
1003
1004 //----------------------------------------------------------------------------
1005 //       8192S CAMDBG Debug CAM Register                                (offset 0x24C, 4 byte)
1006 //----------------------------------------------------------------------------
1007 #define         Dbg_CAM_TXSecCAMInfo    BIT31           //Retrieve lastest Tx Info
1008 #define         Dbg_CAM_SecKeyFound             BIT30           //Security KEY Found
1009
1010
1011 //----------------------------------------------------------------------------
1012 //       8192S SECR Security Configuration Register     (offset 0x250, 1 byte)
1013 //----------------------------------------------------------------------------
1014 #define         SCR_TxUseDK                             BIT0                    //Force Tx Use Default Key
1015 #define         SCR_RxUseDK                             BIT1                    //Force Rx Use Default Key
1016 #define         SCR_TxEncEnable                 BIT2                    //Enable Tx Encryption
1017 #define         SCR_RxDecEnable                 BIT3                    //Enable Rx Decryption
1018 #define         SCR_SKByA2                              BIT4                    //Search kEY BY A2
1019 #define         SCR_NoSKMC                              BIT5                    //No Key Search Multicast
1020 //----------------------------------------------------------------------------
1021 //       8192S CAM Config Setting (offset 0x250, 1 byte)
1022 //----------------------------------------------------------------------------
1023 #define         CAM_VALID                               BIT15
1024 #define         CAM_NOTVALID                    0x0000
1025 #define         CAM_USEDK                               BIT5
1026
1027 #define         CAM_NONE                                0x0
1028 #define         CAM_WEP40                               0x01
1029 #define         CAM_TKIP                                0x02
1030 #define         CAM_AES                                 0x04
1031 #define         CAM_WEP104                              0x05
1032
1033 #define         TOTAL_CAM_ENTRY                 32
1034
1035 #define         CAM_CONFIG_USEDK                TRUE
1036 #define         CAM_CONFIG_NO_USEDK             FALSE
1037
1038 #define         CAM_WRITE                               BIT16
1039 #define         CAM_READ                                0x00000000
1040 #define         CAM_POLLINIG                    BIT31
1041
1042 #define         SCR_UseDK                               0x01
1043 #define         SCR_TxSecEnable         0x02
1044 #define         SCR_RxSecEnable         0x04
1045
1046 //
1047 // 10. Power Save Control Registers      (Offset: 0x0260 - 0x02DF)
1048 //
1049 #define         WOW_PMEN                                BIT0 // Power management Enable.
1050 #define         WOW_WOMEN                       BIT1 // WoW function on or off.
1051 #define         WOW_MAGIC                               BIT2 // Magic packet
1052 #define         WOW_UWF                         BIT3 // Unicast Wakeup frame.
1053
1054 //
1055 // 11. General Purpose Registers        (Offset: 0x02E0 - 0x02FF)
1056 //       8192S GPIO Config Setting (offset 0x2F1, 1 byte)
1057 //----------------------------------------------------------------------------
1058 #define         GPIOMUX_EN                      BIT3 // When this bit is set to "1", GPIO PINs will switch to MAC GPIO Function
1059 #define         GPIOSEL_GPIO            0       // UART or JTAG or pure GPIO
1060 #define         GPIOSEL_PHYDBG          1       // PHYDBG
1061 #define         GPIOSEL_BT                      2       // BT_coex
1062 #define         GPIOSEL_WLANDBG         3       // WLANDBG
1063 #define         GPIOSEL_GPIO_MASK       ~(BIT0|BIT1)
1064
1065 //----------------------------------------------------------------------------
1066
1067 //----------------------------------------------------------------------------
1068 // PHY REG Access Report Register definition
1069 //----------------------------------------------------------------------------
1070 #define         HST_RDBUSY                              BIT0
1071 #define         CPU_WTBUSY                      BIT1
1072
1073 //
1074 // 12. Host Interrupt Status Registers   (Offset: 0x0300 - 0x030F)
1075 //
1076 //----------------------------------------------------------------------------
1077 //       8190 IMR/ISR bits                                              (offset 0xfd,  8bits)
1078 //----------------------------------------------------------------------------
1079 #define         IMR8190_DISABLED        0x0
1080
1081 // IMR DW1 Bit 0-31
1082 #define         IMR_CPUERR                      BIT5            // CPU error interrupt
1083 #define         IMR_ATIMEND                     BIT4            // ATIM Window End Interrupt
1084 #define         IMR_TBDOK                       BIT3            // Transmit Beacon OK Interrupt
1085 #define         IMR_TBDER                       BIT2            // Transmit Beacon Error Interrupt
1086 #define         IMR_BCNDMAINT8          BIT1            // Beacon DMA Interrupt 8
1087 #define         IMR_BCNDMAINT7          BIT0            // Beacon DMA Interrupt 7
1088 // IMR DW0 Bit 0-31
1089
1090 #define         IMR_BCNDMAINT6          BIT31           // Beacon DMA Interrupt 6
1091 #define         IMR_BCNDMAINT5          BIT30           // Beacon DMA Interrupt 5
1092 #define         IMR_BCNDMAINT4          BIT29           // Beacon DMA Interrupt 4
1093 #define         IMR_BCNDMAINT3          BIT28           // Beacon DMA Interrupt 3
1094 #define         IMR_BCNDMAINT2          BIT27           // Beacon DMA Interrupt 2
1095 #define         IMR_BCNDMAINT1          BIT26           // Beacon DMA Interrupt 1
1096 #define         IMR_BCNDOK8                     BIT25           // Beacon Queue DMA OK Interrup 8
1097 #define         IMR_BCNDOK7                     BIT24           // Beacon Queue DMA OK Interrup 7
1098 #define         IMR_BCNDOK6                     BIT23           // Beacon Queue DMA OK Interrup 6
1099 #define         IMR_BCNDOK5                     BIT22           // Beacon Queue DMA OK Interrup 5
1100 #define         IMR_BCNDOK4                     BIT21           // Beacon Queue DMA OK Interrup 4
1101 #define         IMR_BCNDOK3                     BIT20           // Beacon Queue DMA OK Interrup 3
1102 #define         IMR_BCNDOK2                     BIT19           // Beacon Queue DMA OK Interrup 2
1103 #define         IMR_BCNDOK1                     BIT18           // Beacon Queue DMA OK Interrup 1
1104 #define         IMR_TIMEOUT2            BIT17           // Timeout interrupt 2
1105 #define         IMR_TIMEOUT1            BIT16           // Timeout interrupt 1
1106 #define         IMR_TXFOVW                      BIT15           // Transmit FIFO Overflow
1107 #define         IMR_PSTIMEOUT           BIT14           // Power save time out interrupt
1108 #define         IMR_BcnInt                      BIT13           // Beacon DMA Interrupt 0
1109 #define         IMR_RXFOVW                      BIT12           // Receive FIFO Overflow
1110 #define         IMR_RDU                         BIT11           // Receive Descriptor Unavailable
1111 #define         IMR_RXCMDOK                     BIT10           // Receive Command Packet OK
1112 #define         IMR_BDOK                        BIT9            // Beacon Queue DMA OK Interrup
1113 #define         IMR_HIGHDOK                     BIT8            // High Queue DMA OK Interrupt
1114 #define         IMR_COMDOK                      BIT7            // Command Queue DMA OK Interrupt
1115 #define         IMR_MGNTDOK                     BIT6            // Management Queue DMA OK Interrupt
1116 #define         IMR_HCCADOK                     BIT5            // HCCA Queue DMA OK Interrupt
1117 #define         IMR_BKDOK                       BIT4            // AC_BK DMA OK Interrupt
1118 #define         IMR_BEDOK                       BIT3            // AC_BE DMA OK Interrupt
1119 #define         IMR_VIDOK                       BIT2            // AC_VI DMA OK Interrupt
1120 #define         IMR_VODOK                       BIT1            // AC_VO DMA Interrupt
1121 #define         IMR_ROK                         BIT0            // Receive DMA OK Interrupt
1122
1123 //
1124 // 13. Test Mode and Debug Control Registers    (Offset: 0x0310 - 0x034F)
1125 //
1126
1127 //
1128 // 14. PCIE config register     (Offset 0x500-)
1129 //
1130 //----------------------------------------------------------------------------
1131 //       8190 TPPool bits                                       (offset 0xd9, 2 byte)
1132 //----------------------------------------------------------------------------
1133 #define         TPPoll_BKQ                      BIT0                    // BK queue polling
1134 #define         TPPoll_BEQ                      BIT1                    // BE queue polling
1135 #define         TPPoll_VIQ                      BIT2                    // VI queue polling
1136 #define         TPPoll_VOQ                      BIT3                    // VO queue polling
1137 #define         TPPoll_BQ                       BIT4                    // Beacon queue polling
1138 #define         TPPoll_CQ                       BIT5                    // Command queue polling
1139 #define         TPPoll_MQ                       BIT6                    // Management queue polling
1140 #define         TPPoll_HQ                       BIT7                    // High queue polling
1141 #define         TPPoll_HCCAQ            BIT8                    // HCCA queue polling
1142 #define         TPPoll_StopBK           BIT9                    // Stop BK queue
1143 #define         TPPoll_StopBE           BIT10                   // Stop BE queue
1144 #define         TPPoll_StopVI           BIT11                   // Stop VI queue
1145 #define         TPPoll_StopVO           BIT12                   // Stop VO queue
1146 #define         TPPoll_StopMgt          BIT13                   // Stop Mgnt queue
1147 #define         TPPoll_StopHigh         BIT14                   // Stop High queue
1148 #define         TPPoll_StopHCCA         BIT15                   // Stop HCCA queue
1149 #define         TPPoll_SHIFT            8                               // Queue ID mapping
1150
1151 //----------------------------------------------------------------------------
1152 //       8192S PCIF                                                     (Offset 0x500, 32bit)
1153 //----------------------------------------------------------------------------
1154 #define         MXDMA2_16bytes          0x000
1155 #define         MXDMA2_32bytes          0x001
1156 #define         MXDMA2_64bytes          0x010
1157 #define         MXDMA2_128bytes         0x011
1158 #define         MXDMA2_256bytes         0x100
1159 #define         MXDMA2_512bytes         0x101
1160 #define         MXDMA2_1024bytes        0x110
1161 #define         MXDMA2_NoLimit          0x7
1162
1163 #define         MULRW_SHIFT                     3
1164 #define         MXDMA2_RX_SHIFT         4
1165 #define         MXDMA2_TX_SHIFT         0
1166
1167 //----------------------------------------------------------------------------
1168 //       8190 CCX_COMMAND_REG Setting (offset 0x25A, 1 byte)
1169 //----------------------------------------------------------------------------
1170 #define         CCX_CMD_CLM_ENABLE                              BIT0    // Enable Channel Load
1171 #define         CCX_CMD_NHM_ENABLE                              BIT1    // Enable Noise Histogram
1172 #define         CCX_CMD_FUNCTION_ENABLE                 BIT8
1173 // CCX function (Channel Load/RPI/Noise Histogram).
1174 #define         CCX_CMD_IGNORE_CCA                              BIT9
1175 // Treat CCA period as IDLE time for NHM.
1176 #define         CCX_CMD_IGNORE_TXON                             BIT10
1177 // Treat TXON period as IDLE time for NHM.
1178 #define         CCX_CLM_RESULT_READY                    BIT16
1179 // 1: Indicate the result of Channel Load is ready.
1180 #define         CCX_NHM_RESULT_READY                    BIT16
1181 // 1: Indicate the result of Noise histogram is ready.
1182 #define         CCX_CMD_RESET                                   0x0
1183 // Clear all the result of CCX measurement and disable the CCX function.
1184
1185
1186 //----------------------------------------------------------------------------
1187 // 8192S EFUSE
1188 //----------------------------------------------------------------------------
1189 //#define               HWSET_MAX_SIZE_92S                              128
1190
1191
1192 //----------------------------------------------------------------------------
1193 //       8192S EEPROM/EFUSE share register definition.
1194 //----------------------------------------------------------------------------
1195
1196 //----------------------------------------------------------------------------
1197 //       8192S EEROM and Compatible E-Fuse definition. Added by Roger, 2008.10.21.
1198 //----------------------------------------------------------------------------
1199 #define                 RTL8190_EEPROM_ID                               0x8129
1200 #define                 EEPROM_HPON                                     0x02 // LDO settings.
1201 #define                 EEPROM_VID                                              0x08 // USB Vendor ID.
1202 #define                 EEPROM_PID                                              0x0A // USB Product ID.
1203 #define                 EEPROM_USB_OPTIONAL                     0x0C // For optional function.
1204 #define                 EEPROM_USB_PHY_PARA1                    0x0D // For fine tune USB PHY.
1205 #define                 EEPROM_NODE_ADDRESS_BYTE_0      0x12 // MAC address.
1206 #define                 EEPROM_TxPowerDiff                              0x1F
1207
1208 #define                 EEPROM_Version                                  0x50
1209 #define                 EEPROM_ChannelPlan                              0x51 // Map of supported channels.
1210 #define         EEPROM_CustomID                         0x52
1211 #define                 EEPROM_SubCustomID                      0x53 // Reserved  for customer use.
1212
1213
1214         // <Roger_Notes> The followin are for different version of EEPROM contents purpose. 2008.11.22.
1215 #define                 EEPROM_BoardType                                0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU
1216 #define         EEPROM_TxPwIndex                                0x55 //0x55-0x66, Tx Power index.
1217 #define                 EEPROM_PwDiff                                   0x67 // Difference of gain index between legacy and high throughput OFDM.
1218 #define                 EEPROM_ThermalMeter                     0x68 // Thermal meter default value.
1219 #define                 EEPROM_CrystalCap                               0x69 // Crystal Cap.
1220 #define                 EEPROM_TxPowerBase                      0x6a // Tx Power of serving station.
1221 #define                 EEPROM_TSSI_A                                   0x6b //TSSI value of path A.
1222 #define                 EEPROM_TSSI_B                                   0x6c //TSSI value of path B.
1223 #define                 EEPROM_TxPwTkMode                       0x6d //Tx Power tracking mode.
1224 //#define               EEPROM_Reserved                         0x6e //0x6e-0x7f, reserved.
1225
1226 // 2009/02/09 Cosa Add for SD3 requirement
1227 #define                 EEPROM_TX_PWR_HT20_DIFF         0x6e// HT20 Tx Power Index Difference
1228 #define                 DEFAULT_HT20_TXPWR_DIFF         2       // HT20<->40 default Tx Power Index Difference
1229 #define                 EEPROM_TX_PWR_OFDM_DIFF         0x71// OFDM Tx Power Index Difference
1230 #define                 EEPROM_TX_PWR_BAND_EDGE 0x73// TX Power offset at band-edge channel
1231 #define                 TX_PWR_BAND_EDGE_CHK            0x79// Check if band-edge scheme is enabled
1232 #define         EEPROM_Default_LegacyHTTxPowerDiff      0x3
1233 #define         EEPROM_USB_Default_OPTIONAL_FUNC        0x8
1234 #define         EEPROM_USB_Default_PHY_PARAM            0x0
1235 #define         EEPROM_Default_TSSI                     0x0
1236 #define         EEPROM_Default_TxPwrTkMode      0x0
1237 #define                 EEPROM_Default_TxPowerDiff              0x0
1238 #define                 EEPROM_Default_TxPowerBase      0x0
1239 #define                 EEPROM_Default_ThermalMeter     0x7
1240 #define                 EEPROM_Default_PwDiff                   0x4
1241 #define                 EEPROM_Default_CrystalCap               0x5
1242 #define                 EEPROM_Default_TxPower          0x1010
1243 #define                 EEPROM_Default_BoardType                0x02 // Default: 2X2, RTL8192SU(QFPN68)
1244 #define         EEPROM_Default_HT2T_TxPwr               0x10
1245 #define         EEPROM_USB_SN                                   BIT0
1246 #define         EEPROM_USB_REMOTE_WAKEUP        BIT1
1247 #define         EEPROM_USB_DEVICE_PWR           BIT2
1248 #define         EEPROM_EP_NUMBER                                (BIT3|BIT4)
1249
1250 #define         EEPROM_CHANNEL_PLAN_FCC                         0x0
1251 #define         EEPROM_CHANNEL_PLAN_IC                          0x1
1252 #define         EEPROM_CHANNEL_PLAN_ETSI                        0x2
1253 #define         EEPROM_CHANNEL_PLAN_SPAIN                       0x3
1254 #define         EEPROM_CHANNEL_PLAN_FRANCE                      0x4
1255 #define         EEPROM_CHANNEL_PLAN_MKK                         0x5
1256 #define         EEPROM_CHANNEL_PLAN_MKK1                        0x6
1257 #define         EEPROM_CHANNEL_PLAN_ISRAEL                      0x7
1258 #define         EEPROM_CHANNEL_PLAN_TELEC                       0x8
1259 #define         EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN       0x9
1260 #define         EEPROM_CHANNEL_PLAN_WORLD_WIDE_13       0xA
1261 #define         EEPROM_CHANNEL_PLAN_BY_HW_MASK  0x80
1262
1263 #define                 EEPROM_CID_DEFAULT                              0x0
1264 #define                 EEPROM_CID_ALPHA                                0x1
1265 #define         EEPROM_CID_CAMEO                                        0X8
1266 #define                 EEPROM_CID_SITECOM                              0x9
1267
1268 //#define EEPROM_CID_RUNTOP                                             0x2
1269 //#define EEPROM_CID_Senao                                              0x3
1270 //#define EEPROM_CID_TOSHIBA                                            0x4
1271 //#define EEPROM_CID_NetCore                                            0x5
1272 #define                 EEPROM_CID_WHQL                                 0xFE // added by chiyoko for dtm, 20090108
1273
1274 //-----------------------------------------------------------------
1275 // 0x2c0 FW Command Control register definition, added by Roger, 2008.11.27.
1276 //-----------------------------------------------------------------
1277 #define         FW_DIG_DISABLE                          0xfd00cc00
1278 #define         FW_DIG_ENABLE                                   0xfd000000
1279 #define         FW_DIG_HALT                                     0xfd000001
1280 #define         FW_DIG_RESUME                                   0xfd000002
1281 #define         FW_HIGH_PWR_DISABLE                     0xfd000008
1282 #define         FW_HIGH_PWR_ENABLE                      0xfd000009
1283 #define         FW_TXPWR_TRACK_ENABLE           0xfd000017
1284 #define         FW_TXPWR_TRACK_DISABLE          0xfd000018
1285 #define         FW_RA_RESET                                     0xfd0000af
1286 #define         FW_RA_ACTIVE                                    0xfd0000a6
1287 #define         FW_RA_REFRESH                                   0xfd0000a0
1288 #define         FW_RA_ENABLE_BG                         0xfd0000ac
1289 #define         FW_IQK_ENABLE                                   0xf0000020
1290 #define         FW_IQK_SUCCESS                          0x0000dddd
1291 #define         FW_IQK_FAIL                                     0x0000ffff
1292 #define         FW_OP_FAILURE                                   0xffffffff
1293 #define         FW_DM_DISABLE                                   0xfd00aa00
1294 #define         FW_BB_RESET_ENABLE                      0xff00000d
1295 #define         FW_BB_RESET_DISABLE                     0xff00000e
1296
1297 //
1298 //--------------92SU require delete or move to other place later
1299 //
1300
1301
1302
1303 //
1304 //
1305 // 2008/08/06 MH For share the same 92S source/header files, we copy some
1306 // definition to pass 92SU compiler. But we must delete thm later.
1307 //
1308 //
1309
1310 //============================================================================
1311 //       819xUsb Regsiter offset definition
1312 //============================================================================
1313
1314 //2 define it temp!!!
1315 #define RFPC                                    0x5F                    // Rx FIFO Packet Count
1316 #define RCR_9356SEL                     BIT6
1317 #define TCR_LRL_OFFSET          0
1318 #define TCR_SRL_OFFSET          8
1319 #define TCR_MXDMA_OFFSET        21
1320 #define TCR_MXDMA_2048          7
1321 #define TCR_SAT                         BIT24           // Enable Rate depedent ack timeout timer
1322 #define RCR_MXDMA_OFFSET        8
1323 #define RCR_FIFO_OFFSET         13
1324 #define RCR_OnlyErlPkt          BIT31                           // Rx Early mode is performed for packet size greater than 1536
1325 #define CWR                                     0xDC                    // Contention window register
1326 #define RetryCTR                                0xDE                    // Retry Count register
1327
1328
1329 // For backward compatible for 9xUSB
1330 #define         LED1Cfg                         UnusedRegister  // LED1 Configuration Register
1331 #define         LED0Cfg                         UnusedRegister  // LED0 Configuration Register
1332 #define         GPI                                     UnusedRegister  // LED0 Configuration Register
1333 #define         BRSR                            UnusedRegister  // LED0 Configuration Register
1334 #define         CPU_GEN                         UnusedRegister  // LED0 Configuration Register
1335 #define         SIFS                            UnusedRegister  // LED0 Configuration Register
1336
1337 //----------------------------------------------------------------------------
1338 //       8190 CPU General Register              (offset 0x100, 4 byte)
1339 //----------------------------------------------------------------------------
1340 //#define       CPU_CCK_LOOPBACK                        0x00030000
1341 #define         CPU_GEN_SYSTEM_RESET            0x00000001
1342 //#define       CPU_GEN_FIRMWARE_RESET  0x00000008
1343 //#define       CPU_GEN_BOOT_RDY                        0x00000010
1344 //#define       CPU_GEN_FIRM_RDY                        0x00000020
1345 //#define       CPU_GEN_PUT_CODE_OK             0x00000080
1346 //#define       CPU_GEN_BB_RST                  0x00000100
1347 //#define       CPU_GEN_PWR_STB_CPU             0x00000004
1348 //#define       CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF              // Set bit18,17,16 to 0. Set bit19
1349 //#define       CPU_GEN_NO_LOOPBACK_SET 0x00080000              // Set BIT19 to 1
1350
1351 //----------------------------------------------------------------------------
1352 //       8192S EEROM
1353 //----------------------------------------------------------------------------
1354
1355 //#define RTL8190_EEPROM_ID                             0x8129
1356 //#define EEPROM_VID                                            0x08
1357 //#define EEPROM_PID                                            0x0A
1358 //#define EEPROM_USB_OPTIONAL                   0x0C
1359 //#define EEPROM_NODE_ADDRESS_BYTE_0    0x12
1360 //
1361 //#define EEPROM_TxPowerDiff                            0x1F
1362 //#define EEPROM_ThermalMeter                   0x20
1363 //#define EEPROM_PwDiff                                 0x21    //0x21
1364 //#define EEPROM_CrystalCap                             0x22    //0x22
1365 //
1366 //#define EEPROM_TxPwIndex_CCK                  0x23    //0x23
1367 //#define EEPROM_TxPwIndex_OFDM_24G     0x24    //0x24~0x26
1368 #define EEPROM_TxPwIndex_CCK_V1                 0x29    //0x29~0x2B
1369 #define EEPROM_TxPwIndex_OFDM_24G_V1    0x2C    //0x2C~0x2E
1370 #define EEPROM_TxPwIndex_Ver                            0x27    //0x27
1371 //
1372 //#define EEPROM_Default_TxPowerDiff            0x0
1373 //#define EEPROM_Default_ThermalMeter   0x7
1374 //#define EEPROM_Default_PwDiff                 0x4
1375 //#define EEPROM_Default_CrystalCap             0x5
1376 //#define EEPROM_Default_TxPower                        0x1010
1377 //#define EEPROM_Customer_ID                            0x7B    //0x7B:CustomerID
1378 //#define EEPROM_Version                                        0x50    // 0x50
1379 //#define EEPROM_CustomID                               0x52
1380 //#define EEPROM_ChannelPlan                            0x7c    //0x7C
1381 //#define EEPROM_IC_VER                                 0x7d    //0x7D
1382 //#define EEPROM_CRC                                            0x7e    //0x7E~0x7F
1383 //
1384 //
1385 //#define EEPROM_CID_DEFAULT                    0x0
1386 //#define EEPROM_CID_CAMEO                              0x1
1387 //#define EEPROM_CID_RUNTOP                             0x2
1388 //#define EEPROM_CID_Senao                              0x3
1389 //#define EEPROM_CID_TOSHIBA                            0x4     // Toshiba setting, Merge by Jacken, 2008/01/31
1390 //#define EEPROM_CID_NetCore                            0x5
1391
1392
1393 //
1394 //--------------92SU require delete or move to other place later
1395 //
1396
1397 //============================================================
1398 // CCX Related Register
1399 //============================================================
1400 #define         CCX_COMMAND_REG                 0x890
1401 // CCX Measurement Command Register. 4 Bytes.
1402 // Bit[0]: R_CLM_En, 1=enable, 0=disable. Enable or disable "Channel Load
1403 // Measurement (CLM)".
1404 // Bit[1]: R_NHM_En, 1=enable, 0=disable. Enable or disalbe "Noise Histogram
1405 // Measurement (NHM)".
1406 // Bit[2~7]: Reserved
1407 // Bit[8]: R_CCX_En: 1=enable, 0=disable. Enable or disable CCX function.
1408 // Note: After clearing this bit, all the result of all NHM_Result and CLM_
1409 // Result are cleared concurrently.
1410 // Bit[9]: R_Ignore_CCA: 1=enable, 0=disable. Enable means that treat CCA
1411 // period as idle time for NHM.
1412 // Bit[10]: R_Ignore_TXON: 1=enable, 0=disable. Enable means that treat TXON
1413 // period as idle time for NHM.
1414 // Bit[11~31]: Reserved.
1415 #define         CLM_PERIOD_REG                  0x894
1416 // CCX Measurement Period Register, in unit of 4us. 2 Bytes.
1417 #define         NHM_PERIOD_REG                  0x896
1418 // Noise Histogram Measurement Period Register, in unit of 4us. 2Bytes.
1419 #define         NHM_THRESHOLD0                  0x898   // Noise Histogram Meashorement0
1420 #define         NHM_THRESHOLD1                  0x899   // Noise Histogram Meashorement1
1421 #define         NHM_THRESHOLD2                  0x89A   // Noise Histogram Meashorement2
1422 #define         NHM_THRESHOLD3                  0x89B   // Noise Histogram Meashorement3
1423 #define         NHM_THRESHOLD4                  0x89C   // Noise Histogram Meashorement4
1424 #define         NHM_THRESHOLD5                  0x89D   // Noise Histogram Meashorement5
1425 #define         NHM_THRESHOLD6                  0x89E   // Noise Histogram Meashorement6
1426 #define         CLM_RESULT_REG                  0x8D0
1427 // Channel Load result register. 4 Bytes.
1428 // Bit[0~15]: Total measured duration of CLM. The CCA busy fraction is caculate
1429 // by CLM_RESULT_REG/CLM_PERIOD_REG.
1430 // Bit[16]: Indicate the CLM result is ready.
1431 // Bit[17~31]: Reserved.
1432 #define         NHM_RESULT_REG                  0x8D4
1433 // Noise Histogram result register. 4 Bytes.
1434 // Bit[0~15]: Total measured duration of NHM. If R_Ignore_CCA=1 or
1435 // R_Ignore_TXON=1, this value will be less than NHM_PERIOD_REG.
1436 // Bit[16]: Indicate the NHM result is ready.
1437 // Bit[17~31]: Reserved.
1438 #define         NHM_RPI_COUNTER0                0x8D8
1439 // NHM RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
1440 #define         NHM_RPI_COUNTER1                0x8D9
1441 // NHM RPI counter1, the fraction of signal stren in NHM_THRESH0, NHM_THRESH1
1442 #define         NHM_RPI_COUNTER2                0x8DA
1443 // NHM RPI counter2, the fraction of signal stren in NHM_THRESH2, NHM_THRESH3
1444 #define         NHM_RPI_COUNTER3                0x8DB
1445 // NHM RPI counter3, the fraction of signal stren in NHM_THRESH4, NHM_THRESH5
1446 #define         NHM_RPI_COUNTER4                0x8DC
1447 // NHM RPI counter4, the fraction of signal stren in NHM_THRESH6, NHM_THRESH7
1448 #define         NHM_RPI_COUNTER5                0x8DD
1449 // NHM RPI counter5, the fraction of signal stren in NHM_THRESH8, NHM_THRESH9
1450 #define         NHM_RPI_COUNTER6                0x8DE
1451 // NHM RPI counter6, the fraction of signal stren in NHM_THRESH10, NHM_THRESH11
1452 #define         NHM_RPI_COUNTER7                0x8DF
1453 // NHM RPI counter7, the fraction of signal stren in NHM_THRESH12, NHM_THRESH13
1454
1455 #define HAL_RETRY_LIMIT_INFRA                                                   48
1456 #define HAL_RETRY_LIMIT_AP_ADHOC                                                7
1457
1458 // HW Readio OFF switch (GPIO BIT)
1459 #define         HAL_8192S_HW_GPIO_OFF_BIT       BIT3
1460 #define         HAL_8192S_HW_GPIO_OFF_MASK      0xF7
1461 #define         HAL_8192S_HW_GPIO_WPS_BIT       BIT4
1462
1463 #endif  //R8192S_HW
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