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Staging: comedi: fix sched.h build breakage
[linux-2.6/mini2440.git] / drivers / staging / comedi / drivers / ni_pcimio.c
blob24c8b8ed5b4c4c04e8b9c860f13c7c1dcd5ddb49
1 /*
2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22 /*
23 Driver: ni_pcimio
24 Description: National Instruments PCI-MIO-E series and M series (all boards)
25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
27 Status: works
28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
38 PCI-6143, PXI-6143
39 Updated: Wed, 03 Dec 2008 10:51:47 +0000
40
41 These boards are almost identical to the AT-MIO E series, except that
42 they use the PCI bus instead of ISA (i.e., AT). See the notes for
43 the ni_atmio.o driver for additional information about these boards.
44
45 Autocalibration is supported on many of the devices, using the
46 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47 M-Series boards do analog input and analog output calibration entirely
48 in software. The software calibration corrects
49 the analog input for offset, gain and
50 nonlinearity. The analog outputs are corrected for offset and gain.
51 See the comedilib documentation on comedi_get_softcal_converter() for
52 more information.
53
54 By default, the driver uses DMA to transfer analog input data to
55 memory. When DMA is enabled, not all triggering features are
56 supported.
57
58 Digital I/O may not work on 673x.
59
60 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61 With this board all of the convertors perform one simultaineous sample during
62 a scan interval. The period for a scan is used for the convert time in a
63 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
64
65 The RTSI trigger bus is supported on these cards on
66 subdevice 10. See the comedilib documentation for details.
67
68 Information (number of channels, bits, etc.) for some devices may be
69 incorrect. Please check this and submit a bug if there are problems
70 for your device.
71
72 SCXI is probably broken for m-series boards.
73
74 Bugs:
75 - When DMA is enabled, COMEDI_EV_CONVERT does
76 not work correctly.
77
78 */
79 /*
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
82
83 References:
84
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
87
88 322080b.pdf 6711/6713/6715 User Manual
89
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92
93 ISSUES:
94
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
97
98 deal with at-mio-16de-10 revision D to N changes, etc.
99
100 need to add other CALDAC type
101
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use udelay(). Timing specs: (clock)
105 AD8522 30ns
106 DAC8043 120ns
107 DAC8800 60ns
108 MB88341 ?
109
110 */
111
112 #include "../comedidev.h"
113
114 #include <asm/byteorder.h>
115 #include <linux/delay.h>
116
117 #include "ni_stc.h"
118 #include "mite.h"
119
120 /* #define PCI_DEBUG */
121
122 #define PCIDMA
123
124 #define PCIMIO 1
125 #undef ATMIO
126
127 #define MAX_N_CALDACS (16+16+2)
128
129 #define DRV_NAME "ni_pcimio"
130
131 /* The following two tables must be in the same order */
132 static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
133 {
134 PCI_VENDOR_ID_NATINST, 0x0162, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
135 PCI_VENDOR_ID_NATINST, 0x1170, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
136 PCI_VENDOR_ID_NATINST, 0x1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
137 PCI_VENDOR_ID_NATINST, 0x1190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
138 PCI_VENDOR_ID_NATINST, 0x11b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
139 PCI_VENDOR_ID_NATINST, 0x11c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
140 PCI_VENDOR_ID_NATINST, 0x11d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
141 PCI_VENDOR_ID_NATINST, 0x1270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
142 PCI_VENDOR_ID_NATINST, 0x1330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
143 PCI_VENDOR_ID_NATINST, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
144 PCI_VENDOR_ID_NATINST, 0x1350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
145 PCI_VENDOR_ID_NATINST, 0x14e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
146 PCI_VENDOR_ID_NATINST, 0x14f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
147 PCI_VENDOR_ID_NATINST, 0x1580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
148 PCI_VENDOR_ID_NATINST, 0x15b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
149 PCI_VENDOR_ID_NATINST, 0x1880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
150 PCI_VENDOR_ID_NATINST, 0x1870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
151 PCI_VENDOR_ID_NATINST, 0x18b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
152 PCI_VENDOR_ID_NATINST, 0x18c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
153 PCI_VENDOR_ID_NATINST, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
154 PCI_VENDOR_ID_NATINST, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
155 PCI_VENDOR_ID_NATINST, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
156 PCI_VENDOR_ID_NATINST, 0x2890, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
157 PCI_VENDOR_ID_NATINST, 0x28c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
158 PCI_VENDOR_ID_NATINST, 0x2a60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
159 PCI_VENDOR_ID_NATINST, 0x2a70, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
160 PCI_VENDOR_ID_NATINST, 0x2a80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
161 PCI_VENDOR_ID_NATINST, 0x2ab0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
162 PCI_VENDOR_ID_NATINST, 0x2b80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
163 PCI_VENDOR_ID_NATINST, 0x2b90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
164 PCI_VENDOR_ID_NATINST, 0x2c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
165 PCI_VENDOR_ID_NATINST, 0x2ca0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
166 PCI_VENDOR_ID_NATINST, 0x70aa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
167 PCI_VENDOR_ID_NATINST, 0x70ab, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
168 PCI_VENDOR_ID_NATINST, 0x70ac, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
169 PCI_VENDOR_ID_NATINST, 0x70af, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
170 PCI_VENDOR_ID_NATINST, 0x70b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
171 PCI_VENDOR_ID_NATINST, 0x70b4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
172 PCI_VENDOR_ID_NATINST, 0x70b6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
173 PCI_VENDOR_ID_NATINST, 0x70b7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
174 PCI_VENDOR_ID_NATINST, 0x70b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
175 PCI_VENDOR_ID_NATINST, 0x70bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
176 PCI_VENDOR_ID_NATINST, 0x70bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
177 PCI_VENDOR_ID_NATINST, 0x70bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
178 PCI_VENDOR_ID_NATINST, 0x70c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
179 PCI_VENDOR_ID_NATINST, 0x70f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
180 PCI_VENDOR_ID_NATINST, 0x710d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
181 PCI_VENDOR_ID_NATINST, 0x716c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
182 PCI_VENDOR_ID_NATINST, 0x716d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
183 PCI_VENDOR_ID_NATINST, 0x717f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
184 PCI_VENDOR_ID_NATINST, 0x71bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
185 PCI_VENDOR_ID_NATINST, 0x717d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
186 0}
187 };
188
189 MODULE_DEVICE_TABLE(pci, ni_pci_table);
190
191 /* These are not all the possible ao ranges for 628x boards.
192 They can do OFFSET +- REFERENCE where OFFSET can be
193 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
194 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
195 63 different possibilities. An AO channel
196 can not act as it's own OFFSET or REFERENCE.
197 */
198 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
199 RANGE(-10, 10),
200 RANGE(-5, 5),
201 RANGE(-2, 2),
202 RANGE(-1, 1),
203 RANGE(-5, 15),
204 RANGE(0, 10),
205 RANGE(3, 7),
206 RANGE(4, 6),
207 RANGE_ext(-1, 1)
208 }
209 };
210
211 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
212 RANGE(-10, 10),
213 RANGE(-5, 5),
214 RANGE_ext(-1, 1)
215 }
216 };
217
218 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
219 RANGE(-10, 10),
220 }
221 };
222
223 static const struct ni_board_struct ni_boards[] = {
224 {
225 .device_id = 0x0162, /* NI also says 0x1620. typo? */
226 .name = "pci-mio-16xe-50",
227 .n_adchan = 16,
228 .adbits = 16,
229 .ai_fifo_depth = 2048,
230 .alwaysdither = 1,
231 .gainlkup = ai_gain_8,
232 .ai_speed = 50000,
233 .n_aochan = 2,
234 .aobits = 12,
235 .ao_fifo_depth = 0,
236 .ao_range_table = &range_bipolar10,
237 .ao_unipolar = 0,
238 .ao_speed = 50000,
239 .num_p0_dio_channels = 8,
240 .caldac = {dac8800, dac8043},
241 .has_8255 = 0,
242 },
243 {
244 .device_id = 0x1170,
245 .name = "pci-mio-16xe-10", /* aka pci-6030E */
246 .n_adchan = 16,
247 .adbits = 16,
248 .ai_fifo_depth = 512,
249 .alwaysdither = 1,
250 .gainlkup = ai_gain_14,
251 .ai_speed = 10000,
252 .n_aochan = 2,
253 .aobits = 16,
254 .ao_fifo_depth = 2048,
255 .ao_range_table = &range_ni_E_ao_ext,
256 .ao_unipolar = 1,
257 .ao_speed = 10000,
258 .num_p0_dio_channels = 8,
259 .caldac = {dac8800, dac8043, ad8522},
260 .has_8255 = 0,
261 },
262 {
263 .device_id = 0x28c0,
264 .name = "pci-6014",
265 .n_adchan = 16,
266 .adbits = 16,
267 .ai_fifo_depth = 512,
268 .alwaysdither = 1,
269 .gainlkup = ai_gain_4,
270 .ai_speed = 5000,
271 .n_aochan = 2,
272 .aobits = 16,
273 .ao_fifo_depth = 0,
274 .ao_range_table = &range_bipolar10,
275 .ao_unipolar = 0,
276 .ao_speed = 100000,
277 .num_p0_dio_channels = 8,
278 .caldac = {ad8804_debug},
279 .has_8255 = 0,
280 },
281 {
282 .device_id = 0x11d0,
283 .name = "pxi-6030e",
284 .n_adchan = 16,
285 .adbits = 16,
286 .ai_fifo_depth = 512,
287 .alwaysdither = 1,
288 .gainlkup = ai_gain_14,
289 .ai_speed = 10000,
290 .n_aochan = 2,
291 .aobits = 16,
292 .ao_fifo_depth = 2048,
293 .ao_range_table = &range_ni_E_ao_ext,
294 .ao_unipolar = 1,
295 .ao_speed = 10000,
296 .num_p0_dio_channels = 8,
297 .caldac = {dac8800, dac8043, ad8522},
298 .has_8255 = 0,
299 },
300 {
301 .device_id = 0x1180,
302 .name = "pci-mio-16e-1", /* aka pci-6070e */
303 .n_adchan = 16,
304 .adbits = 12,
305 .ai_fifo_depth = 512,
306 .alwaysdither = 0,
307 .gainlkup = ai_gain_16,
308 .ai_speed = 800,
309 .n_aochan = 2,
310 .aobits = 12,
311 .ao_fifo_depth = 2048,
312 .ao_range_table = &range_ni_E_ao_ext,
313 .ao_unipolar = 1,
314 .ao_speed = 1000,
315 .num_p0_dio_channels = 8,
316 .caldac = {mb88341},
317 .has_8255 = 0,
318 },
319 {
320 .device_id = 0x1190,
321 .name = "pci-mio-16e-4", /* aka pci-6040e */
322 .n_adchan = 16,
323 .adbits = 12,
324 .ai_fifo_depth = 512,
325 .alwaysdither = 0,
326 .gainlkup = ai_gain_16,
327 /* .Note = there have been reported problems with full speed
328 * on this board */
329 .ai_speed = 2000,
330 .n_aochan = 2,
331 .aobits = 12,
332 .ao_fifo_depth = 512,
333 .ao_range_table = &range_ni_E_ao_ext,
334 .ao_unipolar = 1,
335 .ao_speed = 1000,
336 .num_p0_dio_channels = 8,
337 .caldac = {ad8804_debug}, /* doc says mb88341 */
338 .has_8255 = 0,
339 },
340 {
341 .device_id = 0x11c0,
342 .name = "pxi-6040e",
343 .n_adchan = 16,
344 .adbits = 12,
345 .ai_fifo_depth = 512,
346 .alwaysdither = 0,
347 .gainlkup = ai_gain_16,
348 .ai_speed = 2000,
349 .n_aochan = 2,
350 .aobits = 12,
351 .ao_fifo_depth = 512,
352 .ao_range_table = &range_ni_E_ao_ext,
353 .ao_unipolar = 1,
354 .ao_speed = 1000,
355 .num_p0_dio_channels = 8,
356 .caldac = {mb88341},
357 .has_8255 = 0,
358 },
359
360 {
361 .device_id = 0x1330,
362 .name = "pci-6031e",
363 .n_adchan = 64,
364 .adbits = 16,
365 .ai_fifo_depth = 512,
366 .alwaysdither = 1,
367 .gainlkup = ai_gain_14,
368 .ai_speed = 10000,
369 .n_aochan = 2,
370 .aobits = 16,
371 .ao_fifo_depth = 2048,
372 .ao_range_table = &range_ni_E_ao_ext,
373 .ao_unipolar = 1,
374 .ao_speed = 10000,
375 .num_p0_dio_channels = 8,
376 .caldac = {dac8800, dac8043, ad8522},
377 .has_8255 = 0,
378 },
379 {
380 .device_id = 0x1270,
381 .name = "pci-6032e",
382 .n_adchan = 16,
383 .adbits = 16,
384 .ai_fifo_depth = 512,
385 .alwaysdither = 1,
386 .gainlkup = ai_gain_14,
387 .ai_speed = 10000,
388 .n_aochan = 0,
389 .aobits = 0,
390 .ao_fifo_depth = 0,
391 .ao_unipolar = 0,
392 .num_p0_dio_channels = 8,
393 .caldac = {dac8800, dac8043, ad8522},
394 .has_8255 = 0,
395 },
396 {
397 .device_id = 0x1340,
398 .name = "pci-6033e",
399 .n_adchan = 64,
400 .adbits = 16,
401 .ai_fifo_depth = 512,
402 .alwaysdither = 1,
403 .gainlkup = ai_gain_14,
404 .ai_speed = 10000,
405 .n_aochan = 0,
406 .aobits = 0,
407 .ao_fifo_depth = 0,
408 .ao_unipolar = 0,
409 .num_p0_dio_channels = 8,
410 .caldac = {dac8800, dac8043, ad8522},
411 .has_8255 = 0,
412 },
413 {
414 .device_id = 0x1350,
415 .name = "pci-6071e",
416 .n_adchan = 64,
417 .adbits = 12,
418 .ai_fifo_depth = 512,
419 .alwaysdither = 1,
420 .gainlkup = ai_gain_16,
421 .ai_speed = 800,
422 .n_aochan = 2,
423 .aobits = 12,
424 .ao_fifo_depth = 2048,
425 .ao_range_table = &range_ni_E_ao_ext,
426 .ao_unipolar = 1,
427 .ao_speed = 1000,
428 .num_p0_dio_channels = 8,
429 .caldac = {ad8804_debug},
430 .has_8255 = 0,
431 },
432 {
433 .device_id = 0x2a60,
434 .name = "pci-6023e",
435 .n_adchan = 16,
436 .adbits = 12,
437 .ai_fifo_depth = 512,
438 .alwaysdither = 0,
439 .gainlkup = ai_gain_4,
440 .ai_speed = 5000,
441 .n_aochan = 0,
442 .aobits = 0,
443 .ao_unipolar = 0,
444 .num_p0_dio_channels = 8,
445 .caldac = {ad8804_debug}, /* manual is wrong */
446 .has_8255 = 0,
447 },
448 {
449 .device_id = 0x2a70,
450 .name = "pci-6024e",
451 .n_adchan = 16,
452 .adbits = 12,
453 .ai_fifo_depth = 512,
454 .alwaysdither = 0,
455 .gainlkup = ai_gain_4,
456 .ai_speed = 5000,
457 .n_aochan = 2,
458 .aobits = 12,
459 .ao_fifo_depth = 0,
460 .ao_range_table = &range_bipolar10,
461 .ao_unipolar = 0,
462 .ao_speed = 100000,
463 .num_p0_dio_channels = 8,
464 .caldac = {ad8804_debug}, /* manual is wrong */
465 .has_8255 = 0,
466 },
467 {
468 .device_id = 0x2a80,
469 .name = "pci-6025e",
470 .n_adchan = 16,
471 .adbits = 12,
472 .ai_fifo_depth = 512,
473 .alwaysdither = 0,
474 .gainlkup = ai_gain_4,
475 .ai_speed = 5000,
476 .n_aochan = 2,
477 .aobits = 12,
478 .ao_fifo_depth = 0,
479 .ao_range_table = &range_bipolar10,
480 .ao_unipolar = 0,
481 .ao_speed = 100000,
482 .num_p0_dio_channels = 8,
483 .caldac = {ad8804_debug}, /* manual is wrong */
484 .has_8255 = 1,
485 },
486 {
487 .device_id = 0x2ab0,
488 .name = "pxi-6025e",
489 .n_adchan = 16,
490 .adbits = 12,
491 .ai_fifo_depth = 512,
492 .alwaysdither = 0,
493 .gainlkup = ai_gain_4,
494 .ai_speed = 5000,
495 .n_aochan = 2,
496 .aobits = 12,
497 .ao_fifo_depth = 0,
498 .ao_range_table = &range_ni_E_ao_ext,
499 .ao_unipolar = 1,
500 .ao_speed = 100000,
501 .num_p0_dio_channels = 8,
502 .caldac = {ad8804_debug}, /* manual is wrong */
503 .has_8255 = 1,
504 },
505
506 {
507 .device_id = 0x2ca0,
508 .name = "pci-6034e",
509 .n_adchan = 16,
510 .adbits = 16,
511 .ai_fifo_depth = 512,
512 .alwaysdither = 1,
513 .gainlkup = ai_gain_4,
514 .ai_speed = 5000,
515 .n_aochan = 0,
516 .aobits = 0,
517 .ao_fifo_depth = 0,
518 .ao_unipolar = 0,
519 .num_p0_dio_channels = 8,
520 .caldac = {ad8804_debug},
521 .has_8255 = 0,
522 },
523 {
524 .device_id = 0x2c80,
525 .name = "pci-6035e",
526 .n_adchan = 16,
527 .adbits = 16,
528 .ai_fifo_depth = 512,
529 .alwaysdither = 1,
530 .gainlkup = ai_gain_4,
531 .ai_speed = 5000,
532 .n_aochan = 2,
533 .aobits = 12,
534 .ao_fifo_depth = 0,
535 .ao_range_table = &range_bipolar10,
536 .ao_unipolar = 0,
537 .ao_speed = 100000,
538 .num_p0_dio_channels = 8,
539 .caldac = {ad8804_debug},
540 .has_8255 = 0,
541 },
542 {
543 .device_id = 0x18b0,
544 .name = "pci-6052e",
545 .n_adchan = 16,
546 .adbits = 16,
547 .ai_fifo_depth = 512,
548 .alwaysdither = 1,
549 .gainlkup = ai_gain_16,
550 .ai_speed = 3000,
551 .n_aochan = 2,
552 .aobits = 16,
553 .ao_unipolar = 1,
554 .ao_fifo_depth = 2048,
555 .ao_range_table = &range_ni_E_ao_ext,
556 .ao_speed = 3000,
557 .num_p0_dio_channels = 8,
558 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
559 },
560 {.device_id = 0x14e0,
561 .name = "pci-6110",
562 .n_adchan = 4,
563 .adbits = 12,
564 .ai_fifo_depth = 8192,
565 .alwaysdither = 0,
566 .gainlkup = ai_gain_611x,
567 .ai_speed = 200,
568 .n_aochan = 2,
569 .aobits = 16,
570 .reg_type = ni_reg_611x,
571 .ao_range_table = &range_bipolar10,
572 .ao_unipolar = 0,
573 .ao_fifo_depth = 2048,
574 .ao_speed = 250,
575 .num_p0_dio_channels = 8,
576 .caldac = {ad8804, ad8804},
577 },
578 {
579 .device_id = 0x14f0,
580 .name = "pci-6111",
581 .n_adchan = 2,
582 .adbits = 12,
583 .ai_fifo_depth = 8192,
584 .alwaysdither = 0,
585 .gainlkup = ai_gain_611x,
586 .ai_speed = 200,
587 .n_aochan = 2,
588 .aobits = 16,
589 .reg_type = ni_reg_611x,
590 .ao_range_table = &range_bipolar10,
591 .ao_unipolar = 0,
592 .ao_fifo_depth = 2048,
593 .ao_speed = 250,
594 .num_p0_dio_channels = 8,
595 .caldac = {ad8804, ad8804},
596 },
597 #if 0
598 /* The 6115 boards probably need their own driver */
599 {
600 .device_id = 0x2ed0,
601 .name = "pci-6115",
602 .n_adchan = 4,
603 .adbits = 12,
604 .ai_fifo_depth = 8192,
605 .alwaysdither = 0,
606 .gainlkup = ai_gain_611x,
607 .ai_speed = 100,
608 .n_aochan = 2,
609 .aobits = 16,
610 .ao_671x = 1,
611 .ao_unipolar = 0,
612 .ao_fifo_depth = 2048,
613 .ao_speed = 250,
614 .num_p0_dio_channels = 8,
615 .reg_611x = 1,
616 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
617 },
618 #endif
619 #if 0
620 {
621 .device_id = 0x0000,
622 .name = "pxi-6115",
623 .n_adchan = 4,
624 .adbits = 12,
625 .ai_fifo_depth = 8192,
626 .alwaysdither = 0,
627 .gainlkup = ai_gain_611x,
628 .ai_speed = 100,
629 .n_aochan = 2,
630 .aobits = 16,
631 .ao_671x = 1,
632 .ao_unipolar = 0,
633 .ao_fifo_depth = 2048,
634 .ao_speed = 250,
635 .reg_611x = 1,
636 .num_p0_dio_channels = 8,
637 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
638 },
639 #endif
640 {
641 .device_id = 0x1880,
642 .name = "pci-6711",
643 .n_adchan = 0, /* no analog input */
644 .n_aochan = 4,
645 .aobits = 12,
646 .ao_unipolar = 0,
647 .ao_fifo_depth = 16384,
648 /* data sheet says 8192, but fifo really holds 16384 samples */
649 .ao_range_table = &range_bipolar10,
650 .ao_speed = 1000,
651 .num_p0_dio_channels = 8,
652 .reg_type = ni_reg_6711,
653 .caldac = {ad8804_debug},
654 },
655 {
656 .device_id = 0x2b90,
657 .name = "pxi-6711",
658 .n_adchan = 0, /* no analog input */
659 .n_aochan = 4,
660 .aobits = 12,
661 .ao_unipolar = 0,
662 .ao_fifo_depth = 16384,
663 .ao_range_table = &range_bipolar10,
664 .ao_speed = 1000,
665 .num_p0_dio_channels = 8,
666 .reg_type = ni_reg_6711,
667 .caldac = {ad8804_debug},
668 },
669 {
670 .device_id = 0x1870,
671 .name = "pci-6713",
672 .n_adchan = 0, /* no analog input */
673 .n_aochan = 8,
674 .aobits = 12,
675 .ao_unipolar = 0,
676 .ao_fifo_depth = 16384,
677 .ao_range_table = &range_bipolar10,
678 .ao_speed = 1000,
679 .num_p0_dio_channels = 8,
680 .reg_type = ni_reg_6713,
681 .caldac = {ad8804_debug, ad8804_debug},
682 },
683 {
684 .device_id = 0x2b80,
685 .name = "pxi-6713",
686 .n_adchan = 0, /* no analog input */
687 .n_aochan = 8,
688 .aobits = 12,
689 .ao_unipolar = 0,
690 .ao_fifo_depth = 16384,
691 .ao_range_table = &range_bipolar10,
692 .ao_speed = 1000,
693 .num_p0_dio_channels = 8,
694 .reg_type = ni_reg_6713,
695 .caldac = {ad8804_debug, ad8804_debug},
696 },
697 {
698 .device_id = 0x2430,
699 .name = "pci-6731",
700 .n_adchan = 0, /* no analog input */
701 .n_aochan = 4,
702 .aobits = 16,
703 .ao_unipolar = 0,
704 .ao_fifo_depth = 8192,
705 .ao_range_table = &range_bipolar10,
706 .ao_speed = 1000,
707 .num_p0_dio_channels = 8,
708 .reg_type = ni_reg_6711,
709 .caldac = {ad8804_debug},
710 },
711 #if 0 /* need device ids */
712 {
713 .device_id = 0x0,
714 .name = "pxi-6731",
715 .n_adchan = 0, /* no analog input */
716 .n_aochan = 4,
717 .aobits = 16,
718 .ao_unipolar = 0,
719 .ao_fifo_depth = 8192,
720 .ao_range_table = &range_bipolar10,
721 .num_p0_dio_channels = 8,
722 .reg_type = ni_reg_6711,
723 .caldac = {ad8804_debug},
724 },
725 #endif
726 {
727 .device_id = 0x2410,
728 .name = "pci-6733",
729 .n_adchan = 0, /* no analog input */
730 .n_aochan = 8,
731 .aobits = 16,
732 .ao_unipolar = 0,
733 .ao_fifo_depth = 16384,
734 .ao_range_table = &range_bipolar10,
735 .ao_speed = 1000,
736 .num_p0_dio_channels = 8,
737 .reg_type = ni_reg_6713,
738 .caldac = {ad8804_debug, ad8804_debug},
739 },
740 {
741 .device_id = 0x2420,
742 .name = "pxi-6733",
743 .n_adchan = 0, /* no analog input */
744 .n_aochan = 8,
745 .aobits = 16,
746 .ao_unipolar = 0,
747 .ao_fifo_depth = 16384,
748 .ao_range_table = &range_bipolar10,
749 .ao_speed = 1000,
750 .num_p0_dio_channels = 8,
751 .reg_type = ni_reg_6713,
752 .caldac = {ad8804_debug, ad8804_debug},
753 },
754 {
755 .device_id = 0x15b0,
756 .name = "pxi-6071e",
757 .n_adchan = 64,
758 .adbits = 12,
759 .ai_fifo_depth = 512,
760 .alwaysdither = 1,
761 .gainlkup = ai_gain_16,
762 .ai_speed = 800,
763 .n_aochan = 2,
764 .aobits = 12,
765 .ao_fifo_depth = 2048,
766 .ao_range_table = &range_ni_E_ao_ext,
767 .ao_unipolar = 1,
768 .ao_speed = 1000,
769 .num_p0_dio_channels = 8,
770 .caldac = {ad8804_debug},
771 .has_8255 = 0,
772 },
773 {
774 .device_id = 0x11b0,
775 .name = "pxi-6070e",
776 .n_adchan = 16,
777 .adbits = 12,
778 .ai_fifo_depth = 512,
779 .alwaysdither = 1,
780 .gainlkup = ai_gain_16,
781 .ai_speed = 800,
782 .n_aochan = 2,
783 .aobits = 12,
784 .ao_fifo_depth = 2048,
785 .ao_range_table = &range_ni_E_ao_ext,
786 .ao_unipolar = 1,
787 .ao_speed = 1000,
788 .num_p0_dio_channels = 8,
789 .caldac = {ad8804_debug},
790 .has_8255 = 0,
791 },
792 {
793 .device_id = 0x18c0,
794 .name = "pxi-6052e",
795 .n_adchan = 16,
796 .adbits = 16,
797 .ai_fifo_depth = 512,
798 .alwaysdither = 1,
799 .gainlkup = ai_gain_16,
800 .ai_speed = 3000,
801 .n_aochan = 2,
802 .aobits = 16,
803 .ao_unipolar = 1,
804 .ao_fifo_depth = 2048,
805 .ao_range_table = &range_ni_E_ao_ext,
806 .ao_speed = 3000,
807 .num_p0_dio_channels = 8,
808 .caldac = {mb88341, mb88341, ad8522},
809 },
810 {
811 .device_id = 0x1580,
812 .name = "pxi-6031e",
813 .n_adchan = 64,
814 .adbits = 16,
815 .ai_fifo_depth = 512,
816 .alwaysdither = 1,
817 .gainlkup = ai_gain_14,
818 .ai_speed = 10000,
819 .n_aochan = 2,
820 .aobits = 16,
821 .ao_fifo_depth = 2048,
822 .ao_range_table = &range_ni_E_ao_ext,
823 .ao_unipolar = 1,
824 .ao_speed = 10000,
825 .num_p0_dio_channels = 8,
826 .caldac = {dac8800, dac8043, ad8522},
827 },
828 {
829 .device_id = 0x2890,
830 .name = "pci-6036e",
831 .n_adchan = 16,
832 .adbits = 16,
833 .ai_fifo_depth = 512,
834 .alwaysdither = 1,
835 .gainlkup = ai_gain_4,
836 .ai_speed = 5000,
837 .n_aochan = 2,
838 .aobits = 16,
839 .ao_fifo_depth = 0,
840 .ao_range_table = &range_bipolar10,
841 .ao_unipolar = 0,
842 .ao_speed = 100000,
843 .num_p0_dio_channels = 8,
844 .caldac = {ad8804_debug},
845 .has_8255 = 0,
846 },
847 {
848 .device_id = 0x70b0,
849 .name = "pci-6220",
850 .n_adchan = 16,
851 .adbits = 16,
852 .ai_fifo_depth = 512,
853 /* .FIXME = guess */
854 .gainlkup = ai_gain_622x,
855 .ai_speed = 4000,
856 .n_aochan = 0,
857 .aobits = 0,
858 .ao_fifo_depth = 0,
859 .num_p0_dio_channels = 8,
860 .reg_type = ni_reg_622x,
861 .ao_unipolar = 0,
862 .caldac = {caldac_none},
863 .has_8255 = 0,
864 },
865 {
866 .device_id = 0x70af,
867 .name = "pci-6221",
868 .n_adchan = 16,
869 .adbits = 16,
870 .ai_fifo_depth = 4095,
871 .gainlkup = ai_gain_622x,
872 .ai_speed = 4000,
873 .n_aochan = 2,
874 .aobits = 16,
875 .ao_fifo_depth = 8191,
876 .ao_range_table = &range_ni_M_622x_ao,
877 .reg_type = ni_reg_622x,
878 .ao_unipolar = 0,
879 .ao_speed = 1200,
880 .num_p0_dio_channels = 8,
881 .caldac = {caldac_none},
882 .has_8255 = 0,
883 },
884 {
885 .device_id = 0x71bc,
886 .name = "pci-6221_37pin",
887 .n_adchan = 16,
888 .adbits = 16,
889 .ai_fifo_depth = 4095,
890 .gainlkup = ai_gain_622x,
891 .ai_speed = 4000,
892 .n_aochan = 2,
893 .aobits = 16,
894 .ao_fifo_depth = 8191,
895 .ao_range_table = &range_ni_M_622x_ao,
896 .reg_type = ni_reg_622x,
897 .ao_unipolar = 0,
898 .ao_speed = 1200,
899 .num_p0_dio_channels = 8,
900 .caldac = {caldac_none},
901 .has_8255 = 0,
902 },
903 {
904 .device_id = 0x70f2,
905 .name = "pci-6224",
906 .n_adchan = 32,
907 .adbits = 16,
908 .ai_fifo_depth = 4095,
909 .gainlkup = ai_gain_622x,
910 .ai_speed = 4000,
911 .n_aochan = 0,
912 .aobits = 0,
913 .ao_fifo_depth = 0,
914 .reg_type = ni_reg_622x,
915 .ao_unipolar = 0,
916 .num_p0_dio_channels = 32,
917 .caldac = {caldac_none},
918 .has_8255 = 0,
919 },
920 {
921 .device_id = 0x70f3,
922 .name = "pxi-6224",
923 .n_adchan = 32,
924 .adbits = 16,
925 .ai_fifo_depth = 4095,
926 .gainlkup = ai_gain_622x,
927 .ai_speed = 4000,
928 .n_aochan = 0,
929 .aobits = 0,
930 .ao_fifo_depth = 0,
931 .reg_type = ni_reg_622x,
932 .ao_unipolar = 0,
933 .num_p0_dio_channels = 32,
934 .caldac = {caldac_none},
935 .has_8255 = 0,
936 },
937 {
938 .device_id = 0x716c,
939 .name = "pci-6225",
940 .n_adchan = 80,
941 .adbits = 16,
942 .ai_fifo_depth = 4095,
943 .gainlkup = ai_gain_622x,
944 .ai_speed = 4000,
945 .n_aochan = 2,
946 .aobits = 16,
947 .ao_fifo_depth = 8191,
948 .ao_range_table = &range_ni_M_622x_ao,
949 .reg_type = ni_reg_622x,
950 .ao_unipolar = 0,
951 .ao_speed = 1200,
952 .num_p0_dio_channels = 32,
953 .caldac = {caldac_none},
954 .has_8255 = 0,
955 },
956 {
957 .device_id = 0x716d,
958 .name = "pxi-6225",
959 .n_adchan = 80,
960 .adbits = 16,
961 .ai_fifo_depth = 4095,
962 .gainlkup = ai_gain_622x,
963 .ai_speed = 4000,
964 .n_aochan = 2,
965 .aobits = 16,
966 .ao_fifo_depth = 8191,
967 .ao_range_table = &range_ni_M_622x_ao,
968 .reg_type = ni_reg_622x,
969 .ao_unipolar = 0,
970 .ao_speed = 1200,
971 .num_p0_dio_channels = 32,
972 .caldac = {caldac_none},
973 .has_8255 = 0,
974 },
975 {
976 .device_id = 0x70aa,
977 .name = "pci-6229",
978 .n_adchan = 32,
979 .adbits = 16,
980 .ai_fifo_depth = 4095,
981 .gainlkup = ai_gain_622x,
982 .ai_speed = 4000,
983 .n_aochan = 4,
984 .aobits = 16,
985 .ao_fifo_depth = 8191,
986 .ao_range_table = &range_ni_M_622x_ao,
987 .reg_type = ni_reg_622x,
988 .ao_unipolar = 0,
989 .ao_speed = 1200,
990 .num_p0_dio_channels = 32,
991 .caldac = {caldac_none},
992 .has_8255 = 0,
993 },
994 {
995 .device_id = 0x70b4,
996 .name = "pci-6250",
997 .n_adchan = 16,
998 .adbits = 16,
999 .ai_fifo_depth = 4095,
1000 .gainlkup = ai_gain_628x,
1001 .ai_speed = 800,
1002 .n_aochan = 0,
1003 .aobits = 0,
1004 .ao_fifo_depth = 0,
1005 .reg_type = ni_reg_625x,
1006 .ao_unipolar = 0,
1007 .num_p0_dio_channels = 8,
1008 .caldac = {caldac_none},
1009 .has_8255 = 0,
1010 },
1011 {
1012 .device_id = 0x70b8,
1013 .name = "pci-6251",
1014 .n_adchan = 16,
1015 .adbits = 16,
1016 .ai_fifo_depth = 4095,
1017 .gainlkup = ai_gain_628x,
1018 .ai_speed = 800,
1019 .n_aochan = 2,
1020 .aobits = 16,
1021 .ao_fifo_depth = 8191,
1022 .ao_range_table = &range_ni_M_625x_ao,
1023 .reg_type = ni_reg_625x,
1024 .ao_unipolar = 0,
1025 .ao_speed = 357,
1026 .num_p0_dio_channels = 8,
1027 .caldac = {caldac_none},
1028 .has_8255 = 0,
1029 },
1030 {
1031 .device_id = 0x717d,
1032 .name = "pcie-6251",
1033 .n_adchan = 16,
1034 .adbits = 16,
1035 .ai_fifo_depth = 4095,
1036 .gainlkup = ai_gain_628x,
1037 .ai_speed = 800,
1038 .n_aochan = 2,
1039 .aobits = 16,
1040 .ao_fifo_depth = 8191,
1041 .ao_range_table = &range_ni_M_625x_ao,
1042 .reg_type = ni_reg_625x,
1043 .ao_unipolar = 0,
1044 .ao_speed = 357,
1045 .num_p0_dio_channels = 8,
1046 .caldac = {caldac_none},
1047 .has_8255 = 0,
1048 },
1049 {
1050 .device_id = 0x70b7,
1051 .name = "pci-6254",
1052 .n_adchan = 32,
1053 .adbits = 16,
1054 .ai_fifo_depth = 4095,
1055 .gainlkup = ai_gain_628x,
1056 .ai_speed = 800,
1057 .n_aochan = 0,
1058 .aobits = 0,
1059 .ao_fifo_depth = 0,
1060 .reg_type = ni_reg_625x,
1061 .ao_unipolar = 0,
1062 .num_p0_dio_channels = 32,
1063 .caldac = {caldac_none},
1064 .has_8255 = 0,
1065 },
1066 {
1067 .device_id = 0x70ab,
1068 .name = "pci-6259",
1069 .n_adchan = 32,
1070 .adbits = 16,
1071 .ai_fifo_depth = 4095,
1072 .gainlkup = ai_gain_628x,
1073 .ai_speed = 800,
1074 .n_aochan = 4,
1075 .aobits = 16,
1076 .ao_fifo_depth = 8191,
1077 .ao_range_table = &range_ni_M_625x_ao,
1078 .reg_type = ni_reg_625x,
1079 .ao_unipolar = 0,
1080 .ao_speed = 357,
1081 .num_p0_dio_channels = 32,
1082 .caldac = {caldac_none},
1083 .has_8255 = 0,
1084 },
1085 {
1086 .device_id = 0x717f,
1087 .name = "pcie-6259",
1088 .n_adchan = 32,
1089 .adbits = 16,
1090 .ai_fifo_depth = 4095,
1091 .gainlkup = ai_gain_628x,
1092 .ai_speed = 800,
1093 .n_aochan = 4,
1094 .aobits = 16,
1095 .ao_fifo_depth = 8191,
1096 .ao_range_table = &range_ni_M_625x_ao,
1097 .reg_type = ni_reg_625x,
1098 .ao_unipolar = 0,
1099 .ao_speed = 357,
1100 .num_p0_dio_channels = 32,
1101 .caldac = {caldac_none},
1102 .has_8255 = 0,
1103 },
1104 {
1105 .device_id = 0x70b6,
1106 .name = "pci-6280",
1107 .n_adchan = 16,
1108 .adbits = 18,
1109 .ai_fifo_depth = 2047,
1110 .gainlkup = ai_gain_628x,
1111 .ai_speed = 1600,
1112 .n_aochan = 0,
1113 .aobits = 0,
1114 .ao_fifo_depth = 8191,
1115 .reg_type = ni_reg_628x,
1116 .ao_unipolar = 0,
1117 .num_p0_dio_channels = 8,
1118 .caldac = {caldac_none},
1119 .has_8255 = 0,
1120 },
1121 {
1122 .device_id = 0x70bd,
1123 .name = "pci-6281",
1124 .n_adchan = 16,
1125 .adbits = 18,
1126 .ai_fifo_depth = 2047,
1127 .gainlkup = ai_gain_628x,
1128 .ai_speed = 1600,
1129 .n_aochan = 2,
1130 .aobits = 16,
1131 .ao_fifo_depth = 8191,
1132 .ao_range_table = &range_ni_M_628x_ao,
1133 .reg_type = ni_reg_628x,
1134 .ao_unipolar = 1,
1135 .ao_speed = 357,
1136 .num_p0_dio_channels = 8,
1137 .caldac = {caldac_none},
1138 .has_8255 = 0,
1139 },
1140 {
1141 .device_id = 0x70bf,
1142 .name = "pxi-6281",
1143 .n_adchan = 16,
1144 .adbits = 18,
1145 .ai_fifo_depth = 2047,
1146 .gainlkup = ai_gain_628x,
1147 .ai_speed = 1600,
1148 .n_aochan = 2,
1149 .aobits = 16,
1150 .ao_fifo_depth = 8191,
1151 .ao_range_table = &range_ni_M_628x_ao,
1152 .reg_type = ni_reg_628x,
1153 .ao_unipolar = 1,
1154 .ao_speed = 357,
1155 .num_p0_dio_channels = 8,
1156 .caldac = {caldac_none},
1157 .has_8255 = 0,
1158 },
1159 {
1160 .device_id = 0x70bc,
1161 .name = "pci-6284",
1162 .n_adchan = 32,
1163 .adbits = 18,
1164 .ai_fifo_depth = 2047,
1165 .gainlkup = ai_gain_628x,
1166 .ai_speed = 1600,
1167 .n_aochan = 0,
1168 .aobits = 0,
1169 .ao_fifo_depth = 0,
1170 .reg_type = ni_reg_628x,
1171 .ao_unipolar = 0,
1172 .num_p0_dio_channels = 32,
1173 .caldac = {caldac_none},
1174 .has_8255 = 0,
1175 },
1176 {
1177 .device_id = 0x70ac,
1178 .name = "pci-6289",
1179 .n_adchan = 32,
1180 .adbits = 18,
1181 .ai_fifo_depth = 2047,
1182 .gainlkup = ai_gain_628x,
1183 .ai_speed = 1600,
1184 .n_aochan = 4,
1185 .aobits = 16,
1186 .ao_fifo_depth = 8191,
1187 .ao_range_table = &range_ni_M_628x_ao,
1188 .reg_type = ni_reg_628x,
1189 .ao_unipolar = 1,
1190 .ao_speed = 357,
1191 .num_p0_dio_channels = 32,
1192 .caldac = {caldac_none},
1193 .has_8255 = 0,
1194 },
1195 {
1196 .device_id = 0x70C0,
1197 .name = "pci-6143",
1198 .n_adchan = 8,
1199 .adbits = 16,
1200 .ai_fifo_depth = 1024,
1201 .alwaysdither = 0,
1202 .gainlkup = ai_gain_6143,
1203 .ai_speed = 4000,
1204 .n_aochan = 0,
1205 .aobits = 0,
1206 .reg_type = ni_reg_6143,
1207 .ao_unipolar = 0,
1208 .ao_fifo_depth = 0,
1209 .num_p0_dio_channels = 8,
1210 .caldac = {ad8804_debug, ad8804_debug},
1211 },
1212 {
1213 .device_id = 0x710D,
1214 .name = "pxi-6143",
1215 .n_adchan = 8,
1216 .adbits = 16,
1217 .ai_fifo_depth = 1024,
1218 .alwaysdither = 0,
1219 .gainlkup = ai_gain_6143,
1220 .ai_speed = 4000,
1221 .n_aochan = 0,
1222 .aobits = 0,
1223 .reg_type = ni_reg_6143,
1224 .ao_unipolar = 0,
1225 .ao_fifo_depth = 0,
1226 .num_p0_dio_channels = 8,
1227 .caldac = {ad8804_debug, ad8804_debug},
1228 },
1229 };
1230
1231 #define n_pcimio_boards ARRAY_SIZE(ni_boards)
1232
1233 static int pcimio_attach(struct comedi_device *dev,
1234 struct comedi_devconfig *it);
1235 static int pcimio_detach(struct comedi_device *dev);
1236 static struct comedi_driver driver_pcimio = {
1237 .driver_name = DRV_NAME,
1238 .module = THIS_MODULE,
1239 .attach = pcimio_attach,
1240 .detach = pcimio_detach,
1241 };
1242
1243 COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table)
1244
1245 struct ni_private {
1246 NI_PRIVATE_COMMON};
1247 #define devpriv ((struct ni_private *)dev->private)
1248
1249 /* How we access registers */
1250
1251 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1252 #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1253 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1254 #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1255 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1256 #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1257
1258 /* How we access STC registers */
1259
1260 /* We automatically take advantage of STC registers that can be
1261 * read/written directly in the I/O space of the board. Most
1262 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1263 * The 611x devices map the write registers to iobase+addr*2, and
1264 * the read registers to iobase+(addr-1)*2. */
1265 /* However, the 611x boards still aren't working, so I'm disabling
1266 * non-windowed STC access temporarily */
1267
1268 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1269 {
1270 unsigned long flags;
1271
1272 spin_lock_irqsave(&devpriv->window_lock, flags);
1273 ni_writew(reg, Window_Address);
1274 ni_writew(data, Window_Data);
1275 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1276 }
1277
1278 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1279 {
1280 unsigned long flags;
1281 uint16_t ret;
1282
1283 spin_lock_irqsave(&devpriv->window_lock, flags);
1284 ni_writew(reg, Window_Address);
1285 ret = ni_readw(Window_Data);
1286 spin_unlock_irqrestore(&devpriv->window_lock, flags);
1287
1288 return ret;
1289 }
1290
1291 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1292 int reg)
1293 {
1294 unsigned offset;
1295 switch (reg) {
1296 case ADC_FIFO_Clear:
1297 offset = M_Offset_AI_FIFO_Clear;
1298 break;
1299 case AI_Command_1_Register:
1300 offset = M_Offset_AI_Command_1;
1301 break;
1302 case AI_Command_2_Register:
1303 offset = M_Offset_AI_Command_2;
1304 break;
1305 case AI_Mode_1_Register:
1306 offset = M_Offset_AI_Mode_1;
1307 break;
1308 case AI_Mode_2_Register:
1309 offset = M_Offset_AI_Mode_2;
1310 break;
1311 case AI_Mode_3_Register:
1312 offset = M_Offset_AI_Mode_3;
1313 break;
1314 case AI_Output_Control_Register:
1315 offset = M_Offset_AI_Output_Control;
1316 break;
1317 case AI_Personal_Register:
1318 offset = M_Offset_AI_Personal;
1319 break;
1320 case AI_SI2_Load_A_Register:
1321 /* this is actually a 32 bit register on m series boards */
1322 ni_writel(data, M_Offset_AI_SI2_Load_A);
1323 return;
1324 break;
1325 case AI_SI2_Load_B_Register:
1326 /* this is actually a 32 bit register on m series boards */
1327 ni_writel(data, M_Offset_AI_SI2_Load_B);
1328 return;
1329 break;
1330 case AI_START_STOP_Select_Register:
1331 offset = M_Offset_AI_START_STOP_Select;
1332 break;
1333 case AI_Trigger_Select_Register:
1334 offset = M_Offset_AI_Trigger_Select;
1335 break;
1336 case Analog_Trigger_Etc_Register:
1337 offset = M_Offset_Analog_Trigger_Etc;
1338 break;
1339 case AO_Command_1_Register:
1340 offset = M_Offset_AO_Command_1;
1341 break;
1342 case AO_Command_2_Register:
1343 offset = M_Offset_AO_Command_2;
1344 break;
1345 case AO_Mode_1_Register:
1346 offset = M_Offset_AO_Mode_1;
1347 break;
1348 case AO_Mode_2_Register:
1349 offset = M_Offset_AO_Mode_2;
1350 break;
1351 case AO_Mode_3_Register:
1352 offset = M_Offset_AO_Mode_3;
1353 break;
1354 case AO_Output_Control_Register:
1355 offset = M_Offset_AO_Output_Control;
1356 break;
1357 case AO_Personal_Register:
1358 offset = M_Offset_AO_Personal;
1359 break;
1360 case AO_Start_Select_Register:
1361 offset = M_Offset_AO_Start_Select;
1362 break;
1363 case AO_Trigger_Select_Register:
1364 offset = M_Offset_AO_Trigger_Select;
1365 break;
1366 case Clock_and_FOUT_Register:
1367 offset = M_Offset_Clock_and_FOUT;
1368 break;
1369 case Configuration_Memory_Clear:
1370 offset = M_Offset_Configuration_Memory_Clear;
1371 break;
1372 case DAC_FIFO_Clear:
1373 offset = M_Offset_AO_FIFO_Clear;
1374 break;
1375 case DIO_Control_Register:
1376 printk
1377 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1378 __func__, reg);
1379 return;
1380 break;
1381 case G_Autoincrement_Register(0):
1382 offset = M_Offset_G0_Autoincrement;
1383 break;
1384 case G_Autoincrement_Register(1):
1385 offset = M_Offset_G1_Autoincrement;
1386 break;
1387 case G_Command_Register(0):
1388 offset = M_Offset_G0_Command;
1389 break;
1390 case G_Command_Register(1):
1391 offset = M_Offset_G1_Command;
1392 break;
1393 case G_Input_Select_Register(0):
1394 offset = M_Offset_G0_Input_Select;
1395 break;
1396 case G_Input_Select_Register(1):
1397 offset = M_Offset_G1_Input_Select;
1398 break;
1399 case G_Mode_Register(0):
1400 offset = M_Offset_G0_Mode;
1401 break;
1402 case G_Mode_Register(1):
1403 offset = M_Offset_G1_Mode;
1404 break;
1405 case Interrupt_A_Ack_Register:
1406 offset = M_Offset_Interrupt_A_Ack;
1407 break;
1408 case Interrupt_A_Enable_Register:
1409 offset = M_Offset_Interrupt_A_Enable;
1410 break;
1411 case Interrupt_B_Ack_Register:
1412 offset = M_Offset_Interrupt_B_Ack;
1413 break;
1414 case Interrupt_B_Enable_Register:
1415 offset = M_Offset_Interrupt_B_Enable;
1416 break;
1417 case Interrupt_Control_Register:
1418 offset = M_Offset_Interrupt_Control;
1419 break;
1420 case IO_Bidirection_Pin_Register:
1421 offset = M_Offset_IO_Bidirection_Pin;
1422 break;
1423 case Joint_Reset_Register:
1424 offset = M_Offset_Joint_Reset;
1425 break;
1426 case RTSI_Trig_A_Output_Register:
1427 offset = M_Offset_RTSI_Trig_A_Output;
1428 break;
1429 case RTSI_Trig_B_Output_Register:
1430 offset = M_Offset_RTSI_Trig_B_Output;
1431 break;
1432 case RTSI_Trig_Direction_Register:
1433 offset = M_Offset_RTSI_Trig_Direction;
1434 break;
1435 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1436 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1437 default:
1438 printk("%s: bug! unhandled register=0x%x in switch.\n",
1439 __func__, reg);
1440 BUG();
1441 return;
1442 break;
1443 }
1444 ni_writew(data, offset);
1445 }
1446
1447 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1448 {
1449 unsigned offset;
1450 switch (reg) {
1451 case AI_Status_1_Register:
1452 offset = M_Offset_AI_Status_1;
1453 break;
1454 case AO_Status_1_Register:
1455 offset = M_Offset_AO_Status_1;
1456 break;
1457 case AO_Status_2_Register:
1458 offset = M_Offset_AO_Status_2;
1459 break;
1460 case DIO_Serial_Input_Register:
1461 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1462 break;
1463 case Joint_Status_1_Register:
1464 offset = M_Offset_Joint_Status_1;
1465 break;
1466 case Joint_Status_2_Register:
1467 offset = M_Offset_Joint_Status_2;
1468 break;
1469 case G_Status_Register:
1470 offset = M_Offset_G01_Status;
1471 break;
1472 default:
1473 printk("%s: bug! unhandled register=0x%x in switch.\n",
1474 __func__, reg);
1475 BUG();
1476 return 0;
1477 break;
1478 }
1479 return ni_readw(offset);
1480 }
1481
1482 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1483 int reg)
1484 {
1485 unsigned offset;
1486 switch (reg) {
1487 case AI_SC_Load_A_Registers:
1488 offset = M_Offset_AI_SC_Load_A;
1489 break;
1490 case AI_SI_Load_A_Registers:
1491 offset = M_Offset_AI_SI_Load_A;
1492 break;
1493 case AO_BC_Load_A_Register:
1494 offset = M_Offset_AO_BC_Load_A;
1495 break;
1496 case AO_UC_Load_A_Register:
1497 offset = M_Offset_AO_UC_Load_A;
1498 break;
1499 case AO_UI_Load_A_Register:
1500 offset = M_Offset_AO_UI_Load_A;
1501 break;
1502 case G_Load_A_Register(0):
1503 offset = M_Offset_G0_Load_A;
1504 break;
1505 case G_Load_A_Register(1):
1506 offset = M_Offset_G1_Load_A;
1507 break;
1508 case G_Load_B_Register(0):
1509 offset = M_Offset_G0_Load_B;
1510 break;
1511 case G_Load_B_Register(1):
1512 offset = M_Offset_G1_Load_B;
1513 break;
1514 default:
1515 printk("%s: bug! unhandled register=0x%x in switch.\n",
1516 __func__, reg);
1517 BUG();
1518 return;
1519 break;
1520 }
1521 ni_writel(data, offset);
1522 }
1523
1524 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1525 {
1526 unsigned offset;
1527 switch (reg) {
1528 case G_HW_Save_Register(0):
1529 offset = M_Offset_G0_HW_Save;
1530 break;
1531 case G_HW_Save_Register(1):
1532 offset = M_Offset_G1_HW_Save;
1533 break;
1534 case G_Save_Register(0):
1535 offset = M_Offset_G0_Save;
1536 break;
1537 case G_Save_Register(1):
1538 offset = M_Offset_G1_Save;
1539 break;
1540 default:
1541 printk("%s: bug! unhandled register=0x%x in switch.\n",
1542 __func__, reg);
1543 BUG();
1544 return 0;
1545 break;
1546 }
1547 return ni_readl(offset);
1548 }
1549
1550 #define interrupt_pin(a) 0
1551 #define IRQ_POLARITY 1
1552
1553 #define NI_E_IRQ_FLAGS IRQF_SHARED
1554
1555 #include "ni_mio_common.c"
1556
1557 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot);
1558 static int pcimio_ai_change(struct comedi_device *dev,
1559 struct comedi_subdevice *s, unsigned long new_size);
1560 static int pcimio_ao_change(struct comedi_device *dev,
1561 struct comedi_subdevice *s, unsigned long new_size);
1562 static int pcimio_gpct0_change(struct comedi_device *dev,
1563 struct comedi_subdevice *s,
1564 unsigned long new_size);
1565 static int pcimio_gpct1_change(struct comedi_device *dev,
1566 struct comedi_subdevice *s,
1567 unsigned long new_size);
1568 static int pcimio_dio_change(struct comedi_device *dev,
1569 struct comedi_subdevice *s,
1570 unsigned long new_size);
1571
1572 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1573 {
1574 static const int Start_Cal_EEPROM = 0x400;
1575 static const unsigned window_size = 10;
1576 static const int serial_number_eeprom_offset = 0x4;
1577 static const int serial_number_eeprom_length = 0x4;
1578 unsigned old_iodwbsr_bits;
1579 unsigned old_iodwbsr1_bits;
1580 unsigned old_iodwcr1_bits;
1581 int i;
1582
1583 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1584 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1585 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1586 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1587 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1588 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1589 writel(0x1 | old_iodwcr1_bits,
1590 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1591 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1592
1593 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1594 for (i = 0; i < serial_number_eeprom_length; ++i) {
1595 char *byte_ptr = (char *)&devpriv->serial_number + i;
1596 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1597 }
1598 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1599
1600 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1601 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1602 }
1603
1604 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1605 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1606 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1607 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1608 }
1609
1610 static void init_6143(struct comedi_device *dev)
1611 {
1612 /* Disable interrupts */
1613 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1614
1615 /* Initialise 6143 AI specific bits */
1616 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1617 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1618 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
1619
1620 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */
1621
1622 /* Strobe Relay disable bit */
1623 devpriv->ai_calib_source_enabled = 0;
1624 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1625 Calibration_Channel_6143);
1626 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1627 }
1628
1629 /* cleans up allocated resources */
1630 static int pcimio_detach(struct comedi_device *dev)
1631 {
1632 mio_common_detach(dev);
1633 if (dev->irq) {
1634 free_irq(dev->irq, dev);
1635 }
1636 if (dev->private) {
1637 mite_free_ring(devpriv->ai_mite_ring);
1638 mite_free_ring(devpriv->ao_mite_ring);
1639 mite_free_ring(devpriv->cdo_mite_ring);
1640 mite_free_ring(devpriv->gpct_mite_ring[0]);
1641 mite_free_ring(devpriv->gpct_mite_ring[1]);
1642 if (devpriv->mite)
1643 mite_unsetup(devpriv->mite);
1644 }
1645
1646 return 0;
1647 }
1648
1649 static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1650 {
1651 int ret;
1652
1653 printk("comedi%d: ni_pcimio:", dev->minor);
1654
1655 ret = ni_alloc_private(dev);
1656 if (ret < 0)
1657 return ret;
1658
1659 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1660 if (ret < 0)
1661 return ret;
1662
1663 printk(" %s", boardtype.name);
1664 dev->board_name = boardtype.name;
1665
1666 if (boardtype.reg_type & ni_reg_m_series_mask) {
1667 devpriv->stc_writew = &m_series_stc_writew;
1668 devpriv->stc_readw = &m_series_stc_readw;
1669 devpriv->stc_writel = &m_series_stc_writel;
1670 devpriv->stc_readl = &m_series_stc_readl;
1671 } else {
1672 devpriv->stc_writew = &e_series_win_out;
1673 devpriv->stc_readw = &e_series_win_in;
1674 devpriv->stc_writel = &win_out2;
1675 devpriv->stc_readl = &win_in2;
1676 }
1677
1678 ret = mite_setup(devpriv->mite);
1679 if (ret < 0) {
1680 printk(" error setting up mite\n");
1681 return ret;
1682 }
1683 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1684 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1685 if (devpriv->ai_mite_ring == NULL)
1686 return -ENOMEM;
1687 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1688 if (devpriv->ao_mite_ring == NULL)
1689 return -ENOMEM;
1690 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1691 if (devpriv->cdo_mite_ring == NULL)
1692 return -ENOMEM;
1693 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1694 if (devpriv->gpct_mite_ring[0] == NULL)
1695 return -ENOMEM;
1696 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1697 if (devpriv->gpct_mite_ring[1] == NULL)
1698 return -ENOMEM;
1699
1700 if (boardtype.reg_type & ni_reg_m_series_mask)
1701 m_series_init_eeprom_buffer(dev);
1702 if (boardtype.reg_type == ni_reg_6143)
1703 init_6143(dev);
1704
1705 dev->irq = mite_irq(devpriv->mite);
1706
1707 if (dev->irq == 0) {
1708 printk(" unknown irq (bad)\n");
1709 } else {
1710 printk(" ( irq = %u )", dev->irq);
1711 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1712 DRV_NAME, dev);
1713 if (ret < 0) {
1714 printk(" irq not available\n");
1715 dev->irq = 0;
1716 }
1717 }
1718
1719 ret = ni_E_init(dev, it);
1720 if (ret < 0)
1721 return ret;
1722
1723 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1724 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1725 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1726 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1727 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1728
1729 return ret;
1730 }
1731
1732 static int pcimio_find_device(struct comedi_device *dev, int bus, int slot)
1733 {
1734 struct mite_struct *mite;
1735 int i;
1736
1737 for (mite = mite_devices; mite; mite = mite->next) {
1738 if (mite->used)
1739 continue;
1740 if (bus || slot) {
1741 if (bus != mite->pcidev->bus->number ||
1742 slot != PCI_SLOT(mite->pcidev->devfn))
1743 continue;
1744 }
1745
1746 for (i = 0; i < n_pcimio_boards; i++) {
1747 if (mite_device_id(mite) == ni_boards[i].device_id) {
1748 dev->board_ptr = ni_boards + i;
1749 devpriv->mite = mite;
1750
1751 return 0;
1752 }
1753 }
1754 }
1755 printk("no device found\n");
1756 mite_list_devices();
1757 return -EIO;
1758 }
1759
1760 static int pcimio_ai_change(struct comedi_device *dev,
1761 struct comedi_subdevice *s, unsigned long new_size)
1762 {
1763 int ret;
1764
1765 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1766 if (ret < 0)
1767 return ret;
1768
1769 return 0;
1770 }
1771
1772 static int pcimio_ao_change(struct comedi_device *dev,
1773 struct comedi_subdevice *s, unsigned long new_size)
1774 {
1775 int ret;
1776
1777 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1778 if (ret < 0)
1779 return ret;
1780
1781 return 0;
1782 }
1783
1784 static int pcimio_gpct0_change(struct comedi_device *dev,
1785 struct comedi_subdevice *s,
1786 unsigned long new_size)
1787 {
1788 int ret;
1789
1790 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1791 if (ret < 0)
1792 return ret;
1793
1794 return 0;
1795 }
1796
1797 static int pcimio_gpct1_change(struct comedi_device *dev,
1798 struct comedi_subdevice *s,
1799 unsigned long new_size)
1800 {
1801 int ret;
1802
1803 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1804 if (ret < 0)
1805 return ret;
1806
1807 return 0;
1808 }
1809
1810 static int pcimio_dio_change(struct comedi_device *dev,
1811 struct comedi_subdevice *s, unsigned long new_size)
1812 {
1813 int ret;
1814
1815 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1816 if (ret < 0)
1817 return ret;
1818
1819 return 0;
1820 }
Support for the Chinese Samsung S3C2440 based development boards