3 * Most 8xx boards use the QSpan PCI bridge. The config address register
4 * is located 0x500 from the base of the bridge control/status registers.
5 * The data register is located at 0x504.
6 * This is a two step operation. First, the address register is written,
7 * then the data register is read/written as required.
8 * I don't know what to do about interrupts (yet).
10 * The RPX Classic implementation shares a chip select for normal
11 * PCI access and QSpan control register addresses. The selection is
12 * further selected by a bit setting in a board control register.
13 * Although it should happen, we disable interrupts during this operation
14 * to make sure some driver doesn't accidentally access the PCI while
15 * we have switched the chip select.
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
25 #include <asm/mpc8xx.h>
26 #include <asm/system.h>
27 #include <asm/machdep.h>
28 #include <asm/pci-bridge.h>
33 * When reading the configuration space, if something does not respond
34 * the bus times out and we get a machine check interrupt. So, the
35 * good ol' exception tables come to mind to trap it and return some
38 * On an error we just return a -1, since that is what the caller wants
39 * returned if nothing is present. I copied this from __get_user_asm,
40 * with the only difference of returning -1 instead of EFAULT.
41 * There is an associated hack in the machine check trap code.
43 * The QSPAN is also a big endian device, that is it makes the PCI
44 * look big endian to us. This presents a problem for the Linux PCI
45 * functions, which assume little endian. For example, we see the
46 * first 32-bit word like this:
47 * ------------------------
48 * | Device ID | Vendor ID |
49 * ------------------------
50 * If we read/write as a double word, that's OK. But in our world,
51 * when read as a word, device ID is at location 0, not location 2 as
52 * the little endian PCI would believe. We have to switch bits in
53 * the PCI addresses given to us to get the data to/from the correct
56 * The QSPAN only supports 4 bits of "slot" in the dev_fn instead of 5.
57 * It always forces the MS bit to zero. Therefore, dev_fn values
58 * greater than 128 are returned as "no device found" errors.
60 * The QSPAN can only perform long word (32-bit) configuration cycles.
61 * The "offset" must have the two LS bits set to zero. Read operations
62 * require we read the entire word and then sort out what should be
63 * returned. Write operations other than long word require that we
64 * read the long word, update the proper word or byte, then write the
65 * entire long word back.
67 * PCI Bridge hack. We assume (correctly) that bus 0 is the primary
68 * PCI bus from the QSPAN. If we are called with a bus number other
69 * than zero, we create a Type 1 configuration access that a downstream
70 * PCI bridge will interpret.
73 #define __get_qspan_pci_config(x, addr, op) \
74 __asm__ __volatile__( \
75 "1: "op" %0,0(%1)\n" \
78 ".section .fixup,\"ax\"\n" \
81 ".section __ex_table,\"a\"\n" \
85 : "=r"(x) : "r"(addr) : " %0")
87 #define QS_CONFIG_ADDR ((volatile uint *)(PCI_CSR_ADDR + 0x500))
88 #define QS_CONFIG_DATA ((volatile uint *)(PCI_CSR_ADDR + 0x504))
90 #define mk_config_addr(bus, dev, offset) \
91 (((bus)<<16) | ((dev)<<8) | (offset & 0xfc))
93 #define mk_config_type1(bus, dev, offset) \
94 mk_config_addr(bus, dev, offset) | 1;
96 static DEFINE_SPINLOCK(pcibios_lock
);
98 int qspan_pcibios_read_config_byte(unsigned char bus
, unsigned char dev_fn
,
99 unsigned char offset
, unsigned char *val
)
103 #ifdef CONFIG_RPXCLASSIC
107 if ((bus
> 7) || (dev_fn
> 127)) {
109 return PCIBIOS_DEVICE_NOT_FOUND
;
112 #ifdef CONFIG_RPXCLASSIC
113 /* disable interrupts */
114 spin_lock_irqsave(&pcibios_lock
, flags
);
115 *((uint
*)RPX_CSR_ADDR
) &= ~BCSR2_QSPACESEL
;
120 *QS_CONFIG_ADDR
= mk_config_addr(bus
, dev_fn
, offset
);
122 *QS_CONFIG_ADDR
= mk_config_type1(bus
, dev_fn
, offset
);
123 __get_qspan_pci_config(temp
, QS_CONFIG_DATA
, "lwz");
125 #ifdef CONFIG_RPXCLASSIC
126 *((uint
*)RPX_CSR_ADDR
) |= BCSR2_QSPACESEL
;
128 spin_unlock_irqrestore(&pcibios_lock
, flags
);
132 cp
= ((u_char
*)&temp
) + (offset
& 0x03);
134 return PCIBIOS_SUCCESSFUL
;
137 int qspan_pcibios_read_config_word(unsigned char bus
, unsigned char dev_fn
,
138 unsigned char offset
, unsigned short *val
)
142 #ifdef CONFIG_RPXCLASSIC
146 if ((bus
> 7) || (dev_fn
> 127)) {
148 return PCIBIOS_DEVICE_NOT_FOUND
;
151 #ifdef CONFIG_RPXCLASSIC
152 /* disable interrupts */
153 spin_lock_irqsave(&pcibios_lock
, flags
);
154 *((uint
*)RPX_CSR_ADDR
) &= ~BCSR2_QSPACESEL
;
159 *QS_CONFIG_ADDR
= mk_config_addr(bus
, dev_fn
, offset
);
161 *QS_CONFIG_ADDR
= mk_config_type1(bus
, dev_fn
, offset
);
162 __get_qspan_pci_config(temp
, QS_CONFIG_DATA
, "lwz");
165 #ifdef CONFIG_RPXCLASSIC
166 *((uint
*)RPX_CSR_ADDR
) |= BCSR2_QSPACESEL
;
168 spin_unlock_irqrestore(&pcibios_lock
, flags
);
171 sp
= ((ushort
*)&temp
) + ((offset
>> 1) & 1);
173 return PCIBIOS_SUCCESSFUL
;
176 int qspan_pcibios_read_config_dword(unsigned char bus
, unsigned char dev_fn
,
177 unsigned char offset
, unsigned int *val
)
179 #ifdef CONFIG_RPXCLASSIC
183 if ((bus
> 7) || (dev_fn
> 127)) {
185 return PCIBIOS_DEVICE_NOT_FOUND
;
188 #ifdef CONFIG_RPXCLASSIC
189 /* disable interrupts */
190 spin_lock_irqsave(&pcibios_lock
, flags
);
191 *((uint
*)RPX_CSR_ADDR
) &= ~BCSR2_QSPACESEL
;
196 *QS_CONFIG_ADDR
= mk_config_addr(bus
, dev_fn
, offset
);
198 *QS_CONFIG_ADDR
= mk_config_type1(bus
, dev_fn
, offset
);
199 __get_qspan_pci_config(*val
, QS_CONFIG_DATA
, "lwz");
201 #ifdef CONFIG_RPXCLASSIC
202 *((uint
*)RPX_CSR_ADDR
) |= BCSR2_QSPACESEL
;
204 spin_unlock_irqrestore(&pcibios_lock
, flags
);
207 return PCIBIOS_SUCCESSFUL
;
210 int qspan_pcibios_write_config_byte(unsigned char bus
, unsigned char dev_fn
,
211 unsigned char offset
, unsigned char val
)
215 #ifdef CONFIG_RPXCLASSIC
219 if ((bus
> 7) || (dev_fn
> 127))
220 return PCIBIOS_DEVICE_NOT_FOUND
;
222 qspan_pcibios_read_config_dword(bus
, dev_fn
, offset
, &temp
);
225 cp
= ((u_char
*)&temp
) + (offset
& 0x03);
228 #ifdef CONFIG_RPXCLASSIC
229 /* disable interrupts */
230 spin_lock_irqsave(&pcibios_lock
, flags
);
231 *((uint
*)RPX_CSR_ADDR
) &= ~BCSR2_QSPACESEL
;
236 *QS_CONFIG_ADDR
= mk_config_addr(bus
, dev_fn
, offset
);
238 *QS_CONFIG_ADDR
= mk_config_type1(bus
, dev_fn
, offset
);
239 *QS_CONFIG_DATA
= temp
;
241 #ifdef CONFIG_RPXCLASSIC
242 *((uint
*)RPX_CSR_ADDR
) |= BCSR2_QSPACESEL
;
244 spin_unlock_irqrestore(&pcibios_lock
, flags
);
247 return PCIBIOS_SUCCESSFUL
;
250 int qspan_pcibios_write_config_word(unsigned char bus
, unsigned char dev_fn
,
251 unsigned char offset
, unsigned short val
)
255 #ifdef CONFIG_RPXCLASSIC
259 if ((bus
> 7) || (dev_fn
> 127))
260 return PCIBIOS_DEVICE_NOT_FOUND
;
262 qspan_pcibios_read_config_dword(bus
, dev_fn
, offset
, &temp
);
265 sp
= ((ushort
*)&temp
) + ((offset
>> 1) & 1);
268 #ifdef CONFIG_RPXCLASSIC
269 /* disable interrupts */
270 spin_lock_irqsave(&pcibios_lock
, flags
);
271 *((uint
*)RPX_CSR_ADDR
) &= ~BCSR2_QSPACESEL
;
276 *QS_CONFIG_ADDR
= mk_config_addr(bus
, dev_fn
, offset
);
278 *QS_CONFIG_ADDR
= mk_config_type1(bus
, dev_fn
, offset
);
279 *QS_CONFIG_DATA
= temp
;
281 #ifdef CONFIG_RPXCLASSIC
282 *((uint
*)RPX_CSR_ADDR
) |= BCSR2_QSPACESEL
;
284 spin_unlock_irqrestore(&pcibios_lock
, flags
);
287 return PCIBIOS_SUCCESSFUL
;
290 int qspan_pcibios_write_config_dword(unsigned char bus
, unsigned char dev_fn
,
291 unsigned char offset
, unsigned int val
)
293 #ifdef CONFIG_RPXCLASSIC
297 if ((bus
> 7) || (dev_fn
> 127))
298 return PCIBIOS_DEVICE_NOT_FOUND
;
300 #ifdef CONFIG_RPXCLASSIC
301 /* disable interrupts */
302 spin_lock_irqsave(&pcibios_lock
, flags
);
303 *((uint
*)RPX_CSR_ADDR
) &= ~BCSR2_QSPACESEL
;
308 *QS_CONFIG_ADDR
= mk_config_addr(bus
, dev_fn
, offset
);
310 *QS_CONFIG_ADDR
= mk_config_type1(bus
, dev_fn
, offset
);
311 *(unsigned int *)QS_CONFIG_DATA
= val
;
313 #ifdef CONFIG_RPXCLASSIC
314 *((uint
*)RPX_CSR_ADDR
) |= BCSR2_QSPACESEL
;
316 spin_unlock_irqrestore(&pcibios_lock
, flags
);
319 return PCIBIOS_SUCCESSFUL
;
322 int qspan_pcibios_find_device(unsigned short vendor
, unsigned short dev_id
,
323 unsigned short index
, unsigned char *bus_ptr
,
324 unsigned char *dev_fn_ptr
)
327 unsigned int x
, vendev
;
329 if (vendor
== 0xffff)
330 return PCIBIOS_BAD_VENDOR_ID
;
331 vendev
= (dev_id
<< 16) + vendor
;
333 for (devfn
= 0; devfn
< 32; devfn
++) {
334 qspan_pcibios_read_config_dword(0, devfn
<<3, PCI_VENDOR_ID
, &x
);
338 *dev_fn_ptr
= devfn
<<3;
339 return PCIBIOS_SUCCESSFUL
;
344 return PCIBIOS_DEVICE_NOT_FOUND
;
347 int qspan_pcibios_find_class(unsigned int class_code
, unsigned short index
,
348 unsigned char *bus_ptr
, unsigned char *dev_fn_ptr
)
353 for (devnr
= 0; devnr
< 32; devnr
++) {
354 qspan_pcibios_read_config_dword(0, devnr
<<3, PCI_CLASS_REVISION
, &x
);
355 if ((x
>>8) == class_code
) {
358 *dev_fn_ptr
= devnr
<<3;
359 return PCIBIOS_SUCCESSFUL
;
364 return PCIBIOS_DEVICE_NOT_FOUND
;
368 m8xx_pcibios_fixup(void)
370 /* Lots to do here, all board and configuration specific. */
374 m8xx_setup_pci_ptrs(void)
376 set_config_access_method(qspan
);
378 ppc_md
.pcibios_fixup
= m8xx_pcibios_fixup
;