| blob | 9e8050ea1225fa05c002328203d76ca94d82f6dc |
1 /*
2 * arch/ppc64/kernel/head.S
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 *
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
13 *
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 *
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
24 */
26 #include <linux/config.h>
27 #include <linux/threads.h>
28 #include <asm/processor.h>
29 #include <asm/page.h>
30 #include <asm/mmu.h>
31 #include <asm/systemcfg.h>
32 #include <asm/ppc_asm.h>
33 #include <asm/asm-offsets.h>
34 #include <asm/bug.h>
35 #include <asm/cputable.h>
36 #include <asm/setup.h>
37 #include <asm/hvcall.h>
38 #include <asm/iseries/lpar_map.h>
39 #include <asm/thread_info.h>
41 #ifdef CONFIG_PPC_ISERIES
42 #define DO_SOFT_DISABLE
43 #endif
45 /*
46 * We layout physical memory as follows:
47 * 0x0000 - 0x00ff : Secondary processor spin code
48 * 0x0100 - 0x2fff : pSeries Interrupt prologs
49 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
50 * 0x6000 - 0x6fff : Initial (CPU0) segment table
51 * 0x7000 - 0x7fff : FWNMI data area
52 * 0x8000 - : Early init and support code
53 */
55 /*
56 * SPRG Usage
57 *
58 * Register Definition
59 *
60 * SPRG0 reserved for hypervisor
61 * SPRG1 temp - used to save gpr
62 * SPRG2 temp - used to save gpr
63 * SPRG3 virt addr of paca
64 */
66 /*
67 * Entering into this code we make the following assumptions:
68 * For pSeries:
69 * 1. The MMU is off & open firmware is running in real mode.
70 * 2. The kernel is entered at __start
71 *
72 * For iSeries:
73 * 1. The MMU is on (as it always is for iSeries)
74 * 2. The kernel is entered at system_reset_iSeries
75 */
77 .text
78 .globl _stext
79 _stext:
80 #ifdef CONFIG_PPC_MULTIPLATFORM
81 _GLOBAL(__start)
82 /* NOP this out unconditionally */
83 BEGIN_FTR_SECTION
84 b .__start_initialization_multiplatform
85 END_FTR_SECTION(0, 1)
86 #endif /* CONFIG_PPC_MULTIPLATFORM */
88 /* Catch branch to 0 in real mode */
89 trap
91 #ifdef CONFIG_PPC_ISERIES
92 /*
93 * At offset 0x20, there is a pointer to iSeries LPAR data.
94 * This is required by the hypervisor
95 */
96 . = 0x20
97 .llong hvReleaseData-KERNELBASE
99 /*
100 * At offset 0x28 and 0x30 are offsets to the mschunks_map
101 * array (used by the iSeries LPAR debugger to do translation
102 * between physical addresses and absolute addresses) and
103 * to the pidhash table (also used by the debugger)
104 */
105 .llong mschunks_map-KERNELBASE
106 .llong 0 /* pidhash-KERNELBASE SFRXXX */
108 /* Offset 0x38 - Pointer to start of embedded System.map */
109 .globl embedded_sysmap_start
110 embedded_sysmap_start:
111 .llong 0
112 /* Offset 0x40 - Pointer to end of embedded System.map */
113 .globl embedded_sysmap_end
114 embedded_sysmap_end:
115 .llong 0
117 #endif /* CONFIG_PPC_ISERIES */
119 /* Secondary processors spin on this value until it goes to 1. */
120 .globl __secondary_hold_spinloop
121 __secondary_hold_spinloop:
122 .llong 0x0
124 /* Secondary processors write this value with their cpu # */
125 /* after they enter the spin loop immediately below. */
126 .globl __secondary_hold_acknowledge
127 __secondary_hold_acknowledge:
128 .llong 0x0
130 . = 0x60
131 /*
132 * The following code is used on pSeries to hold secondary processors
133 * in a spin loop after they have been freed from OpenFirmware, but
134 * before the bulk of the kernel has been relocated. This code
135 * is relocated to physical address 0x60 before prom_init is run.
136 * All of it must fit below the first exception vector at 0x100.
137 */
138 _GLOBAL(__secondary_hold)
139 mfmsr r24
140 ori r24,r24,MSR_RI
141 mtmsrd r24 /* RI on */
143 /* Grab our linux cpu number */
144 mr r24,r3
146 /* Tell the master cpu we're here */
147 /* Relocation is off & we are located at an address less */
148 /* than 0x100, so only need to grab low order offset. */
149 std r24,__secondary_hold_acknowledge@l(0)
150 sync
152 /* All secondary cpus wait here until told to start. */
153 100: ld r4,__secondary_hold_spinloop@l(0)
154 cmpdi 0,r4,1
155 bne 100b
157 #ifdef CONFIG_HMT
158 b .hmt_init
159 #else
160 #ifdef CONFIG_SMP
161 mr r3,r24
162 b .pSeries_secondary_smp_init
163 #else
164 BUG_OPCODE
165 #endif
166 #endif
168 /* This value is used to mark exception frames on the stack. */
169 .section ".toc","aw"
170 exception_marker:
171 .tc ID_72656773_68657265[TC],0x7265677368657265
172 .text
174 /*
175 * The following macros define the code that appears as
176 * the prologue to each of the exception handlers. They
177 * are split into two parts to allow a single kernel binary
178 * to be used for pSeries and iSeries.
179 * LOL. One day... - paulus
180 */
182 /*
183 * We make as much of the exception code common between native
184 * exception handlers (including pSeries LPAR) and iSeries LPAR
185 * implementations as possible.
186 */
188 /*
189 * This is the start of the interrupt handlers for pSeries
190 * This code runs with relocation off.
191 */
192 #define EX_R9 0
193 #define EX_R10 8
194 #define EX_R11 16
195 #define EX_R12 24
196 #define EX_R13 32
197 #define EX_SRR0 40
198 #define EX_DAR 48
199 #define EX_DSISR 56
200 #define EX_CCR 60
201 #define EX_R3 64
202 #define EX_LR 72
204 #define EXCEPTION_PROLOG_PSERIES(area, label) \
205 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
206 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
207 std r10,area+EX_R10(r13); \
208 std r11,area+EX_R11(r13); \
209 std r12,area+EX_R12(r13); \
210 mfspr r9,SPRN_SPRG1; \
211 std r9,area+EX_R13(r13); \
212 mfcr r9; \
213 clrrdi r12,r13,32; /* get high part of &label */ \
214 mfmsr r10; \
215 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
216 ori r12,r12,(label)@l; /* virt addr of handler */ \
217 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
218 mtspr SPRN_SRR0,r12; \
219 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
220 mtspr SPRN_SRR1,r10; \
221 rfid; \
222 b . /* prevent speculative execution */
224 /*
225 * This is the start of the interrupt handlers for iSeries
226 * This code runs with relocation on.
227 */
228 #define EXCEPTION_PROLOG_ISERIES_1(area) \
229 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
230 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
231 std r10,area+EX_R10(r13); \
232 std r11,area+EX_R11(r13); \
233 std r12,area+EX_R12(r13); \
234 mfspr r9,SPRN_SPRG1; \
235 std r9,area+EX_R13(r13); \
236 mfcr r9
238 #define EXCEPTION_PROLOG_ISERIES_2 \
239 mfmsr r10; \
240 ld r11,PACALPPACA+LPPACASRR0(r13); \
241 ld r12,PACALPPACA+LPPACASRR1(r13); \
242 ori r10,r10,MSR_RI; \
243 mtmsrd r10,1
245 /*
246 * The common exception prolog is used for all except a few exceptions
247 * such as a segment miss on a kernel address. We have to be prepared
248 * to take another exception from the point where we first touch the
249 * kernel stack onwards.
250 *
251 * On entry r13 points to the paca, r9-r13 are saved in the paca,
252 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
253 * SRR1, and relocation is on.
254 */
255 #define EXCEPTION_PROLOG_COMMON(n, area) \
256 andi. r10,r12,MSR_PR; /* See if coming from user */ \
257 mr r10,r1; /* Save r1 */ \
258 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
259 beq- 1f; \
260 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
261 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
262 bge- cr1,bad_stack; /* abort if it is */ \
263 std r9,_CCR(r1); /* save CR in stackframe */ \
264 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
265 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
266 std r10,0(r1); /* make stack chain pointer */ \
267 std r0,GPR0(r1); /* save r0 in stackframe */ \
268 std r10,GPR1(r1); /* save r1 in stackframe */ \
269 std r2,GPR2(r1); /* save r2 in stackframe */ \
270 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
271 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
272 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
273 ld r10,area+EX_R10(r13); \
274 std r9,GPR9(r1); \
275 std r10,GPR10(r1); \
276 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
277 ld r10,area+EX_R12(r13); \
278 ld r11,area+EX_R13(r13); \
279 std r9,GPR11(r1); \
280 std r10,GPR12(r1); \
281 std r11,GPR13(r1); \
282 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
283 mflr r9; /* save LR in stackframe */ \
284 std r9,_LINK(r1); \
285 mfctr r10; /* save CTR in stackframe */ \
286 std r10,_CTR(r1); \
287 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
288 std r11,_XER(r1); \
289 li r9,(n)+1; \
290 std r9,_TRAP(r1); /* set trap number */ \
291 li r10,0; \
292 ld r11,exception_marker@toc(r2); \
293 std r10,RESULT(r1); /* clear regs->result */ \
294 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
296 /*
297 * Exception vectors.
298 */
299 #define STD_EXCEPTION_PSERIES(n, label) \
300 . = n; \
301 .globl label##_pSeries; \
302 label##_pSeries: \
303 HMT_MEDIUM; \
304 mtspr SPRN_SPRG1,r13; /* save r13 */ \
305 RUNLATCH_ON(r13); \
306 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
308 #define STD_EXCEPTION_ISERIES(n, label, area) \
309 .globl label##_iSeries; \
310 label##_iSeries: \
311 HMT_MEDIUM; \
312 mtspr SPRN_SPRG1,r13; /* save r13 */ \
313 RUNLATCH_ON(r13); \
314 EXCEPTION_PROLOG_ISERIES_1(area); \
315 EXCEPTION_PROLOG_ISERIES_2; \
316 b label##_common
318 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
319 .globl label##_iSeries; \
320 label##_iSeries: \
321 HMT_MEDIUM; \
322 mtspr SPRN_SPRG1,r13; /* save r13 */ \
323 RUNLATCH_ON(r13); \
324 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
325 lbz r10,PACAPROCENABLED(r13); \
326 cmpwi 0,r10,0; \
327 beq- label##_iSeries_masked; \
328 EXCEPTION_PROLOG_ISERIES_2; \
329 b label##_common; \
331 #ifdef DO_SOFT_DISABLE
332 #define DISABLE_INTS \
333 lbz r10,PACAPROCENABLED(r13); \
334 li r11,0; \
335 std r10,SOFTE(r1); \
336 mfmsr r10; \
337 stb r11,PACAPROCENABLED(r13); \
338 ori r10,r10,MSR_EE; \
339 mtmsrd r10,1
341 #define ENABLE_INTS \
342 lbz r10,PACAPROCENABLED(r13); \
343 mfmsr r11; \
344 std r10,SOFTE(r1); \
345 ori r11,r11,MSR_EE; \
346 mtmsrd r11,1
348 #else /* hard enable/disable interrupts */
349 #define DISABLE_INTS
351 #define ENABLE_INTS \
352 ld r12,_MSR(r1); \
353 mfmsr r11; \
354 rlwimi r11,r12,0,MSR_EE; \
355 mtmsrd r11,1
357 #endif
359 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
360 .align 7; \
361 .globl label##_common; \
362 label##_common: \
363 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
364 DISABLE_INTS; \
365 bl .save_nvgprs; \
366 addi r3,r1,STACK_FRAME_OVERHEAD; \
367 bl hdlr; \
368 b .ret_from_except
370 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
371 .align 7; \
372 .globl label##_common; \
373 label##_common: \
374 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
375 DISABLE_INTS; \
376 addi r3,r1,STACK_FRAME_OVERHEAD; \
377 bl hdlr; \
378 b .ret_from_except_lite
380 /*
381 * Start of pSeries system interrupt routines
382 */
383 . = 0x100
384 .globl __start_interrupts
385 __start_interrupts:
387 STD_EXCEPTION_PSERIES(0x100, system_reset)
389 . = 0x200
390 _machine_check_pSeries:
391 HMT_MEDIUM
392 mtspr SPRN_SPRG1,r13 /* save r13 */
393 RUNLATCH_ON(r13)
394 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
396 . = 0x300
397 .globl data_access_pSeries
398 data_access_pSeries:
399 HMT_MEDIUM
400 mtspr SPRN_SPRG1,r13
401 BEGIN_FTR_SECTION
402 mtspr SPRN_SPRG2,r12
403 mfspr r13,SPRN_DAR
404 mfspr r12,SPRN_DSISR
405 srdi r13,r13,60
406 rlwimi r13,r12,16,0x20
407 mfcr r12
408 cmpwi r13,0x2c
409 beq .do_stab_bolted_pSeries
410 mtcrf 0x80,r12
411 mfspr r12,SPRN_SPRG2
412 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
413 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
415 . = 0x380
416 .globl data_access_slb_pSeries
417 data_access_slb_pSeries:
418 HMT_MEDIUM
419 mtspr SPRN_SPRG1,r13
420 RUNLATCH_ON(r13)
421 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
422 std r3,PACA_EXSLB+EX_R3(r13)
423 mfspr r3,SPRN_DAR
424 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
425 mfcr r9
426 #ifdef __DISABLED__
427 /* Keep that around for when we re-implement dynamic VSIDs */
428 cmpdi r3,0
429 bge slb_miss_user_pseries
430 #endif /* __DISABLED__ */
431 std r10,PACA_EXSLB+EX_R10(r13)
432 std r11,PACA_EXSLB+EX_R11(r13)
433 std r12,PACA_EXSLB+EX_R12(r13)
434 mfspr r10,SPRN_SPRG1
435 std r10,PACA_EXSLB+EX_R13(r13)
436 mfspr r12,SPRN_SRR1 /* and SRR1 */
437 b .slb_miss_realmode /* Rel. branch works in real mode */
439 STD_EXCEPTION_PSERIES(0x400, instruction_access)
441 . = 0x480
442 .globl instruction_access_slb_pSeries
443 instruction_access_slb_pSeries:
444 HMT_MEDIUM
445 mtspr SPRN_SPRG1,r13
446 RUNLATCH_ON(r13)
447 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
448 std r3,PACA_EXSLB+EX_R3(r13)
449 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
450 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
451 mfcr r9
452 #ifdef __DISABLED__
453 /* Keep that around for when we re-implement dynamic VSIDs */
454 cmpdi r3,0
455 bge slb_miss_user_pseries
456 #endif /* __DISABLED__ */
457 std r10,PACA_EXSLB+EX_R10(r13)
458 std r11,PACA_EXSLB+EX_R11(r13)
459 std r12,PACA_EXSLB+EX_R12(r13)
460 mfspr r10,SPRN_SPRG1
461 std r10,PACA_EXSLB+EX_R13(r13)
462 mfspr r12,SPRN_SRR1 /* and SRR1 */
463 b .slb_miss_realmode /* Rel. branch works in real mode */
465 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
466 STD_EXCEPTION_PSERIES(0x600, alignment)
467 STD_EXCEPTION_PSERIES(0x700, program_check)
468 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
469 STD_EXCEPTION_PSERIES(0x900, decrementer)
470 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
471 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
473 . = 0xc00
474 .globl system_call_pSeries
475 system_call_pSeries:
476 HMT_MEDIUM
477 RUNLATCH_ON(r9)
478 mr r9,r13
479 mfmsr r10
480 mfspr r13,SPRN_SPRG3
481 mfspr r11,SPRN_SRR0
482 clrrdi r12,r13,32
483 oris r12,r12,system_call_common@h
484 ori r12,r12,system_call_common@l
485 mtspr SPRN_SRR0,r12
486 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
487 mfspr r12,SPRN_SRR1
488 mtspr SPRN_SRR1,r10
489 rfid
490 b . /* prevent speculative execution */
492 STD_EXCEPTION_PSERIES(0xd00, single_step)
493 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
495 /* We need to deal with the Altivec unavailable exception
496 * here which is at 0xf20, thus in the middle of the
497 * prolog code of the PerformanceMonitor one. A little
498 * trickery is thus necessary
499 */
500 . = 0xf00
501 b performance_monitor_pSeries
503 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
505 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
506 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
508 . = 0x3000
510 /*** pSeries interrupt support ***/
512 /* moved from 0xf00 */
513 STD_EXCEPTION_PSERIES(., performance_monitor)
515 .align 7
516 _GLOBAL(do_stab_bolted_pSeries)
517 mtcrf 0x80,r12
518 mfspr r12,SPRN_SPRG2
519 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
521 /*
522 * We have some room here we use that to put
523 * the peries slb miss user trampoline code so it's reasonably
524 * away from slb_miss_user_common to avoid problems with rfid
525 *
526 * This is used for when the SLB miss handler has to go virtual,
527 * which doesn't happen for now anymore but will once we re-implement
528 * dynamic VSIDs for shared page tables
529 */
530 #ifdef __DISABLED__
531 slb_miss_user_pseries:
532 std r10,PACA_EXGEN+EX_R10(r13)
533 std r11,PACA_EXGEN+EX_R11(r13)
534 std r12,PACA_EXGEN+EX_R12(r13)
535 mfspr r10,SPRG1
536 ld r11,PACA_EXSLB+EX_R9(r13)
537 ld r12,PACA_EXSLB+EX_R3(r13)
538 std r10,PACA_EXGEN+EX_R13(r13)
539 std r11,PACA_EXGEN+EX_R9(r13)
540 std r12,PACA_EXGEN+EX_R3(r13)
541 clrrdi r12,r13,32
542 mfmsr r10
543 mfspr r11,SRR0 /* save SRR0 */
544 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
545 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
546 mtspr SRR0,r12
547 mfspr r12,SRR1 /* and SRR1 */
548 mtspr SRR1,r10
549 rfid
550 b . /* prevent spec. execution */
551 #endif /* __DISABLED__ */
553 /*
554 * Vectors for the FWNMI option. Share common code.
555 */
556 .globl system_reset_fwnmi
557 system_reset_fwnmi:
558 HMT_MEDIUM
559 mtspr SPRN_SPRG1,r13 /* save r13 */
560 RUNLATCH_ON(r13)
561 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
563 .globl machine_check_fwnmi
564 machine_check_fwnmi:
565 HMT_MEDIUM
566 mtspr SPRN_SPRG1,r13 /* save r13 */
567 RUNLATCH_ON(r13)
568 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
570 #ifdef CONFIG_PPC_ISERIES
571 /*** ISeries-LPAR interrupt handlers ***/
573 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
575 .globl data_access_iSeries
576 data_access_iSeries:
577 mtspr SPRN_SPRG1,r13
578 BEGIN_FTR_SECTION
579 mtspr SPRN_SPRG2,r12
580 mfspr r13,SPRN_DAR
581 mfspr r12,SPRN_DSISR
582 srdi r13,r13,60
583 rlwimi r13,r12,16,0x20
584 mfcr r12
585 cmpwi r13,0x2c
586 beq .do_stab_bolted_iSeries
587 mtcrf 0x80,r12
588 mfspr r12,SPRN_SPRG2
589 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
590 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
591 EXCEPTION_PROLOG_ISERIES_2
592 b data_access_common
594 .do_stab_bolted_iSeries:
595 mtcrf 0x80,r12
596 mfspr r12,SPRN_SPRG2
597 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
598 EXCEPTION_PROLOG_ISERIES_2
599 b .do_stab_bolted
601 .globl data_access_slb_iSeries
602 data_access_slb_iSeries:
603 mtspr SPRN_SPRG1,r13 /* save r13 */
604 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
605 std r3,PACA_EXSLB+EX_R3(r13)
606 mfspr r3,SPRN_DAR
607 std r9,PACA_EXSLB+EX_R9(r13)
608 mfcr r9
609 #ifdef __DISABLED__
610 cmpdi r3,0
611 bge slb_miss_user_iseries
612 #endif
613 std r10,PACA_EXSLB+EX_R10(r13)
614 std r11,PACA_EXSLB+EX_R11(r13)
615 std r12,PACA_EXSLB+EX_R12(r13)
616 mfspr r10,SPRN_SPRG1
617 std r10,PACA_EXSLB+EX_R13(r13)
618 ld r12,PACALPPACA+LPPACASRR1(r13);
619 b .slb_miss_realmode
621 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
623 .globl instruction_access_slb_iSeries
624 instruction_access_slb_iSeries:
625 mtspr SPRN_SPRG1,r13 /* save r13 */
626 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
627 std r3,PACA_EXSLB+EX_R3(r13)
628 ld r3,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
629 std r9,PACA_EXSLB+EX_R9(r13)
630 mfcr r9
631 #ifdef __DISABLED__
632 cmpdi r3,0
633 bge .slb_miss_user_iseries
634 #endif
635 std r10,PACA_EXSLB+EX_R10(r13)
636 std r11,PACA_EXSLB+EX_R11(r13)
637 std r12,PACA_EXSLB+EX_R12(r13)
638 mfspr r10,SPRN_SPRG1
639 std r10,PACA_EXSLB+EX_R13(r13)
640 ld r12,PACALPPACA+LPPACASRR1(r13);
641 b .slb_miss_realmode
643 #ifdef __DISABLED__
644 slb_miss_user_iseries:
645 std r10,PACA_EXGEN+EX_R10(r13)
646 std r11,PACA_EXGEN+EX_R11(r13)
647 std r12,PACA_EXGEN+EX_R12(r13)
648 mfspr r10,SPRG1
649 ld r11,PACA_EXSLB+EX_R9(r13)
650 ld r12,PACA_EXSLB+EX_R3(r13)
651 std r10,PACA_EXGEN+EX_R13(r13)
652 std r11,PACA_EXGEN+EX_R9(r13)
653 std r12,PACA_EXGEN+EX_R3(r13)
654 EXCEPTION_PROLOG_ISERIES_2
655 b slb_miss_user_common
656 #endif
658 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
659 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
660 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
661 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
662 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
663 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
664 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
666 .globl system_call_iSeries
667 system_call_iSeries:
668 mr r9,r13
669 mfspr r13,SPRN_SPRG3
670 EXCEPTION_PROLOG_ISERIES_2
671 b system_call_common
673 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
674 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
675 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
677 .globl system_reset_iSeries
678 system_reset_iSeries:
679 mfspr r13,SPRN_SPRG3 /* Get paca address */
680 mfmsr r24
681 ori r24,r24,MSR_RI
682 mtmsrd r24 /* RI on */
683 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
684 cmpwi 0,r24,0 /* Are we processor 0? */
685 beq .__start_initialization_iSeries /* Start up the first processor */
686 mfspr r4,SPRN_CTRLF
687 li r5,CTRL_RUNLATCH /* Turn off the run light */
688 andc r4,r4,r5
689 mtspr SPRN_CTRLT,r4
691 1:
692 HMT_LOW
693 #ifdef CONFIG_SMP
694 lbz r23,PACAPROCSTART(r13) /* Test if this processor
695 * should start */
696 sync
697 LOADADDR(r3,current_set)
698 sldi r28,r24,3 /* get current_set[cpu#] */
699 ldx r3,r3,r28
700 addi r1,r3,THREAD_SIZE
701 subi r1,r1,STACK_FRAME_OVERHEAD
703 cmpwi 0,r23,0
704 beq iSeries_secondary_smp_loop /* Loop until told to go */
705 bne .__secondary_start /* Loop until told to go */
706 iSeries_secondary_smp_loop:
707 /* Let the Hypervisor know we are alive */
708 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
709 lis r3,0x8002
710 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
711 #else /* CONFIG_SMP */
712 /* Yield the processor. This is required for non-SMP kernels
713 which are running on multi-threaded machines. */
714 lis r3,0x8000
715 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
716 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
717 li r4,0 /* "yield timed" */
718 li r5,-1 /* "yield forever" */
719 #endif /* CONFIG_SMP */
720 li r0,-1 /* r0=-1 indicates a Hypervisor call */
721 sc /* Invoke the hypervisor via a system call */
722 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
723 b 1b /* If SMP not configured, secondaries
724 * loop forever */
726 .globl decrementer_iSeries_masked
727 decrementer_iSeries_masked:
728 li r11,1
729 stb r11,PACALPPACA+LPPACADECRINT(r13)
730 lwz r12,PACADEFAULTDECR(r13)
731 mtspr SPRN_DEC,r12
732 /* fall through */
734 .globl hardware_interrupt_iSeries_masked
735 hardware_interrupt_iSeries_masked:
736 mtcrf 0x80,r9 /* Restore regs */
737 ld r11,PACALPPACA+LPPACASRR0(r13)
738 ld r12,PACALPPACA+LPPACASRR1(r13)
739 mtspr SPRN_SRR0,r11
740 mtspr SPRN_SRR1,r12
741 ld r9,PACA_EXGEN+EX_R9(r13)
742 ld r10,PACA_EXGEN+EX_R10(r13)
743 ld r11,PACA_EXGEN+EX_R11(r13)
744 ld r12,PACA_EXGEN+EX_R12(r13)
745 ld r13,PACA_EXGEN+EX_R13(r13)
746 rfid
747 b . /* prevent speculative execution */
748 #endif /* CONFIG_PPC_ISERIES */
750 /*** Common interrupt handlers ***/
752 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
754 /*
755 * Machine check is different because we use a different
756 * save area: PACA_EXMC instead of PACA_EXGEN.
757 */
758 .align 7
759 .globl machine_check_common
760 machine_check_common:
761 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
762 DISABLE_INTS
763 bl .save_nvgprs
764 addi r3,r1,STACK_FRAME_OVERHEAD
765 bl .machine_check_exception
766 b .ret_from_except
768 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
769 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
770 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
771 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
772 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
773 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
774 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
775 #ifdef CONFIG_ALTIVEC
776 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
777 #else
778 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
779 #endif
781 /*
782 * Here we have detected that the kernel stack pointer is bad.
783 * R9 contains the saved CR, r13 points to the paca,
784 * r10 contains the (bad) kernel stack pointer,
785 * r11 and r12 contain the saved SRR0 and SRR1.
786 * We switch to using an emergency stack, save the registers there,
787 * and call kernel_bad_stack(), which panics.
788 */
789 bad_stack:
790 ld r1,PACAEMERGSP(r13)
791 subi r1,r1,64+INT_FRAME_SIZE
792 std r9,_CCR(r1)
793 std r10,GPR1(r1)
794 std r11,_NIP(r1)
795 std r12,_MSR(r1)
796 mfspr r11,SPRN_DAR
797 mfspr r12,SPRN_DSISR
798 std r11,_DAR(r1)
799 std r12,_DSISR(r1)
800 mflr r10
801 mfctr r11
802 mfxer r12
803 std r10,_LINK(r1)
804 std r11,_CTR(r1)
805 std r12,_XER(r1)
806 SAVE_GPR(0,r1)
807 SAVE_GPR(2,r1)
808 SAVE_4GPRS(3,r1)
809 SAVE_2GPRS(7,r1)
810 SAVE_10GPRS(12,r1)
811 SAVE_10GPRS(22,r1)
812 addi r11,r1,INT_FRAME_SIZE
813 std r11,0(r1)
814 li r12,0
815 std r12,0(r11)
816 ld r2,PACATOC(r13)
817 1: addi r3,r1,STACK_FRAME_OVERHEAD
818 bl .kernel_bad_stack
819 b 1b
821 /*
822 * Return from an exception with minimal checks.
823 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
824 * If interrupts have been enabled, or anything has been
825 * done that might have changed the scheduling status of
826 * any task or sent any task a signal, you should use
827 * ret_from_except or ret_from_except_lite instead of this.
828 */
829 .globl fast_exception_return
830 fast_exception_return:
831 ld r12,_MSR(r1)
832 ld r11,_NIP(r1)
833 andi. r3,r12,MSR_RI /* check if RI is set */
834 beq- unrecov_fer
835 ld r3,_CCR(r1)
836 ld r4,_LINK(r1)
837 ld r5,_CTR(r1)
838 ld r6,_XER(r1)
839 mtcr r3
840 mtlr r4
841 mtctr r5
842 mtxer r6
843 REST_GPR(0, r1)
844 REST_8GPRS(2, r1)
846 mfmsr r10
847 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
848 mtmsrd r10,1
850 mtspr SPRN_SRR1,r12
851 mtspr SPRN_SRR0,r11
852 REST_4GPRS(10, r1)
853 ld r1,GPR1(r1)
854 rfid
855 b . /* prevent speculative execution */
857 unrecov_fer:
858 bl .save_nvgprs
859 1: addi r3,r1,STACK_FRAME_OVERHEAD
860 bl .unrecoverable_exception
861 b 1b
863 /*
864 * Here r13 points to the paca, r9 contains the saved CR,
865 * SRR0 and SRR1 are saved in r11 and r12,
866 * r9 - r13 are saved in paca->exgen.
867 */
868 .align 7
869 .globl data_access_common
870 data_access_common:
871 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
872 mfspr r10,SPRN_DAR
873 std r10,PACA_EXGEN+EX_DAR(r13)
874 mfspr r10,SPRN_DSISR
875 stw r10,PACA_EXGEN+EX_DSISR(r13)
876 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
877 ld r3,PACA_EXGEN+EX_DAR(r13)
878 lwz r4,PACA_EXGEN+EX_DSISR(r13)
879 li r5,0x300
880 b .do_hash_page /* Try to handle as hpte fault */
882 .align 7
883 .globl instruction_access_common
884 instruction_access_common:
885 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
886 ld r3,_NIP(r1)
887 andis. r4,r12,0x5820
888 li r5,0x400
889 b .do_hash_page /* Try to handle as hpte fault */
891 /*
892 * Here is the common SLB miss user that is used when going to virtual
893 * mode for SLB misses, that is currently not used
894 */
895 #ifdef __DISABLED__
896 .align 7
897 .globl slb_miss_user_common
898 slb_miss_user_common:
899 mflr r10
900 std r3,PACA_EXGEN+EX_DAR(r13)
901 stw r9,PACA_EXGEN+EX_CCR(r13)
902 std r10,PACA_EXGEN+EX_LR(r13)
903 std r11,PACA_EXGEN+EX_SRR0(r13)
904 bl .slb_allocate_user
906 ld r10,PACA_EXGEN+EX_LR(r13)
907 ld r3,PACA_EXGEN+EX_R3(r13)
908 lwz r9,PACA_EXGEN+EX_CCR(r13)
909 ld r11,PACA_EXGEN+EX_SRR0(r13)
910 mtlr r10
911 beq- slb_miss_fault
913 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
914 beq- unrecov_user_slb
915 mfmsr r10
917 .machine push
918 .machine "power4"
919 mtcrf 0x80,r9
920 .machine pop
922 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
923 mtmsrd r10,1
925 mtspr SRR0,r11
926 mtspr SRR1,r12
928 ld r9,PACA_EXGEN+EX_R9(r13)
929 ld r10,PACA_EXGEN+EX_R10(r13)
930 ld r11,PACA_EXGEN+EX_R11(r13)
931 ld r12,PACA_EXGEN+EX_R12(r13)
932 ld r13,PACA_EXGEN+EX_R13(r13)
933 rfid
934 b .
936 slb_miss_fault:
937 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
938 ld r4,PACA_EXGEN+EX_DAR(r13)
939 li r5,0
940 std r4,_DAR(r1)
941 std r5,_DSISR(r1)
942 b .handle_page_fault
944 unrecov_user_slb:
945 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
946 DISABLE_INTS
947 bl .save_nvgprs
948 1: addi r3,r1,STACK_FRAME_OVERHEAD
949 bl .unrecoverable_exception
950 b 1b
952 #endif /* __DISABLED__ */
955 /*
956 * r13 points to the PACA, r9 contains the saved CR,
957 * r12 contain the saved SRR1, SRR0 is still ready for return
958 * r3 has the faulting address
959 * r9 - r13 are saved in paca->exslb.
960 * r3 is saved in paca->slb_r3
961 * We assume we aren't going to take any exceptions during this procedure.
962 */
963 _GLOBAL(slb_miss_realmode)
964 mflr r10
966 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
967 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
969 bl .slb_allocate_realmode
971 /* All done -- return from exception. */
973 ld r10,PACA_EXSLB+EX_LR(r13)
974 ld r3,PACA_EXSLB+EX_R3(r13)
975 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
976 #ifdef CONFIG_PPC_ISERIES
977 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
978 #endif /* CONFIG_PPC_ISERIES */
980 mtlr r10
982 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
983 beq- unrecov_slb
985 .machine push
986 .machine "power4"
987 mtcrf 0x80,r9
988 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
989 .machine pop
991 #ifdef CONFIG_PPC_ISERIES
992 mtspr SPRN_SRR0,r11
993 mtspr SPRN_SRR1,r12
994 #endif /* CONFIG_PPC_ISERIES */
995 ld r9,PACA_EXSLB+EX_R9(r13)
996 ld r10,PACA_EXSLB+EX_R10(r13)
997 ld r11,PACA_EXSLB+EX_R11(r13)
998 ld r12,PACA_EXSLB+EX_R12(r13)
999 ld r13,PACA_EXSLB+EX_R13(r13)
1000 rfid
1001 b . /* prevent speculative execution */
1003 unrecov_slb:
1004 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1005 DISABLE_INTS
1006 bl .save_nvgprs
1007 1: addi r3,r1,STACK_FRAME_OVERHEAD
1008 bl .unrecoverable_exception
1009 b 1b
1011 .align 7
1012 .globl hardware_interrupt_common
1013 .globl hardware_interrupt_entry
1014 hardware_interrupt_common:
1015 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1016 hardware_interrupt_entry:
1017 DISABLE_INTS
1018 addi r3,r1,STACK_FRAME_OVERHEAD
1019 bl .do_IRQ
1020 b .ret_from_except_lite
1022 .align 7
1023 .globl alignment_common
1024 alignment_common:
1025 mfspr r10,SPRN_DAR
1026 std r10,PACA_EXGEN+EX_DAR(r13)
1027 mfspr r10,SPRN_DSISR
1028 stw r10,PACA_EXGEN+EX_DSISR(r13)
1029 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1030 ld r3,PACA_EXGEN+EX_DAR(r13)
1031 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1032 std r3,_DAR(r1)
1033 std r4,_DSISR(r1)
1034 bl .save_nvgprs
1035 addi r3,r1,STACK_FRAME_OVERHEAD
1036 ENABLE_INTS
1037 bl .alignment_exception
1038 b .ret_from_except
1040 .align 7
1041 .globl program_check_common
1042 program_check_common:
1043 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1044 bl .save_nvgprs
1045 addi r3,r1,STACK_FRAME_OVERHEAD
1046 ENABLE_INTS
1047 bl .program_check_exception
1048 b .ret_from_except
1050 .align 7
1051 .globl fp_unavailable_common
1052 fp_unavailable_common:
1053 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1054 bne .load_up_fpu /* if from user, just load it up */
1055 bl .save_nvgprs
1056 addi r3,r1,STACK_FRAME_OVERHEAD
1057 ENABLE_INTS
1058 bl .kernel_fp_unavailable_exception
1059 BUG_OPCODE
1061 .align 7
1062 .globl altivec_unavailable_common
1063 altivec_unavailable_common:
1064 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1065 #ifdef CONFIG_ALTIVEC
1066 BEGIN_FTR_SECTION
1067 bne .load_up_altivec /* if from user, just load it up */
1068 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1069 #endif
1070 bl .save_nvgprs
1071 addi r3,r1,STACK_FRAME_OVERHEAD
1072 ENABLE_INTS
1073 bl .altivec_unavailable_exception
1074 b .ret_from_except
1076 #ifdef CONFIG_ALTIVEC
1077 /*
1078 * load_up_altivec(unused, unused, tsk)
1079 * Disable VMX for the task which had it previously,
1080 * and save its vector registers in its thread_struct.
1081 * Enables the VMX for use in the kernel on return.
1082 * On SMP we know the VMX is free, since we give it up every
1083 * switch (ie, no lazy save of the vector registers).
1084 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1085 */
1086 _STATIC(load_up_altivec)
1087 mfmsr r5 /* grab the current MSR */
1088 oris r5,r5,MSR_VEC@h
1089 mtmsrd r5 /* enable use of VMX now */
1090 isync
1092 /*
1093 * For SMP, we don't do lazy VMX switching because it just gets too
1094 * horrendously complex, especially when a task switches from one CPU
1095 * to another. Instead we call giveup_altvec in switch_to.
1096 * VRSAVE isn't dealt with here, that is done in the normal context
1097 * switch code. Note that we could rely on vrsave value to eventually
1098 * avoid saving all of the VREGs here...
1099 */
1100 #ifndef CONFIG_SMP
1101 ld r3,last_task_used_altivec@got(r2)
1102 ld r4,0(r3)
1103 cmpdi 0,r4,0
1104 beq 1f
1105 /* Save VMX state to last_task_used_altivec's THREAD struct */
1106 addi r4,r4,THREAD
1107 SAVE_32VRS(0,r5,r4)
1108 mfvscr vr0
1109 li r10,THREAD_VSCR
1110 stvx vr0,r10,r4
1111 /* Disable VMX for last_task_used_altivec */
1112 ld r5,PT_REGS(r4)
1113 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1114 lis r6,MSR_VEC@h
1115 andc r4,r4,r6
1116 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1117 1:
1118 #endif /* CONFIG_SMP */
1119 /* Hack: if we get an altivec unavailable trap with VRSAVE
1120 * set to all zeros, we assume this is a broken application
1121 * that fails to set it properly, and thus we switch it to
1122 * all 1's
1123 */
1124 mfspr r4,SPRN_VRSAVE
1125 cmpdi 0,r4,0
1126 bne+ 1f
1127 li r4,-1
1128 mtspr SPRN_VRSAVE,r4
1129 1:
1130 /* enable use of VMX after return */
1131 ld r4,PACACURRENT(r13)
1132 addi r5,r4,THREAD /* Get THREAD */
1133 oris r12,r12,MSR_VEC@h
1134 std r12,_MSR(r1)
1135 li r4,1
1136 li r10,THREAD_VSCR
1137 stw r4,THREAD_USED_VR(r5)
1138 lvx vr0,r10,r5
1139 mtvscr vr0
1140 REST_32VRS(0,r4,r5)
1141 #ifndef CONFIG_SMP
1142 /* Update last_task_used_math to 'current' */
1143 subi r4,r5,THREAD /* Back to 'current' */
1144 std r4,0(r3)
1145 #endif /* CONFIG_SMP */
1146 /* restore registers and return */
1147 b fast_exception_return
1148 #endif /* CONFIG_ALTIVEC */
1150 /*
1151 * Hash table stuff
1152 */
1153 .align 7
1154 _GLOBAL(do_hash_page)
1155 std r3,_DAR(r1)
1156 std r4,_DSISR(r1)
1158 andis. r0,r4,0xa450 /* weird error? */
1159 bne- .handle_page_fault /* if not, try to insert a HPTE */
1160 BEGIN_FTR_SECTION
1161 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1162 bne- .do_ste_alloc /* If so handle it */
1163 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1165 /*
1166 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1167 * accessing a userspace segment (even from the kernel). We assume
1168 * kernel addresses always have the high bit set.
1169 */
1170 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1171 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1172 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1173 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1174 ori r4,r4,1 /* add _PAGE_PRESENT */
1175 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1177 /*
1178 * On iSeries, we soft-disable interrupts here, then
1179 * hard-enable interrupts so that the hash_page code can spin on
1180 * the hash_table_lock without problems on a shared processor.
1181 */
1182 DISABLE_INTS
1184 /*
1185 * r3 contains the faulting address
1186 * r4 contains the required access permissions
1187 * r5 contains the trap number
1188 *
1189 * at return r3 = 0 for success
1190 */
1191 bl .hash_page /* build HPTE if possible */
1192 cmpdi r3,0 /* see if hash_page succeeded */
1194 #ifdef DO_SOFT_DISABLE
1195 /*
1196 * If we had interrupts soft-enabled at the point where the
1197 * DSI/ISI occurred, and an interrupt came in during hash_page,
1198 * handle it now.
1199 * We jump to ret_from_except_lite rather than fast_exception_return
1200 * because ret_from_except_lite will check for and handle pending
1201 * interrupts if necessary.
1202 */
1203 beq .ret_from_except_lite
1204 /* For a hash failure, we don't bother re-enabling interrupts */
1205 ble- 12f
1207 /*
1208 * hash_page couldn't handle it, set soft interrupt enable back
1209 * to what it was before the trap. Note that .local_irq_restore
1210 * handles any interrupts pending at this point.
1211 */
1212 ld r3,SOFTE(r1)
1213 bl .local_irq_restore
1214 b 11f
1215 #else
1216 beq fast_exception_return /* Return from exception on success */
1217 ble- 12f /* Failure return from hash_page */
1219 /* fall through */
1220 #endif
1222 /* Here we have a page fault that hash_page can't handle. */
1223 _GLOBAL(handle_page_fault)
1224 ENABLE_INTS
1225 11: ld r4,_DAR(r1)
1226 ld r5,_DSISR(r1)
1227 addi r3,r1,STACK_FRAME_OVERHEAD
1228 bl .do_page_fault
1229 cmpdi r3,0
1230 beq+ .ret_from_except_lite
1231 bl .save_nvgprs
1232 mr r5,r3
1233 addi r3,r1,STACK_FRAME_OVERHEAD
1234 lwz r4,_DAR(r1)
1235 bl .bad_page_fault
1236 b .ret_from_except
1238 /* We have a page fault that hash_page could handle but HV refused
1239 * the PTE insertion
1240 */
1241 12: bl .save_nvgprs
1242 addi r3,r1,STACK_FRAME_OVERHEAD
1243 lwz r4,_DAR(r1)
1244 bl .low_hash_fault
1245 b .ret_from_except
1247 /* here we have a segment miss */
1248 _GLOBAL(do_ste_alloc)
1249 bl .ste_allocate /* try to insert stab entry */
1250 cmpdi r3,0
1251 beq+ fast_exception_return
1252 b .handle_page_fault
1254 /*
1255 * r13 points to the PACA, r9 contains the saved CR,
1256 * r11 and r12 contain the saved SRR0 and SRR1.
1257 * r9 - r13 are saved in paca->exslb.
1258 * We assume we aren't going to take any exceptions during this procedure.
1259 * We assume (DAR >> 60) == 0xc.
1260 */
1261 .align 7
1262 _GLOBAL(do_stab_bolted)
1263 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1264 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1266 /* Hash to the primary group */
1267 ld r10,PACASTABVIRT(r13)
1268 mfspr r11,SPRN_DAR
1269 srdi r11,r11,28
1270 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1272 /* Calculate VSID */
1273 /* This is a kernel address, so protovsid = ESID */
1274 ASM_VSID_SCRAMBLE(r11, r9)
1275 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1277 /* Search the primary group for a free entry */
1278 1: ld r11,0(r10) /* Test valid bit of the current ste */
1279 andi. r11,r11,0x80
1280 beq 2f
1281 addi r10,r10,16
1282 andi. r11,r10,0x70
1283 bne 1b
1285 /* Stick for only searching the primary group for now. */
1286 /* At least for now, we use a very simple random castout scheme */
1287 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1288 mftb r11
1289 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1290 ori r11,r11,0x10
1292 /* r10 currently points to an ste one past the group of interest */
1293 /* make it point to the randomly selected entry */
1294 subi r10,r10,128
1295 or r10,r10,r11 /* r10 is the entry to invalidate */
1297 isync /* mark the entry invalid */
1298 ld r11,0(r10)
1299 rldicl r11,r11,56,1 /* clear the valid bit */
1300 rotldi r11,r11,8
1301 std r11,0(r10)
1302 sync
1304 clrrdi r11,r11,28 /* Get the esid part of the ste */
1305 slbie r11
1307 2: std r9,8(r10) /* Store the vsid part of the ste */
1308 eieio
1310 mfspr r11,SPRN_DAR /* Get the new esid */
1311 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1312 ori r11,r11,0x90 /* Turn on valid and kp */
1313 std r11,0(r10) /* Put new entry back into the stab */
1315 sync
1317 /* All done -- return from exception. */
1318 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1319 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1321 andi. r10,r12,MSR_RI
1322 beq- unrecov_slb
1324 mtcrf 0x80,r9 /* restore CR */
1326 mfmsr r10
1327 clrrdi r10,r10,2
1328 mtmsrd r10,1
1330 mtspr SPRN_SRR0,r11
1331 mtspr SPRN_SRR1,r12
1332 ld r9,PACA_EXSLB+EX_R9(r13)
1333 ld r10,PACA_EXSLB+EX_R10(r13)
1334 ld r11,PACA_EXSLB+EX_R11(r13)
1335 ld r12,PACA_EXSLB+EX_R12(r13)
1336 ld r13,PACA_EXSLB+EX_R13(r13)
1337 rfid
1338 b . /* prevent speculative execution */
1340 /*
1341 * Space for CPU0's segment table.
1342 *
1343 * On iSeries, the hypervisor must fill in at least one entry before
1344 * we get control (with relocate on). The address is give to the hv
1345 * as a page number (see xLparMap in lpardata.c), so this must be at a
1346 * fixed address (the linker can't compute (u64)&initial_stab >>
1347 * PAGE_SHIFT).
1348 */
1349 . = STAB0_PHYS_ADDR /* 0x6000 */
1350 .globl initial_stab
1351 initial_stab:
1352 .space 4096
1354 /*
1355 * Data area reserved for FWNMI option.
1356 * This address (0x7000) is fixed by the RPA.
1357 */
1358 .= 0x7000
1359 .globl fwnmi_data_area
1360 fwnmi_data_area:
1362 /* iSeries does not use the FWNMI stuff, so it is safe to put
1363 * this here, even if we later allow kernels that will boot on
1364 * both pSeries and iSeries */
1365 #ifdef CONFIG_PPC_ISERIES
1366 . = LPARMAP_PHYS
1367 #include "lparmap.s"
1368 /*
1369 * This ".text" is here for old compilers that generate a trailing
1370 * .note section when compiling .c files to .s
1371 */
1372 .text
1373 #endif /* CONFIG_PPC_ISERIES */
1375 . = 0x8000
1377 /*
1378 * On pSeries, secondary processors spin in the following code.
1379 * At entry, r3 = this processor's number (physical cpu id)
1380 */
1381 _GLOBAL(pSeries_secondary_smp_init)
1382 mr r24,r3
1384 /* turn on 64-bit mode */
1385 bl .enable_64b_mode
1386 isync
1388 /* Copy some CPU settings from CPU 0 */
1389 bl .__restore_cpu_setup
1391 /* Set up a paca value for this processor. Since we have the
1392 * physical cpu id in r24, we need to search the pacas to find
1393 * which logical id maps to our physical one.
1394 */
1395 LOADADDR(r13, paca) /* Get base vaddr of paca array */
1396 li r5,0 /* logical cpu id */
1397 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1398 cmpw r6,r24 /* Compare to our id */
1399 beq 2f
1400 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1401 addi r5,r5,1
1402 cmpwi r5,NR_CPUS
1403 blt 1b
1405 mr r3,r24 /* not found, copy phys to r3 */
1406 b .kexec_wait /* next kernel might do better */
1408 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1409 /* From now on, r24 is expected to be logical cpuid */
1410 mr r24,r5
1411 3: HMT_LOW
1412 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1413 /* start. */
1414 sync
1416 /* Create a temp kernel stack for use before relocation is on. */
1417 ld r1,PACAEMERGSP(r13)
1418 subi r1,r1,STACK_FRAME_OVERHEAD
1420 cmpwi 0,r23,0
1421 #ifdef CONFIG_SMP
1422 bne .__secondary_start
1423 #endif
1424 b 3b /* Loop until told to go */
1426 #ifdef CONFIG_PPC_ISERIES
1427 _STATIC(__start_initialization_iSeries)
1428 /* Clear out the BSS */
1429 LOADADDR(r11,__bss_stop)
1430 LOADADDR(r8,__bss_start)
1431 sub r11,r11,r8 /* bss size */
1432 addi r11,r11,7 /* round up to an even double word */
1433 rldicl. r11,r11,61,3 /* shift right by 3 */
1434 beq 4f
1435 addi r8,r8,-8
1436 li r0,0
1437 mtctr r11 /* zero this many doublewords */
1438 3: stdu r0,8(r8)
1439 bdnz 3b
1440 4:
1441 LOADADDR(r1,init_thread_union)
1442 addi r1,r1,THREAD_SIZE
1443 li r0,0
1444 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1446 LOADADDR(r3,cpu_specs)
1447 LOADADDR(r4,cur_cpu_spec)
1448 li r5,0
1449 bl .identify_cpu
1451 LOADADDR(r2,__toc_start)
1452 addi r2,r2,0x4000
1453 addi r2,r2,0x4000
1455 bl .iSeries_early_setup
1456 bl .early_setup
1458 /* relocation is on at this point */
1460 b .start_here_common
1461 #endif /* CONFIG_PPC_ISERIES */
1463 #ifdef CONFIG_PPC_MULTIPLATFORM
1465 _STATIC(__mmu_off)
1466 mfmsr r3
1467 andi. r0,r3,MSR_IR|MSR_DR
1468 beqlr
1469 andc r3,r3,r0
1470 mtspr SPRN_SRR0,r4
1471 mtspr SPRN_SRR1,r3
1472 sync
1473 rfid
1474 b . /* prevent speculative execution */
1477 /*
1478 * Here is our main kernel entry point. We support currently 2 kind of entries
1479 * depending on the value of r5.
1480 *
1481 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1482 * in r3...r7
1483 *
1484 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1485 * DT block, r4 is a physical pointer to the kernel itself
1486 *
1487 */
1488 _GLOBAL(__start_initialization_multiplatform)
1489 /*
1490 * Are we booted from a PROM Of-type client-interface ?
1491 */
1492 cmpldi cr0,r5,0
1493 bne .__boot_from_prom /* yes -> prom */
1495 /* Save parameters */
1496 mr r31,r3
1497 mr r30,r4
1499 /* Make sure we are running in 64 bits mode */
1500 bl .enable_64b_mode
1502 /* Setup some critical 970 SPRs before switching MMU off */
1503 bl .__970_cpu_preinit
1505 /* cpu # */
1506 li r24,0
1508 /* Switch off MMU if not already */
1509 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1510 add r4,r4,r30
1511 bl .__mmu_off
1512 b .__after_prom_start
1514 _STATIC(__boot_from_prom)
1515 /* Save parameters */
1516 mr r31,r3
1517 mr r30,r4
1518 mr r29,r5
1519 mr r28,r6
1520 mr r27,r7
1522 /* Make sure we are running in 64 bits mode */
1523 bl .enable_64b_mode
1525 /* put a relocation offset into r3 */
1526 bl .reloc_offset
1528 LOADADDR(r2,__toc_start)
1529 addi r2,r2,0x4000
1530 addi r2,r2,0x4000
1532 /* Relocate the TOC from a virt addr to a real addr */
1533 sub r2,r2,r3
1535 /* Restore parameters */
1536 mr r3,r31
1537 mr r4,r30
1538 mr r5,r29
1539 mr r6,r28
1540 mr r7,r27
1542 /* Do all of the interaction with OF client interface */
1543 bl .prom_init
1544 /* We never return */
1545 trap
1547 /*
1548 * At this point, r3 contains the physical address we are running at,
1549 * returned by prom_init()
1550 */
1551 _STATIC(__after_prom_start)
1553 /*
1554 * We need to run with __start at physical address 0.
1555 * This will leave some code in the first 256B of
1556 * real memory, which are reserved for software use.
1557 * The remainder of the first page is loaded with the fixed
1558 * interrupt vectors. The next two pages are filled with
1559 * unknown exception placeholders.
1560 *
1561 * Note: This process overwrites the OF exception vectors.
1562 * r26 == relocation offset
1563 * r27 == KERNELBASE
1564 */
1565 bl .reloc_offset
1566 mr r26,r3
1567 SET_REG_TO_CONST(r27,KERNELBASE)
1569 li r3,0 /* target addr */
1571 // XXX FIXME: Use phys returned by OF (r30)
1572 sub r4,r27,r26 /* source addr */
1573 /* current address of _start */
1574 /* i.e. where we are running */
1575 /* the source addr */
1577 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1578 sub r5,r5,r27
1580 li r6,0x100 /* Start offset, the first 0x100 */
1581 /* bytes were copied earlier. */
1583 bl .copy_and_flush /* copy the first n bytes */
1584 /* this includes the code being */
1585 /* executed here. */
1587 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1588 mtctr r0 /* that we just made/relocated */
1589 bctr
1591 4: LOADADDR(r5,klimit)
1592 sub r5,r5,r26
1593 ld r5,0(r5) /* get the value of klimit */
1594 sub r5,r5,r27
1595 bl .copy_and_flush /* copy the rest */
1596 b .start_here_multiplatform
1598 #endif /* CONFIG_PPC_MULTIPLATFORM */
1600 /*
1601 * Copy routine used to copy the kernel to start at physical address 0
1602 * and flush and invalidate the caches as needed.
1603 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1604 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1605 *
1606 * Note: this routine *only* clobbers r0, r6 and lr
1607 */
1608 _GLOBAL(copy_and_flush)
1609 addi r5,r5,-8
1610 addi r6,r6,-8
1611 4: li r0,16 /* Use the least common */
1612 /* denominator cache line */
1613 /* size. This results in */
1614 /* extra cache line flushes */
1615 /* but operation is correct. */
1616 /* Can't get cache line size */
1617 /* from NACA as it is being */
1618 /* moved too. */
1620 mtctr r0 /* put # words/line in ctr */
1621 3: addi r6,r6,8 /* copy a cache line */
1622 ldx r0,r6,r4
1623 stdx r0,r6,r3
1624 bdnz 3b
1625 dcbst r6,r3 /* write it to memory */
1626 sync
1627 icbi r6,r3 /* flush the icache line */
1628 cmpld 0,r6,r5
1629 blt 4b
1630 sync
1631 addi r5,r5,8
1632 addi r6,r6,8
1633 blr
1635 .align 8
1636 copy_to_here:
1638 #ifdef CONFIG_SMP
1639 #ifdef CONFIG_PPC_PMAC
1640 /*
1641 * On PowerMac, secondary processors starts from the reset vector, which
1642 * is temporarily turned into a call to one of the functions below.
1643 */
1644 .section ".text";
1645 .align 2 ;
1647 .globl __secondary_start_pmac_0
1648 __secondary_start_pmac_0:
1649 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1650 li r24,0
1651 b 1f
1652 li r24,1
1653 b 1f
1654 li r24,2
1655 b 1f
1656 li r24,3
1657 1:
1659 _GLOBAL(pmac_secondary_start)
1660 /* turn on 64-bit mode */
1661 bl .enable_64b_mode
1662 isync
1664 /* Copy some CPU settings from CPU 0 */
1665 bl .__restore_cpu_setup
1667 /* pSeries do that early though I don't think we really need it */
1668 mfmsr r3
1669 ori r3,r3,MSR_RI
1670 mtmsrd r3 /* RI on */
1672 /* Set up a paca value for this processor. */
1673 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1674 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1675 add r13,r13,r4 /* for this processor. */
1676 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1678 /* Create a temp kernel stack for use before relocation is on. */
1679 ld r1,PACAEMERGSP(r13)
1680 subi r1,r1,STACK_FRAME_OVERHEAD
1682 b .__secondary_start
1684 #endif /* CONFIG_PPC_PMAC */
1686 /*
1687 * This function is called after the master CPU has released the
1688 * secondary processors. The execution environment is relocation off.
1689 * The paca for this processor has the following fields initialized at
1690 * this point:
1691 * 1. Processor number
1692 * 2. Segment table pointer (virtual address)
1693 * On entry the following are set:
1694 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1695 * r24 = cpu# (in Linux terms)
1696 * r13 = paca virtual address
1697 * SPRG3 = paca virtual address
1698 */
1699 _GLOBAL(__secondary_start)
1701 HMT_MEDIUM /* Set thread priority to MEDIUM */
1703 ld r2,PACATOC(r13)
1704 li r6,0
1705 stb r6,PACAPROCENABLED(r13)
1707 #ifndef CONFIG_PPC_ISERIES
1708 /* Initialize the page table pointer register. */
1709 LOADADDR(r6,_SDR1)
1710 ld r6,0(r6) /* get the value of _SDR1 */
1711 mtspr SPRN_SDR1,r6 /* set the htab location */
1712 #endif
1713 /* Initialize the first segment table (or SLB) entry */
1714 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1715 BEGIN_FTR_SECTION
1716 bl .stab_initialize
1717 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1718 bl .slb_initialize
1720 /* Initialize the kernel stack. Just a repeat for iSeries. */
1721 LOADADDR(r3,current_set)
1722 sldi r28,r24,3 /* get current_set[cpu#] */
1723 ldx r1,r3,r28
1724 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1725 std r1,PACAKSAVE(r13)
1727 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1728 ori r4,r3,1 /* turn on valid bit */
1730 #ifdef CONFIG_PPC_ISERIES
1731 li r0,-1 /* hypervisor call */
1732 li r3,1
1733 sldi r3,r3,63 /* 0x8000000000000000 */
1734 ori r3,r3,4 /* 0x8000000000000004 */
1735 sc /* HvCall_setASR */
1736 #else
1737 /* set the ASR */
1738 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1739 ld r3,0(r3)
1740 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1741 andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
1742 beq 98f /* branch if result is 0 */
1743 mfspr r3,SPRN_PVR
1744 srwi r3,r3,16
1745 cmpwi r3,0x37 /* SStar */
1746 beq 97f
1747 cmpwi r3,0x36 /* IStar */
1748 beq 97f
1749 cmpwi r3,0x34 /* Pulsar */
1750 bne 98f
1751 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1752 HVSC /* Invoking hcall */
1753 b 99f
1754 98: /* !(rpa hypervisor) || !(star) */
1755 mtasr r4 /* set the stab location */
1756 99:
1757 #endif
1758 li r7,0
1759 mtlr r7
1761 /* enable MMU and jump to start_secondary */
1762 LOADADDR(r3,.start_secondary_prolog)
1763 SET_REG_TO_CONST(r4, MSR_KERNEL)
1764 #ifdef DO_SOFT_DISABLE
1765 ori r4,r4,MSR_EE
1766 #endif
1767 mtspr SPRN_SRR0,r3
1768 mtspr SPRN_SRR1,r4
1769 rfid
1770 b . /* prevent speculative execution */
1772 /*
1773 * Running with relocation on at this point. All we want to do is
1774 * zero the stack back-chain pointer before going into C code.
1775 */
1776 _GLOBAL(start_secondary_prolog)
1777 li r3,0
1778 std r3,0(r1) /* Zero the stack frame pointer */
1779 bl .start_secondary
1780 #endif
1782 /*
1783 * This subroutine clobbers r11 and r12
1784 */
1785 _GLOBAL(enable_64b_mode)
1786 mfmsr r11 /* grab the current MSR */
1787 li r12,1
1788 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1789 or r11,r11,r12
1790 li r12,1
1791 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1792 or r11,r11,r12
1793 mtmsrd r11
1794 isync
1795 blr
1797 #ifdef CONFIG_PPC_MULTIPLATFORM
1798 /*
1799 * This is where the main kernel code starts.
1800 */
1801 _STATIC(start_here_multiplatform)
1802 /* get a new offset, now that the kernel has moved. */
1803 bl .reloc_offset
1804 mr r26,r3
1806 /* Clear out the BSS. It may have been done in prom_init,
1807 * already but that's irrelevant since prom_init will soon
1808 * be detached from the kernel completely. Besides, we need
1809 * to clear it now for kexec-style entry.
1810 */
1811 LOADADDR(r11,__bss_stop)
1812 LOADADDR(r8,__bss_start)
1813 sub r11,r11,r8 /* bss size */
1814 addi r11,r11,7 /* round up to an even double word */
1815 rldicl. r11,r11,61,3 /* shift right by 3 */
1816 beq 4f
1817 addi r8,r8,-8
1818 li r0,0
1819 mtctr r11 /* zero this many doublewords */
1820 3: stdu r0,8(r8)
1821 bdnz 3b
1822 4:
1824 mfmsr r6
1825 ori r6,r6,MSR_RI
1826 mtmsrd r6 /* RI on */
1828 #ifdef CONFIG_HMT
1829 /* Start up the second thread on cpu 0 */
1830 mfspr r3,SPRN_PVR
1831 srwi r3,r3,16
1832 cmpwi r3,0x34 /* Pulsar */
1833 beq 90f
1834 cmpwi r3,0x36 /* Icestar */
1835 beq 90f
1836 cmpwi r3,0x37 /* SStar */
1837 beq 90f
1838 b 91f /* HMT not supported */
1839 90: li r3,0
1840 bl .hmt_start_secondary
1841 91:
1842 #endif
1844 /* The following gets the stack and TOC set up with the regs */
1845 /* pointing to the real addr of the kernel stack. This is */
1846 /* all done to support the C function call below which sets */
1847 /* up the htab. This is done because we have relocated the */
1848 /* kernel but are still running in real mode. */
1850 LOADADDR(r3,init_thread_union)
1851 sub r3,r3,r26
1853 /* set up a stack pointer (physical address) */
1854 addi r1,r3,THREAD_SIZE
1855 li r0,0
1856 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1858 /* set up the TOC (physical address) */
1859 LOADADDR(r2,__toc_start)
1860 addi r2,r2,0x4000
1861 addi r2,r2,0x4000
1862 sub r2,r2,r26
1864 LOADADDR(r3,cpu_specs)
1865 sub r3,r3,r26
1866 LOADADDR(r4,cur_cpu_spec)
1867 sub r4,r4,r26
1868 mr r5,r26
1869 bl .identify_cpu
1871 /* Save some low level config HIDs of CPU0 to be copied to
1872 * other CPUs later on, or used for suspend/resume
1873 */
1874 bl .__save_cpu_setup
1875 sync
1877 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1878 * note that boot_cpuid can always be 0 nowadays since there is
1879 * nowhere it can be initialized differently before we reach this
1880 * code
1881 */
1882 LOADADDR(r27, boot_cpuid)
1883 sub r27,r27,r26
1884 lwz r27,0(r27)
1886 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1887 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1888 add r13,r13,r24 /* for this processor. */
1889 sub r13,r13,r26 /* convert to physical addr */
1890 mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */
1892 /* Do very early kernel initializations, including initial hash table,
1893 * stab and slb setup before we turn on relocation. */
1895 /* Restore parameters passed from prom_init/kexec */
1896 mr r3,r31
1897 bl .early_setup
1899 /* set the ASR */
1900 ld r3,PACASTABREAL(r13)
1901 ori r4,r3,1 /* turn on valid bit */
1902 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1903 ld r3,0(r3)
1904 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1905 andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */
1906 beq 98f /* branch if result is 0 */
1907 mfspr r3,SPRN_PVR
1908 srwi r3,r3,16
1909 cmpwi r3,0x37 /* SStar */
1910 beq 97f
1911 cmpwi r3,0x36 /* IStar */
1912 beq 97f
1913 cmpwi r3,0x34 /* Pulsar */
1914 bne 98f
1915 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1916 HVSC /* Invoking hcall */
1917 b 99f
1918 98: /* !(rpa hypervisor) || !(star) */
1919 mtasr r4 /* set the stab location */
1920 99:
1921 /* Set SDR1 (hash table pointer) */
1922 ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */
1923 ld r3,0(r3)
1924 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1925 /* Test if bit 0 is set (LPAR bit) */
1926 andi. r3,r3,PLATFORM_LPAR
1927 bne 98f /* branch if result is !0 */
1928 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1929 sub r6,r6,r26
1930 ld r6,0(r6) /* get the value of _SDR1 */
1931 mtspr SPRN_SDR1,r6 /* set the htab location */
1932 98:
1933 LOADADDR(r3,.start_here_common)
1934 SET_REG_TO_CONST(r4, MSR_KERNEL)
1935 mtspr SPRN_SRR0,r3
1936 mtspr SPRN_SRR1,r4
1937 rfid
1938 b . /* prevent speculative execution */
1939 #endif /* CONFIG_PPC_MULTIPLATFORM */
1941 /* This is where all platforms converge execution */
1942 _STATIC(start_here_common)
1943 /* relocation is on at this point */
1945 /* The following code sets up the SP and TOC now that we are */
1946 /* running with translation enabled. */
1948 LOADADDR(r3,init_thread_union)
1950 /* set up the stack */
1951 addi r1,r3,THREAD_SIZE
1952 li r0,0
1953 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1955 /* Apply the CPUs-specific fixups (nop out sections not relevant
1956 * to this CPU
1957 */
1958 li r3,0
1959 bl .do_cpu_ftr_fixups
1961 LOADADDR(r26, boot_cpuid)
1962 lwz r26,0(r26)
1964 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1965 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1966 add r13,r13,r24 /* for this processor. */
1967 mtspr SPRN_SPRG3,r13
1969 /* ptr to current */
1970 LOADADDR(r4,init_task)
1971 std r4,PACACURRENT(r13)
1973 /* Load the TOC */
1974 ld r2,PACATOC(r13)
1975 std r1,PACAKSAVE(r13)
1977 bl .setup_system
1979 /* Load up the kernel context */
1980 5:
1981 #ifdef DO_SOFT_DISABLE
1982 li r5,0
1983 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1984 mfmsr r5
1985 ori r5,r5,MSR_EE /* Hard Enabled */
1986 mtmsrd r5
1987 #endif
1989 bl .start_kernel
1991 _GLOBAL(hmt_init)
1992 #ifdef CONFIG_HMT
1993 LOADADDR(r5, hmt_thread_data)
1994 mfspr r7,SPRN_PVR
1995 srwi r7,r7,16
1996 cmpwi r7,0x34 /* Pulsar */
1997 beq 90f
1998 cmpwi r7,0x36 /* Icestar */
1999 beq 91f
2000 cmpwi r7,0x37 /* SStar */
2001 beq 91f
2002 b 101f
2003 90: mfspr r6,SPRN_PIR
2004 andi. r6,r6,0x1f
2005 b 92f
2006 91: mfspr r6,SPRN_PIR
2007 andi. r6,r6,0x3ff
2008 92: sldi r4,r24,3
2009 stwx r6,r5,r4
2010 bl .hmt_start_secondary
2011 b 101f
2013 __hmt_secondary_hold:
2014 LOADADDR(r5, hmt_thread_data)
2015 clrldi r5,r5,4
2016 li r7,0
2017 mfspr r6,SPRN_PIR
2018 mfspr r8,SPRN_PVR
2019 srwi r8,r8,16
2020 cmpwi r8,0x34
2021 bne 93f
2022 andi. r6,r6,0x1f
2023 b 103f
2024 93: andi. r6,r6,0x3f
2026 103: lwzx r8,r5,r7
2027 cmpw r8,r6
2028 beq 104f
2029 addi r7,r7,8
2030 b 103b
2032 104: addi r7,r7,4
2033 lwzx r9,r5,r7
2034 mr r24,r9
2035 101:
2036 #endif
2037 mr r3,r24
2038 b .pSeries_secondary_smp_init
2040 #ifdef CONFIG_HMT
2041 _GLOBAL(hmt_start_secondary)
2042 LOADADDR(r4,__hmt_secondary_hold)
2043 clrldi r4,r4,4
2044 mtspr SPRN_NIADORM, r4
2045 mfspr r4, SPRN_MSRDORM
2046 li r5, -65
2047 and r4, r4, r5
2048 mtspr SPRN_MSRDORM, r4
2049 lis r4,0xffef
2050 ori r4,r4,0x7403
2051 mtspr SPRN_TSC, r4
2052 li r4,0x1f4
2053 mtspr SPRN_TST, r4
2054 mfspr r4, SPRN_HID0
2055 ori r4, r4, 0x1
2056 mtspr SPRN_HID0, r4
2057 mfspr r4, SPRN_CTRLF
2058 oris r4, r4, 0x40
2059 mtspr SPRN_CTRLT, r4
2060 blr
2061 #endif
2063 /*
2064 * We put a few things here that have to be page-aligned.
2065 * This stuff goes at the beginning of the bss, which is page-aligned.
2066 */
2067 .section ".bss"
2069 .align PAGE_SHIFT
2071 .globl empty_zero_page
2072 empty_zero_page:
2073 .space PAGE_SIZE
2075 .globl swapper_pg_dir
2076 swapper_pg_dir:
2077 .space PAGE_SIZE
2079 /*
2080 * This space gets a copy of optional info passed to us by the bootstrap
2081 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2082 */
2083 .globl cmd_line
2084 cmd_line:
2085 .space COMMAND_LINE_SIZE