1 /* linux/drivers/mfd/sm501.c
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci.h>
22 #include <linux/gpio.h>
23 #include <linux/i2c-gpio.h>
25 #include <linux/sm501.h>
26 #include <linux/sm501-regs.h>
27 #include <linux/serial_8250.h>
32 struct list_head list
;
33 struct platform_device pdev
;
38 struct sm501_gpio_chip
{
39 struct gpio_chip gpio
;
40 struct sm501_gpio
*ourgpio
; /* to get back to parent. */
41 void __iomem
*regbase
;
45 struct sm501_gpio_chip low
;
46 struct sm501_gpio_chip high
;
49 unsigned int registered
: 1;
51 struct resource
*regs_res
;
54 struct sm501_devdata
{
56 struct mutex clock_lock
;
57 struct list_head devices
;
58 struct sm501_gpio gpio
;
61 struct resource
*io_res
;
62 struct resource
*mem_res
;
63 struct resource
*regs_claim
;
64 struct sm501_platdata
*platdata
;
67 unsigned int in_suspend
;
68 unsigned long pm_misc
;
78 #define MHZ (1000 * 1000)
81 static const unsigned int div_tab
[] = {
108 static unsigned long decode_div(unsigned long pll2
, unsigned long val
,
109 unsigned int lshft
, unsigned int selbit
,
115 return pll2
/ div_tab
[(val
>> lshft
) & mask
];
118 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
122 * Print out the current clock configuration for the device
125 static void sm501_dump_clk(struct sm501_devdata
*sm
)
127 unsigned long misct
= readl(sm
->regs
+ SM501_MISC_TIMING
);
128 unsigned long pm0
= readl(sm
->regs
+ SM501_POWER_MODE_0_CLOCK
);
129 unsigned long pm1
= readl(sm
->regs
+ SM501_POWER_MODE_1_CLOCK
);
130 unsigned long pmc
= readl(sm
->regs
+ SM501_POWER_MODE_CONTROL
);
131 unsigned long sdclk0
, sdclk1
;
132 unsigned long pll2
= 0;
134 switch (misct
& 0x30) {
149 sdclk0
= (misct
& (1<<12)) ? pll2
: 288 * MHZ
;
150 sdclk0
/= div_tab
[((misct
>> 8) & 0xf)];
152 sdclk1
= (misct
& (1<<20)) ? pll2
: 288 * MHZ
;
153 sdclk1
/= div_tab
[((misct
>> 16) & 0xf)];
155 dev_dbg(sm
->dev
, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
158 dev_dbg(sm
->dev
, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
159 fmt_freq(pll2
), sdclk0
, sdclk1
);
161 dev_dbg(sm
->dev
, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0
, sdclk1
);
163 dev_dbg(sm
->dev
, "PM0[%c]: "
164 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
165 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
166 (pmc
& 3 ) == 0 ? '*' : '-',
167 fmt_freq(decode_div(pll2
, pm0
, 24, 1<<29, 31)),
168 fmt_freq(decode_div(pll2
, pm0
, 16, 1<<20, 15)),
169 fmt_freq(decode_div(pll2
, pm0
, 8, 1<<12, 15)),
170 fmt_freq(decode_div(pll2
, pm0
, 0, 1<<4, 15)));
172 dev_dbg(sm
->dev
, "PM1[%c]: "
173 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
174 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
175 (pmc
& 3 ) == 1 ? '*' : '-',
176 fmt_freq(decode_div(pll2
, pm1
, 24, 1<<29, 31)),
177 fmt_freq(decode_div(pll2
, pm1
, 16, 1<<20, 15)),
178 fmt_freq(decode_div(pll2
, pm1
, 8, 1<<12, 15)),
179 fmt_freq(decode_div(pll2
, pm1
, 0, 1<<4, 15)));
182 static void sm501_dump_regs(struct sm501_devdata
*sm
)
184 void __iomem
*regs
= sm
->regs
;
186 dev_info(sm
->dev
, "System Control %08x\n",
187 readl(regs
+ SM501_SYSTEM_CONTROL
));
188 dev_info(sm
->dev
, "Misc Control %08x\n",
189 readl(regs
+ SM501_MISC_CONTROL
));
190 dev_info(sm
->dev
, "GPIO Control Low %08x\n",
191 readl(regs
+ SM501_GPIO31_0_CONTROL
));
192 dev_info(sm
->dev
, "GPIO Control Hi %08x\n",
193 readl(regs
+ SM501_GPIO63_32_CONTROL
));
194 dev_info(sm
->dev
, "DRAM Control %08x\n",
195 readl(regs
+ SM501_DRAM_CONTROL
));
196 dev_info(sm
->dev
, "Arbitration Ctrl %08x\n",
197 readl(regs
+ SM501_ARBTRTN_CONTROL
));
198 dev_info(sm
->dev
, "Misc Timing %08x\n",
199 readl(regs
+ SM501_MISC_TIMING
));
202 static void sm501_dump_gate(struct sm501_devdata
*sm
)
204 dev_info(sm
->dev
, "CurrentGate %08x\n",
205 readl(sm
->regs
+ SM501_CURRENT_GATE
));
206 dev_info(sm
->dev
, "CurrentClock %08x\n",
207 readl(sm
->regs
+ SM501_CURRENT_CLOCK
));
208 dev_info(sm
->dev
, "PowerModeControl %08x\n",
209 readl(sm
->regs
+ SM501_POWER_MODE_CONTROL
));
213 static inline void sm501_dump_gate(struct sm501_devdata
*sm
) { }
214 static inline void sm501_dump_regs(struct sm501_devdata
*sm
) { }
215 static inline void sm501_dump_clk(struct sm501_devdata
*sm
) { }
223 static void sm501_sync_regs(struct sm501_devdata
*sm
)
228 static inline void sm501_mdelay(struct sm501_devdata
*sm
, unsigned int delay
)
230 /* during suspend/resume, we are currently not allowed to sleep,
231 * so change to using mdelay() instead of msleep() if we
232 * are in one of these paths */
240 /* sm501_misc_control
242 * alters the miscellaneous control parameters
245 int sm501_misc_control(struct device
*dev
,
246 unsigned long set
, unsigned long clear
)
248 struct sm501_devdata
*sm
= dev_get_drvdata(dev
);
253 spin_lock_irqsave(&sm
->reg_lock
, save
);
255 misc
= readl(sm
->regs
+ SM501_MISC_CONTROL
);
256 to
= (misc
& ~clear
) | set
;
259 writel(to
, sm
->regs
+ SM501_MISC_CONTROL
);
262 dev_dbg(sm
->dev
, "MISC_CONTROL %08lx\n", misc
);
265 spin_unlock_irqrestore(&sm
->reg_lock
, save
);
269 EXPORT_SYMBOL_GPL(sm501_misc_control
);
273 * Modify a register in the SM501 which may be shared with other
277 unsigned long sm501_modify_reg(struct device
*dev
,
282 struct sm501_devdata
*sm
= dev_get_drvdata(dev
);
286 spin_lock_irqsave(&sm
->reg_lock
, save
);
288 data
= readl(sm
->regs
+ reg
);
292 writel(data
, sm
->regs
+ reg
);
295 spin_unlock_irqrestore(&sm
->reg_lock
, save
);
300 EXPORT_SYMBOL_GPL(sm501_modify_reg
);
304 * alters the power active gate to set specific units on or off
307 int sm501_unit_power(struct device
*dev
, unsigned int unit
, unsigned int to
)
309 struct sm501_devdata
*sm
= dev_get_drvdata(dev
);
314 mutex_lock(&sm
->clock_lock
);
316 mode
= readl(sm
->regs
+ SM501_POWER_MODE_CONTROL
);
317 gate
= readl(sm
->regs
+ SM501_CURRENT_GATE
);
318 clock
= readl(sm
->regs
+ SM501_CURRENT_CLOCK
);
320 mode
&= 3; /* get current power mode */
322 if (unit
>= ARRAY_SIZE(sm
->unit_power
)) {
323 dev_err(dev
, "%s: bad unit %d\n", __func__
, unit
);
327 dev_dbg(sm
->dev
, "%s: unit %d, cur %d, to %d\n", __func__
, unit
,
328 sm
->unit_power
[unit
], to
);
330 if (to
== 0 && sm
->unit_power
[unit
] == 0) {
331 dev_err(sm
->dev
, "unit %d is already shutdown\n", unit
);
335 sm
->unit_power
[unit
] += to
? 1 : -1;
336 to
= sm
->unit_power
[unit
] ? 1 : 0;
339 if (gate
& (1 << unit
))
343 if (!(gate
& (1 << unit
)))
345 gate
&= ~(1 << unit
);
350 writel(gate
, sm
->regs
+ SM501_POWER_MODE_0_GATE
);
351 writel(clock
, sm
->regs
+ SM501_POWER_MODE_0_CLOCK
);
356 writel(gate
, sm
->regs
+ SM501_POWER_MODE_1_GATE
);
357 writel(clock
, sm
->regs
+ SM501_POWER_MODE_1_CLOCK
);
365 writel(mode
, sm
->regs
+ SM501_POWER_MODE_CONTROL
);
368 dev_dbg(sm
->dev
, "gate %08lx, clock %08lx, mode %08lx\n",
371 sm501_mdelay(sm
, 16);
374 mutex_unlock(&sm
->clock_lock
);
378 EXPORT_SYMBOL_GPL(sm501_unit_power
);
381 /* Perform a rounded division. */
382 static long sm501fb_round_div(long num
, long denom
)
384 /* n / d + 1 / 2 = (2n + d) / 2d */
385 return (2 * num
+ denom
) / (2 * denom
);
388 /* clock value structure. */
393 unsigned int m
, n
, k
;
398 * Calculates the nearest discrete clock frequency that
399 * can be achieved with the specified input clock.
400 * the maximum divisor is 3 or 5
403 static int sm501_calc_clock(unsigned long freq
,
404 struct sm501_clock
*clock
,
414 /* try dividers 1 and 3 for CRT and for panel,
415 try divider 5 for panel only.*/
417 for (divider
= 1; divider
<= max_div
; divider
+= 2) {
418 /* try all 8 shift values.*/
419 for (shift
= 0; shift
< 8; shift
++) {
420 /* Calculate difference to requested clock */
421 diff
= sm501fb_round_div(mclk
, divider
<< shift
) - freq
;
425 /* If it is less than the current, use it */
426 if (diff
< *best_diff
) {
430 clock
->divider
= divider
;
431 clock
->shift
= shift
;
442 * Calculates the nearest discrete clock frequency that can be
443 * achieved using the programmable PLL.
444 * the maximum divisor is 3 or 5
447 static unsigned long sm501_calc_pll(unsigned long freq
,
448 struct sm501_clock
*clock
,
452 unsigned int m
, n
, k
;
453 long best_diff
= 999999999;
456 * The SM502 datasheet doesn't specify the min/max values for M and N.
457 * N = 1 at least doesn't work in practice.
459 for (m
= 2; m
<= 255; m
++) {
460 for (n
= 2; n
<= 127; n
++) {
461 for (k
= 0; k
<= 1; k
++) {
462 mclk
= (24000000UL * m
/ n
) >> k
;
464 if (sm501_calc_clock(freq
, clock
, max_div
,
474 /* Return best clock. */
475 return clock
->mclk
/ (clock
->divider
<< clock
->shift
);
478 /* sm501_select_clock
480 * Calculates the nearest discrete clock frequency that can be
481 * achieved using the 288MHz and 336MHz PLLs.
482 * the maximum divisor is 3 or 5
485 static unsigned long sm501_select_clock(unsigned long freq
,
486 struct sm501_clock
*clock
,
490 long best_diff
= 999999999;
492 /* Try 288MHz and 336MHz clocks. */
493 for (mclk
= 288000000; mclk
<= 336000000; mclk
+= 48000000) {
494 sm501_calc_clock(freq
, clock
, max_div
, mclk
, &best_diff
);
497 /* Return best clock. */
498 return clock
->mclk
/ (clock
->divider
<< clock
->shift
);
503 * set one of the four clock sources to the closest available frequency to
507 unsigned long sm501_set_clock(struct device
*dev
,
509 unsigned long req_freq
)
511 struct sm501_devdata
*sm
= dev_get_drvdata(dev
);
512 unsigned long mode
= readl(sm
->regs
+ SM501_POWER_MODE_CONTROL
);
513 unsigned long gate
= readl(sm
->regs
+ SM501_CURRENT_GATE
);
514 unsigned long clock
= readl(sm
->regs
+ SM501_CURRENT_CLOCK
);
516 unsigned int pll_reg
= 0;
517 unsigned long sm501_freq
; /* the actual frequency acheived */
519 struct sm501_clock to
;
521 /* find achivable discrete frequency and setup register value
522 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
523 * has an extra bit for the divider */
526 case SM501_CLOCK_P2XCLK
:
527 /* This clock is divided in half so to achive the
528 * requested frequency the value must be multiplied by
529 * 2. This clock also has an additional pre divisor */
531 if (sm
->rev
>= 0xC0) {
532 /* SM502 -> use the programmable PLL */
533 sm501_freq
= (sm501_calc_pll(2 * req_freq
,
535 reg
= to
.shift
& 0x07;/* bottom 3 bits are shift */
537 reg
|= 0x08; /* /3 divider required */
538 else if (to
.divider
== 5)
539 reg
|= 0x10; /* /5 divider required */
540 reg
|= 0x40; /* select the programmable PLL */
541 pll_reg
= 0x20000 | (to
.k
<< 15) | (to
.n
<< 8) | to
.m
;
543 sm501_freq
= (sm501_select_clock(2 * req_freq
,
545 reg
= to
.shift
& 0x07;/* bottom 3 bits are shift */
547 reg
|= 0x08; /* /3 divider required */
548 else if (to
.divider
== 5)
549 reg
|= 0x10; /* /5 divider required */
550 if (to
.mclk
!= 288000000)
551 reg
|= 0x20; /* which mclk pll is source */
555 case SM501_CLOCK_V2XCLK
:
556 /* This clock is divided in half so to achive the
557 * requested frequency the value must be multiplied by 2. */
559 sm501_freq
= (sm501_select_clock(2 * req_freq
, &to
, 3) / 2);
560 reg
=to
.shift
& 0x07; /* bottom 3 bits are shift */
562 reg
|= 0x08; /* /3 divider required */
563 if (to
.mclk
!= 288000000)
564 reg
|= 0x10; /* which mclk pll is source */
567 case SM501_CLOCK_MCLK
:
568 case SM501_CLOCK_M1XCLK
:
569 /* These clocks are the same and not further divided */
571 sm501_freq
= sm501_select_clock( req_freq
, &to
, 3);
572 reg
=to
.shift
& 0x07; /* bottom 3 bits are shift */
574 reg
|= 0x08; /* /3 divider required */
575 if (to
.mclk
!= 288000000)
576 reg
|= 0x10; /* which mclk pll is source */
580 return 0; /* this is bad */
583 mutex_lock(&sm
->clock_lock
);
585 mode
= readl(sm
->regs
+ SM501_POWER_MODE_CONTROL
);
586 gate
= readl(sm
->regs
+ SM501_CURRENT_GATE
);
587 clock
= readl(sm
->regs
+ SM501_CURRENT_CLOCK
);
589 clock
= clock
& ~(0xFF << clksrc
);
590 clock
|= reg
<<clksrc
;
592 mode
&= 3; /* find current mode */
596 writel(gate
, sm
->regs
+ SM501_POWER_MODE_0_GATE
);
597 writel(clock
, sm
->regs
+ SM501_POWER_MODE_0_CLOCK
);
602 writel(gate
, sm
->regs
+ SM501_POWER_MODE_1_GATE
);
603 writel(clock
, sm
->regs
+ SM501_POWER_MODE_1_CLOCK
);
608 mutex_unlock(&sm
->clock_lock
);
612 writel(mode
, sm
->regs
+ SM501_POWER_MODE_CONTROL
);
615 writel(pll_reg
, sm
->regs
+ SM501_PROGRAMMABLE_PLL_CONTROL
);
619 dev_info(sm
->dev
, "gate %08lx, clock %08lx, mode %08lx\n",
622 sm501_mdelay(sm
, 16);
623 mutex_unlock(&sm
->clock_lock
);
630 EXPORT_SYMBOL_GPL(sm501_set_clock
);
634 * finds the closest available frequency for a given clock
637 unsigned long sm501_find_clock(struct device
*dev
,
639 unsigned long req_freq
)
641 struct sm501_devdata
*sm
= dev_get_drvdata(dev
);
642 unsigned long sm501_freq
; /* the frequency achiveable by the 501 */
643 struct sm501_clock to
;
646 case SM501_CLOCK_P2XCLK
:
647 if (sm
->rev
>= 0xC0) {
648 /* SM502 -> use the programmable PLL */
649 sm501_freq
= (sm501_calc_pll(2 * req_freq
,
652 sm501_freq
= (sm501_select_clock(2 * req_freq
,
657 case SM501_CLOCK_V2XCLK
:
658 sm501_freq
= (sm501_select_clock(2 * req_freq
, &to
, 3) / 2);
661 case SM501_CLOCK_MCLK
:
662 case SM501_CLOCK_M1XCLK
:
663 sm501_freq
= sm501_select_clock(req_freq
, &to
, 3);
667 sm501_freq
= 0; /* error */
673 EXPORT_SYMBOL_GPL(sm501_find_clock
);
675 static struct sm501_device
*to_sm_device(struct platform_device
*pdev
)
677 return container_of(pdev
, struct sm501_device
, pdev
);
680 /* sm501_device_release
682 * A release function for the platform devices we create to allow us to
683 * free any items we allocated
686 static void sm501_device_release(struct device
*dev
)
688 kfree(to_sm_device(to_platform_device(dev
)));
691 /* sm501_create_subdev
693 * Create a skeleton platform device with resources for passing to a
697 static struct platform_device
*
698 sm501_create_subdev(struct sm501_devdata
*sm
, char *name
,
699 unsigned int res_count
, unsigned int platform_data_size
)
701 struct sm501_device
*smdev
;
703 smdev
= kzalloc(sizeof(struct sm501_device
) +
704 (sizeof(struct resource
) * res_count
) +
705 platform_data_size
, GFP_KERNEL
);
709 smdev
->pdev
.dev
.release
= sm501_device_release
;
711 smdev
->pdev
.name
= name
;
712 smdev
->pdev
.id
= sm
->pdev_id
;
713 smdev
->pdev
.dev
.parent
= sm
->dev
;
716 smdev
->pdev
.resource
= (struct resource
*)(smdev
+1);
717 smdev
->pdev
.num_resources
= res_count
;
719 if (platform_data_size
)
720 smdev
->pdev
.dev
.platform_data
= (void *)(smdev
+1);
725 /* sm501_register_device
727 * Register a platform device created with sm501_create_subdev()
730 static int sm501_register_device(struct sm501_devdata
*sm
,
731 struct platform_device
*pdev
)
733 struct sm501_device
*smdev
= to_sm_device(pdev
);
737 for (ptr
= 0; ptr
< pdev
->num_resources
; ptr
++) {
738 printk("%s[%d] flags %08lx: %08llx..%08llx\n",
740 pdev
->resource
[ptr
].flags
,
741 (unsigned long long)pdev
->resource
[ptr
].start
,
742 (unsigned long long)pdev
->resource
[ptr
].end
);
745 ret
= platform_device_register(pdev
);
748 dev_dbg(sm
->dev
, "registered %s\n", pdev
->name
);
749 list_add_tail(&smdev
->list
, &sm
->devices
);
751 dev_err(sm
->dev
, "error registering %s (%d)\n",
757 /* sm501_create_subio
759 * Fill in an IO resource for a sub device
762 static void sm501_create_subio(struct sm501_devdata
*sm
,
763 struct resource
*res
,
764 resource_size_t offs
,
765 resource_size_t size
)
767 res
->flags
= IORESOURCE_MEM
;
768 res
->parent
= sm
->io_res
;
769 res
->start
= sm
->io_res
->start
+ offs
;
770 res
->end
= res
->start
+ size
- 1;
775 * Fill in an MEM resource for a sub device
778 static void sm501_create_mem(struct sm501_devdata
*sm
,
779 struct resource
*res
,
780 resource_size_t
*offs
,
781 resource_size_t size
)
783 *offs
-= size
; /* adjust memory size */
785 res
->flags
= IORESOURCE_MEM
;
786 res
->parent
= sm
->mem_res
;
787 res
->start
= sm
->mem_res
->start
+ *offs
;
788 res
->end
= res
->start
+ size
- 1;
793 * Fill in an IRQ resource for a sub device
796 static void sm501_create_irq(struct sm501_devdata
*sm
,
797 struct resource
*res
)
799 res
->flags
= IORESOURCE_IRQ
;
801 res
->start
= res
->end
= sm
->irq
;
804 static int sm501_register_usbhost(struct sm501_devdata
*sm
,
805 resource_size_t
*mem_avail
)
807 struct platform_device
*pdev
;
809 pdev
= sm501_create_subdev(sm
, "sm501-usb", 3, 0);
813 sm501_create_subio(sm
, &pdev
->resource
[0], 0x40000, 0x20000);
814 sm501_create_mem(sm
, &pdev
->resource
[1], mem_avail
, 256*1024);
815 sm501_create_irq(sm
, &pdev
->resource
[2]);
817 return sm501_register_device(sm
, pdev
);
820 static void sm501_setup_uart_data(struct sm501_devdata
*sm
,
821 struct plat_serial8250_port
*uart_data
,
824 uart_data
->membase
= sm
->regs
+ offset
;
825 uart_data
->mapbase
= sm
->io_res
->start
+ offset
;
826 uart_data
->iotype
= UPIO_MEM
;
827 uart_data
->irq
= sm
->irq
;
828 uart_data
->flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
| UPF_SHARE_IRQ
;
829 uart_data
->regshift
= 2;
830 uart_data
->uartclk
= (9600 * 16);
833 static int sm501_register_uart(struct sm501_devdata
*sm
, int devices
)
835 struct platform_device
*pdev
;
836 struct plat_serial8250_port
*uart_data
;
838 pdev
= sm501_create_subdev(sm
, "serial8250", 0,
839 sizeof(struct plat_serial8250_port
) * 3);
843 uart_data
= pdev
->dev
.platform_data
;
845 if (devices
& SM501_USE_UART0
) {
846 sm501_setup_uart_data(sm
, uart_data
++, 0x30000);
847 sm501_unit_power(sm
->dev
, SM501_GATE_UART0
, 1);
848 sm501_modify_reg(sm
->dev
, SM501_IRQ_MASK
, 1 << 12, 0);
849 sm501_modify_reg(sm
->dev
, SM501_GPIO63_32_CONTROL
, 0x01e0, 0);
851 if (devices
& SM501_USE_UART1
) {
852 sm501_setup_uart_data(sm
, uart_data
++, 0x30020);
853 sm501_unit_power(sm
->dev
, SM501_GATE_UART1
, 1);
854 sm501_modify_reg(sm
->dev
, SM501_IRQ_MASK
, 1 << 13, 0);
855 sm501_modify_reg(sm
->dev
, SM501_GPIO63_32_CONTROL
, 0x1e00, 0);
858 pdev
->id
= PLAT8250_DEV_SM501
;
860 return sm501_register_device(sm
, pdev
);
863 static int sm501_register_display(struct sm501_devdata
*sm
,
864 resource_size_t
*mem_avail
)
866 struct platform_device
*pdev
;
868 pdev
= sm501_create_subdev(sm
, "sm501-fb", 4, 0);
872 sm501_create_subio(sm
, &pdev
->resource
[0], 0x80000, 0x10000);
873 sm501_create_subio(sm
, &pdev
->resource
[1], 0x100000, 0x50000);
874 sm501_create_mem(sm
, &pdev
->resource
[2], mem_avail
, *mem_avail
);
875 sm501_create_irq(sm
, &pdev
->resource
[3]);
877 return sm501_register_device(sm
, pdev
);
880 #ifdef CONFIG_MFD_SM501_GPIO
882 static inline struct sm501_gpio_chip
*to_sm501_gpio(struct gpio_chip
*gc
)
884 return container_of(gc
, struct sm501_gpio_chip
, gpio
);
887 static inline struct sm501_devdata
*sm501_gpio_to_dev(struct sm501_gpio
*gpio
)
889 return container_of(gpio
, struct sm501_devdata
, gpio
);
892 static int sm501_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
895 struct sm501_gpio_chip
*smgpio
= to_sm501_gpio(chip
);
896 unsigned long result
;
898 result
= readl(smgpio
->regbase
+ SM501_GPIO_DATA_LOW
);
904 static void sm501_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
907 struct sm501_gpio_chip
*smchip
= to_sm501_gpio(chip
);
908 struct sm501_gpio
*smgpio
= smchip
->ourgpio
;
909 unsigned long bit
= 1 << offset
;
910 void __iomem
*regs
= smchip
->regbase
;
914 dev_dbg(sm501_gpio_to_dev(smgpio
)->dev
, "%s(%p,%d)\n",
915 __func__
, chip
, offset
);
917 spin_lock_irqsave(&smgpio
->lock
, save
);
919 val
= readl(regs
+ SM501_GPIO_DATA_LOW
) & ~bit
;
924 sm501_sync_regs(sm501_gpio_to_dev(smgpio
));
925 spin_unlock_irqrestore(&smgpio
->lock
, save
);
928 static int sm501_gpio_input(struct gpio_chip
*chip
, unsigned offset
)
930 struct sm501_gpio_chip
*smchip
= to_sm501_gpio(chip
);
931 struct sm501_gpio
*smgpio
= smchip
->ourgpio
;
932 void __iomem
*regs
= smchip
->regbase
;
933 unsigned long bit
= 1 << offset
;
937 dev_info(sm501_gpio_to_dev(smgpio
)->dev
, "%s(%p,%d)\n",
938 __func__
, chip
, offset
);
940 spin_lock_irqsave(&smgpio
->lock
, save
);
942 ddr
= readl(regs
+ SM501_GPIO_DDR_LOW
);
943 writel(ddr
& ~bit
, regs
+ SM501_GPIO_DDR_LOW
);
945 sm501_sync_regs(sm501_gpio_to_dev(smgpio
));
946 spin_unlock_irqrestore(&smgpio
->lock
, save
);
951 static int sm501_gpio_output(struct gpio_chip
*chip
,
952 unsigned offset
, int value
)
954 struct sm501_gpio_chip
*smchip
= to_sm501_gpio(chip
);
955 struct sm501_gpio
*smgpio
= smchip
->ourgpio
;
956 unsigned long bit
= 1 << offset
;
957 void __iomem
*regs
= smchip
->regbase
;
962 dev_dbg(sm501_gpio_to_dev(smgpio
)->dev
, "%s(%p,%d,%d)\n",
963 __func__
, chip
, offset
, value
);
965 spin_lock_irqsave(&smgpio
->lock
, save
);
967 val
= readl(regs
+ SM501_GPIO_DATA_LOW
);
974 ddr
= readl(regs
+ SM501_GPIO_DDR_LOW
);
975 writel(ddr
| bit
, regs
+ SM501_GPIO_DDR_LOW
);
977 sm501_sync_regs(sm501_gpio_to_dev(smgpio
));
978 writel(val
, regs
+ SM501_GPIO_DATA_LOW
);
980 sm501_sync_regs(sm501_gpio_to_dev(smgpio
));
981 spin_unlock_irqrestore(&smgpio
->lock
, save
);
986 static struct gpio_chip gpio_chip_template
= {
988 .direction_input
= sm501_gpio_input
,
989 .direction_output
= sm501_gpio_output
,
990 .set
= sm501_gpio_set
,
991 .get
= sm501_gpio_get
,
994 static int __devinit
sm501_gpio_register_chip(struct sm501_devdata
*sm
,
995 struct sm501_gpio
*gpio
,
996 struct sm501_gpio_chip
*chip
)
998 struct sm501_platdata
*pdata
= sm
->platdata
;
999 struct gpio_chip
*gchip
= &chip
->gpio
;
1000 int base
= pdata
->gpio_base
;
1002 memcpy(chip
, &gpio_chip_template
, sizeof(struct gpio_chip
));
1004 if (chip
== &gpio
->high
) {
1007 chip
->regbase
= gpio
->regs
+ SM501_GPIO_DATA_HIGH
;
1008 gchip
->label
= "SM501-HIGH";
1010 chip
->regbase
= gpio
->regs
+ SM501_GPIO_DATA_LOW
;
1011 gchip
->label
= "SM501-LOW";
1015 chip
->ourgpio
= gpio
;
1017 return gpiochip_add(gchip
);
1020 static int sm501_register_gpio(struct sm501_devdata
*sm
)
1022 struct sm501_gpio
*gpio
= &sm
->gpio
;
1023 resource_size_t iobase
= sm
->io_res
->start
+ SM501_GPIO
;
1027 dev_dbg(sm
->dev
, "registering gpio block %08llx\n",
1028 (unsigned long long)iobase
);
1030 spin_lock_init(&gpio
->lock
);
1032 gpio
->regs_res
= request_mem_region(iobase
, 0x20, "sm501-gpio");
1033 if (gpio
->regs_res
== NULL
) {
1034 dev_err(sm
->dev
, "gpio: failed to request region\n");
1038 gpio
->regs
= ioremap(iobase
, 0x20);
1039 if (gpio
->regs
== NULL
) {
1040 dev_err(sm
->dev
, "gpio: failed to remap registers\n");
1045 /* Register both our chips. */
1047 ret
= sm501_gpio_register_chip(sm
, gpio
, &gpio
->low
);
1049 dev_err(sm
->dev
, "failed to add low chip\n");
1053 ret
= sm501_gpio_register_chip(sm
, gpio
, &gpio
->high
);
1055 dev_err(sm
->dev
, "failed to add high chip\n");
1059 gpio
->registered
= 1;
1064 tmp
= gpiochip_remove(&gpio
->low
.gpio
);
1066 dev_err(sm
->dev
, "cannot remove low chip, cannot tidy up\n");
1071 release_resource(gpio
->regs_res
);
1072 kfree(gpio
->regs_res
);
1077 static void sm501_gpio_remove(struct sm501_devdata
*sm
)
1081 ret
= gpiochip_remove(&sm
->gpio
.low
.gpio
);
1083 dev_err(sm
->dev
, "cannot remove low chip, cannot tidy up\n");
1085 ret
= gpiochip_remove(&sm
->gpio
.high
.gpio
);
1087 dev_err(sm
->dev
, "cannot remove high chip, cannot tidy up\n");
1090 static int sm501_gpio_pin2nr(struct sm501_devdata
*sm
, unsigned int pin
)
1092 struct sm501_gpio
*gpio
= &sm
->gpio
;
1093 return pin
+ (pin
< 32) ? gpio
->low
.gpio
.base
: gpio
->high
.gpio
.base
;
1096 static int sm501_register_gpio(struct sm501_devdata
*sm
)
1101 static void sm501_gpio_remove(struct sm501_devdata
*sm
)
1105 static int sm501_gpio_pin2nr(struct sm501_devdata
*sm
, unsigned int pin
)
1111 static int sm501_register_gpio_i2c_instance(struct sm501_devdata
*sm
,
1112 struct sm501_platdata_gpio_i2c
*iic
)
1114 struct i2c_gpio_platform_data
*icd
;
1115 struct platform_device
*pdev
;
1117 pdev
= sm501_create_subdev(sm
, "i2c-gpio", 0,
1118 sizeof(struct i2c_gpio_platform_data
));
1122 icd
= pdev
->dev
.platform_data
;
1124 /* We keep the pin_sda and pin_scl fields relative in case the
1125 * same platform data is passed to >1 SM501.
1128 icd
->sda_pin
= sm501_gpio_pin2nr(sm
, iic
->pin_sda
);
1129 icd
->scl_pin
= sm501_gpio_pin2nr(sm
, iic
->pin_scl
);
1130 icd
->timeout
= iic
->timeout
;
1131 icd
->udelay
= iic
->udelay
;
1133 /* note, we can't use either of the pin numbers, as the i2c-gpio
1134 * driver uses the platform.id field to generate the bus number
1135 * to register with the i2c core; The i2c core doesn't have enough
1136 * entries to deal with anything we currently use.
1139 pdev
->id
= iic
->bus_num
;
1141 dev_info(sm
->dev
, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1143 icd
->sda_pin
, iic
->pin_sda
, icd
->scl_pin
, iic
->pin_scl
);
1145 return sm501_register_device(sm
, pdev
);
1148 static int sm501_register_gpio_i2c(struct sm501_devdata
*sm
,
1149 struct sm501_platdata
*pdata
)
1151 struct sm501_platdata_gpio_i2c
*iic
= pdata
->gpio_i2c
;
1155 for (index
= 0; index
< pdata
->gpio_i2c_nr
; index
++, iic
++) {
1156 ret
= sm501_register_gpio_i2c_instance(sm
, iic
);
1166 * Debug attribute to attach to parent device to show core registers
1169 static ssize_t
sm501_dbg_regs(struct device
*dev
,
1170 struct device_attribute
*attr
, char *buff
)
1172 struct sm501_devdata
*sm
= dev_get_drvdata(dev
) ;
1177 for (reg
= 0x00; reg
< 0x70; reg
+= 4) {
1178 ret
= sprintf(ptr
, "%08x = %08x\n",
1179 reg
, readl(sm
->regs
+ reg
));
1187 static DEVICE_ATTR(dbg_regs
, 0666, sm501_dbg_regs
, NULL
);
1191 * Helper function for the init code to setup a register
1193 * clear the bits which are set in r->mask, and then set
1194 * the bits set in r->set.
1197 static inline void sm501_init_reg(struct sm501_devdata
*sm
,
1199 struct sm501_reg_init
*r
)
1203 tmp
= readl(sm
->regs
+ reg
);
1206 writel(tmp
, sm
->regs
+ reg
);
1211 * Setup core register values
1214 static void sm501_init_regs(struct sm501_devdata
*sm
,
1215 struct sm501_initdata
*init
)
1217 sm501_misc_control(sm
->dev
,
1218 init
->misc_control
.set
,
1219 init
->misc_control
.mask
);
1221 sm501_init_reg(sm
, SM501_MISC_TIMING
, &init
->misc_timing
);
1222 sm501_init_reg(sm
, SM501_GPIO31_0_CONTROL
, &init
->gpio_low
);
1223 sm501_init_reg(sm
, SM501_GPIO63_32_CONTROL
, &init
->gpio_high
);
1226 dev_info(sm
->dev
, "setting M1XCLK to %ld\n", init
->m1xclk
);
1227 sm501_set_clock(sm
->dev
, SM501_CLOCK_M1XCLK
, init
->m1xclk
);
1231 dev_info(sm
->dev
, "setting MCLK to %ld\n", init
->mclk
);
1232 sm501_set_clock(sm
->dev
, SM501_CLOCK_MCLK
, init
->mclk
);
1237 /* Check the PLL sources for the M1CLK and M1XCLK
1239 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1240 * there is a risk (see errata AB-5) that the SM501 will cease proper
1241 * function. If this happens, then it is likely the SM501 will
1245 static int sm501_check_clocks(struct sm501_devdata
*sm
)
1247 unsigned long pwrmode
= readl(sm
->regs
+ SM501_CURRENT_CLOCK
);
1248 unsigned long msrc
= (pwrmode
& SM501_POWERMODE_M_SRC
);
1249 unsigned long m1src
= (pwrmode
& SM501_POWERMODE_M1_SRC
);
1251 return ((msrc
== 0 && m1src
!= 0) || (msrc
!= 0 && m1src
== 0));
1254 static unsigned int sm501_mem_local
[] = {
1265 * Common init code for an SM501
1268 static int sm501_init_dev(struct sm501_devdata
*sm
)
1270 struct sm501_initdata
*idata
;
1271 struct sm501_platdata
*pdata
;
1272 resource_size_t mem_avail
;
1273 unsigned long dramctrl
;
1274 unsigned long devid
;
1277 mutex_init(&sm
->clock_lock
);
1278 spin_lock_init(&sm
->reg_lock
);
1280 INIT_LIST_HEAD(&sm
->devices
);
1282 devid
= readl(sm
->regs
+ SM501_DEVICEID
);
1284 if ((devid
& SM501_DEVICEID_IDMASK
) != SM501_DEVICEID_SM501
) {
1285 dev_err(sm
->dev
, "incorrect device id %08lx\n", devid
);
1290 writel(0, sm
->regs
+ SM501_IRQ_MASK
);
1292 dramctrl
= readl(sm
->regs
+ SM501_DRAM_CONTROL
);
1293 mem_avail
= sm501_mem_local
[(dramctrl
>> 13) & 0x7];
1295 dev_info(sm
->dev
, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1296 sm
->regs
, devid
, (unsigned long)mem_avail
>> 20, sm
->irq
);
1298 sm
->rev
= devid
& SM501_DEVICEID_REVMASK
;
1300 sm501_dump_gate(sm
);
1302 ret
= device_create_file(sm
->dev
, &dev_attr_dbg_regs
);
1304 dev_err(sm
->dev
, "failed to create debug regs file\n");
1308 /* check to see if we have some device initialisation */
1310 pdata
= sm
->platdata
;
1311 idata
= pdata
? pdata
->init
: NULL
;
1314 sm501_init_regs(sm
, idata
);
1316 if (idata
->devices
& SM501_USE_USB_HOST
)
1317 sm501_register_usbhost(sm
, &mem_avail
);
1318 if (idata
->devices
& (SM501_USE_UART0
| SM501_USE_UART1
))
1319 sm501_register_uart(sm
, idata
->devices
);
1320 if (idata
->devices
& SM501_USE_GPIO
)
1321 sm501_register_gpio(sm
);
1324 if (pdata
->gpio_i2c
!= NULL
&& pdata
->gpio_i2c_nr
> 0) {
1325 if (!sm
->gpio
.registered
)
1326 dev_err(sm
->dev
, "no gpio registered for i2c gpio.\n");
1328 sm501_register_gpio_i2c(sm
, pdata
);
1331 ret
= sm501_check_clocks(sm
);
1333 dev_err(sm
->dev
, "M1X and M clocks sourced from different "
1338 /* always create a framebuffer */
1339 sm501_register_display(sm
, &mem_avail
);
1344 static int sm501_plat_probe(struct platform_device
*dev
)
1346 struct sm501_devdata
*sm
;
1349 sm
= kzalloc(sizeof(struct sm501_devdata
), GFP_KERNEL
);
1351 dev_err(&dev
->dev
, "no memory for device data\n");
1356 sm
->dev
= &dev
->dev
;
1357 sm
->pdev_id
= dev
->id
;
1358 sm
->irq
= platform_get_irq(dev
, 0);
1359 sm
->io_res
= platform_get_resource(dev
, IORESOURCE_MEM
, 1);
1360 sm
->mem_res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
1361 sm
->platdata
= dev
->dev
.platform_data
;
1364 dev_err(&dev
->dev
, "failed to get irq resource\n");
1369 if (sm
->io_res
== NULL
|| sm
->mem_res
== NULL
) {
1370 dev_err(&dev
->dev
, "failed to get IO resource\n");
1375 sm
->regs_claim
= request_mem_region(sm
->io_res
->start
,
1378 if (sm
->regs_claim
== NULL
) {
1379 dev_err(&dev
->dev
, "cannot claim registers\n");
1384 platform_set_drvdata(dev
, sm
);
1386 sm
->regs
= ioremap(sm
->io_res
->start
,
1387 (sm
->io_res
->end
- sm
->io_res
->start
) - 1);
1389 if (sm
->regs
== NULL
) {
1390 dev_err(&dev
->dev
, "cannot remap registers\n");
1395 return sm501_init_dev(sm
);
1398 release_resource(sm
->regs_claim
);
1399 kfree(sm
->regs_claim
);
1409 /* power management support */
1411 static void sm501_set_power(struct sm501_devdata
*sm
, int on
)
1413 struct sm501_platdata
*pd
= sm
->platdata
;
1418 if (pd
->get_power
) {
1419 if (pd
->get_power(sm
->dev
) == on
) {
1420 dev_dbg(sm
->dev
, "is already %d\n", on
);
1425 if (pd
->set_power
) {
1426 dev_dbg(sm
->dev
, "setting power to %d\n", on
);
1428 pd
->set_power(sm
->dev
, on
);
1429 sm501_mdelay(sm
, 10);
1433 static int sm501_plat_suspend(struct platform_device
*pdev
, pm_message_t state
)
1435 struct sm501_devdata
*sm
= platform_get_drvdata(pdev
);
1438 sm
->pm_misc
= readl(sm
->regs
+ SM501_MISC_CONTROL
);
1440 sm501_dump_regs(sm
);
1443 if (sm
->platdata
->flags
& SM501_FLAG_SUSPEND_OFF
)
1444 sm501_set_power(sm
, 0);
1450 static int sm501_plat_resume(struct platform_device
*pdev
)
1452 struct sm501_devdata
*sm
= platform_get_drvdata(pdev
);
1454 sm501_set_power(sm
, 1);
1456 sm501_dump_regs(sm
);
1457 sm501_dump_gate(sm
);
1460 /* check to see if we are in the same state as when suspended */
1462 if (readl(sm
->regs
+ SM501_MISC_CONTROL
) != sm
->pm_misc
) {
1463 dev_info(sm
->dev
, "SM501_MISC_CONTROL changed over sleep\n");
1464 writel(sm
->pm_misc
, sm
->regs
+ SM501_MISC_CONTROL
);
1466 /* our suspend causes the controller state to change,
1467 * either by something attempting setup, power loss,
1468 * or an external reset event on power change */
1470 if (sm
->platdata
&& sm
->platdata
->init
) {
1471 sm501_init_regs(sm
, sm
->platdata
->init
);
1475 /* dump our state from resume */
1477 sm501_dump_regs(sm
);
1485 #define sm501_plat_suspend NULL
1486 #define sm501_plat_resume NULL
1489 /* Initialisation data for PCI devices */
1491 static struct sm501_initdata sm501_pci_initdata
= {
1493 .set
= 0x3F000000, /* 24bit panel */
1497 .set
= 0x010100, /* SDRAM timing */
1501 .set
= SM501_MISC_PNL_24BIT
,
1505 .devices
= SM501_USE_ALL
,
1507 /* Errata AB-3 says that 72MHz is the fastest available
1508 * for 33MHZ PCI with proper bus-mastering operation */
1511 .m1xclk
= 144 * MHZ
,
1514 static struct sm501_platdata_fbsub sm501_pdata_fbsub
= {
1515 .flags
= (SM501FB_FLAG_USE_INIT_MODE
|
1516 SM501FB_FLAG_USE_HWCURSOR
|
1517 SM501FB_FLAG_USE_HWACCEL
|
1518 SM501FB_FLAG_DISABLE_AT_EXIT
),
1521 static struct sm501_platdata_fb sm501_fb_pdata
= {
1522 .fb_route
= SM501_FB_OWN
,
1523 .fb_crt
= &sm501_pdata_fbsub
,
1524 .fb_pnl
= &sm501_pdata_fbsub
,
1527 static struct sm501_platdata sm501_pci_platdata
= {
1528 .init
= &sm501_pci_initdata
,
1529 .fb
= &sm501_fb_pdata
,
1533 static int sm501_pci_probe(struct pci_dev
*dev
,
1534 const struct pci_device_id
*id
)
1536 struct sm501_devdata
*sm
;
1539 sm
= kzalloc(sizeof(struct sm501_devdata
), GFP_KERNEL
);
1541 dev_err(&dev
->dev
, "no memory for device data\n");
1546 /* set a default set of platform data */
1547 dev
->dev
.platform_data
= sm
->platdata
= &sm501_pci_platdata
;
1549 /* set a hopefully unique id for our child platform devices */
1550 sm
->pdev_id
= 32 + dev
->devfn
;
1552 pci_set_drvdata(dev
, sm
);
1554 err
= pci_enable_device(dev
);
1556 dev_err(&dev
->dev
, "cannot enable device\n");
1560 sm
->dev
= &dev
->dev
;
1564 /* if the system is big-endian, we most probably have a
1565 * translation in the IO layer making the PCI bus little endian
1566 * so make the framebuffer swapped pixels */
1568 sm501_fb_pdata
.flags
|= SM501_FBPD_SWAP_FB_ENDIAN
;
1571 /* check our resources */
1573 if (!(pci_resource_flags(dev
, 0) & IORESOURCE_MEM
)) {
1574 dev_err(&dev
->dev
, "region #0 is not memory?\n");
1579 if (!(pci_resource_flags(dev
, 1) & IORESOURCE_MEM
)) {
1580 dev_err(&dev
->dev
, "region #1 is not memory?\n");
1585 /* make our resources ready for sharing */
1587 sm
->io_res
= &dev
->resource
[1];
1588 sm
->mem_res
= &dev
->resource
[0];
1590 sm
->regs_claim
= request_mem_region(sm
->io_res
->start
,
1592 if (sm
->regs_claim
== NULL
) {
1593 dev_err(&dev
->dev
, "cannot claim registers\n");
1598 sm
->regs
= ioremap(pci_resource_start(dev
, 1),
1599 pci_resource_len(dev
, 1));
1601 if (sm
->regs
== NULL
) {
1602 dev_err(&dev
->dev
, "cannot remap registers\n");
1611 release_resource(sm
->regs_claim
);
1612 kfree(sm
->regs_claim
);
1614 pci_disable_device(dev
);
1616 pci_set_drvdata(dev
, NULL
);
1622 static void sm501_remove_sub(struct sm501_devdata
*sm
,
1623 struct sm501_device
*smdev
)
1625 list_del(&smdev
->list
);
1626 platform_device_unregister(&smdev
->pdev
);
1629 static void sm501_dev_remove(struct sm501_devdata
*sm
)
1631 struct sm501_device
*smdev
, *tmp
;
1633 list_for_each_entry_safe(smdev
, tmp
, &sm
->devices
, list
)
1634 sm501_remove_sub(sm
, smdev
);
1636 device_remove_file(sm
->dev
, &dev_attr_dbg_regs
);
1638 if (sm
->gpio
.registered
)
1639 sm501_gpio_remove(sm
);
1642 static void sm501_pci_remove(struct pci_dev
*dev
)
1644 struct sm501_devdata
*sm
= pci_get_drvdata(dev
);
1646 sm501_dev_remove(sm
);
1649 release_resource(sm
->regs_claim
);
1650 kfree(sm
->regs_claim
);
1652 pci_set_drvdata(dev
, NULL
);
1653 pci_disable_device(dev
);
1656 static int sm501_plat_remove(struct platform_device
*dev
)
1658 struct sm501_devdata
*sm
= platform_get_drvdata(dev
);
1660 sm501_dev_remove(sm
);
1663 release_resource(sm
->regs_claim
);
1664 kfree(sm
->regs_claim
);
1669 static struct pci_device_id sm501_pci_tbl
[] = {
1670 { 0x126f, 0x0501, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
1674 MODULE_DEVICE_TABLE(pci
, sm501_pci_tbl
);
1676 static struct pci_driver sm501_pci_drv
= {
1678 .id_table
= sm501_pci_tbl
,
1679 .probe
= sm501_pci_probe
,
1680 .remove
= sm501_pci_remove
,
1683 MODULE_ALIAS("platform:sm501");
1685 static struct platform_driver sm501_plat_drv
= {
1688 .owner
= THIS_MODULE
,
1690 .probe
= sm501_plat_probe
,
1691 .remove
= sm501_plat_remove
,
1692 .suspend
= sm501_plat_suspend
,
1693 .resume
= sm501_plat_resume
,
1696 static int __init
sm501_base_init(void)
1698 platform_driver_register(&sm501_plat_drv
);
1699 return pci_register_driver(&sm501_pci_drv
);
1702 static void __exit
sm501_base_exit(void)
1704 platform_driver_unregister(&sm501_plat_drv
);
1705 pci_unregister_driver(&sm501_pci_drv
);
1708 module_init(sm501_base_init
);
1709 module_exit(sm501_base_exit
);
1711 MODULE_DESCRIPTION("SM501 Core Driver");
1712 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1713 MODULE_LICENSE("GPL v2");