?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/pvops: add a paravirt_ident functions to allow special patching
[linux-2.6/mini2440.git] / arch / x86 / include / asm / paravirt.h
blob961d10c12f16c1efda86be90b20d4411e56e69b4
1 #ifndef _ASM_X86_PARAVIRT_H
2 #define _ASM_X86_PARAVIRT_H
3 /* Various instructions on x86 need to be replaced for
4 * para-virtualization: those hooks are defined here. */
5
6 #ifdef CONFIG_PARAVIRT
7 #include <asm/page.h>
8 #include <asm/asm.h>
9
10 /* Bitmask of what can be clobbered: usually at least eax. */
11 #define CLBR_NONE 0
12 #define CLBR_EAX (1 << 0)
13 #define CLBR_ECX (1 << 1)
14 #define CLBR_EDX (1 << 2)
15
16 #ifdef CONFIG_X86_64
17 #define CLBR_RSI (1 << 3)
18 #define CLBR_RDI (1 << 4)
19 #define CLBR_R8 (1 << 5)
20 #define CLBR_R9 (1 << 6)
21 #define CLBR_R10 (1 << 7)
22 #define CLBR_R11 (1 << 8)
23 #define CLBR_ANY ((1 << 9) - 1)
24 #include <asm/desc_defs.h>
25 #else
26 /* CLBR_ANY should match all regs platform has. For i386, that's just it */
27 #define CLBR_ANY ((1 << 3) - 1)
28 #endif /* X86_64 */
29
30 #ifndef __ASSEMBLY__
31 #include <linux/types.h>
32 #include <linux/cpumask.h>
33 #include <asm/kmap_types.h>
34 #include <asm/desc_defs.h>
35
36 struct page;
37 struct thread_struct;
38 struct desc_ptr;
39 struct tss_struct;
40 struct mm_struct;
41 struct desc_struct;
42
43 /* general info */
44 struct pv_info {
45 unsigned int kernel_rpl;
46 int shared_kernel_pmd;
47 int paravirt_enabled;
48 const char *name;
49 };
50
51 struct pv_init_ops {
52 /*
53 * Patch may replace one of the defined code sequences with
54 * arbitrary code, subject to the same register constraints.
55 * This generally means the code is not free to clobber any
56 * registers other than EAX. The patch function should return
57 * the number of bytes of code generated, as we nop pad the
58 * rest in generic code.
59 */
60 unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
61 unsigned long addr, unsigned len);
62
63 /* Basic arch-specific setup */
64 void (*arch_setup)(void);
65 char *(*memory_setup)(void);
66 void (*post_allocator_init)(void);
67
68 /* Print a banner to identify the environment */
69 void (*banner)(void);
70 };
71
72
73 struct pv_lazy_ops {
74 /* Set deferred update mode, used for batching operations. */
75 void (*enter)(void);
76 void (*leave)(void);
77 };
78
79 struct pv_time_ops {
80 void (*time_init)(void);
81
82 /* Set and set time of day */
83 unsigned long (*get_wallclock)(void);
84 int (*set_wallclock)(unsigned long);
85
86 unsigned long long (*sched_clock)(void);
87 unsigned long (*get_tsc_khz)(void);
88 };
89
90 struct pv_cpu_ops {
91 /* hooks for various privileged instructions */
92 unsigned long (*get_debugreg)(int regno);
93 void (*set_debugreg)(int regno, unsigned long value);
94
95 void (*clts)(void);
96
97 unsigned long (*read_cr0)(void);
98 void (*write_cr0)(unsigned long);
99
100 unsigned long (*read_cr4_safe)(void);
101 unsigned long (*read_cr4)(void);
102 void (*write_cr4)(unsigned long);
103
104 #ifdef CONFIG_X86_64
105 unsigned long (*read_cr8)(void);
106 void (*write_cr8)(unsigned long);
107 #endif
108
109 /* Segment descriptor handling */
110 void (*load_tr_desc)(void);
111 void (*load_gdt)(const struct desc_ptr *);
112 void (*load_idt)(const struct desc_ptr *);
113 void (*store_gdt)(struct desc_ptr *);
114 void (*store_idt)(struct desc_ptr *);
115 void (*set_ldt)(const void *desc, unsigned entries);
116 unsigned long (*store_tr)(void);
117 void (*load_tls)(struct thread_struct *t, unsigned int cpu);
118 #ifdef CONFIG_X86_64
119 void (*load_gs_index)(unsigned int idx);
120 #endif
121 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
122 const void *desc);
123 void (*write_gdt_entry)(struct desc_struct *,
124 int entrynum, const void *desc, int size);
125 void (*write_idt_entry)(gate_desc *,
126 int entrynum, const gate_desc *gate);
127 void (*alloc_ldt)(struct desc_struct *ldt, unsigned entries);
128 void (*free_ldt)(struct desc_struct *ldt, unsigned entries);
129
130 void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
131
132 void (*set_iopl_mask)(unsigned mask);
133
134 void (*wbinvd)(void);
135 void (*io_delay)(void);
136
137 /* cpuid emulation, mostly so that caps bits can be disabled */
138 void (*cpuid)(unsigned int *eax, unsigned int *ebx,
139 unsigned int *ecx, unsigned int *edx);
140
141 /* MSR, PMC and TSR operations.
142 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */
143 u64 (*read_msr_amd)(unsigned int msr, int *err);
144 u64 (*read_msr)(unsigned int msr, int *err);
145 int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
146
147 u64 (*read_tsc)(void);
148 u64 (*read_pmc)(int counter);
149 unsigned long long (*read_tscp)(unsigned int *aux);
150
151 /*
152 * Atomically enable interrupts and return to userspace. This
153 * is only ever used to return to 32-bit processes; in a
154 * 64-bit kernel, it's used for 32-on-64 compat processes, but
155 * never native 64-bit processes. (Jump, not call.)
156 */
157 void (*irq_enable_sysexit)(void);
158
159 /*
160 * Switch to usermode gs and return to 64-bit usermode using
161 * sysret. Only used in 64-bit kernels to return to 64-bit
162 * processes. Usermode register state, including %rsp, must
163 * already be restored.
164 */
165 void (*usergs_sysret64)(void);
166
167 /*
168 * Switch to usermode gs and return to 32-bit usermode using
169 * sysret. Used to return to 32-on-64 compat processes.
170 * Other usermode register state, including %esp, must already
171 * be restored.
172 */
173 void (*usergs_sysret32)(void);
174
175 /* Normal iret. Jump to this with the standard iret stack
176 frame set up. */
177 void (*iret)(void);
178
179 void (*swapgs)(void);
180
181 struct pv_lazy_ops lazy_mode;
182 };
183
184 struct pv_irq_ops {
185 void (*init_IRQ)(void);
186
187 /*
188 * Get/set interrupt state. save_fl and restore_fl are only
189 * expected to use X86_EFLAGS_IF; all other bits
190 * returned from save_fl are undefined, and may be ignored by
191 * restore_fl.
192 */
193 unsigned long (*save_fl)(void);
194 void (*restore_fl)(unsigned long);
195 void (*irq_disable)(void);
196 void (*irq_enable)(void);
197 void (*safe_halt)(void);
198 void (*halt)(void);
199
200 #ifdef CONFIG_X86_64
201 void (*adjust_exception_frame)(void);
202 #endif
203 };
204
205 struct pv_apic_ops {
206 #ifdef CONFIG_X86_LOCAL_APIC
207 void (*setup_boot_clock)(void);
208 void (*setup_secondary_clock)(void);
209
210 void (*startup_ipi_hook)(int phys_apicid,
211 unsigned long start_eip,
212 unsigned long start_esp);
213 #endif
214 };
215
216 struct pv_mmu_ops {
217 /*
218 * Called before/after init_mm pagetable setup. setup_start
219 * may reset %cr3, and may pre-install parts of the pagetable;
220 * pagetable setup is expected to preserve any existing
221 * mapping.
222 */
223 void (*pagetable_setup_start)(pgd_t *pgd_base);
224 void (*pagetable_setup_done)(pgd_t *pgd_base);
225
226 unsigned long (*read_cr2)(void);
227 void (*write_cr2)(unsigned long);
228
229 unsigned long (*read_cr3)(void);
230 void (*write_cr3)(unsigned long);
231
232 /*
233 * Hooks for intercepting the creation/use/destruction of an
234 * mm_struct.
235 */
236 void (*activate_mm)(struct mm_struct *prev,
237 struct mm_struct *next);
238 void (*dup_mmap)(struct mm_struct *oldmm,
239 struct mm_struct *mm);
240 void (*exit_mmap)(struct mm_struct *mm);
241
242
243 /* TLB operations */
244 void (*flush_tlb_user)(void);
245 void (*flush_tlb_kernel)(void);
246 void (*flush_tlb_single)(unsigned long addr);
247 void (*flush_tlb_others)(const struct cpumask *cpus,
248 struct mm_struct *mm,
249 unsigned long va);
250
251 /* Hooks for allocating and freeing a pagetable top-level */
252 int (*pgd_alloc)(struct mm_struct *mm);
253 void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd);
254
255 /*
256 * Hooks for allocating/releasing pagetable pages when they're
257 * attached to a pagetable
258 */
259 void (*alloc_pte)(struct mm_struct *mm, unsigned long pfn);
260 void (*alloc_pmd)(struct mm_struct *mm, unsigned long pfn);
261 void (*alloc_pmd_clone)(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count);
262 void (*alloc_pud)(struct mm_struct *mm, unsigned long pfn);
263 void (*release_pte)(unsigned long pfn);
264 void (*release_pmd)(unsigned long pfn);
265 void (*release_pud)(unsigned long pfn);
266
267 /* Pagetable manipulation functions */
268 void (*set_pte)(pte_t *ptep, pte_t pteval);
269 void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
270 pte_t *ptep, pte_t pteval);
271 void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
272 void (*pte_update)(struct mm_struct *mm, unsigned long addr,
273 pte_t *ptep);
274 void (*pte_update_defer)(struct mm_struct *mm,
275 unsigned long addr, pte_t *ptep);
276
277 pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr,
278 pte_t *ptep);
279 void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr,
280 pte_t *ptep, pte_t pte);
281
282 pteval_t (*pte_val)(pte_t);
283 pte_t (*make_pte)(pteval_t pte);
284
285 pgdval_t (*pgd_val)(pgd_t);
286 pgd_t (*make_pgd)(pgdval_t pgd);
287
288 #if PAGETABLE_LEVELS >= 3
289 #ifdef CONFIG_X86_PAE
290 void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
291 void (*set_pte_present)(struct mm_struct *mm, unsigned long addr,
292 pte_t *ptep, pte_t pte);
293 void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
294 pte_t *ptep);
295 void (*pmd_clear)(pmd_t *pmdp);
296
297 #endif /* CONFIG_X86_PAE */
298
299 void (*set_pud)(pud_t *pudp, pud_t pudval);
300
301 pmdval_t (*pmd_val)(pmd_t);
302 pmd_t (*make_pmd)(pmdval_t pmd);
303
304 #if PAGETABLE_LEVELS == 4
305 pudval_t (*pud_val)(pud_t);
306 pud_t (*make_pud)(pudval_t pud);
307
308 void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
309 #endif /* PAGETABLE_LEVELS == 4 */
310 #endif /* PAGETABLE_LEVELS >= 3 */
311
312 #ifdef CONFIG_HIGHPTE
313 void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
314 #endif
315
316 struct pv_lazy_ops lazy_mode;
317
318 /* dom0 ops */
319
320 /* Sometimes the physical address is a pfn, and sometimes its
321 an mfn. We can tell which is which from the index. */
322 void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx,
323 unsigned long phys, pgprot_t flags);
324 };
325
326 struct raw_spinlock;
327 struct pv_lock_ops {
328 int (*spin_is_locked)(struct raw_spinlock *lock);
329 int (*spin_is_contended)(struct raw_spinlock *lock);
330 void (*spin_lock)(struct raw_spinlock *lock);
331 void (*spin_lock_flags)(struct raw_spinlock *lock, unsigned long flags);
332 int (*spin_trylock)(struct raw_spinlock *lock);
333 void (*spin_unlock)(struct raw_spinlock *lock);
334 };
335
336 /* This contains all the paravirt structures: we get a convenient
337 * number for each function using the offset which we use to indicate
338 * what to patch. */
339 struct paravirt_patch_template {
340 struct pv_init_ops pv_init_ops;
341 struct pv_time_ops pv_time_ops;
342 struct pv_cpu_ops pv_cpu_ops;
343 struct pv_irq_ops pv_irq_ops;
344 struct pv_apic_ops pv_apic_ops;
345 struct pv_mmu_ops pv_mmu_ops;
346 struct pv_lock_ops pv_lock_ops;
347 };
348
349 extern struct pv_info pv_info;
350 extern struct pv_init_ops pv_init_ops;
351 extern struct pv_time_ops pv_time_ops;
352 extern struct pv_cpu_ops pv_cpu_ops;
353 extern struct pv_irq_ops pv_irq_ops;
354 extern struct pv_apic_ops pv_apic_ops;
355 extern struct pv_mmu_ops pv_mmu_ops;
356 extern struct pv_lock_ops pv_lock_ops;
357
358 #define PARAVIRT_PATCH(x) \
359 (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
360
361 #define paravirt_type(op) \
362 [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \
363 [paravirt_opptr] "m" (op)
364 #define paravirt_clobber(clobber) \
365 [paravirt_clobber] "i" (clobber)
366
367 /*
368 * Generate some code, and mark it as patchable by the
369 * apply_paravirt() alternate instruction patcher.
370 */
371 #define _paravirt_alt(insn_string, type, clobber) \
372 "771:\n\t" insn_string "\n" "772:\n" \
373 ".pushsection .parainstructions,\"a\"\n" \
374 _ASM_ALIGN "\n" \
375 _ASM_PTR " 771b\n" \
376 " .byte " type "\n" \
377 " .byte 772b-771b\n" \
378 " .short " clobber "\n" \
379 ".popsection\n"
380
381 /* Generate patchable code, with the default asm parameters. */
382 #define paravirt_alt(insn_string) \
383 _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
384
385 /* Simple instruction patching code. */
386 #define DEF_NATIVE(ops, name, code) \
387 extern const char start_##ops##_##name[], end_##ops##_##name[]; \
388 asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
389
390 unsigned paravirt_patch_nop(void);
391 unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len);
392 unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len);
393 unsigned paravirt_patch_ignore(unsigned len);
394 unsigned paravirt_patch_call(void *insnbuf,
395 const void *target, u16 tgt_clobbers,
396 unsigned long addr, u16 site_clobbers,
397 unsigned len);
398 unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
399 unsigned long addr, unsigned len);
400 unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
401 unsigned long addr, unsigned len);
402
403 unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
404 const char *start, const char *end);
405
406 unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
407 unsigned long addr, unsigned len);
408
409 int paravirt_disable_iospace(void);
410
411 /*
412 * This generates an indirect call based on the operation type number.
413 * The type number, computed in PARAVIRT_PATCH, is derived from the
414 * offset into the paravirt_patch_template structure, and can therefore be
415 * freely converted back into a structure offset.
416 */
417 #define PARAVIRT_CALL "call *%[paravirt_opptr];"
418
419 /*
420 * These macros are intended to wrap calls through one of the paravirt
421 * ops structs, so that they can be later identified and patched at
422 * runtime.
423 *
424 * Normally, a call to a pv_op function is a simple indirect call:
425 * (pv_op_struct.operations)(args...).
426 *
427 * Unfortunately, this is a relatively slow operation for modern CPUs,
428 * because it cannot necessarily determine what the destination
429 * address is. In this case, the address is a runtime constant, so at
430 * the very least we can patch the call to e a simple direct call, or
431 * ideally, patch an inline implementation into the callsite. (Direct
432 * calls are essentially free, because the call and return addresses
433 * are completely predictable.)
434 *
435 * For i386, these macros rely on the standard gcc "regparm(3)" calling
436 * convention, in which the first three arguments are placed in %eax,
437 * %edx, %ecx (in that order), and the remaining arguments are placed
438 * on the stack. All caller-save registers (eax,edx,ecx) are expected
439 * to be modified (either clobbered or used for return values).
440 * X86_64, on the other hand, already specifies a register-based calling
441 * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
442 * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
443 * special handling for dealing with 4 arguments, unlike i386.
444 * However, x86_64 also have to clobber all caller saved registers, which
445 * unfortunately, are quite a bit (r8 - r11)
446 *
447 * The call instruction itself is marked by placing its start address
448 * and size into the .parainstructions section, so that
449 * apply_paravirt() in arch/i386/kernel/alternative.c can do the
450 * appropriate patching under the control of the backend pv_init_ops
451 * implementation.
452 *
453 * Unfortunately there's no way to get gcc to generate the args setup
454 * for the call, and then allow the call itself to be generated by an
455 * inline asm. Because of this, we must do the complete arg setup and
456 * return value handling from within these macros. This is fairly
457 * cumbersome.
458 *
459 * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
460 * It could be extended to more arguments, but there would be little
461 * to be gained from that. For each number of arguments, there are
462 * the two VCALL and CALL variants for void and non-void functions.
463 *
464 * When there is a return value, the invoker of the macro must specify
465 * the return type. The macro then uses sizeof() on that type to
466 * determine whether its a 32 or 64 bit value, and places the return
467 * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
468 * 64-bit). For x86_64 machines, it just returns at %rax regardless of
469 * the return value size.
470 *
471 * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
472 * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
473 * in low,high order
474 *
475 * Small structures are passed and returned in registers. The macro
476 * calling convention can't directly deal with this, so the wrapper
477 * functions must do this.
478 *
479 * These PVOP_* macros are only defined within this header. This
480 * means that all uses must be wrapped in inline functions. This also
481 * makes sure the incoming and outgoing types are always correct.
482 */
483 #ifdef CONFIG_X86_32
484 #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx
485 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS
486 #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \
487 "=c" (__ecx)
488 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS
489 #define EXTRA_CLOBBERS
490 #define VEXTRA_CLOBBERS
491 #else
492 #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx
493 #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax
494 #define PVOP_VCALL_CLOBBERS "=D" (__edi), \
495 "=S" (__esi), "=d" (__edx), \
496 "=c" (__ecx)
497
498 #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax)
499
500 #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11"
501 #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
502 #endif
503
504 #ifdef CONFIG_PARAVIRT_DEBUG
505 #define PVOP_TEST_NULL(op) BUG_ON(op == NULL)
506 #else
507 #define PVOP_TEST_NULL(op) ((void)op)
508 #endif
509
510 #define __PVOP_CALL(rettype, op, pre, post, ...) \
511 ({ \
512 rettype __ret; \
513 PVOP_CALL_ARGS; \
514 PVOP_TEST_NULL(op); \
515 /* This is 32-bit specific, but is okay in 64-bit */ \
516 /* since this condition will never hold */ \
517 if (sizeof(rettype) > sizeof(unsigned long)) { \
518 asm volatile(pre \
519 paravirt_alt(PARAVIRT_CALL) \
520 post \
521 : PVOP_CALL_CLOBBERS \
522 : paravirt_type(op), \
523 paravirt_clobber(CLBR_ANY), \
524 ##__VA_ARGS__ \
525 : "memory", "cc" EXTRA_CLOBBERS); \
526 __ret = (rettype)((((u64)__edx) << 32) | __eax); \
527 } else { \
528 asm volatile(pre \
529 paravirt_alt(PARAVIRT_CALL) \
530 post \
531 : PVOP_CALL_CLOBBERS \
532 : paravirt_type(op), \
533 paravirt_clobber(CLBR_ANY), \
534 ##__VA_ARGS__ \
535 : "memory", "cc" EXTRA_CLOBBERS); \
536 __ret = (rettype)__eax; \
537 } \
538 __ret; \
539 })
540 #define __PVOP_VCALL(op, pre, post, ...) \
541 ({ \
542 PVOP_VCALL_ARGS; \
543 PVOP_TEST_NULL(op); \
544 asm volatile(pre \
545 paravirt_alt(PARAVIRT_CALL) \
546 post \
547 : PVOP_VCALL_CLOBBERS \
548 : paravirt_type(op), \
549 paravirt_clobber(CLBR_ANY), \
550 ##__VA_ARGS__ \
551 : "memory", "cc" VEXTRA_CLOBBERS); \
552 })
553
554 #define PVOP_CALL0(rettype, op) \
555 __PVOP_CALL(rettype, op, "", "")
556 #define PVOP_VCALL0(op) \
557 __PVOP_VCALL(op, "", "")
558
559 #define PVOP_CALL1(rettype, op, arg1) \
560 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)))
561 #define PVOP_VCALL1(op, arg1) \
562 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)))
563
564 #define PVOP_CALL2(rettype, op, arg1, arg2) \
565 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
566 "1" ((unsigned long)(arg2)))
567 #define PVOP_VCALL2(op, arg1, arg2) \
568 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
569 "1" ((unsigned long)(arg2)))
570
571 #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \
572 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
573 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
574 #define PVOP_VCALL3(op, arg1, arg2, arg3) \
575 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
576 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)))
577
578 /* This is the only difference in x86_64. We can make it much simpler */
579 #ifdef CONFIG_X86_32
580 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
581 __PVOP_CALL(rettype, op, \
582 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
583 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
584 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
585 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
586 __PVOP_VCALL(op, \
587 "push %[_arg4];", "lea 4(%%esp),%%esp;", \
588 "0" ((u32)(arg1)), "1" ((u32)(arg2)), \
589 "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
590 #else
591 #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \
592 __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \
593 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
594 "3"((unsigned long)(arg4)))
595 #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \
596 __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \
597 "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \
598 "3"((unsigned long)(arg4)))
599 #endif
600
601 static inline int paravirt_enabled(void)
602 {
603 return pv_info.paravirt_enabled;
604 }
605
606 static inline void load_sp0(struct tss_struct *tss,
607 struct thread_struct *thread)
608 {
609 PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread);
610 }
611
612 #define ARCH_SETUP pv_init_ops.arch_setup();
613 static inline unsigned long get_wallclock(void)
614 {
615 return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock);
616 }
617
618 static inline int set_wallclock(unsigned long nowtime)
619 {
620 return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime);
621 }
622
623 static inline void (*choose_time_init(void))(void)
624 {
625 return pv_time_ops.time_init;
626 }
627
628 /* The paravirtualized CPUID instruction. */
629 static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
630 unsigned int *ecx, unsigned int *edx)
631 {
632 PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx);
633 }
634
635 /*
636 * These special macros can be used to get or set a debugging register
637 */
638 static inline unsigned long paravirt_get_debugreg(int reg)
639 {
640 return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg);
641 }
642 #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg)
643 static inline void set_debugreg(unsigned long val, int reg)
644 {
645 PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val);
646 }
647
648 static inline void clts(void)
649 {
650 PVOP_VCALL0(pv_cpu_ops.clts);
651 }
652
653 static inline unsigned long read_cr0(void)
654 {
655 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0);
656 }
657
658 static inline void write_cr0(unsigned long x)
659 {
660 PVOP_VCALL1(pv_cpu_ops.write_cr0, x);
661 }
662
663 static inline unsigned long read_cr2(void)
664 {
665 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2);
666 }
667
668 static inline void write_cr2(unsigned long x)
669 {
670 PVOP_VCALL1(pv_mmu_ops.write_cr2, x);
671 }
672
673 static inline unsigned long read_cr3(void)
674 {
675 return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3);
676 }
677
678 static inline void write_cr3(unsigned long x)
679 {
680 PVOP_VCALL1(pv_mmu_ops.write_cr3, x);
681 }
682
683 static inline unsigned long read_cr4(void)
684 {
685 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);
686 }
687 static inline unsigned long read_cr4_safe(void)
688 {
689 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);
690 }
691
692 static inline void write_cr4(unsigned long x)
693 {
694 PVOP_VCALL1(pv_cpu_ops.write_cr4, x);
695 }
696
697 #ifdef CONFIG_X86_64
698 static inline unsigned long read_cr8(void)
699 {
700 return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8);
701 }
702
703 static inline void write_cr8(unsigned long x)
704 {
705 PVOP_VCALL1(pv_cpu_ops.write_cr8, x);
706 }
707 #endif
708
709 static inline void raw_safe_halt(void)
710 {
711 PVOP_VCALL0(pv_irq_ops.safe_halt);
712 }
713
714 static inline void halt(void)
715 {
716 PVOP_VCALL0(pv_irq_ops.safe_halt);
717 }
718
719 static inline void wbinvd(void)
720 {
721 PVOP_VCALL0(pv_cpu_ops.wbinvd);
722 }
723
724 #define get_kernel_rpl() (pv_info.kernel_rpl)
725
726 static inline u64 paravirt_read_msr(unsigned msr, int *err)
727 {
728 return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
729 }
730 static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
731 {
732 return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
733 }
734 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
735 {
736 return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
737 }
738
739 /* These should all do BUG_ON(_err), but our headers are too tangled. */
740 #define rdmsr(msr, val1, val2) \
741 do { \
742 int _err; \
743 u64 _l = paravirt_read_msr(msr, &_err); \
744 val1 = (u32)_l; \
745 val2 = _l >> 32; \
746 } while (0)
747
748 #define wrmsr(msr, val1, val2) \
749 do { \
750 paravirt_write_msr(msr, val1, val2); \
751 } while (0)
752
753 #define rdmsrl(msr, val) \
754 do { \
755 int _err; \
756 val = paravirt_read_msr(msr, &_err); \
757 } while (0)
758
759 #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32)
760 #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b)
761
762 /* rdmsr with exception handling */
763 #define rdmsr_safe(msr, a, b) \
764 ({ \
765 int _err; \
766 u64 _l = paravirt_read_msr(msr, &_err); \
767 (*a) = (u32)_l; \
768 (*b) = _l >> 32; \
769 _err; \
770 })
771
772 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
773 {
774 int err;
775
776 *p = paravirt_read_msr(msr, &err);
777 return err;
778 }
779 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
780 {
781 int err;
782
783 *p = paravirt_read_msr_amd(msr, &err);
784 return err;
785 }
786
787 static inline u64 paravirt_read_tsc(void)
788 {
789 return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
790 }
791
792 #define rdtscl(low) \
793 do { \
794 u64 _l = paravirt_read_tsc(); \
795 low = (int)_l; \
796 } while (0)
797
798 #define rdtscll(val) (val = paravirt_read_tsc())
799
800 static inline unsigned long long paravirt_sched_clock(void)
801 {
802 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
803 }
804 #define calibrate_tsc() (pv_time_ops.get_tsc_khz())
805
806 static inline unsigned long long paravirt_read_pmc(int counter)
807 {
808 return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter);
809 }
810
811 #define rdpmc(counter, low, high) \
812 do { \
813 u64 _l = paravirt_read_pmc(counter); \
814 low = (u32)_l; \
815 high = _l >> 32; \
816 } while (0)
817
818 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
819 {
820 return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
821 }
822
823 #define rdtscp(low, high, aux) \
824 do { \
825 int __aux; \
826 unsigned long __val = paravirt_rdtscp(&__aux); \
827 (low) = (u32)__val; \
828 (high) = (u32)(__val >> 32); \
829 (aux) = __aux; \
830 } while (0)
831
832 #define rdtscpll(val, aux) \
833 do { \
834 unsigned long __aux; \
835 val = paravirt_rdtscp(&__aux); \
836 (aux) = __aux; \
837 } while (0)
838
839 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
840 {
841 PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
842 }
843
844 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
845 {
846 PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
847 }
848
849 static inline void load_TR_desc(void)
850 {
851 PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
852 }
853 static inline void load_gdt(const struct desc_ptr *dtr)
854 {
855 PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr);
856 }
857 static inline void load_idt(const struct desc_ptr *dtr)
858 {
859 PVOP_VCALL1(pv_cpu_ops.load_idt, dtr);
860 }
861 static inline void set_ldt(const void *addr, unsigned entries)
862 {
863 PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries);
864 }
865 static inline void store_gdt(struct desc_ptr *dtr)
866 {
867 PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr);
868 }
869 static inline void store_idt(struct desc_ptr *dtr)
870 {
871 PVOP_VCALL1(pv_cpu_ops.store_idt, dtr);
872 }
873 static inline unsigned long paravirt_store_tr(void)
874 {
875 return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr);
876 }
877 #define store_tr(tr) ((tr) = paravirt_store_tr())
878 static inline void load_TLS(struct thread_struct *t, unsigned cpu)
879 {
880 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
881 }
882
883 #ifdef CONFIG_X86_64
884 static inline void load_gs_index(unsigned int gs)
885 {
886 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
887 }
888 #endif
889
890 static inline void write_ldt_entry(struct desc_struct *dt, int entry,
891 const void *desc)
892 {
893 PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc);
894 }
895
896 static inline void write_gdt_entry(struct desc_struct *dt, int entry,
897 void *desc, int type)
898 {
899 PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type);
900 }
901
902 static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g)
903 {
904 PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g);
905 }
906 static inline void set_iopl_mask(unsigned mask)
907 {
908 PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask);
909 }
910
911 /* The paravirtualized I/O functions */
912 static inline void slow_down_io(void)
913 {
914 pv_cpu_ops.io_delay();
915 #ifdef REALLY_SLOW_IO
916 pv_cpu_ops.io_delay();
917 pv_cpu_ops.io_delay();
918 pv_cpu_ops.io_delay();
919 #endif
920 }
921
922 #ifdef CONFIG_X86_LOCAL_APIC
923 static inline void setup_boot_clock(void)
924 {
925 PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
926 }
927
928 static inline void setup_secondary_clock(void)
929 {
930 PVOP_VCALL0(pv_apic_ops.setup_secondary_clock);
931 }
932 #endif
933
934 static inline void paravirt_post_allocator_init(void)
935 {
936 if (pv_init_ops.post_allocator_init)
937 (*pv_init_ops.post_allocator_init)();
938 }
939
940 static inline void paravirt_pagetable_setup_start(pgd_t *base)
941 {
942 (*pv_mmu_ops.pagetable_setup_start)(base);
943 }
944
945 static inline void paravirt_pagetable_setup_done(pgd_t *base)
946 {
947 (*pv_mmu_ops.pagetable_setup_done)(base);
948 }
949
950 #ifdef CONFIG_SMP
951 static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip,
952 unsigned long start_esp)
953 {
954 PVOP_VCALL3(pv_apic_ops.startup_ipi_hook,
955 phys_apicid, start_eip, start_esp);
956 }
957 #endif
958
959 static inline void paravirt_activate_mm(struct mm_struct *prev,
960 struct mm_struct *next)
961 {
962 PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next);
963 }
964
965 static inline void arch_dup_mmap(struct mm_struct *oldmm,
966 struct mm_struct *mm)
967 {
968 PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm);
969 }
970
971 static inline void arch_exit_mmap(struct mm_struct *mm)
972 {
973 PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm);
974 }
975
976 static inline void __flush_tlb(void)
977 {
978 PVOP_VCALL0(pv_mmu_ops.flush_tlb_user);
979 }
980 static inline void __flush_tlb_global(void)
981 {
982 PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel);
983 }
984 static inline void __flush_tlb_single(unsigned long addr)
985 {
986 PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr);
987 }
988
989 static inline void flush_tlb_others(const struct cpumask *cpumask,
990 struct mm_struct *mm,
991 unsigned long va)
992 {
993 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, cpumask, mm, va);
994 }
995
996 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
997 {
998 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
999 }
1000
1001 static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
1002 {
1003 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
1004 }
1005
1006 static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
1007 {
1008 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
1009 }
1010 static inline void paravirt_release_pte(unsigned long pfn)
1011 {
1012 PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
1013 }
1014
1015 static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
1016 {
1017 PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
1018 }
1019
1020 static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
1021 unsigned long start, unsigned long count)
1022 {
1023 PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
1024 }
1025 static inline void paravirt_release_pmd(unsigned long pfn)
1026 {
1027 PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
1028 }
1029
1030 static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
1031 {
1032 PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
1033 }
1034 static inline void paravirt_release_pud(unsigned long pfn)
1035 {
1036 PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
1037 }
1038
1039 #ifdef CONFIG_HIGHPTE
1040 static inline void *kmap_atomic_pte(struct page *page, enum km_type type)
1041 {
1042 unsigned long ret;
1043 ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type);
1044 return (void *)ret;
1045 }
1046 #endif
1047
1048 static inline void pte_update(struct mm_struct *mm, unsigned long addr,
1049 pte_t *ptep)
1050 {
1051 PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep);
1052 }
1053
1054 static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr,
1055 pte_t *ptep)
1056 {
1057 PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep);
1058 }
1059
1060 static inline pte_t __pte(pteval_t val)
1061 {
1062 pteval_t ret;
1063
1064 if (sizeof(pteval_t) > sizeof(long))
1065 ret = PVOP_CALL2(pteval_t,
1066 pv_mmu_ops.make_pte,
1067 val, (u64)val >> 32);
1068 else
1069 ret = PVOP_CALL1(pteval_t,
1070 pv_mmu_ops.make_pte,
1071 val);
1072
1073 return (pte_t) { .pte = ret };
1074 }
1075
1076 static inline pteval_t pte_val(pte_t pte)
1077 {
1078 pteval_t ret;
1079
1080 if (sizeof(pteval_t) > sizeof(long))
1081 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val,
1082 pte.pte, (u64)pte.pte >> 32);
1083 else
1084 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val,
1085 pte.pte);
1086
1087 return ret;
1088 }
1089
1090 static inline pgd_t __pgd(pgdval_t val)
1091 {
1092 pgdval_t ret;
1093
1094 if (sizeof(pgdval_t) > sizeof(long))
1095 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd,
1096 val, (u64)val >> 32);
1097 else
1098 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd,
1099 val);
1100
1101 return (pgd_t) { ret };
1102 }
1103
1104 static inline pgdval_t pgd_val(pgd_t pgd)
1105 {
1106 pgdval_t ret;
1107
1108 if (sizeof(pgdval_t) > sizeof(long))
1109 ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val,
1110 pgd.pgd, (u64)pgd.pgd >> 32);
1111 else
1112 ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val,
1113 pgd.pgd);
1114
1115 return ret;
1116 }
1117
1118 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1119 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
1120 pte_t *ptep)
1121 {
1122 pteval_t ret;
1123
1124 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
1125 mm, addr, ptep);
1126
1127 return (pte_t) { .pte = ret };
1128 }
1129
1130 static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
1131 pte_t *ptep, pte_t pte)
1132 {
1133 if (sizeof(pteval_t) > sizeof(long))
1134 /* 5 arg words */
1135 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
1136 else
1137 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
1138 mm, addr, ptep, pte.pte);
1139 }
1140
1141 static inline void set_pte(pte_t *ptep, pte_t pte)
1142 {
1143 if (sizeof(pteval_t) > sizeof(long))
1144 PVOP_VCALL3(pv_mmu_ops.set_pte, ptep,
1145 pte.pte, (u64)pte.pte >> 32);
1146 else
1147 PVOP_VCALL2(pv_mmu_ops.set_pte, ptep,
1148 pte.pte);
1149 }
1150
1151 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
1152 pte_t *ptep, pte_t pte)
1153 {
1154 if (sizeof(pteval_t) > sizeof(long))
1155 /* 5 arg words */
1156 pv_mmu_ops.set_pte_at(mm, addr, ptep, pte);
1157 else
1158 PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte);
1159 }
1160
1161 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
1162 {
1163 pmdval_t val = native_pmd_val(pmd);
1164
1165 if (sizeof(pmdval_t) > sizeof(long))
1166 PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32);
1167 else
1168 PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val);
1169 }
1170
1171 #if PAGETABLE_LEVELS >= 3
1172 static inline pmd_t __pmd(pmdval_t val)
1173 {
1174 pmdval_t ret;
1175
1176 if (sizeof(pmdval_t) > sizeof(long))
1177 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd,
1178 val, (u64)val >> 32);
1179 else
1180 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd,
1181 val);
1182
1183 return (pmd_t) { ret };
1184 }
1185
1186 static inline pmdval_t pmd_val(pmd_t pmd)
1187 {
1188 pmdval_t ret;
1189
1190 if (sizeof(pmdval_t) > sizeof(long))
1191 ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val,
1192 pmd.pmd, (u64)pmd.pmd >> 32);
1193 else
1194 ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val,
1195 pmd.pmd);
1196
1197 return ret;
1198 }
1199
1200 static inline void set_pud(pud_t *pudp, pud_t pud)
1201 {
1202 pudval_t val = native_pud_val(pud);
1203
1204 if (sizeof(pudval_t) > sizeof(long))
1205 PVOP_VCALL3(pv_mmu_ops.set_pud, pudp,
1206 val, (u64)val >> 32);
1207 else
1208 PVOP_VCALL2(pv_mmu_ops.set_pud, pudp,
1209 val);
1210 }
1211 #if PAGETABLE_LEVELS == 4
1212 static inline pud_t __pud(pudval_t val)
1213 {
1214 pudval_t ret;
1215
1216 if (sizeof(pudval_t) > sizeof(long))
1217 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud,
1218 val, (u64)val >> 32);
1219 else
1220 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud,
1221 val);
1222
1223 return (pud_t) { ret };
1224 }
1225
1226 static inline pudval_t pud_val(pud_t pud)
1227 {
1228 pudval_t ret;
1229
1230 if (sizeof(pudval_t) > sizeof(long))
1231 ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val,
1232 pud.pud, (u64)pud.pud >> 32);
1233 else
1234 ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val,
1235 pud.pud);
1236
1237 return ret;
1238 }
1239
1240 static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1241 {
1242 pgdval_t val = native_pgd_val(pgd);
1243
1244 if (sizeof(pgdval_t) > sizeof(long))
1245 PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp,
1246 val, (u64)val >> 32);
1247 else
1248 PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp,
1249 val);
1250 }
1251
1252 static inline void pgd_clear(pgd_t *pgdp)
1253 {
1254 set_pgd(pgdp, __pgd(0));
1255 }
1256
1257 static inline void pud_clear(pud_t *pudp)
1258 {
1259 set_pud(pudp, __pud(0));
1260 }
1261
1262 #endif /* PAGETABLE_LEVELS == 4 */
1263
1264 #endif /* PAGETABLE_LEVELS >= 3 */
1265
1266 #ifdef CONFIG_X86_PAE
1267 /* Special-case pte-setting operations for PAE, which can't update a
1268 64-bit pte atomically */
1269 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1270 {
1271 PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep,
1272 pte.pte, pte.pte >> 32);
1273 }
1274
1275 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1276 pte_t *ptep, pte_t pte)
1277 {
1278 /* 5 arg words */
1279 pv_mmu_ops.set_pte_present(mm, addr, ptep, pte);
1280 }
1281
1282 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1283 pte_t *ptep)
1284 {
1285 PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep);
1286 }
1287
1288 static inline void pmd_clear(pmd_t *pmdp)
1289 {
1290 PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp);
1291 }
1292 #else /* !CONFIG_X86_PAE */
1293 static inline void set_pte_atomic(pte_t *ptep, pte_t pte)
1294 {
1295 set_pte(ptep, pte);
1296 }
1297
1298 static inline void set_pte_present(struct mm_struct *mm, unsigned long addr,
1299 pte_t *ptep, pte_t pte)
1300 {
1301 set_pte(ptep, pte);
1302 }
1303
1304 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
1305 pte_t *ptep)
1306 {
1307 set_pte_at(mm, addr, ptep, __pte(0));
1308 }
1309
1310 static inline void pmd_clear(pmd_t *pmdp)
1311 {
1312 set_pmd(pmdp, __pmd(0));
1313 }
1314 #endif /* CONFIG_X86_PAE */
1315
1316 /* Lazy mode for batching updates / context switch */
1317 enum paravirt_lazy_mode {
1318 PARAVIRT_LAZY_NONE,
1319 PARAVIRT_LAZY_MMU,
1320 PARAVIRT_LAZY_CPU,
1321 };
1322
1323 enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
1324 void paravirt_enter_lazy_cpu(void);
1325 void paravirt_leave_lazy_cpu(void);
1326 void paravirt_enter_lazy_mmu(void);
1327 void paravirt_leave_lazy_mmu(void);
1328 void paravirt_leave_lazy(enum paravirt_lazy_mode mode);
1329
1330 #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE
1331 static inline void arch_enter_lazy_cpu_mode(void)
1332 {
1333 PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter);
1334 }
1335
1336 static inline void arch_leave_lazy_cpu_mode(void)
1337 {
1338 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
1339 }
1340
1341 static inline void arch_flush_lazy_cpu_mode(void)
1342 {
1343 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
1344 arch_leave_lazy_cpu_mode();
1345 arch_enter_lazy_cpu_mode();
1346 }
1347 }
1348
1349
1350 #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1351 static inline void arch_enter_lazy_mmu_mode(void)
1352 {
1353 PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter);
1354 }
1355
1356 static inline void arch_leave_lazy_mmu_mode(void)
1357 {
1358 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
1359 }
1360
1361 static inline void arch_flush_lazy_mmu_mode(void)
1362 {
1363 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
1364 arch_leave_lazy_mmu_mode();
1365 arch_enter_lazy_mmu_mode();
1366 }
1367 }
1368
1369 static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
1370 unsigned long phys, pgprot_t flags)
1371 {
1372 pv_mmu_ops.set_fixmap(idx, phys, flags);
1373 }
1374
1375 void _paravirt_nop(void);
1376 u32 _paravirt_ident_32(u32);
1377 u64 _paravirt_ident_64(u64);
1378
1379 #define paravirt_nop ((void *)_paravirt_nop)
1380
1381 void paravirt_use_bytelocks(void);
1382
1383 #ifdef CONFIG_SMP
1384
1385 static inline int __raw_spin_is_locked(struct raw_spinlock *lock)
1386 {
1387 return PVOP_CALL1(int, pv_lock_ops.spin_is_locked, lock);
1388 }
1389
1390 static inline int __raw_spin_is_contended(struct raw_spinlock *lock)
1391 {
1392 return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock);
1393 }
1394
1395 static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
1396 {
1397 PVOP_VCALL1(pv_lock_ops.spin_lock, lock);
1398 }
1399
1400 static __always_inline void __raw_spin_lock_flags(struct raw_spinlock *lock,
1401 unsigned long flags)
1402 {
1403 PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags);
1404 }
1405
1406 static __always_inline int __raw_spin_trylock(struct raw_spinlock *lock)
1407 {
1408 return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock);
1409 }
1410
1411 static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
1412 {
1413 PVOP_VCALL1(pv_lock_ops.spin_unlock, lock);
1414 }
1415
1416 #endif
1417
1418 /* These all sit in the .parainstructions section to tell us what to patch. */
1419 struct paravirt_patch_site {
1420 u8 *instr; /* original instructions */
1421 u8 instrtype; /* type of this instruction */
1422 u8 len; /* length of original instruction */
1423 u16 clobbers; /* what registers you may clobber */
1424 };
1425
1426 extern struct paravirt_patch_site __parainstructions[],
1427 __parainstructions_end[];
1428
1429 #ifdef CONFIG_X86_32
1430 #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;"
1431 #define PV_RESTORE_REGS "popl %%edx; popl %%ecx"
1432 #define PV_FLAGS_ARG "0"
1433 #define PV_EXTRA_CLOBBERS
1434 #define PV_VEXTRA_CLOBBERS
1435 #else
1436 /* We save some registers, but all of them, that's too much. We clobber all
1437 * caller saved registers but the argument parameter */
1438 #define PV_SAVE_REGS "pushq %%rdi;"
1439 #define PV_RESTORE_REGS "popq %%rdi;"
1440 #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx", "rsi"
1441 #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx", "rsi"
1442 #define PV_FLAGS_ARG "D"
1443 #endif
1444
1445 static inline unsigned long __raw_local_save_flags(void)
1446 {
1447 unsigned long f;
1448
1449 asm volatile(paravirt_alt(PV_SAVE_REGS
1450 PARAVIRT_CALL
1451 PV_RESTORE_REGS)
1452 : "=a"(f)
1453 : paravirt_type(pv_irq_ops.save_fl),
1454 paravirt_clobber(CLBR_EAX)
1455 : "memory", "cc" PV_VEXTRA_CLOBBERS);
1456 return f;
1457 }
1458
1459 static inline void raw_local_irq_restore(unsigned long f)
1460 {
1461 asm volatile(paravirt_alt(PV_SAVE_REGS
1462 PARAVIRT_CALL
1463 PV_RESTORE_REGS)
1464 : "=a"(f)
1465 : PV_FLAGS_ARG(f),
1466 paravirt_type(pv_irq_ops.restore_fl),
1467 paravirt_clobber(CLBR_EAX)
1468 : "memory", "cc" PV_EXTRA_CLOBBERS);
1469 }
1470
1471 static inline void raw_local_irq_disable(void)
1472 {
1473 asm volatile(paravirt_alt(PV_SAVE_REGS
1474 PARAVIRT_CALL
1475 PV_RESTORE_REGS)
1476 :
1477 : paravirt_type(pv_irq_ops.irq_disable),
1478 paravirt_clobber(CLBR_EAX)
1479 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1480 }
1481
1482 static inline void raw_local_irq_enable(void)
1483 {
1484 asm volatile(paravirt_alt(PV_SAVE_REGS
1485 PARAVIRT_CALL
1486 PV_RESTORE_REGS)
1487 :
1488 : paravirt_type(pv_irq_ops.irq_enable),
1489 paravirt_clobber(CLBR_EAX)
1490 : "memory", "eax", "cc" PV_EXTRA_CLOBBERS);
1491 }
1492
1493 static inline unsigned long __raw_local_irq_save(void)
1494 {
1495 unsigned long f;
1496
1497 f = __raw_local_save_flags();
1498 raw_local_irq_disable();
1499 return f;
1500 }
1501
1502
1503 /* Make sure as little as possible of this mess escapes. */
1504 #undef PARAVIRT_CALL
1505 #undef __PVOP_CALL
1506 #undef __PVOP_VCALL
1507 #undef PVOP_VCALL0
1508 #undef PVOP_CALL0
1509 #undef PVOP_VCALL1
1510 #undef PVOP_CALL1
1511 #undef PVOP_VCALL2
1512 #undef PVOP_CALL2
1513 #undef PVOP_VCALL3
1514 #undef PVOP_CALL3
1515 #undef PVOP_VCALL4
1516 #undef PVOP_CALL4
1517
1518 #else /* __ASSEMBLY__ */
1519
1520 #define _PVSITE(ptype, clobbers, ops, word, algn) \
1521 771:; \
1522 ops; \
1523 772:; \
1524 .pushsection .parainstructions,"a"; \
1525 .align algn; \
1526 word 771b; \
1527 .byte ptype; \
1528 .byte 772b-771b; \
1529 .short clobbers; \
1530 .popsection
1531
1532
1533 #ifdef CONFIG_X86_64
1534 #define PV_SAVE_REGS \
1535 push %rax; \
1536 push %rcx; \
1537 push %rdx; \
1538 push %rsi; \
1539 push %rdi; \
1540 push %r8; \
1541 push %r9; \
1542 push %r10; \
1543 push %r11
1544 #define PV_RESTORE_REGS \
1545 pop %r11; \
1546 pop %r10; \
1547 pop %r9; \
1548 pop %r8; \
1549 pop %rdi; \
1550 pop %rsi; \
1551 pop %rdx; \
1552 pop %rcx; \
1553 pop %rax
1554 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1555 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1556 #define PARA_INDIRECT(addr) *addr(%rip)
1557 #else
1558 #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1559 #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1560 #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1561 #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1562 #define PARA_INDIRECT(addr) *%cs:addr
1563 #endif
1564
1565 #define INTERRUPT_RETURN \
1566 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1567 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
1568
1569 #define DISABLE_INTERRUPTS(clobbers) \
1570 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1571 PV_SAVE_REGS; \
1572 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
1573 PV_RESTORE_REGS;) \
1574
1575 #define ENABLE_INTERRUPTS(clobbers) \
1576 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1577 PV_SAVE_REGS; \
1578 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
1579 PV_RESTORE_REGS;)
1580
1581 #define USERGS_SYSRET32 \
1582 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \
1583 CLBR_NONE, \
1584 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32))
1585
1586 #ifdef CONFIG_X86_32
1587 #define GET_CR0_INTO_EAX \
1588 push %ecx; push %edx; \
1589 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
1590 pop %edx; pop %ecx
1591
1592 #define ENABLE_INTERRUPTS_SYSEXIT \
1593 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1594 CLBR_NONE, \
1595 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1596
1597
1598 #else /* !CONFIG_X86_32 */
1599
1600 /*
1601 * If swapgs is used while the userspace stack is still current,
1602 * there's no way to call a pvop. The PV replacement *must* be
1603 * inlined, or the swapgs instruction must be trapped and emulated.
1604 */
1605 #define SWAPGS_UNSAFE_STACK \
1606 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1607 swapgs)
1608
1609 #define SWAPGS \
1610 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1611 PV_SAVE_REGS; \
1612 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \
1613 PV_RESTORE_REGS \
1614 )
1615
1616 #define GET_CR2_INTO_RCX \
1617 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \
1618 movq %rax, %rcx; \
1619 xorq %rax, %rax;
1620
1621 #define PARAVIRT_ADJUST_EXCEPTION_FRAME \
1622 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
1623 CLBR_NONE, \
1624 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame))
1625
1626 #define USERGS_SYSRET64 \
1627 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
1628 CLBR_NONE, \
1629 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
1630
1631 #define ENABLE_INTERRUPTS_SYSEXIT32 \
1632 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1633 CLBR_NONE, \
1634 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1635 #endif /* CONFIG_X86_32 */
1636
1637 #endif /* __ASSEMBLY__ */
1638 #endif /* CONFIG_PARAVIRT */
1639 #endif /* _ASM_X86_PARAVIRT_H */
Support for the Chinese Samsung S3C2440 based development boards