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Blackfin SPI Driver: SPI slave select code cleanup
[linux-2.6/mini2440.git] / drivers / spi / spi_bfin5xx.c
blobb797ece0b10c655b8282f9378b7967ae2c313e8b
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/ioport.h>
17 #include <linux/irq.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi.h>
23 #include <linux/workqueue.h>
24
25 #include <asm/dma.h>
26 #include <asm/portmux.h>
27 #include <asm/bfin5xx_spi.h>
28 #include <asm/cacheflush.h>
29
30 #define DRV_NAME "bfin-spi"
31 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
32 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
33 #define DRV_VERSION "1.0"
34
35 MODULE_AUTHOR(DRV_AUTHOR);
36 MODULE_DESCRIPTION(DRV_DESC);
37 MODULE_LICENSE("GPL");
38
39 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
40
41 #define START_STATE ((void *)0)
42 #define RUNNING_STATE ((void *)1)
43 #define DONE_STATE ((void *)2)
44 #define ERROR_STATE ((void *)-1)
45 #define QUEUE_RUNNING 0
46 #define QUEUE_STOPPED 1
47
48 struct driver_data {
49 /* Driver model hookup */
50 struct platform_device *pdev;
51
52 /* SPI framework hookup */
53 struct spi_master *master;
54
55 /* Regs base of SPI controller */
56 void __iomem *regs_base;
57
58 /* Pin request list */
59 u16 *pin_req;
60
61 /* BFIN hookup */
62 struct bfin5xx_spi_master *master_info;
63
64 /* Driver message queue */
65 struct workqueue_struct *workqueue;
66 struct work_struct pump_messages;
67 spinlock_t lock;
68 struct list_head queue;
69 int busy;
70 int run;
71
72 /* Message Transfer pump */
73 struct tasklet_struct pump_transfers;
74
75 /* Current message transfer state info */
76 struct spi_message *cur_msg;
77 struct spi_transfer *cur_transfer;
78 struct chip_data *cur_chip;
79 size_t len_in_bytes;
80 size_t len;
81 void *tx;
82 void *tx_end;
83 void *rx;
84 void *rx_end;
85
86 /* DMA stuffs */
87 int dma_channel;
88 int dma_mapped;
89 int dma_requested;
90 dma_addr_t rx_dma;
91 dma_addr_t tx_dma;
92
93 size_t rx_map_len;
94 size_t tx_map_len;
95 u8 n_bytes;
96 int cs_change;
97 void (*write) (struct driver_data *);
98 void (*read) (struct driver_data *);
99 void (*duplex) (struct driver_data *);
100 };
101
102 struct chip_data {
103 u16 ctl_reg;
104 u16 baud;
105 u16 flag;
106
107 u8 chip_select_num;
108 u8 n_bytes;
109 u8 width; /* 0 or 1 */
110 u8 enable_dma;
111 u8 bits_per_word; /* 8 or 16 */
112 u8 cs_change_per_word;
113 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
114 void (*write) (struct driver_data *);
115 void (*read) (struct driver_data *);
116 void (*duplex) (struct driver_data *);
117 };
118
119 #define DEFINE_SPI_REG(reg, off) \
120 static inline u16 read_##reg(struct driver_data *drv_data) \
121 { return bfin_read16(drv_data->regs_base + off); } \
122 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
123 { bfin_write16(drv_data->regs_base + off, v); }
124
125 DEFINE_SPI_REG(CTRL, 0x00)
126 DEFINE_SPI_REG(FLAG, 0x04)
127 DEFINE_SPI_REG(STAT, 0x08)
128 DEFINE_SPI_REG(TDBR, 0x0C)
129 DEFINE_SPI_REG(RDBR, 0x10)
130 DEFINE_SPI_REG(BAUD, 0x14)
131 DEFINE_SPI_REG(SHAW, 0x18)
132
133 static void bfin_spi_enable(struct driver_data *drv_data)
134 {
135 u16 cr;
136
137 cr = read_CTRL(drv_data);
138 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
139 }
140
141 static void bfin_spi_disable(struct driver_data *drv_data)
142 {
143 u16 cr;
144
145 cr = read_CTRL(drv_data);
146 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
147 }
148
149 /* Caculate the SPI_BAUD register value based on input HZ */
150 static u16 hz_to_spi_baud(u32 speed_hz)
151 {
152 u_long sclk = get_sclk();
153 u16 spi_baud = (sclk / (2 * speed_hz));
154
155 if ((sclk % (2 * speed_hz)) > 0)
156 spi_baud++;
157
158 if (spi_baud < MIN_SPI_BAUD_VAL)
159 spi_baud = MIN_SPI_BAUD_VAL;
160
161 return spi_baud;
162 }
163
164 static int flush(struct driver_data *drv_data)
165 {
166 unsigned long limit = loops_per_jiffy << 1;
167
168 /* wait for stop and clear stat */
169 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
170 cpu_relax();
171
172 write_STAT(drv_data, BIT_STAT_CLR);
173
174 return limit;
175 }
176
177 /* Chip select operation functions for cs_change flag */
178 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
179 {
180 u16 flag = read_FLAG(drv_data);
181
182 flag |= chip->flag;
183 flag &= ~(chip->flag << 8);
184
185 write_FLAG(drv_data, flag);
186 }
187
188 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
189 {
190 u16 flag = read_FLAG(drv_data);
191
192 flag |= (chip->flag << 8);
193
194 write_FLAG(drv_data, flag);
195
196 /* Move delay here for consistency */
197 if (chip->cs_chg_udelay)
198 udelay(chip->cs_chg_udelay);
199 }
200
201 /* stop controller and re-config current chip*/
202 static void restore_state(struct driver_data *drv_data)
203 {
204 struct chip_data *chip = drv_data->cur_chip;
205
206 /* Clear status and disable clock */
207 write_STAT(drv_data, BIT_STAT_CLR);
208 bfin_spi_disable(drv_data);
209 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
210
211 /* Load the registers */
212 write_CTRL(drv_data, chip->ctl_reg);
213 write_BAUD(drv_data, chip->baud);
214
215 bfin_spi_enable(drv_data);
216 cs_active(drv_data, chip);
217 }
218
219 /* used to kick off transfer in rx mode */
220 static unsigned short dummy_read(struct driver_data *drv_data)
221 {
222 unsigned short tmp;
223 tmp = read_RDBR(drv_data);
224 return tmp;
225 }
226
227 static void null_writer(struct driver_data *drv_data)
228 {
229 u8 n_bytes = drv_data->n_bytes;
230
231 while (drv_data->tx < drv_data->tx_end) {
232 write_TDBR(drv_data, 0);
233 while ((read_STAT(drv_data) & BIT_STAT_TXS))
234 cpu_relax();
235 drv_data->tx += n_bytes;
236 }
237 }
238
239 static void null_reader(struct driver_data *drv_data)
240 {
241 u8 n_bytes = drv_data->n_bytes;
242 dummy_read(drv_data);
243
244 while (drv_data->rx < drv_data->rx_end) {
245 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
246 cpu_relax();
247 dummy_read(drv_data);
248 drv_data->rx += n_bytes;
249 }
250 }
251
252 static void u8_writer(struct driver_data *drv_data)
253 {
254 dev_dbg(&drv_data->pdev->dev,
255 "cr8-s is 0x%x\n", read_STAT(drv_data));
256
257 while (drv_data->tx < drv_data->tx_end) {
258 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
259 while (read_STAT(drv_data) & BIT_STAT_TXS)
260 cpu_relax();
261 ++drv_data->tx;
262 }
263
264 /* poll for SPI completion before return */
265 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
266 cpu_relax();
267 }
268
269 static void u8_cs_chg_writer(struct driver_data *drv_data)
270 {
271 struct chip_data *chip = drv_data->cur_chip;
272
273 while (drv_data->tx < drv_data->tx_end) {
274 cs_active(drv_data, chip);
275
276 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
277 while (read_STAT(drv_data) & BIT_STAT_TXS)
278 cpu_relax();
279 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
280 cpu_relax();
281
282 cs_deactive(drv_data, chip);
283
284 ++drv_data->tx;
285 }
286 }
287
288 static void u8_reader(struct driver_data *drv_data)
289 {
290 dev_dbg(&drv_data->pdev->dev,
291 "cr-8 is 0x%x\n", read_STAT(drv_data));
292
293 /* poll for SPI completion before start */
294 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
295 cpu_relax();
296
297 /* clear TDBR buffer before read(else it will be shifted out) */
298 write_TDBR(drv_data, 0xFFFF);
299
300 dummy_read(drv_data);
301
302 while (drv_data->rx < drv_data->rx_end - 1) {
303 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
304 cpu_relax();
305 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
306 ++drv_data->rx;
307 }
308
309 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
310 cpu_relax();
311 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
312 ++drv_data->rx;
313 }
314
315 static void u8_cs_chg_reader(struct driver_data *drv_data)
316 {
317 struct chip_data *chip = drv_data->cur_chip;
318
319 while (drv_data->rx < drv_data->rx_end) {
320 cs_active(drv_data, chip);
321 read_RDBR(drv_data); /* kick off */
322
323 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
324 cpu_relax();
325 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
326 cpu_relax();
327
328 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
329 cs_deactive(drv_data, chip);
330
331 ++drv_data->rx;
332 }
333 }
334
335 static void u8_duplex(struct driver_data *drv_data)
336 {
337 /* in duplex mode, clk is triggered by writing of TDBR */
338 while (drv_data->rx < drv_data->rx_end) {
339 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
340 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
341 cpu_relax();
342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
343 cpu_relax();
344 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
345 ++drv_data->rx;
346 ++drv_data->tx;
347 }
348 }
349
350 static void u8_cs_chg_duplex(struct driver_data *drv_data)
351 {
352 struct chip_data *chip = drv_data->cur_chip;
353
354 while (drv_data->rx < drv_data->rx_end) {
355 cs_active(drv_data, chip);
356
357 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
358
359 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
360 cpu_relax();
361 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
362 cpu_relax();
363 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
364
365 cs_deactive(drv_data, chip);
366
367 ++drv_data->rx;
368 ++drv_data->tx;
369 }
370 }
371
372 static void u16_writer(struct driver_data *drv_data)
373 {
374 dev_dbg(&drv_data->pdev->dev,
375 "cr16 is 0x%x\n", read_STAT(drv_data));
376
377 while (drv_data->tx < drv_data->tx_end) {
378 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
379 while ((read_STAT(drv_data) & BIT_STAT_TXS))
380 cpu_relax();
381 drv_data->tx += 2;
382 }
383
384 /* poll for SPI completion before return */
385 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
386 cpu_relax();
387 }
388
389 static void u16_cs_chg_writer(struct driver_data *drv_data)
390 {
391 struct chip_data *chip = drv_data->cur_chip;
392
393 while (drv_data->tx < drv_data->tx_end) {
394 cs_active(drv_data, chip);
395
396 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
397 while ((read_STAT(drv_data) & BIT_STAT_TXS))
398 cpu_relax();
399 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
400 cpu_relax();
401
402 cs_deactive(drv_data, chip);
403
404 drv_data->tx += 2;
405 }
406 }
407
408 static void u16_reader(struct driver_data *drv_data)
409 {
410 dev_dbg(&drv_data->pdev->dev,
411 "cr-16 is 0x%x\n", read_STAT(drv_data));
412
413 /* poll for SPI completion before start */
414 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
415 cpu_relax();
416
417 /* clear TDBR buffer before read(else it will be shifted out) */
418 write_TDBR(drv_data, 0xFFFF);
419
420 dummy_read(drv_data);
421
422 while (drv_data->rx < (drv_data->rx_end - 2)) {
423 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
424 cpu_relax();
425 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
426 drv_data->rx += 2;
427 }
428
429 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
430 cpu_relax();
431 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
432 drv_data->rx += 2;
433 }
434
435 static void u16_cs_chg_reader(struct driver_data *drv_data)
436 {
437 struct chip_data *chip = drv_data->cur_chip;
438
439 /* poll for SPI completion before start */
440 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
441 cpu_relax();
442
443 /* clear TDBR buffer before read(else it will be shifted out) */
444 write_TDBR(drv_data, 0xFFFF);
445
446 cs_active(drv_data, chip);
447 dummy_read(drv_data);
448
449 while (drv_data->rx < drv_data->rx_end - 2) {
450 cs_deactive(drv_data, chip);
451
452 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
453 cpu_relax();
454 cs_active(drv_data, chip);
455 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
456 drv_data->rx += 2;
457 }
458 cs_deactive(drv_data, chip);
459
460 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
461 cpu_relax();
462 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
463 drv_data->rx += 2;
464 }
465
466 static void u16_duplex(struct driver_data *drv_data)
467 {
468 /* in duplex mode, clk is triggered by writing of TDBR */
469 while (drv_data->tx < drv_data->tx_end) {
470 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
471 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
472 cpu_relax();
473 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
474 cpu_relax();
475 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
476 drv_data->rx += 2;
477 drv_data->tx += 2;
478 }
479 }
480
481 static void u16_cs_chg_duplex(struct driver_data *drv_data)
482 {
483 struct chip_data *chip = drv_data->cur_chip;
484
485 while (drv_data->tx < drv_data->tx_end) {
486 cs_active(drv_data, chip);
487
488 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
489 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
490 cpu_relax();
491 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
492 cpu_relax();
493 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
494
495 cs_deactive(drv_data, chip);
496
497 drv_data->rx += 2;
498 drv_data->tx += 2;
499 }
500 }
501
502 /* test if ther is more transfer to be done */
503 static void *next_transfer(struct driver_data *drv_data)
504 {
505 struct spi_message *msg = drv_data->cur_msg;
506 struct spi_transfer *trans = drv_data->cur_transfer;
507
508 /* Move to next transfer */
509 if (trans->transfer_list.next != &msg->transfers) {
510 drv_data->cur_transfer =
511 list_entry(trans->transfer_list.next,
512 struct spi_transfer, transfer_list);
513 return RUNNING_STATE;
514 } else
515 return DONE_STATE;
516 }
517
518 /*
519 * caller already set message->status;
520 * dma and pio irqs are blocked give finished message back
521 */
522 static void giveback(struct driver_data *drv_data)
523 {
524 struct chip_data *chip = drv_data->cur_chip;
525 struct spi_transfer *last_transfer;
526 unsigned long flags;
527 struct spi_message *msg;
528
529 spin_lock_irqsave(&drv_data->lock, flags);
530 msg = drv_data->cur_msg;
531 drv_data->cur_msg = NULL;
532 drv_data->cur_transfer = NULL;
533 drv_data->cur_chip = NULL;
534 queue_work(drv_data->workqueue, &drv_data->pump_messages);
535 spin_unlock_irqrestore(&drv_data->lock, flags);
536
537 last_transfer = list_entry(msg->transfers.prev,
538 struct spi_transfer, transfer_list);
539
540 msg->state = NULL;
541
542 /* disable chip select signal. And not stop spi in autobuffer mode */
543 if (drv_data->tx_dma != 0xFFFF) {
544 cs_deactive(drv_data, chip);
545 bfin_spi_disable(drv_data);
546 }
547
548 if (!drv_data->cs_change)
549 cs_deactive(drv_data, chip);
550
551 if (msg->complete)
552 msg->complete(msg->context);
553 }
554
555 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
556 {
557 struct driver_data *drv_data = dev_id;
558 struct chip_data *chip = drv_data->cur_chip;
559 struct spi_message *msg = drv_data->cur_msg;
560 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
561 u16 spistat = read_STAT(drv_data);
562
563 dev_dbg(&drv_data->pdev->dev,
564 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
565 dmastat, spistat);
566
567 clear_dma_irqstat(drv_data->dma_channel);
568
569 /* Wait for DMA to complete */
570 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
571 cpu_relax();
572
573 /*
574 * wait for the last transaction shifted out. HRM states:
575 * at this point there may still be data in the SPI DMA FIFO waiting
576 * to be transmitted ... software needs to poll TXS in the SPI_STAT
577 * register until it goes low for 2 successive reads
578 */
579 if (drv_data->tx != NULL) {
580 while ((read_STAT(drv_data) & TXS) ||
581 (read_STAT(drv_data) & TXS))
582 cpu_relax();
583 }
584
585 while (!(read_STAT(drv_data) & SPIF))
586 cpu_relax();
587
588 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
589 msg->state = ERROR_STATE;
590 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
591 } else {
592 msg->actual_length += drv_data->len_in_bytes;
593
594 if (drv_data->cs_change)
595 cs_deactive(drv_data, chip);
596
597 /* Move to next transfer */
598 msg->state = next_transfer(drv_data);
599 }
600
601 /* Schedule transfer tasklet */
602 tasklet_schedule(&drv_data->pump_transfers);
603
604 /* free the irq handler before next transfer */
605 dev_dbg(&drv_data->pdev->dev,
606 "disable dma channel irq%d\n",
607 drv_data->dma_channel);
608 dma_disable_irq(drv_data->dma_channel);
609
610 return IRQ_HANDLED;
611 }
612
613 static void pump_transfers(unsigned long data)
614 {
615 struct driver_data *drv_data = (struct driver_data *)data;
616 struct spi_message *message = NULL;
617 struct spi_transfer *transfer = NULL;
618 struct spi_transfer *previous = NULL;
619 struct chip_data *chip = NULL;
620 u8 width;
621 u16 cr, dma_width, dma_config;
622 u32 tranf_success = 1;
623 u8 full_duplex = 0;
624
625 /* Get current state information */
626 message = drv_data->cur_msg;
627 transfer = drv_data->cur_transfer;
628 chip = drv_data->cur_chip;
629
630 /*
631 * if msg is error or done, report it back using complete() callback
632 */
633
634 /* Handle for abort */
635 if (message->state == ERROR_STATE) {
636 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
637 message->status = -EIO;
638 giveback(drv_data);
639 return;
640 }
641
642 /* Handle end of message */
643 if (message->state == DONE_STATE) {
644 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
645 message->status = 0;
646 giveback(drv_data);
647 return;
648 }
649
650 /* Delay if requested at end of transfer */
651 if (message->state == RUNNING_STATE) {
652 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
653 previous = list_entry(transfer->transfer_list.prev,
654 struct spi_transfer, transfer_list);
655 if (previous->delay_usecs)
656 udelay(previous->delay_usecs);
657 }
658
659 /* Setup the transfer state based on the type of transfer */
660 if (flush(drv_data) == 0) {
661 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
662 message->status = -EIO;
663 giveback(drv_data);
664 return;
665 }
666
667 if (transfer->tx_buf != NULL) {
668 drv_data->tx = (void *)transfer->tx_buf;
669 drv_data->tx_end = drv_data->tx + transfer->len;
670 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
671 transfer->tx_buf, drv_data->tx_end);
672 } else {
673 drv_data->tx = NULL;
674 }
675
676 if (transfer->rx_buf != NULL) {
677 full_duplex = transfer->tx_buf != NULL;
678 drv_data->rx = transfer->rx_buf;
679 drv_data->rx_end = drv_data->rx + transfer->len;
680 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
681 transfer->rx_buf, drv_data->rx_end);
682 } else {
683 drv_data->rx = NULL;
684 }
685
686 drv_data->rx_dma = transfer->rx_dma;
687 drv_data->tx_dma = transfer->tx_dma;
688 drv_data->len_in_bytes = transfer->len;
689 drv_data->cs_change = transfer->cs_change;
690
691 /* Bits per word setup */
692 switch (transfer->bits_per_word) {
693 case 8:
694 drv_data->n_bytes = 1;
695 width = CFG_SPI_WORDSIZE8;
696 drv_data->read = chip->cs_change_per_word ?
697 u8_cs_chg_reader : u8_reader;
698 drv_data->write = chip->cs_change_per_word ?
699 u8_cs_chg_writer : u8_writer;
700 drv_data->duplex = chip->cs_change_per_word ?
701 u8_cs_chg_duplex : u8_duplex;
702 break;
703
704 case 16:
705 drv_data->n_bytes = 2;
706 width = CFG_SPI_WORDSIZE16;
707 drv_data->read = chip->cs_change_per_word ?
708 u16_cs_chg_reader : u16_reader;
709 drv_data->write = chip->cs_change_per_word ?
710 u16_cs_chg_writer : u16_writer;
711 drv_data->duplex = chip->cs_change_per_word ?
712 u16_cs_chg_duplex : u16_duplex;
713 break;
714
715 default:
716 /* No change, the same as default setting */
717 drv_data->n_bytes = chip->n_bytes;
718 width = chip->width;
719 drv_data->write = drv_data->tx ? chip->write : null_writer;
720 drv_data->read = drv_data->rx ? chip->read : null_reader;
721 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
722 break;
723 }
724 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
725 cr |= (width << 8);
726 write_CTRL(drv_data, cr);
727
728 if (width == CFG_SPI_WORDSIZE16) {
729 drv_data->len = (transfer->len) >> 1;
730 } else {
731 drv_data->len = transfer->len;
732 }
733 dev_dbg(&drv_data->pdev->dev,
734 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
735 drv_data->write, chip->write, null_writer);
736
737 /* speed and width has been set on per message */
738 message->state = RUNNING_STATE;
739 dma_config = 0;
740
741 /* Speed setup (surely valid because already checked) */
742 if (transfer->speed_hz)
743 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
744 else
745 write_BAUD(drv_data, chip->baud);
746
747 write_STAT(drv_data, BIT_STAT_CLR);
748 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
749 cs_active(drv_data, chip);
750
751 dev_dbg(&drv_data->pdev->dev,
752 "now pumping a transfer: width is %d, len is %d\n",
753 width, transfer->len);
754
755 /*
756 * Try to map dma buffer and do a dma transfer. If successful use,
757 * different way to r/w according to the enable_dma settings and if
758 * we are not doing a full duplex transfer (since the hardware does
759 * not support full duplex DMA transfers).
760 */
761 if (!full_duplex && drv_data->cur_chip->enable_dma
762 && drv_data->len > 6) {
763
764 unsigned long dma_start_addr;
765
766 disable_dma(drv_data->dma_channel);
767 clear_dma_irqstat(drv_data->dma_channel);
768 bfin_spi_disable(drv_data);
769
770 /* config dma channel */
771 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
772 set_dma_x_count(drv_data->dma_channel, drv_data->len);
773 if (width == CFG_SPI_WORDSIZE16) {
774 set_dma_x_modify(drv_data->dma_channel, 2);
775 dma_width = WDSIZE_16;
776 } else {
777 set_dma_x_modify(drv_data->dma_channel, 1);
778 dma_width = WDSIZE_8;
779 }
780
781 /* poll for SPI completion before start */
782 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
783 cpu_relax();
784
785 /* dirty hack for autobuffer DMA mode */
786 if (drv_data->tx_dma == 0xFFFF) {
787 dev_dbg(&drv_data->pdev->dev,
788 "doing autobuffer DMA out.\n");
789
790 /* no irq in autobuffer mode */
791 dma_config =
792 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
793 set_dma_config(drv_data->dma_channel, dma_config);
794 set_dma_start_addr(drv_data->dma_channel,
795 (unsigned long)drv_data->tx);
796 enable_dma(drv_data->dma_channel);
797
798 /* start SPI transfer */
799 write_CTRL(drv_data,
800 (cr | BIT_CTL_TIMOD_DMA_TX | BIT_CTL_ENABLE));
801
802 /* just return here, there can only be one transfer
803 * in this mode
804 */
805 message->status = 0;
806 giveback(drv_data);
807 return;
808 }
809
810 /* In dma mode, rx or tx must be NULL in one transfer */
811 dma_config = (RESTART | dma_width | DI_EN);
812 if (drv_data->rx != NULL) {
813 /* set transfer mode, and enable SPI */
814 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
815 drv_data->rx, drv_data->len_in_bytes);
816
817 /* invalidate caches, if needed */
818 if (bfin_addr_dcachable((unsigned long) drv_data->rx))
819 invalidate_dcache_range((unsigned long) drv_data->rx,
820 (unsigned long) (drv_data->rx +
821 drv_data->len_in_bytes));
822
823 /* clear tx reg soformer data is not shifted out */
824 write_TDBR(drv_data, 0xFFFF);
825
826 dma_config |= WNR;
827 dma_start_addr = (unsigned long)drv_data->rx;
828 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
829
830 } else if (drv_data->tx != NULL) {
831 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
832
833 /* flush caches, if needed */
834 if (bfin_addr_dcachable((unsigned long) drv_data->tx))
835 flush_dcache_range((unsigned long) drv_data->tx,
836 (unsigned long) (drv_data->tx +
837 drv_data->len_in_bytes));
838
839 dma_start_addr = (unsigned long)drv_data->tx;
840 cr |= BIT_CTL_TIMOD_DMA_TX;
841
842 } else
843 BUG();
844
845 /* start dma */
846 dma_enable_irq(drv_data->dma_channel);
847 set_dma_config(drv_data->dma_channel, dma_config);
848 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
849 enable_dma(drv_data->dma_channel);
850
851 /* start SPI transfer */
852 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
853
854 } else {
855 /* IO mode write then read */
856 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
857
858 if (full_duplex) {
859 /* full duplex mode */
860 BUG_ON((drv_data->tx_end - drv_data->tx) !=
861 (drv_data->rx_end - drv_data->rx));
862 dev_dbg(&drv_data->pdev->dev,
863 "IO duplex: cr is 0x%x\n", cr);
864
865 /* set SPI transfer mode */
866 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
867
868 drv_data->duplex(drv_data);
869
870 if (drv_data->tx != drv_data->tx_end)
871 tranf_success = 0;
872 } else if (drv_data->tx != NULL) {
873 /* write only half duplex */
874 dev_dbg(&drv_data->pdev->dev,
875 "IO write: cr is 0x%x\n", cr);
876
877 /* set SPI transfer mode */
878 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
879
880 drv_data->write(drv_data);
881
882 if (drv_data->tx != drv_data->tx_end)
883 tranf_success = 0;
884 } else if (drv_data->rx != NULL) {
885 /* read only half duplex */
886 dev_dbg(&drv_data->pdev->dev,
887 "IO read: cr is 0x%x\n", cr);
888
889 /* set SPI transfer mode */
890 write_CTRL(drv_data, (cr | CFG_SPI_READ));
891
892 drv_data->read(drv_data);
893 if (drv_data->rx != drv_data->rx_end)
894 tranf_success = 0;
895 }
896
897 if (!tranf_success) {
898 dev_dbg(&drv_data->pdev->dev,
899 "IO write error!\n");
900 message->state = ERROR_STATE;
901 } else {
902 /* Update total byte transfered */
903 message->actual_length += drv_data->len_in_bytes;
904
905 /* Move to next transfer of this msg */
906 message->state = next_transfer(drv_data);
907 }
908
909 /* Schedule next transfer tasklet */
910 tasklet_schedule(&drv_data->pump_transfers);
911
912 }
913 }
914
915 /* pop a msg from queue and kick off real transfer */
916 static void pump_messages(struct work_struct *work)
917 {
918 struct driver_data *drv_data;
919 unsigned long flags;
920
921 drv_data = container_of(work, struct driver_data, pump_messages);
922
923 /* Lock queue and check for queue work */
924 spin_lock_irqsave(&drv_data->lock, flags);
925 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
926 /* pumper kicked off but no work to do */
927 drv_data->busy = 0;
928 spin_unlock_irqrestore(&drv_data->lock, flags);
929 return;
930 }
931
932 /* Make sure we are not already running a message */
933 if (drv_data->cur_msg) {
934 spin_unlock_irqrestore(&drv_data->lock, flags);
935 return;
936 }
937
938 /* Extract head of queue */
939 drv_data->cur_msg = list_entry(drv_data->queue.next,
940 struct spi_message, queue);
941
942 /* Setup the SSP using the per chip configuration */
943 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
944 restore_state(drv_data);
945
946 list_del_init(&drv_data->cur_msg->queue);
947
948 /* Initial message state */
949 drv_data->cur_msg->state = START_STATE;
950 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
951 struct spi_transfer, transfer_list);
952
953 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
954 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
955 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
956 drv_data->cur_chip->ctl_reg);
957
958 dev_dbg(&drv_data->pdev->dev,
959 "the first transfer len is %d\n",
960 drv_data->cur_transfer->len);
961
962 /* Mark as busy and launch transfers */
963 tasklet_schedule(&drv_data->pump_transfers);
964
965 drv_data->busy = 1;
966 spin_unlock_irqrestore(&drv_data->lock, flags);
967 }
968
969 /*
970 * got a msg to transfer, queue it in drv_data->queue.
971 * And kick off message pumper
972 */
973 static int transfer(struct spi_device *spi, struct spi_message *msg)
974 {
975 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
976 unsigned long flags;
977
978 spin_lock_irqsave(&drv_data->lock, flags);
979
980 if (drv_data->run == QUEUE_STOPPED) {
981 spin_unlock_irqrestore(&drv_data->lock, flags);
982 return -ESHUTDOWN;
983 }
984
985 msg->actual_length = 0;
986 msg->status = -EINPROGRESS;
987 msg->state = START_STATE;
988
989 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
990 list_add_tail(&msg->queue, &drv_data->queue);
991
992 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
993 queue_work(drv_data->workqueue, &drv_data->pump_messages);
994
995 spin_unlock_irqrestore(&drv_data->lock, flags);
996
997 return 0;
998 }
999
1000 #define MAX_SPI_SSEL 7
1001
1002 static u16 ssel[][MAX_SPI_SSEL] = {
1003 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1004 P_SPI0_SSEL4, P_SPI0_SSEL5,
1005 P_SPI0_SSEL6, P_SPI0_SSEL7},
1006
1007 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1008 P_SPI1_SSEL4, P_SPI1_SSEL5,
1009 P_SPI1_SSEL6, P_SPI1_SSEL7},
1010
1011 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1012 P_SPI2_SSEL4, P_SPI2_SSEL5,
1013 P_SPI2_SSEL6, P_SPI2_SSEL7},
1014 };
1015
1016 /* first setup for new devices */
1017 static int setup(struct spi_device *spi)
1018 {
1019 struct bfin5xx_spi_chip *chip_info = NULL;
1020 struct chip_data *chip;
1021 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1022 u8 spi_flg;
1023
1024 /* Abort device setup if requested features are not supported */
1025 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1026 dev_err(&spi->dev, "requested mode not fully supported\n");
1027 return -EINVAL;
1028 }
1029
1030 /* Zero (the default) here means 8 bits */
1031 if (!spi->bits_per_word)
1032 spi->bits_per_word = 8;
1033
1034 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1035 return -EINVAL;
1036
1037 /* Only alloc (or use chip_info) on first setup */
1038 chip = spi_get_ctldata(spi);
1039 if (chip == NULL) {
1040 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1041 if (!chip)
1042 return -ENOMEM;
1043
1044 chip->enable_dma = 0;
1045 chip_info = spi->controller_data;
1046 }
1047
1048 /* chip_info isn't always needed */
1049 if (chip_info) {
1050 /* Make sure people stop trying to set fields via ctl_reg
1051 * when they should actually be using common SPI framework.
1052 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1053 * Not sure if a user actually needs/uses any of these,
1054 * but let's assume (for now) they do.
1055 */
1056 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1057 dev_err(&spi->dev, "do not set bits in ctl_reg "
1058 "that the SPI framework manages\n");
1059 return -EINVAL;
1060 }
1061
1062 chip->enable_dma = chip_info->enable_dma != 0
1063 && drv_data->master_info->enable_dma;
1064 chip->ctl_reg = chip_info->ctl_reg;
1065 chip->bits_per_word = chip_info->bits_per_word;
1066 chip->cs_change_per_word = chip_info->cs_change_per_word;
1067 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1068 }
1069
1070 /* translate common spi framework into our register */
1071 if (spi->mode & SPI_CPOL)
1072 chip->ctl_reg |= CPOL;
1073 if (spi->mode & SPI_CPHA)
1074 chip->ctl_reg |= CPHA;
1075 if (spi->mode & SPI_LSB_FIRST)
1076 chip->ctl_reg |= LSBF;
1077 /* we dont support running in slave mode (yet?) */
1078 chip->ctl_reg |= MSTR;
1079
1080 /*
1081 * if any one SPI chip is registered and wants DMA, request the
1082 * DMA channel for it
1083 */
1084 if (chip->enable_dma && !drv_data->dma_requested) {
1085 /* register dma irq handler */
1086 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1087 dev_dbg(&spi->dev,
1088 "Unable to request BlackFin SPI DMA channel\n");
1089 return -ENODEV;
1090 }
1091 if (set_dma_callback(drv_data->dma_channel,
1092 dma_irq_handler, drv_data) < 0) {
1093 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1094 return -EPERM;
1095 }
1096 dma_disable_irq(drv_data->dma_channel);
1097 drv_data->dma_requested = 1;
1098 }
1099
1100 /*
1101 * Notice: for blackfin, the speed_hz is the value of register
1102 * SPI_BAUD, not the real baudrate
1103 */
1104 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1105 spi_flg = ~(1 << (spi->chip_select));
1106 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1107 chip->chip_select_num = spi->chip_select;
1108
1109 switch (chip->bits_per_word) {
1110 case 8:
1111 chip->n_bytes = 1;
1112 chip->width = CFG_SPI_WORDSIZE8;
1113 chip->read = chip->cs_change_per_word ?
1114 u8_cs_chg_reader : u8_reader;
1115 chip->write = chip->cs_change_per_word ?
1116 u8_cs_chg_writer : u8_writer;
1117 chip->duplex = chip->cs_change_per_word ?
1118 u8_cs_chg_duplex : u8_duplex;
1119 break;
1120
1121 case 16:
1122 chip->n_bytes = 2;
1123 chip->width = CFG_SPI_WORDSIZE16;
1124 chip->read = chip->cs_change_per_word ?
1125 u16_cs_chg_reader : u16_reader;
1126 chip->write = chip->cs_change_per_word ?
1127 u16_cs_chg_writer : u16_writer;
1128 chip->duplex = chip->cs_change_per_word ?
1129 u16_cs_chg_duplex : u16_duplex;
1130 break;
1131
1132 default:
1133 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1134 chip->bits_per_word);
1135 kfree(chip);
1136 return -ENODEV;
1137 }
1138
1139 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1140 spi->modalias, chip->width, chip->enable_dma);
1141 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1142 chip->ctl_reg, chip->flag);
1143
1144 spi_set_ctldata(spi, chip);
1145
1146 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1147 if ((chip->chip_select_num > 0)
1148 && (chip->chip_select_num <= spi->master->num_chipselect))
1149 peripheral_request(ssel[spi->master->bus_num]
1150 [chip->chip_select_num-1], spi->modalias);
1151
1152 cs_deactive(drv_data, chip);
1153
1154 return 0;
1155 }
1156
1157 /*
1158 * callback for spi framework.
1159 * clean driver specific data
1160 */
1161 static void cleanup(struct spi_device *spi)
1162 {
1163 struct chip_data *chip = spi_get_ctldata(spi);
1164
1165 if ((chip->chip_select_num > 0)
1166 && (chip->chip_select_num <= spi->master->num_chipselect))
1167 peripheral_free(ssel[spi->master->bus_num]
1168 [chip->chip_select_num-1]);
1169
1170 kfree(chip);
1171 }
1172
1173 static inline int init_queue(struct driver_data *drv_data)
1174 {
1175 INIT_LIST_HEAD(&drv_data->queue);
1176 spin_lock_init(&drv_data->lock);
1177
1178 drv_data->run = QUEUE_STOPPED;
1179 drv_data->busy = 0;
1180
1181 /* init transfer tasklet */
1182 tasklet_init(&drv_data->pump_transfers,
1183 pump_transfers, (unsigned long)drv_data);
1184
1185 /* init messages workqueue */
1186 INIT_WORK(&drv_data->pump_messages, pump_messages);
1187 drv_data->workqueue = create_singlethread_workqueue(
1188 dev_name(drv_data->master->dev.parent));
1189 if (drv_data->workqueue == NULL)
1190 return -EBUSY;
1191
1192 return 0;
1193 }
1194
1195 static inline int start_queue(struct driver_data *drv_data)
1196 {
1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&drv_data->lock, flags);
1200
1201 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1202 spin_unlock_irqrestore(&drv_data->lock, flags);
1203 return -EBUSY;
1204 }
1205
1206 drv_data->run = QUEUE_RUNNING;
1207 drv_data->cur_msg = NULL;
1208 drv_data->cur_transfer = NULL;
1209 drv_data->cur_chip = NULL;
1210 spin_unlock_irqrestore(&drv_data->lock, flags);
1211
1212 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1213
1214 return 0;
1215 }
1216
1217 static inline int stop_queue(struct driver_data *drv_data)
1218 {
1219 unsigned long flags;
1220 unsigned limit = 500;
1221 int status = 0;
1222
1223 spin_lock_irqsave(&drv_data->lock, flags);
1224
1225 /*
1226 * This is a bit lame, but is optimized for the common execution path.
1227 * A wait_queue on the drv_data->busy could be used, but then the common
1228 * execution path (pump_messages) would be required to call wake_up or
1229 * friends on every SPI message. Do this instead
1230 */
1231 drv_data->run = QUEUE_STOPPED;
1232 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1233 spin_unlock_irqrestore(&drv_data->lock, flags);
1234 msleep(10);
1235 spin_lock_irqsave(&drv_data->lock, flags);
1236 }
1237
1238 if (!list_empty(&drv_data->queue) || drv_data->busy)
1239 status = -EBUSY;
1240
1241 spin_unlock_irqrestore(&drv_data->lock, flags);
1242
1243 return status;
1244 }
1245
1246 static inline int destroy_queue(struct driver_data *drv_data)
1247 {
1248 int status;
1249
1250 status = stop_queue(drv_data);
1251 if (status != 0)
1252 return status;
1253
1254 destroy_workqueue(drv_data->workqueue);
1255
1256 return 0;
1257 }
1258
1259 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1260 {
1261 struct device *dev = &pdev->dev;
1262 struct bfin5xx_spi_master *platform_info;
1263 struct spi_master *master;
1264 struct driver_data *drv_data = 0;
1265 struct resource *res;
1266 int status = 0;
1267
1268 platform_info = dev->platform_data;
1269
1270 /* Allocate master with space for drv_data */
1271 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1272 if (!master) {
1273 dev_err(&pdev->dev, "can not alloc spi_master\n");
1274 return -ENOMEM;
1275 }
1276
1277 drv_data = spi_master_get_devdata(master);
1278 drv_data->master = master;
1279 drv_data->master_info = platform_info;
1280 drv_data->pdev = pdev;
1281 drv_data->pin_req = platform_info->pin_req;
1282
1283 master->bus_num = pdev->id;
1284 master->num_chipselect = platform_info->num_chipselect;
1285 master->cleanup = cleanup;
1286 master->setup = setup;
1287 master->transfer = transfer;
1288
1289 /* Find and map our resources */
1290 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291 if (res == NULL) {
1292 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1293 status = -ENOENT;
1294 goto out_error_get_res;
1295 }
1296
1297 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1298 if (drv_data->regs_base == NULL) {
1299 dev_err(dev, "Cannot map IO\n");
1300 status = -ENXIO;
1301 goto out_error_ioremap;
1302 }
1303
1304 drv_data->dma_channel = platform_get_irq(pdev, 0);
1305 if (drv_data->dma_channel < 0) {
1306 dev_err(dev, "No DMA channel specified\n");
1307 status = -ENOENT;
1308 goto out_error_no_dma_ch;
1309 }
1310
1311 /* Initial and start queue */
1312 status = init_queue(drv_data);
1313 if (status != 0) {
1314 dev_err(dev, "problem initializing queue\n");
1315 goto out_error_queue_alloc;
1316 }
1317
1318 status = start_queue(drv_data);
1319 if (status != 0) {
1320 dev_err(dev, "problem starting queue\n");
1321 goto out_error_queue_alloc;
1322 }
1323
1324 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1325 if (status != 0) {
1326 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1327 goto out_error_queue_alloc;
1328 }
1329
1330 /* Register with the SPI framework */
1331 platform_set_drvdata(pdev, drv_data);
1332 status = spi_register_master(master);
1333 if (status != 0) {
1334 dev_err(dev, "problem registering spi master\n");
1335 goto out_error_queue_alloc;
1336 }
1337
1338 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1339 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1340 drv_data->dma_channel);
1341 return status;
1342
1343 out_error_queue_alloc:
1344 destroy_queue(drv_data);
1345 out_error_no_dma_ch:
1346 iounmap((void *) drv_data->regs_base);
1347 out_error_ioremap:
1348 out_error_get_res:
1349 spi_master_put(master);
1350
1351 return status;
1352 }
1353
1354 /* stop hardware and remove the driver */
1355 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1356 {
1357 struct driver_data *drv_data = platform_get_drvdata(pdev);
1358 int status = 0;
1359
1360 if (!drv_data)
1361 return 0;
1362
1363 /* Remove the queue */
1364 status = destroy_queue(drv_data);
1365 if (status != 0)
1366 return status;
1367
1368 /* Disable the SSP at the peripheral and SOC level */
1369 bfin_spi_disable(drv_data);
1370
1371 /* Release DMA */
1372 if (drv_data->master_info->enable_dma) {
1373 if (dma_channel_active(drv_data->dma_channel))
1374 free_dma(drv_data->dma_channel);
1375 }
1376
1377 /* Disconnect from the SPI framework */
1378 spi_unregister_master(drv_data->master);
1379
1380 peripheral_free_list(drv_data->pin_req);
1381
1382 /* Prevent double remove */
1383 platform_set_drvdata(pdev, NULL);
1384
1385 return 0;
1386 }
1387
1388 #ifdef CONFIG_PM
1389 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1390 {
1391 struct driver_data *drv_data = platform_get_drvdata(pdev);
1392 int status = 0;
1393
1394 status = stop_queue(drv_data);
1395 if (status != 0)
1396 return status;
1397
1398 /* stop hardware */
1399 bfin_spi_disable(drv_data);
1400
1401 return 0;
1402 }
1403
1404 static int bfin5xx_spi_resume(struct platform_device *pdev)
1405 {
1406 struct driver_data *drv_data = platform_get_drvdata(pdev);
1407 int status = 0;
1408
1409 /* Enable the SPI interface */
1410 bfin_spi_enable(drv_data);
1411
1412 /* Start the queue running */
1413 status = start_queue(drv_data);
1414 if (status != 0) {
1415 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1416 return status;
1417 }
1418
1419 return 0;
1420 }
1421 #else
1422 #define bfin5xx_spi_suspend NULL
1423 #define bfin5xx_spi_resume NULL
1424 #endif /* CONFIG_PM */
1425
1426 MODULE_ALIAS("platform:bfin-spi");
1427 static struct platform_driver bfin5xx_spi_driver = {
1428 .driver = {
1429 .name = DRV_NAME,
1430 .owner = THIS_MODULE,
1431 },
1432 .suspend = bfin5xx_spi_suspend,
1433 .resume = bfin5xx_spi_resume,
1434 .remove = __devexit_p(bfin5xx_spi_remove),
1435 };
1436
1437 static int __init bfin5xx_spi_init(void)
1438 {
1439 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1440 }
1441 module_init(bfin5xx_spi_init);
1442
1443 static void __exit bfin5xx_spi_exit(void)
1444 {
1445 platform_driver_unregister(&bfin5xx_spi_driver);
1446 }
1447 module_exit(bfin5xx_spi_exit);
Support for the Chinese Samsung S3C2440 based development boards