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drm: add initial r300 3D support.
[linux-2.6/mini2440.git] / drivers / char / drm / radeon_cp.c
blob6d9080a3ca7e97fefb3302959bb445ce3dc0aac0
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
35 #include "r300_reg.h"
36
37 #define RADEON_FIFO_DEBUG 0
38
39 static int radeon_do_cleanup_cp( drm_device_t *dev );
40
41 /* CP microcode (from ATI) */
42 static u32 R200_cp_microcode[][2] = {
43 { 0x21007000, 0000000000 },
44 { 0x20007000, 0000000000 },
45 { 0x000000ab, 0x00000004 },
46 { 0x000000af, 0x00000004 },
47 { 0x66544a49, 0000000000 },
48 { 0x49494174, 0000000000 },
49 { 0x54517d83, 0000000000 },
50 { 0x498d8b64, 0000000000 },
51 { 0x49494949, 0000000000 },
52 { 0x49da493c, 0000000000 },
53 { 0x49989898, 0000000000 },
54 { 0xd34949d5, 0000000000 },
55 { 0x9dc90e11, 0000000000 },
56 { 0xce9b9b9b, 0000000000 },
57 { 0x000f0000, 0x00000016 },
58 { 0x352e232c, 0000000000 },
59 { 0x00000013, 0x00000004 },
60 { 0x000f0000, 0x00000016 },
61 { 0x352e272c, 0000000000 },
62 { 0x000f0001, 0x00000016 },
63 { 0x3239362f, 0000000000 },
64 { 0x000077ef, 0x00000002 },
65 { 0x00061000, 0x00000002 },
66 { 0x00000020, 0x0000001a },
67 { 0x00004000, 0x0000001e },
68 { 0x00061000, 0x00000002 },
69 { 0x00000020, 0x0000001a },
70 { 0x00004000, 0x0000001e },
71 { 0x00061000, 0x00000002 },
72 { 0x00000020, 0x0000001a },
73 { 0x00004000, 0x0000001e },
74 { 0x00000016, 0x00000004 },
75 { 0x0003802a, 0x00000002 },
76 { 0x040067e0, 0x00000002 },
77 { 0x00000016, 0x00000004 },
78 { 0x000077e0, 0x00000002 },
79 { 0x00065000, 0x00000002 },
80 { 0x000037e1, 0x00000002 },
81 { 0x040067e1, 0x00000006 },
82 { 0x000077e0, 0x00000002 },
83 { 0x000077e1, 0x00000002 },
84 { 0x000077e1, 0x00000006 },
85 { 0xffffffff, 0000000000 },
86 { 0x10000000, 0000000000 },
87 { 0x0003802a, 0x00000002 },
88 { 0x040067e0, 0x00000006 },
89 { 0x00007675, 0x00000002 },
90 { 0x00007676, 0x00000002 },
91 { 0x00007677, 0x00000002 },
92 { 0x00007678, 0x00000006 },
93 { 0x0003802b, 0x00000002 },
94 { 0x04002676, 0x00000002 },
95 { 0x00007677, 0x00000002 },
96 { 0x00007678, 0x00000006 },
97 { 0x0000002e, 0x00000018 },
98 { 0x0000002e, 0x00000018 },
99 { 0000000000, 0x00000006 },
100 { 0x0000002f, 0x00000018 },
101 { 0x0000002f, 0x00000018 },
102 { 0000000000, 0x00000006 },
103 { 0x01605000, 0x00000002 },
104 { 0x00065000, 0x00000002 },
105 { 0x00098000, 0x00000002 },
106 { 0x00061000, 0x00000002 },
107 { 0x64c0603d, 0x00000004 },
108 { 0x00080000, 0x00000016 },
109 { 0000000000, 0000000000 },
110 { 0x0400251d, 0x00000002 },
111 { 0x00007580, 0x00000002 },
112 { 0x00067581, 0x00000002 },
113 { 0x04002580, 0x00000002 },
114 { 0x00067581, 0x00000002 },
115 { 0x00000046, 0x00000004 },
116 { 0x00005000, 0000000000 },
117 { 0x00061000, 0x00000002 },
118 { 0x0000750e, 0x00000002 },
119 { 0x00019000, 0x00000002 },
120 { 0x00011055, 0x00000014 },
121 { 0x00000055, 0x00000012 },
122 { 0x0400250f, 0x00000002 },
123 { 0x0000504a, 0x00000004 },
124 { 0x00007565, 0x00000002 },
125 { 0x00007566, 0x00000002 },
126 { 0x00000051, 0x00000004 },
127 { 0x01e655b4, 0x00000002 },
128 { 0x4401b0dc, 0x00000002 },
129 { 0x01c110dc, 0x00000002 },
130 { 0x2666705d, 0x00000018 },
131 { 0x040c2565, 0x00000002 },
132 { 0x0000005d, 0x00000018 },
133 { 0x04002564, 0x00000002 },
134 { 0x00007566, 0x00000002 },
135 { 0x00000054, 0x00000004 },
136 { 0x00401060, 0x00000008 },
137 { 0x00101000, 0x00000002 },
138 { 0x000d80ff, 0x00000002 },
139 { 0x00800063, 0x00000008 },
140 { 0x000f9000, 0x00000002 },
141 { 0x000e00ff, 0x00000002 },
142 { 0000000000, 0x00000006 },
143 { 0x00000080, 0x00000018 },
144 { 0x00000054, 0x00000004 },
145 { 0x00007576, 0x00000002 },
146 { 0x00065000, 0x00000002 },
147 { 0x00009000, 0x00000002 },
148 { 0x00041000, 0x00000002 },
149 { 0x0c00350e, 0x00000002 },
150 { 0x00049000, 0x00000002 },
151 { 0x00051000, 0x00000002 },
152 { 0x01e785f8, 0x00000002 },
153 { 0x00200000, 0x00000002 },
154 { 0x00600073, 0x0000000c },
155 { 0x00007563, 0x00000002 },
156 { 0x006075f0, 0x00000021 },
157 { 0x20007068, 0x00000004 },
158 { 0x00005068, 0x00000004 },
159 { 0x00007576, 0x00000002 },
160 { 0x00007577, 0x00000002 },
161 { 0x0000750e, 0x00000002 },
162 { 0x0000750f, 0x00000002 },
163 { 0x00a05000, 0x00000002 },
164 { 0x00600076, 0x0000000c },
165 { 0x006075f0, 0x00000021 },
166 { 0x000075f8, 0x00000002 },
167 { 0x00000076, 0x00000004 },
168 { 0x000a750e, 0x00000002 },
169 { 0x0020750f, 0x00000002 },
170 { 0x00600079, 0x00000004 },
171 { 0x00007570, 0x00000002 },
172 { 0x00007571, 0x00000002 },
173 { 0x00007572, 0x00000006 },
174 { 0x00005000, 0x00000002 },
175 { 0x00a05000, 0x00000002 },
176 { 0x00007568, 0x00000002 },
177 { 0x00061000, 0x00000002 },
178 { 0x00000084, 0x0000000c },
179 { 0x00058000, 0x00000002 },
180 { 0x0c607562, 0x00000002 },
181 { 0x00000086, 0x00000004 },
182 { 0x00600085, 0x00000004 },
183 { 0x400070dd, 0000000000 },
184 { 0x000380dd, 0x00000002 },
185 { 0x00000093, 0x0000001c },
186 { 0x00065095, 0x00000018 },
187 { 0x040025bb, 0x00000002 },
188 { 0x00061096, 0x00000018 },
189 { 0x040075bc, 0000000000 },
190 { 0x000075bb, 0x00000002 },
191 { 0x000075bc, 0000000000 },
192 { 0x00090000, 0x00000006 },
193 { 0x00090000, 0x00000002 },
194 { 0x000d8002, 0x00000006 },
195 { 0x00005000, 0x00000002 },
196 { 0x00007821, 0x00000002 },
197 { 0x00007800, 0000000000 },
198 { 0x00007821, 0x00000002 },
199 { 0x00007800, 0000000000 },
200 { 0x01665000, 0x00000002 },
201 { 0x000a0000, 0x00000002 },
202 { 0x000671cc, 0x00000002 },
203 { 0x0286f1cd, 0x00000002 },
204 { 0x000000a3, 0x00000010 },
205 { 0x21007000, 0000000000 },
206 { 0x000000aa, 0x0000001c },
207 { 0x00065000, 0x00000002 },
208 { 0x000a0000, 0x00000002 },
209 { 0x00061000, 0x00000002 },
210 { 0x000b0000, 0x00000002 },
211 { 0x38067000, 0x00000002 },
212 { 0x000a00a6, 0x00000004 },
213 { 0x20007000, 0000000000 },
214 { 0x01200000, 0x00000002 },
215 { 0x20077000, 0x00000002 },
216 { 0x01200000, 0x00000002 },
217 { 0x20007000, 0000000000 },
218 { 0x00061000, 0x00000002 },
219 { 0x0120751b, 0x00000002 },
220 { 0x8040750a, 0x00000002 },
221 { 0x8040750b, 0x00000002 },
222 { 0x00110000, 0x00000002 },
223 { 0x000380dd, 0x00000002 },
224 { 0x000000bd, 0x0000001c },
225 { 0x00061096, 0x00000018 },
226 { 0x844075bd, 0x00000002 },
227 { 0x00061095, 0x00000018 },
228 { 0x840075bb, 0x00000002 },
229 { 0x00061096, 0x00000018 },
230 { 0x844075bc, 0x00000002 },
231 { 0x000000c0, 0x00000004 },
232 { 0x804075bd, 0x00000002 },
233 { 0x800075bb, 0x00000002 },
234 { 0x804075bc, 0x00000002 },
235 { 0x00108000, 0x00000002 },
236 { 0x01400000, 0x00000002 },
237 { 0x006000c4, 0x0000000c },
238 { 0x20c07000, 0x00000020 },
239 { 0x000000c6, 0x00000012 },
240 { 0x00800000, 0x00000006 },
241 { 0x0080751d, 0x00000006 },
242 { 0x000025bb, 0x00000002 },
243 { 0x000040c0, 0x00000004 },
244 { 0x0000775c, 0x00000002 },
245 { 0x00a05000, 0x00000002 },
246 { 0x00661000, 0x00000002 },
247 { 0x0460275d, 0x00000020 },
248 { 0x00004000, 0000000000 },
249 { 0x00007999, 0x00000002 },
250 { 0x00a05000, 0x00000002 },
251 { 0x00661000, 0x00000002 },
252 { 0x0460299b, 0x00000020 },
253 { 0x00004000, 0000000000 },
254 { 0x01e00830, 0x00000002 },
255 { 0x21007000, 0000000000 },
256 { 0x00005000, 0x00000002 },
257 { 0x00038042, 0x00000002 },
258 { 0x040025e0, 0x00000002 },
259 { 0x000075e1, 0000000000 },
260 { 0x00000001, 0000000000 },
261 { 0x000380d9, 0x00000002 },
262 { 0x04007394, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 { 0000000000, 0000000000 },
299 };
300
301
302 static u32 radeon_cp_microcode[][2] = {
303 { 0x21007000, 0000000000 },
304 { 0x20007000, 0000000000 },
305 { 0x000000b4, 0x00000004 },
306 { 0x000000b8, 0x00000004 },
307 { 0x6f5b4d4c, 0000000000 },
308 { 0x4c4c427f, 0000000000 },
309 { 0x5b568a92, 0000000000 },
310 { 0x4ca09c6d, 0000000000 },
311 { 0xad4c4c4c, 0000000000 },
312 { 0x4ce1af3d, 0000000000 },
313 { 0xd8afafaf, 0000000000 },
314 { 0xd64c4cdc, 0000000000 },
315 { 0x4cd10d10, 0000000000 },
316 { 0x000f0000, 0x00000016 },
317 { 0x362f242d, 0000000000 },
318 { 0x00000012, 0x00000004 },
319 { 0x000f0000, 0x00000016 },
320 { 0x362f282d, 0000000000 },
321 { 0x000380e7, 0x00000002 },
322 { 0x04002c97, 0x00000002 },
323 { 0x000f0001, 0x00000016 },
324 { 0x333a3730, 0000000000 },
325 { 0x000077ef, 0x00000002 },
326 { 0x00061000, 0x00000002 },
327 { 0x00000021, 0x0000001a },
328 { 0x00004000, 0x0000001e },
329 { 0x00061000, 0x00000002 },
330 { 0x00000021, 0x0000001a },
331 { 0x00004000, 0x0000001e },
332 { 0x00061000, 0x00000002 },
333 { 0x00000021, 0x0000001a },
334 { 0x00004000, 0x0000001e },
335 { 0x00000017, 0x00000004 },
336 { 0x0003802b, 0x00000002 },
337 { 0x040067e0, 0x00000002 },
338 { 0x00000017, 0x00000004 },
339 { 0x000077e0, 0x00000002 },
340 { 0x00065000, 0x00000002 },
341 { 0x000037e1, 0x00000002 },
342 { 0x040067e1, 0x00000006 },
343 { 0x000077e0, 0x00000002 },
344 { 0x000077e1, 0x00000002 },
345 { 0x000077e1, 0x00000006 },
346 { 0xffffffff, 0000000000 },
347 { 0x10000000, 0000000000 },
348 { 0x0003802b, 0x00000002 },
349 { 0x040067e0, 0x00000006 },
350 { 0x00007675, 0x00000002 },
351 { 0x00007676, 0x00000002 },
352 { 0x00007677, 0x00000002 },
353 { 0x00007678, 0x00000006 },
354 { 0x0003802c, 0x00000002 },
355 { 0x04002676, 0x00000002 },
356 { 0x00007677, 0x00000002 },
357 { 0x00007678, 0x00000006 },
358 { 0x0000002f, 0x00000018 },
359 { 0x0000002f, 0x00000018 },
360 { 0000000000, 0x00000006 },
361 { 0x00000030, 0x00000018 },
362 { 0x00000030, 0x00000018 },
363 { 0000000000, 0x00000006 },
364 { 0x01605000, 0x00000002 },
365 { 0x00065000, 0x00000002 },
366 { 0x00098000, 0x00000002 },
367 { 0x00061000, 0x00000002 },
368 { 0x64c0603e, 0x00000004 },
369 { 0x000380e6, 0x00000002 },
370 { 0x040025c5, 0x00000002 },
371 { 0x00080000, 0x00000016 },
372 { 0000000000, 0000000000 },
373 { 0x0400251d, 0x00000002 },
374 { 0x00007580, 0x00000002 },
375 { 0x00067581, 0x00000002 },
376 { 0x04002580, 0x00000002 },
377 { 0x00067581, 0x00000002 },
378 { 0x00000049, 0x00000004 },
379 { 0x00005000, 0000000000 },
380 { 0x000380e6, 0x00000002 },
381 { 0x040025c5, 0x00000002 },
382 { 0x00061000, 0x00000002 },
383 { 0x0000750e, 0x00000002 },
384 { 0x00019000, 0x00000002 },
385 { 0x00011055, 0x00000014 },
386 { 0x00000055, 0x00000012 },
387 { 0x0400250f, 0x00000002 },
388 { 0x0000504f, 0x00000004 },
389 { 0x000380e6, 0x00000002 },
390 { 0x040025c5, 0x00000002 },
391 { 0x00007565, 0x00000002 },
392 { 0x00007566, 0x00000002 },
393 { 0x00000058, 0x00000004 },
394 { 0x000380e6, 0x00000002 },
395 { 0x040025c5, 0x00000002 },
396 { 0x01e655b4, 0x00000002 },
397 { 0x4401b0e4, 0x00000002 },
398 { 0x01c110e4, 0x00000002 },
399 { 0x26667066, 0x00000018 },
400 { 0x040c2565, 0x00000002 },
401 { 0x00000066, 0x00000018 },
402 { 0x04002564, 0x00000002 },
403 { 0x00007566, 0x00000002 },
404 { 0x0000005d, 0x00000004 },
405 { 0x00401069, 0x00000008 },
406 { 0x00101000, 0x00000002 },
407 { 0x000d80ff, 0x00000002 },
408 { 0x0080006c, 0x00000008 },
409 { 0x000f9000, 0x00000002 },
410 { 0x000e00ff, 0x00000002 },
411 { 0000000000, 0x00000006 },
412 { 0x0000008f, 0x00000018 },
413 { 0x0000005b, 0x00000004 },
414 { 0x000380e6, 0x00000002 },
415 { 0x040025c5, 0x00000002 },
416 { 0x00007576, 0x00000002 },
417 { 0x00065000, 0x00000002 },
418 { 0x00009000, 0x00000002 },
419 { 0x00041000, 0x00000002 },
420 { 0x0c00350e, 0x00000002 },
421 { 0x00049000, 0x00000002 },
422 { 0x00051000, 0x00000002 },
423 { 0x01e785f8, 0x00000002 },
424 { 0x00200000, 0x00000002 },
425 { 0x0060007e, 0x0000000c },
426 { 0x00007563, 0x00000002 },
427 { 0x006075f0, 0x00000021 },
428 { 0x20007073, 0x00000004 },
429 { 0x00005073, 0x00000004 },
430 { 0x000380e6, 0x00000002 },
431 { 0x040025c5, 0x00000002 },
432 { 0x00007576, 0x00000002 },
433 { 0x00007577, 0x00000002 },
434 { 0x0000750e, 0x00000002 },
435 { 0x0000750f, 0x00000002 },
436 { 0x00a05000, 0x00000002 },
437 { 0x00600083, 0x0000000c },
438 { 0x006075f0, 0x00000021 },
439 { 0x000075f8, 0x00000002 },
440 { 0x00000083, 0x00000004 },
441 { 0x000a750e, 0x00000002 },
442 { 0x000380e6, 0x00000002 },
443 { 0x040025c5, 0x00000002 },
444 { 0x0020750f, 0x00000002 },
445 { 0x00600086, 0x00000004 },
446 { 0x00007570, 0x00000002 },
447 { 0x00007571, 0x00000002 },
448 { 0x00007572, 0x00000006 },
449 { 0x000380e6, 0x00000002 },
450 { 0x040025c5, 0x00000002 },
451 { 0x00005000, 0x00000002 },
452 { 0x00a05000, 0x00000002 },
453 { 0x00007568, 0x00000002 },
454 { 0x00061000, 0x00000002 },
455 { 0x00000095, 0x0000000c },
456 { 0x00058000, 0x00000002 },
457 { 0x0c607562, 0x00000002 },
458 { 0x00000097, 0x00000004 },
459 { 0x000380e6, 0x00000002 },
460 { 0x040025c5, 0x00000002 },
461 { 0x00600096, 0x00000004 },
462 { 0x400070e5, 0000000000 },
463 { 0x000380e6, 0x00000002 },
464 { 0x040025c5, 0x00000002 },
465 { 0x000380e5, 0x00000002 },
466 { 0x000000a8, 0x0000001c },
467 { 0x000650aa, 0x00000018 },
468 { 0x040025bb, 0x00000002 },
469 { 0x000610ab, 0x00000018 },
470 { 0x040075bc, 0000000000 },
471 { 0x000075bb, 0x00000002 },
472 { 0x000075bc, 0000000000 },
473 { 0x00090000, 0x00000006 },
474 { 0x00090000, 0x00000002 },
475 { 0x000d8002, 0x00000006 },
476 { 0x00007832, 0x00000002 },
477 { 0x00005000, 0x00000002 },
478 { 0x000380e7, 0x00000002 },
479 { 0x04002c97, 0x00000002 },
480 { 0x00007820, 0x00000002 },
481 { 0x00007821, 0x00000002 },
482 { 0x00007800, 0000000000 },
483 { 0x01200000, 0x00000002 },
484 { 0x20077000, 0x00000002 },
485 { 0x01200000, 0x00000002 },
486 { 0x20007000, 0x00000002 },
487 { 0x00061000, 0x00000002 },
488 { 0x0120751b, 0x00000002 },
489 { 0x8040750a, 0x00000002 },
490 { 0x8040750b, 0x00000002 },
491 { 0x00110000, 0x00000002 },
492 { 0x000380e5, 0x00000002 },
493 { 0x000000c6, 0x0000001c },
494 { 0x000610ab, 0x00000018 },
495 { 0x844075bd, 0x00000002 },
496 { 0x000610aa, 0x00000018 },
497 { 0x840075bb, 0x00000002 },
498 { 0x000610ab, 0x00000018 },
499 { 0x844075bc, 0x00000002 },
500 { 0x000000c9, 0x00000004 },
501 { 0x804075bd, 0x00000002 },
502 { 0x800075bb, 0x00000002 },
503 { 0x804075bc, 0x00000002 },
504 { 0x00108000, 0x00000002 },
505 { 0x01400000, 0x00000002 },
506 { 0x006000cd, 0x0000000c },
507 { 0x20c07000, 0x00000020 },
508 { 0x000000cf, 0x00000012 },
509 { 0x00800000, 0x00000006 },
510 { 0x0080751d, 0x00000006 },
511 { 0000000000, 0000000000 },
512 { 0x0000775c, 0x00000002 },
513 { 0x00a05000, 0x00000002 },
514 { 0x00661000, 0x00000002 },
515 { 0x0460275d, 0x00000020 },
516 { 0x00004000, 0000000000 },
517 { 0x01e00830, 0x00000002 },
518 { 0x21007000, 0000000000 },
519 { 0x6464614d, 0000000000 },
520 { 0x69687420, 0000000000 },
521 { 0x00000073, 0000000000 },
522 { 0000000000, 0000000000 },
523 { 0x00005000, 0x00000002 },
524 { 0x000380d0, 0x00000002 },
525 { 0x040025e0, 0x00000002 },
526 { 0x000075e1, 0000000000 },
527 { 0x00000001, 0000000000 },
528 { 0x000380e0, 0x00000002 },
529 { 0x04002394, 0x00000002 },
530 { 0x00005000, 0000000000 },
531 { 0000000000, 0000000000 },
532 { 0000000000, 0000000000 },
533 { 0x00000008, 0000000000 },
534 { 0x00000004, 0000000000 },
535 { 0000000000, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 { 0000000000, 0000000000 },
559 };
560
561 static u32 R300_cp_microcode[][2] = {
562 { 0x4200e000, 0000000000 },
563 { 0x4000e000, 0000000000 },
564 { 0x000000af, 0x00000008 },
565 { 0x000000b3, 0x00000008 },
566 { 0x6c5a504f, 0000000000 },
567 { 0x4f4f497a, 0000000000 },
568 { 0x5a578288, 0000000000 },
569 { 0x4f91906a, 0000000000 },
570 { 0x4f4f4f4f, 0000000000 },
571 { 0x4fe24f44, 0000000000 },
572 { 0x4f9c9c9c, 0000000000 },
573 { 0xdc4f4fde, 0000000000 },
574 { 0xa1cd4f4f, 0000000000 },
575 { 0xd29d9d9d, 0000000000 },
576 { 0x4f0f9fd7, 0000000000 },
577 { 0x000ca000, 0x00000004 },
578 { 0x000d0012, 0x00000038 },
579 { 0x0000e8b4, 0x00000004 },
580 { 0x000d0014, 0x00000038 },
581 { 0x0000e8b6, 0x00000004 },
582 { 0x000d0016, 0x00000038 },
583 { 0x0000e854, 0x00000004 },
584 { 0x000d0018, 0x00000038 },
585 { 0x0000e855, 0x00000004 },
586 { 0x000d001a, 0x00000038 },
587 { 0x0000e856, 0x00000004 },
588 { 0x000d001c, 0x00000038 },
589 { 0x0000e857, 0x00000004 },
590 { 0x000d001e, 0x00000038 },
591 { 0x0000e824, 0x00000004 },
592 { 0x000d0020, 0x00000038 },
593 { 0x0000e825, 0x00000004 },
594 { 0x000d0022, 0x00000038 },
595 { 0x0000e830, 0x00000004 },
596 { 0x000d0024, 0x00000038 },
597 { 0x0000f0c0, 0x00000004 },
598 { 0x000d0026, 0x00000038 },
599 { 0x0000f0c1, 0x00000004 },
600 { 0x000d0028, 0x00000038 },
601 { 0x0000f041, 0x00000004 },
602 { 0x000d002a, 0x00000038 },
603 { 0x0000f184, 0x00000004 },
604 { 0x000d002c, 0x00000038 },
605 { 0x0000f185, 0x00000004 },
606 { 0x000d002e, 0x00000038 },
607 { 0x0000f186, 0x00000004 },
608 { 0x000d0030, 0x00000038 },
609 { 0x0000f187, 0x00000004 },
610 { 0x000d0032, 0x00000038 },
611 { 0x0000f180, 0x00000004 },
612 { 0x000d0034, 0x00000038 },
613 { 0x0000f393, 0x00000004 },
614 { 0x000d0036, 0x00000038 },
615 { 0x0000f38a, 0x00000004 },
616 { 0x000d0038, 0x00000038 },
617 { 0x0000f38e, 0x00000004 },
618 { 0x0000e821, 0x00000004 },
619 { 0x0140a000, 0x00000004 },
620 { 0x00000043, 0x00000018 },
621 { 0x00cce800, 0x00000004 },
622 { 0x001b0001, 0x00000004 },
623 { 0x08004800, 0x00000004 },
624 { 0x001b0001, 0x00000004 },
625 { 0x08004800, 0x00000004 },
626 { 0x001b0001, 0x00000004 },
627 { 0x08004800, 0x00000004 },
628 { 0x0000003a, 0x00000008 },
629 { 0x0000a000, 0000000000 },
630 { 0x02c0a000, 0x00000004 },
631 { 0x000ca000, 0x00000004 },
632 { 0x00130000, 0x00000004 },
633 { 0x000c2000, 0x00000004 },
634 { 0xc980c045, 0x00000008 },
635 { 0x2000451d, 0x00000004 },
636 { 0x0000e580, 0x00000004 },
637 { 0x000ce581, 0x00000004 },
638 { 0x08004580, 0x00000004 },
639 { 0x000ce581, 0x00000004 },
640 { 0x0000004c, 0x00000008 },
641 { 0x0000a000, 0000000000 },
642 { 0x000c2000, 0x00000004 },
643 { 0x0000e50e, 0x00000004 },
644 { 0x00032000, 0x00000004 },
645 { 0x00022056, 0x00000028 },
646 { 0x00000056, 0x00000024 },
647 { 0x0800450f, 0x00000004 },
648 { 0x0000a050, 0x00000008 },
649 { 0x0000e565, 0x00000004 },
650 { 0x0000e566, 0x00000004 },
651 { 0x00000057, 0x00000008 },
652 { 0x03cca5b4, 0x00000004 },
653 { 0x05432000, 0x00000004 },
654 { 0x00022000, 0x00000004 },
655 { 0x4ccce063, 0x00000030 },
656 { 0x08274565, 0x00000004 },
657 { 0x00000063, 0x00000030 },
658 { 0x08004564, 0x00000004 },
659 { 0x0000e566, 0x00000004 },
660 { 0x0000005a, 0x00000008 },
661 { 0x00802066, 0x00000010 },
662 { 0x00202000, 0x00000004 },
663 { 0x001b00ff, 0x00000004 },
664 { 0x01000069, 0x00000010 },
665 { 0x001f2000, 0x00000004 },
666 { 0x001c00ff, 0x00000004 },
667 { 0000000000, 0x0000000c },
668 { 0x00000085, 0x00000030 },
669 { 0x0000005a, 0x00000008 },
670 { 0x0000e576, 0x00000004 },
671 { 0x000ca000, 0x00000004 },
672 { 0x00012000, 0x00000004 },
673 { 0x00082000, 0x00000004 },
674 { 0x1800650e, 0x00000004 },
675 { 0x00092000, 0x00000004 },
676 { 0x000a2000, 0x00000004 },
677 { 0x000f0000, 0x00000004 },
678 { 0x00400000, 0x00000004 },
679 { 0x00000079, 0x00000018 },
680 { 0x0000e563, 0x00000004 },
681 { 0x00c0e5f9, 0x000000c2 },
682 { 0x0000006e, 0x00000008 },
683 { 0x0000a06e, 0x00000008 },
684 { 0x0000e576, 0x00000004 },
685 { 0x0000e577, 0x00000004 },
686 { 0x0000e50e, 0x00000004 },
687 { 0x0000e50f, 0x00000004 },
688 { 0x0140a000, 0x00000004 },
689 { 0x0000007c, 0x00000018 },
690 { 0x00c0e5f9, 0x000000c2 },
691 { 0x0000007c, 0x00000008 },
692 { 0x0014e50e, 0x00000004 },
693 { 0x0040e50f, 0x00000004 },
694 { 0x00c0007f, 0x00000008 },
695 { 0x0000e570, 0x00000004 },
696 { 0x0000e571, 0x00000004 },
697 { 0x0000e572, 0x0000000c },
698 { 0x0000a000, 0x00000004 },
699 { 0x0140a000, 0x00000004 },
700 { 0x0000e568, 0x00000004 },
701 { 0x000c2000, 0x00000004 },
702 { 0x00000089, 0x00000018 },
703 { 0x000b0000, 0x00000004 },
704 { 0x18c0e562, 0x00000004 },
705 { 0x0000008b, 0x00000008 },
706 { 0x00c0008a, 0x00000008 },
707 { 0x000700e4, 0x00000004 },
708 { 0x00000097, 0x00000038 },
709 { 0x000ca099, 0x00000030 },
710 { 0x080045bb, 0x00000004 },
711 { 0x000c209a, 0x00000030 },
712 { 0x0800e5bc, 0000000000 },
713 { 0x0000e5bb, 0x00000004 },
714 { 0x0000e5bc, 0000000000 },
715 { 0x00120000, 0x0000000c },
716 { 0x00120000, 0x00000004 },
717 { 0x001b0002, 0x0000000c },
718 { 0x0000a000, 0x00000004 },
719 { 0x0000e821, 0x00000004 },
720 { 0x0000e800, 0000000000 },
721 { 0x0000e821, 0x00000004 },
722 { 0x0000e82e, 0000000000 },
723 { 0x02cca000, 0x00000004 },
724 { 0x00140000, 0x00000004 },
725 { 0x000ce1cc, 0x00000004 },
726 { 0x050de1cd, 0x00000004 },
727 { 0x000000a7, 0x00000020 },
728 { 0x4200e000, 0000000000 },
729 { 0x000000ae, 0x00000038 },
730 { 0x000ca000, 0x00000004 },
731 { 0x00140000, 0x00000004 },
732 { 0x000c2000, 0x00000004 },
733 { 0x00160000, 0x00000004 },
734 { 0x700ce000, 0x00000004 },
735 { 0x001400aa, 0x00000008 },
736 { 0x4000e000, 0000000000 },
737 { 0x02400000, 0x00000004 },
738 { 0x400ee000, 0x00000004 },
739 { 0x02400000, 0x00000004 },
740 { 0x4000e000, 0000000000 },
741 { 0x000c2000, 0x00000004 },
742 { 0x0240e51b, 0x00000004 },
743 { 0x0080e50a, 0x00000005 },
744 { 0x0080e50b, 0x00000005 },
745 { 0x00220000, 0x00000004 },
746 { 0x000700e4, 0x00000004 },
747 { 0x000000c1, 0x00000038 },
748 { 0x000c209a, 0x00000030 },
749 { 0x0880e5bd, 0x00000005 },
750 { 0x000c2099, 0x00000030 },
751 { 0x0800e5bb, 0x00000005 },
752 { 0x000c209a, 0x00000030 },
753 { 0x0880e5bc, 0x00000005 },
754 { 0x000000c4, 0x00000008 },
755 { 0x0080e5bd, 0x00000005 },
756 { 0x0000e5bb, 0x00000005 },
757 { 0x0080e5bc, 0x00000005 },
758 { 0x00210000, 0x00000004 },
759 { 0x02800000, 0x00000004 },
760 { 0x00c000c8, 0x00000018 },
761 { 0x4180e000, 0x00000040 },
762 { 0x000000ca, 0x00000024 },
763 { 0x01000000, 0x0000000c },
764 { 0x0100e51d, 0x0000000c },
765 { 0x000045bb, 0x00000004 },
766 { 0x000080c4, 0x00000008 },
767 { 0x0000f3ce, 0x00000004 },
768 { 0x0140a000, 0x00000004 },
769 { 0x00cc2000, 0x00000004 },
770 { 0x08c053cf, 0x00000040 },
771 { 0x00008000, 0000000000 },
772 { 0x0000f3d2, 0x00000004 },
773 { 0x0140a000, 0x00000004 },
774 { 0x00cc2000, 0x00000004 },
775 { 0x08c053d3, 0x00000040 },
776 { 0x00008000, 0000000000 },
777 { 0x0000f39d, 0x00000004 },
778 { 0x0140a000, 0x00000004 },
779 { 0x00cc2000, 0x00000004 },
780 { 0x08c0539e, 0x00000040 },
781 { 0x00008000, 0000000000 },
782 { 0x03c00830, 0x00000004 },
783 { 0x4200e000, 0000000000 },
784 { 0x0000a000, 0x00000004 },
785 { 0x200045e0, 0x00000004 },
786 { 0x0000e5e1, 0000000000 },
787 { 0x00000001, 0000000000 },
788 { 0x000700e1, 0x00000004 },
789 { 0x0800e394, 0000000000 },
790 { 0000000000, 0000000000 },
791 { 0000000000, 0000000000 },
792 { 0000000000, 0000000000 },
793 { 0000000000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0000000000, 0000000000 },
796 { 0000000000, 0000000000 },
797 { 0000000000, 0000000000 },
798 { 0000000000, 0000000000 },
799 { 0000000000, 0000000000 },
800 { 0000000000, 0000000000 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805 { 0000000000, 0000000000 },
806 { 0000000000, 0000000000 },
807 { 0000000000, 0000000000 },
808 { 0000000000, 0000000000 },
809 { 0000000000, 0000000000 },
810 { 0000000000, 0000000000 },
811 { 0000000000, 0000000000 },
812 { 0000000000, 0000000000 },
813 { 0000000000, 0000000000 },
814 { 0000000000, 0000000000 },
815 { 0000000000, 0000000000 },
816 { 0000000000, 0000000000 },
817 { 0000000000, 0000000000 },
818 };
819
820 static int RADEON_READ_PLL(drm_device_t *dev, int addr)
821 {
822 drm_radeon_private_t *dev_priv = dev->dev_private;
823
824 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
825 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
826 }
827
828 #if RADEON_FIFO_DEBUG
829 static void radeon_status( drm_radeon_private_t *dev_priv )
830 {
831 printk( "%s:\n", __FUNCTION__ );
832 printk( "RBBM_STATUS = 0x%08x\n",
833 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
834 printk( "CP_RB_RTPR = 0x%08x\n",
835 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
836 printk( "CP_RB_WTPR = 0x%08x\n",
837 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
838 printk( "AIC_CNTL = 0x%08x\n",
839 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
840 printk( "AIC_STAT = 0x%08x\n",
841 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
842 printk( "AIC_PT_BASE = 0x%08x\n",
843 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
844 printk( "TLB_ADDR = 0x%08x\n",
845 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
846 printk( "TLB_DATA = 0x%08x\n",
847 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
848 }
849 #endif
850
851
852 /* ================================================================
853 * Engine, FIFO control
854 */
855
856 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
857 {
858 u32 tmp;
859 int i;
860
861 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
862
863 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
864 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
865 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
866
867 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
868 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
869 & RADEON_RB2D_DC_BUSY) ) {
870 return 0;
871 }
872 DRM_UDELAY( 1 );
873 }
874
875 #if RADEON_FIFO_DEBUG
876 DRM_ERROR( "failed!\n" );
877 radeon_status( dev_priv );
878 #endif
879 return DRM_ERR(EBUSY);
880 }
881
882 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
883 int entries )
884 {
885 int i;
886
887 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
888
889 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
890 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
891 & RADEON_RBBM_FIFOCNT_MASK );
892 if ( slots >= entries ) return 0;
893 DRM_UDELAY( 1 );
894 }
895
896 #if RADEON_FIFO_DEBUG
897 DRM_ERROR( "failed!\n" );
898 radeon_status( dev_priv );
899 #endif
900 return DRM_ERR(EBUSY);
901 }
902
903 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
904 {
905 int i, ret;
906
907 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
908
909 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
910 if ( ret ) return ret;
911
912 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
913 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
914 & RADEON_RBBM_ACTIVE) ) {
915 radeon_do_pixcache_flush( dev_priv );
916 return 0;
917 }
918 DRM_UDELAY( 1 );
919 }
920
921 #if RADEON_FIFO_DEBUG
922 DRM_ERROR( "failed!\n" );
923 radeon_status( dev_priv );
924 #endif
925 return DRM_ERR(EBUSY);
926 }
927
928
929 /* ================================================================
930 * CP control, initialization
931 */
932
933 /* Load the microcode for the CP */
934 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
935 {
936 int i;
937 DRM_DEBUG( "\n" );
938
939 radeon_do_wait_for_idle( dev_priv );
940
941 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
942
943 if (dev_priv->microcode_version==UCODE_R200) {
944 DRM_INFO("Loading R200 Microcode\n");
945 for ( i = 0 ; i < 256 ; i++ )
946 {
947 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
948 R200_cp_microcode[i][1] );
949 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
950 R200_cp_microcode[i][0] );
951 }
952 } else if (dev_priv->microcode_version==UCODE_R300) {
953 DRM_INFO("Loading R300 Microcode\n");
954 for ( i = 0 ; i < 256 ; i++ )
955 {
956 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
957 R300_cp_microcode[i][1] );
958 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
959 R300_cp_microcode[i][0] );
960 }
961 } else {
962 for ( i = 0 ; i < 256 ; i++ ) {
963 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
964 radeon_cp_microcode[i][1] );
965 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
966 radeon_cp_microcode[i][0] );
967 }
968 }
969 }
970
971 /* Flush any pending commands to the CP. This should only be used just
972 * prior to a wait for idle, as it informs the engine that the command
973 * stream is ending.
974 */
975 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
976 {
977 DRM_DEBUG( "\n" );
978 #if 0
979 u32 tmp;
980
981 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
982 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
983 #endif
984 }
985
986 /* Wait for the CP to go idle.
987 */
988 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
989 {
990 RING_LOCALS;
991 DRM_DEBUG( "\n" );
992
993 BEGIN_RING( 6 );
994
995 RADEON_PURGE_CACHE();
996 RADEON_PURGE_ZCACHE();
997 RADEON_WAIT_UNTIL_IDLE();
998
999 ADVANCE_RING();
1000 COMMIT_RING();
1001
1002 return radeon_do_wait_for_idle( dev_priv );
1003 }
1004
1005 /* Start the Command Processor.
1006 */
1007 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
1008 {
1009 RING_LOCALS;
1010 DRM_DEBUG( "\n" );
1011
1012 radeon_do_wait_for_idle( dev_priv );
1013
1014 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
1015
1016 dev_priv->cp_running = 1;
1017
1018 BEGIN_RING( 6 );
1019
1020 RADEON_PURGE_CACHE();
1021 RADEON_PURGE_ZCACHE();
1022 RADEON_WAIT_UNTIL_IDLE();
1023
1024 ADVANCE_RING();
1025 COMMIT_RING();
1026 }
1027
1028 /* Reset the Command Processor. This will not flush any pending
1029 * commands, so you must wait for the CP command stream to complete
1030 * before calling this routine.
1031 */
1032 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
1033 {
1034 u32 cur_read_ptr;
1035 DRM_DEBUG( "\n" );
1036
1037 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1038 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1039 SET_RING_HEAD( dev_priv, cur_read_ptr );
1040 dev_priv->ring.tail = cur_read_ptr;
1041 }
1042
1043 /* Stop the Command Processor. This will not flush any pending
1044 * commands, so you must flush the command stream and wait for the CP
1045 * to go idle before calling this routine.
1046 */
1047 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
1048 {
1049 DRM_DEBUG( "\n" );
1050
1051 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
1052
1053 dev_priv->cp_running = 0;
1054 }
1055
1056 /* Reset the engine. This will stop the CP if it is running.
1057 */
1058 static int radeon_do_engine_reset( drm_device_t *dev )
1059 {
1060 drm_radeon_private_t *dev_priv = dev->dev_private;
1061 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1062 DRM_DEBUG( "\n" );
1063
1064 radeon_do_pixcache_flush( dev_priv );
1065
1066 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
1067 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
1068
1069 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
1070 RADEON_FORCEON_MCLKA |
1071 RADEON_FORCEON_MCLKB |
1072 RADEON_FORCEON_YCLKA |
1073 RADEON_FORCEON_YCLKB |
1074 RADEON_FORCEON_MC |
1075 RADEON_FORCEON_AIC ) );
1076
1077 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
1078
1079 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
1080 RADEON_SOFT_RESET_CP |
1081 RADEON_SOFT_RESET_HI |
1082 RADEON_SOFT_RESET_SE |
1083 RADEON_SOFT_RESET_RE |
1084 RADEON_SOFT_RESET_PP |
1085 RADEON_SOFT_RESET_E2 |
1086 RADEON_SOFT_RESET_RB ) );
1087 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1088 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
1089 ~( RADEON_SOFT_RESET_CP |
1090 RADEON_SOFT_RESET_HI |
1091 RADEON_SOFT_RESET_SE |
1092 RADEON_SOFT_RESET_RE |
1093 RADEON_SOFT_RESET_PP |
1094 RADEON_SOFT_RESET_E2 |
1095 RADEON_SOFT_RESET_RB ) ) );
1096 RADEON_READ( RADEON_RBBM_SOFT_RESET );
1097
1098
1099 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
1100 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
1101 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
1102
1103 /* Reset the CP ring */
1104 radeon_do_cp_reset( dev_priv );
1105
1106 /* The CP is no longer running after an engine reset */
1107 dev_priv->cp_running = 0;
1108
1109 /* Reset any pending vertex, indirect buffers */
1110 radeon_freelist_reset( dev );
1111
1112 return 0;
1113 }
1114
1115 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
1116 drm_radeon_private_t *dev_priv )
1117 {
1118 u32 ring_start, cur_read_ptr;
1119 u32 tmp;
1120
1121 /* Initialize the memory controller */
1122 RADEON_WRITE( RADEON_MC_FB_LOCATION,
1123 ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
1124 | ( dev_priv->fb_location >> 16 ) );
1125
1126 #if __OS_HAS_AGP
1127 if ( !dev_priv->is_pci ) {
1128 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
1129 (((dev_priv->gart_vm_start - 1 +
1130 dev_priv->gart_size) & 0xffff0000) |
1131 (dev_priv->gart_vm_start >> 16)) );
1132
1133 ring_start = (dev_priv->cp_ring->offset
1134 - dev->agp->base
1135 + dev_priv->gart_vm_start);
1136 } else
1137 #endif
1138 ring_start = (dev_priv->cp_ring->offset
1139 - dev->sg->handle
1140 + dev_priv->gart_vm_start);
1141
1142 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
1143
1144 /* Set the write pointer delay */
1145 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
1146
1147 /* Initialize the ring buffer's read and write pointers */
1148 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
1149 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
1150 SET_RING_HEAD( dev_priv, cur_read_ptr );
1151 dev_priv->ring.tail = cur_read_ptr;
1152
1153 #if __OS_HAS_AGP
1154 if ( !dev_priv->is_pci ) {
1155 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1156 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1157 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1158 dev_priv->ring_rptr->offset
1159 - dev->agp->base
1160 + dev_priv->gart_vm_start);
1161 } else
1162 #endif
1163 {
1164 drm_sg_mem_t *entry = dev->sg;
1165 unsigned long tmp_ofs, page_ofs;
1166
1167 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1168 page_ofs = tmp_ofs >> PAGE_SHIFT;
1169
1170 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
1171 entry->busaddr[page_ofs]);
1172 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
1173 (unsigned long) entry->busaddr[page_ofs],
1174 entry->handle + tmp_ofs );
1175 }
1176
1177 /* Initialize the scratch register pointer. This will cause
1178 * the scratch register values to be written out to memory
1179 * whenever they are updated.
1180 *
1181 * We simply put this behind the ring read pointer, this works
1182 * with PCI GART as well as (whatever kind of) AGP GART
1183 */
1184 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
1185 + RADEON_SCRATCH_REG_OFFSET );
1186
1187 dev_priv->scratch = ((__volatile__ u32 *)
1188 dev_priv->ring_rptr->handle +
1189 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1190
1191 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
1192
1193 /* Writeback doesn't seem to work everywhere, test it first */
1194 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
1195 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
1196
1197 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
1198 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
1199 break;
1200 DRM_UDELAY( 1 );
1201 }
1202
1203 if ( tmp < dev_priv->usec_timeout ) {
1204 dev_priv->writeback_works = 1;
1205 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
1206 } else {
1207 dev_priv->writeback_works = 0;
1208 DRM_DEBUG( "writeback test failed\n" );
1209 }
1210
1211 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1212 RADEON_WRITE( RADEON_LAST_FRAME_REG,
1213 dev_priv->sarea_priv->last_frame );
1214
1215 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1216 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
1217 dev_priv->sarea_priv->last_dispatch );
1218
1219 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1220 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
1221 dev_priv->sarea_priv->last_clear );
1222
1223 /* Set ring buffer size */
1224 #ifdef __BIG_ENDIAN
1225 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
1226 #else
1227 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
1228 #endif
1229
1230 radeon_do_wait_for_idle( dev_priv );
1231
1232 /* Turn on bus mastering */
1233 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
1234 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
1235
1236 /* Sync everything up */
1237 RADEON_WRITE( RADEON_ISYNC_CNTL,
1238 (RADEON_ISYNC_ANY2D_IDLE3D |
1239 RADEON_ISYNC_ANY3D_IDLE2D |
1240 RADEON_ISYNC_WAIT_IDLEGUI |
1241 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
1242 }
1243
1244 /* Enable or disable PCI GART on the chip */
1245 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
1246 {
1247 u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
1248
1249 if ( on ) {
1250 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
1251
1252 /* set PCI GART page-table base address
1253 */
1254 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1255
1256 /* set address range for PCI address translate
1257 */
1258 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
1259 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1260 + dev_priv->gart_size - 1);
1261
1262 /* Turn off AGP aperture -- is this required for PCI GART?
1263 */
1264 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1265 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1266 } else {
1267 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1268 }
1269 }
1270
1271 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1272 {
1273 drm_radeon_private_t *dev_priv = dev->dev_private;;
1274 DRM_DEBUG( "\n" );
1275
1276 dev_priv->is_pci = init->is_pci;
1277
1278 if ( dev_priv->is_pci && !dev->sg ) {
1279 DRM_ERROR( "PCI GART memory not allocated!\n" );
1280 dev->dev_private = (void *)dev_priv;
1281 radeon_do_cleanup_cp(dev);
1282 return DRM_ERR(EINVAL);
1283 }
1284
1285 dev_priv->usec_timeout = init->usec_timeout;
1286 if ( dev_priv->usec_timeout < 1 ||
1287 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1288 DRM_DEBUG( "TIMEOUT problem!\n" );
1289 dev->dev_private = (void *)dev_priv;
1290 radeon_do_cleanup_cp(dev);
1291 return DRM_ERR(EINVAL);
1292 }
1293
1294 switch(init->func) {
1295 case RADEON_INIT_R200_CP:
1296 dev_priv->microcode_version=UCODE_R200;
1297 break;
1298 case RADEON_INIT_R300_CP:
1299 dev_priv->microcode_version=UCODE_R300;
1300 break;
1301 default:
1302 dev_priv->microcode_version=UCODE_R100;
1303 }
1304
1305 dev_priv->do_boxes = 0;
1306 dev_priv->cp_mode = init->cp_mode;
1307
1308 /* We don't support anything other than bus-mastering ring mode,
1309 * but the ring can be in either AGP or PCI space for the ring
1310 * read pointer.
1311 */
1312 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1313 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1314 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1315 dev->dev_private = (void *)dev_priv;
1316 radeon_do_cleanup_cp(dev);
1317 return DRM_ERR(EINVAL);
1318 }
1319
1320 switch ( init->fb_bpp ) {
1321 case 16:
1322 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1323 break;
1324 case 32:
1325 default:
1326 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1327 break;
1328 }
1329 dev_priv->front_offset = init->front_offset;
1330 dev_priv->front_pitch = init->front_pitch;
1331 dev_priv->back_offset = init->back_offset;
1332 dev_priv->back_pitch = init->back_pitch;
1333
1334 switch ( init->depth_bpp ) {
1335 case 16:
1336 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1337 break;
1338 case 32:
1339 default:
1340 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1341 break;
1342 }
1343 dev_priv->depth_offset = init->depth_offset;
1344 dev_priv->depth_pitch = init->depth_pitch;
1345
1346 /* Hardware state for depth clears. Remove this if/when we no
1347 * longer clear the depth buffer with a 3D rectangle. Hard-code
1348 * all values to prevent unwanted 3D state from slipping through
1349 * and screwing with the clear operation.
1350 */
1351 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1352 (dev_priv->color_fmt << 10) |
1353 (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1354
1355 dev_priv->depth_clear.rb3d_zstencilcntl =
1356 (dev_priv->depth_fmt |
1357 RADEON_Z_TEST_ALWAYS |
1358 RADEON_STENCIL_TEST_ALWAYS |
1359 RADEON_STENCIL_S_FAIL_REPLACE |
1360 RADEON_STENCIL_ZPASS_REPLACE |
1361 RADEON_STENCIL_ZFAIL_REPLACE |
1362 RADEON_Z_WRITE_ENABLE);
1363
1364 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1365 RADEON_BFACE_SOLID |
1366 RADEON_FFACE_SOLID |
1367 RADEON_FLAT_SHADE_VTX_LAST |
1368 RADEON_DIFFUSE_SHADE_FLAT |
1369 RADEON_ALPHA_SHADE_FLAT |
1370 RADEON_SPECULAR_SHADE_FLAT |
1371 RADEON_FOG_SHADE_FLAT |
1372 RADEON_VTX_PIX_CENTER_OGL |
1373 RADEON_ROUND_MODE_TRUNC |
1374 RADEON_ROUND_PREC_8TH_PIX);
1375
1376 DRM_GETSAREA();
1377
1378 dev_priv->fb_offset = init->fb_offset;
1379 dev_priv->mmio_offset = init->mmio_offset;
1380 dev_priv->ring_offset = init->ring_offset;
1381 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1382 dev_priv->buffers_offset = init->buffers_offset;
1383 dev_priv->gart_textures_offset = init->gart_textures_offset;
1384
1385 if(!dev_priv->sarea) {
1386 DRM_ERROR("could not find sarea!\n");
1387 dev->dev_private = (void *)dev_priv;
1388 radeon_do_cleanup_cp(dev);
1389 return DRM_ERR(EINVAL);
1390 }
1391
1392 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1393 if(!dev_priv->mmio) {
1394 DRM_ERROR("could not find mmio region!\n");
1395 dev->dev_private = (void *)dev_priv;
1396 radeon_do_cleanup_cp(dev);
1397 return DRM_ERR(EINVAL);
1398 }
1399 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1400 if(!dev_priv->cp_ring) {
1401 DRM_ERROR("could not find cp ring region!\n");
1402 dev->dev_private = (void *)dev_priv;
1403 radeon_do_cleanup_cp(dev);
1404 return DRM_ERR(EINVAL);
1405 }
1406 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1407 if(!dev_priv->ring_rptr) {
1408 DRM_ERROR("could not find ring read pointer!\n");
1409 dev->dev_private = (void *)dev_priv;
1410 radeon_do_cleanup_cp(dev);
1411 return DRM_ERR(EINVAL);
1412 }
1413 dev->agp_buffer_token = init->buffers_offset;
1414 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1415 if(!dev->agp_buffer_map) {
1416 DRM_ERROR("could not find dma buffer region!\n");
1417 dev->dev_private = (void *)dev_priv;
1418 radeon_do_cleanup_cp(dev);
1419 return DRM_ERR(EINVAL);
1420 }
1421
1422 if ( init->gart_textures_offset ) {
1423 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1424 if ( !dev_priv->gart_textures ) {
1425 DRM_ERROR("could not find GART texture region!\n");
1426 dev->dev_private = (void *)dev_priv;
1427 radeon_do_cleanup_cp(dev);
1428 return DRM_ERR(EINVAL);
1429 }
1430 }
1431
1432 dev_priv->sarea_priv =
1433 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1434 init->sarea_priv_offset);
1435
1436 #if __OS_HAS_AGP
1437 if ( !dev_priv->is_pci ) {
1438 drm_core_ioremap( dev_priv->cp_ring, dev );
1439 drm_core_ioremap( dev_priv->ring_rptr, dev );
1440 drm_core_ioremap( dev->agp_buffer_map, dev );
1441 if(!dev_priv->cp_ring->handle ||
1442 !dev_priv->ring_rptr->handle ||
1443 !dev->agp_buffer_map->handle) {
1444 DRM_ERROR("could not find ioremap agp regions!\n");
1445 dev->dev_private = (void *)dev_priv;
1446 radeon_do_cleanup_cp(dev);
1447 return DRM_ERR(EINVAL);
1448 }
1449 } else
1450 #endif
1451 {
1452 dev_priv->cp_ring->handle =
1453 (void *)dev_priv->cp_ring->offset;
1454 dev_priv->ring_rptr->handle =
1455 (void *)dev_priv->ring_rptr->offset;
1456 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1457
1458 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1459 dev_priv->cp_ring->handle );
1460 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1461 dev_priv->ring_rptr->handle );
1462 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1463 dev->agp_buffer_map->handle );
1464 }
1465
1466 dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1467 & 0xffff ) << 16;
1468
1469 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1470 ( ( dev_priv->front_offset
1471 + dev_priv->fb_location ) >> 10 ) );
1472
1473 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1474 ( ( dev_priv->back_offset
1475 + dev_priv->fb_location ) >> 10 ) );
1476
1477 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1478 ( ( dev_priv->depth_offset
1479 + dev_priv->fb_location ) >> 10 ) );
1480
1481
1482 dev_priv->gart_size = init->gart_size;
1483 dev_priv->gart_vm_start = dev_priv->fb_location
1484 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1485
1486 #if __OS_HAS_AGP
1487 if ( !dev_priv->is_pci )
1488 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1489 - dev->agp->base
1490 + dev_priv->gart_vm_start);
1491 else
1492 #endif
1493 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1494 - dev->sg->handle
1495 + dev_priv->gart_vm_start);
1496
1497 DRM_DEBUG( "dev_priv->gart_size %d\n",
1498 dev_priv->gart_size );
1499 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1500 dev_priv->gart_vm_start );
1501 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1502 dev_priv->gart_buffers_offset );
1503
1504 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1505 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1506 + init->ring_size / sizeof(u32));
1507 dev_priv->ring.size = init->ring_size;
1508 dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 );
1509
1510 dev_priv->ring.tail_mask =
1511 (dev_priv->ring.size / sizeof(u32)) - 1;
1512
1513 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1514
1515 #if __OS_HAS_AGP
1516 if ( !dev_priv->is_pci ) {
1517 /* Turn off PCI GART */
1518 radeon_set_pcigart( dev_priv, 0 );
1519 } else
1520 #endif
1521 {
1522 if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
1523 &dev_priv->bus_pci_gart)) {
1524 DRM_ERROR( "failed to init PCI GART!\n" );
1525 dev->dev_private = (void *)dev_priv;
1526 radeon_do_cleanup_cp(dev);
1527 return DRM_ERR(ENOMEM);
1528 }
1529
1530 /* Turn on PCI GART */
1531 radeon_set_pcigart( dev_priv, 1 );
1532 }
1533
1534 radeon_cp_load_microcode( dev_priv );
1535 radeon_cp_init_ring_buffer( dev, dev_priv );
1536
1537 dev_priv->last_buf = 0;
1538
1539 dev->dev_private = (void *)dev_priv;
1540
1541 radeon_do_engine_reset( dev );
1542
1543 return 0;
1544 }
1545
1546 static int radeon_do_cleanup_cp( drm_device_t *dev )
1547 {
1548 drm_radeon_private_t *dev_priv = dev->dev_private;
1549 DRM_DEBUG( "\n" );
1550
1551 /* Make sure interrupts are disabled here because the uninstall ioctl
1552 * may not have been called from userspace and after dev_private
1553 * is freed, it's too late.
1554 */
1555 if ( dev->irq_enabled ) drm_irq_uninstall(dev);
1556
1557 #if __OS_HAS_AGP
1558 if ( !dev_priv->is_pci ) {
1559 if ( dev_priv->cp_ring != NULL )
1560 drm_core_ioremapfree( dev_priv->cp_ring, dev );
1561 if ( dev_priv->ring_rptr != NULL )
1562 drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1563 if ( dev->agp_buffer_map != NULL )
1564 {
1565 drm_core_ioremapfree( dev->agp_buffer_map, dev );
1566 dev->agp_buffer_map = NULL;
1567 }
1568 } else
1569 #endif
1570 {
1571 if (!drm_ati_pcigart_cleanup( dev,
1572 dev_priv->phys_pci_gart,
1573 dev_priv->bus_pci_gart ))
1574 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1575 }
1576
1577 /* only clear to the start of flags */
1578 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1579
1580 return 0;
1581 }
1582
1583 /* This code will reinit the Radeon CP hardware after a resume from disc.
1584 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1585 * here we make sure that all Radeon hardware initialisation is re-done without
1586 * affecting running applications.
1587 *
1588 * Charl P. Botha <http://cpbotha.net>
1589 */
1590 static int radeon_do_resume_cp( drm_device_t *dev )
1591 {
1592 drm_radeon_private_t *dev_priv = dev->dev_private;
1593
1594 if ( !dev_priv ) {
1595 DRM_ERROR( "Called with no initialization\n" );
1596 return DRM_ERR( EINVAL );
1597 }
1598
1599 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1600
1601 #if __OS_HAS_AGP
1602 if ( !dev_priv->is_pci ) {
1603 /* Turn off PCI GART */
1604 radeon_set_pcigart( dev_priv, 0 );
1605 } else
1606 #endif
1607 {
1608 /* Turn on PCI GART */
1609 radeon_set_pcigart( dev_priv, 1 );
1610 }
1611
1612 radeon_cp_load_microcode( dev_priv );
1613 radeon_cp_init_ring_buffer( dev, dev_priv );
1614
1615 radeon_do_engine_reset( dev );
1616
1617 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1618
1619 return 0;
1620 }
1621
1622
1623 int radeon_cp_init( DRM_IOCTL_ARGS )
1624 {
1625 DRM_DEVICE;
1626 drm_radeon_init_t init;
1627
1628 LOCK_TEST_WITH_RETURN( dev, filp );
1629
1630 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1631
1632 if(init.func == RADEON_INIT_R300_CP)
1633 r300_init_reg_flags();
1634
1635 switch ( init.func ) {
1636 case RADEON_INIT_CP:
1637 case RADEON_INIT_R200_CP:
1638 case RADEON_INIT_R300_CP:
1639 return radeon_do_init_cp( dev, &init );
1640 case RADEON_CLEANUP_CP:
1641 return radeon_do_cleanup_cp( dev );
1642 }
1643
1644 return DRM_ERR(EINVAL);
1645 }
1646
1647 int radeon_cp_start( DRM_IOCTL_ARGS )
1648 {
1649 DRM_DEVICE;
1650 drm_radeon_private_t *dev_priv = dev->dev_private;
1651 DRM_DEBUG( "\n" );
1652
1653 LOCK_TEST_WITH_RETURN( dev, filp );
1654
1655 if ( dev_priv->cp_running ) {
1656 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1657 return 0;
1658 }
1659 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1660 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1661 __FUNCTION__, dev_priv->cp_mode );
1662 return 0;
1663 }
1664
1665 radeon_do_cp_start( dev_priv );
1666
1667 return 0;
1668 }
1669
1670 /* Stop the CP. The engine must have been idled before calling this
1671 * routine.
1672 */
1673 int radeon_cp_stop( DRM_IOCTL_ARGS )
1674 {
1675 DRM_DEVICE;
1676 drm_radeon_private_t *dev_priv = dev->dev_private;
1677 drm_radeon_cp_stop_t stop;
1678 int ret;
1679 DRM_DEBUG( "\n" );
1680
1681 LOCK_TEST_WITH_RETURN( dev, filp );
1682
1683 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1684
1685 if (!dev_priv->cp_running)
1686 return 0;
1687
1688 /* Flush any pending CP commands. This ensures any outstanding
1689 * commands are exectuted by the engine before we turn it off.
1690 */
1691 if ( stop.flush ) {
1692 radeon_do_cp_flush( dev_priv );
1693 }
1694
1695 /* If we fail to make the engine go idle, we return an error
1696 * code so that the DRM ioctl wrapper can try again.
1697 */
1698 if ( stop.idle ) {
1699 ret = radeon_do_cp_idle( dev_priv );
1700 if ( ret ) return ret;
1701 }
1702
1703 /* Finally, we can turn off the CP. If the engine isn't idle,
1704 * we will get some dropped triangles as they won't be fully
1705 * rendered before the CP is shut down.
1706 */
1707 radeon_do_cp_stop( dev_priv );
1708
1709 /* Reset the engine */
1710 radeon_do_engine_reset( dev );
1711
1712 return 0;
1713 }
1714
1715
1716 void radeon_do_release( drm_device_t *dev )
1717 {
1718 drm_radeon_private_t *dev_priv = dev->dev_private;
1719 int i, ret;
1720
1721 if (dev_priv) {
1722 if (dev_priv->cp_running) {
1723 /* Stop the cp */
1724 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1725 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1726 #ifdef __linux__
1727 schedule();
1728 #else
1729 tsleep(&ret, PZERO, "rdnrel", 1);
1730 #endif
1731 }
1732 radeon_do_cp_stop( dev_priv );
1733 radeon_do_engine_reset( dev );
1734 }
1735
1736 /* Disable *all* interrupts */
1737 if (dev_priv->mmio) /* remove this after permanent addmaps */
1738 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1739
1740 if (dev_priv->mmio) {/* remove all surfaces */
1741 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1742 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1743 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1744 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1745 }
1746 }
1747
1748 /* Free memory heap structures */
1749 radeon_mem_takedown( &(dev_priv->gart_heap) );
1750 radeon_mem_takedown( &(dev_priv->fb_heap) );
1751
1752 /* deallocate kernel resources */
1753 radeon_do_cleanup_cp( dev );
1754 }
1755 }
1756
1757 /* Just reset the CP ring. Called as part of an X Server engine reset.
1758 */
1759 int radeon_cp_reset( DRM_IOCTL_ARGS )
1760 {
1761 DRM_DEVICE;
1762 drm_radeon_private_t *dev_priv = dev->dev_private;
1763 DRM_DEBUG( "\n" );
1764
1765 LOCK_TEST_WITH_RETURN( dev, filp );
1766
1767 if ( !dev_priv ) {
1768 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1769 return DRM_ERR(EINVAL);
1770 }
1771
1772 radeon_do_cp_reset( dev_priv );
1773
1774 /* The CP is no longer running after an engine reset */
1775 dev_priv->cp_running = 0;
1776
1777 return 0;
1778 }
1779
1780 int radeon_cp_idle( DRM_IOCTL_ARGS )
1781 {
1782 DRM_DEVICE;
1783 drm_radeon_private_t *dev_priv = dev->dev_private;
1784 DRM_DEBUG( "\n" );
1785
1786 LOCK_TEST_WITH_RETURN( dev, filp );
1787
1788 return radeon_do_cp_idle( dev_priv );
1789 }
1790
1791 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1792 */
1793 int radeon_cp_resume( DRM_IOCTL_ARGS )
1794 {
1795 DRM_DEVICE;
1796
1797 return radeon_do_resume_cp(dev);
1798 }
1799
1800
1801 int radeon_engine_reset( DRM_IOCTL_ARGS )
1802 {
1803 DRM_DEVICE;
1804 DRM_DEBUG( "\n" );
1805
1806 LOCK_TEST_WITH_RETURN( dev, filp );
1807
1808 return radeon_do_engine_reset( dev );
1809 }
1810
1811
1812 /* ================================================================
1813 * Fullscreen mode
1814 */
1815
1816 /* KW: Deprecated to say the least:
1817 */
1818 int radeon_fullscreen( DRM_IOCTL_ARGS )
1819 {
1820 return 0;
1821 }
1822
1823
1824 /* ================================================================
1825 * Freelist management
1826 */
1827
1828 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1829 * bufs until freelist code is used. Note this hides a problem with
1830 * the scratch register * (used to keep track of last buffer
1831 * completed) being written to before * the last buffer has actually
1832 * completed rendering.
1833 *
1834 * KW: It's also a good way to find free buffers quickly.
1835 *
1836 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1837 * sleep. However, bugs in older versions of radeon_accel.c mean that
1838 * we essentially have to do this, else old clients will break.
1839 *
1840 * However, it does leave open a potential deadlock where all the
1841 * buffers are held by other clients, which can't release them because
1842 * they can't get the lock.
1843 */
1844
1845 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1846 {
1847 drm_device_dma_t *dma = dev->dma;
1848 drm_radeon_private_t *dev_priv = dev->dev_private;
1849 drm_radeon_buf_priv_t *buf_priv;
1850 drm_buf_t *buf;
1851 int i, t;
1852 int start;
1853
1854 if ( ++dev_priv->last_buf >= dma->buf_count )
1855 dev_priv->last_buf = 0;
1856
1857 start = dev_priv->last_buf;
1858
1859 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1860 u32 done_age = GET_SCRATCH( 1 );
1861 DRM_DEBUG("done_age = %d\n",done_age);
1862 for ( i = start ; i < dma->buf_count ; i++ ) {
1863 buf = dma->buflist[i];
1864 buf_priv = buf->dev_private;
1865 if ( buf->filp == 0 || (buf->pending &&
1866 buf_priv->age <= done_age) ) {
1867 dev_priv->stats.requested_bufs++;
1868 buf->pending = 0;
1869 return buf;
1870 }
1871 start = 0;
1872 }
1873
1874 if (t) {
1875 DRM_UDELAY( 1 );
1876 dev_priv->stats.freelist_loops++;
1877 }
1878 }
1879
1880 DRM_DEBUG( "returning NULL!\n" );
1881 return NULL;
1882 }
1883 #if 0
1884 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1885 {
1886 drm_device_dma_t *dma = dev->dma;
1887 drm_radeon_private_t *dev_priv = dev->dev_private;
1888 drm_radeon_buf_priv_t *buf_priv;
1889 drm_buf_t *buf;
1890 int i, t;
1891 int start;
1892 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1893
1894 if ( ++dev_priv->last_buf >= dma->buf_count )
1895 dev_priv->last_buf = 0;
1896
1897 start = dev_priv->last_buf;
1898 dev_priv->stats.freelist_loops++;
1899
1900 for ( t = 0 ; t < 2 ; t++ ) {
1901 for ( i = start ; i < dma->buf_count ; i++ ) {
1902 buf = dma->buflist[i];
1903 buf_priv = buf->dev_private;
1904 if ( buf->filp == 0 || (buf->pending &&
1905 buf_priv->age <= done_age) ) {
1906 dev_priv->stats.requested_bufs++;
1907 buf->pending = 0;
1908 return buf;
1909 }
1910 }
1911 start = 0;
1912 }
1913
1914 return NULL;
1915 }
1916 #endif
1917
1918 void radeon_freelist_reset( drm_device_t *dev )
1919 {
1920 drm_device_dma_t *dma = dev->dma;
1921 drm_radeon_private_t *dev_priv = dev->dev_private;
1922 int i;
1923
1924 dev_priv->last_buf = 0;
1925 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1926 drm_buf_t *buf = dma->buflist[i];
1927 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1928 buf_priv->age = 0;
1929 }
1930 }
1931
1932
1933 /* ================================================================
1934 * CP command submission
1935 */
1936
1937 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1938 {
1939 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1940 int i;
1941 u32 last_head = GET_RING_HEAD( dev_priv );
1942
1943 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1944 u32 head = GET_RING_HEAD( dev_priv );
1945
1946 ring->space = (head - ring->tail) * sizeof(u32);
1947 if ( ring->space <= 0 )
1948 ring->space += ring->size;
1949 if ( ring->space > n )
1950 return 0;
1951
1952 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1953
1954 if (head != last_head)
1955 i = 0;
1956 last_head = head;
1957
1958 DRM_UDELAY( 1 );
1959 }
1960
1961 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1962 #if RADEON_FIFO_DEBUG
1963 radeon_status( dev_priv );
1964 DRM_ERROR( "failed!\n" );
1965 #endif
1966 return DRM_ERR(EBUSY);
1967 }
1968
1969 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1970 {
1971 int i;
1972 drm_buf_t *buf;
1973
1974 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1975 buf = radeon_freelist_get( dev );
1976 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1977
1978 buf->filp = filp;
1979
1980 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1981 sizeof(buf->idx) ) )
1982 return DRM_ERR(EFAULT);
1983 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1984 sizeof(buf->total) ) )
1985 return DRM_ERR(EFAULT);
1986
1987 d->granted_count++;
1988 }
1989 return 0;
1990 }
1991
1992 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1993 {
1994 DRM_DEVICE;
1995 drm_device_dma_t *dma = dev->dma;
1996 int ret = 0;
1997 drm_dma_t __user *argp = (void __user *)data;
1998 drm_dma_t d;
1999
2000 LOCK_TEST_WITH_RETURN( dev, filp );
2001
2002 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
2003
2004 /* Please don't send us buffers.
2005 */
2006 if ( d.send_count != 0 ) {
2007 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
2008 DRM_CURRENTPID, d.send_count );
2009 return DRM_ERR(EINVAL);
2010 }
2011
2012 /* We'll send you buffers.
2013 */
2014 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
2015 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
2016 DRM_CURRENTPID, d.request_count, dma->buf_count );
2017 return DRM_ERR(EINVAL);
2018 }
2019
2020 d.granted_count = 0;
2021
2022 if ( d.request_count ) {
2023 ret = radeon_cp_get_buffers( filp, dev, &d );
2024 }
2025
2026 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
2027
2028 return ret;
2029 }
2030
2031 int radeon_driver_preinit(struct drm_device *dev, unsigned long flags)
2032 {
2033 drm_radeon_private_t *dev_priv;
2034 int ret = 0;
2035
2036 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2037 if (dev_priv == NULL)
2038 return DRM_ERR(ENOMEM);
2039
2040 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2041 dev->dev_private = (void *)dev_priv;
2042 dev_priv->flags = flags;
2043
2044 switch (flags & CHIP_FAMILY_MASK) {
2045 case CHIP_R100:
2046 case CHIP_RV200:
2047 case CHIP_R200:
2048 case CHIP_R300:
2049 case CHIP_R420:
2050 dev_priv->flags |= CHIP_HAS_HIERZ;
2051 break;
2052 default:
2053 /* all other chips have no hierarchical z buffer */
2054 break;
2055 }
2056
2057 if (drm_device_is_agp(dev))
2058 dev_priv->flags |= CHIP_IS_AGP;
2059
2060 DRM_DEBUG("%s card detected\n",
2061 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2062 return ret;
2063 }
2064
2065 int radeon_presetup(struct drm_device *dev)
2066 {
2067 int ret;
2068 drm_local_map_t *map;
2069 drm_radeon_private_t *dev_priv = dev->dev_private;
2070
2071 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2072 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2073 _DRM_READ_ONLY, &dev_priv->mmio);
2074 if (ret != 0)
2075 return ret;
2076
2077 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2078 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2079 _DRM_WRITE_COMBINING, &map);
2080 if (ret != 0)
2081 return ret;
2082
2083 return 0;
2084 }
2085
2086 int radeon_driver_postcleanup(struct drm_device *dev)
2087 {
2088 drm_radeon_private_t *dev_priv = dev->dev_private;
2089
2090 DRM_DEBUG("\n");
2091
2092 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2093
2094 dev->dev_private = NULL;
2095 return 0;
2096 }
Support for the Chinese Samsung S3C2440 based development boards