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sh: sh7785lcr: fix defconfig for 29-bit mode
[linux-2.6/mini2440.git] / drivers / mfd / tc6393xb.c
blob77a12fc8045e4367fff065f861237035e658f597
1 /*
2 * Toshiba TC6393XB SoC support
3 *
4 * Copyright(c) 2005-2006 Chris Humbert
5 * Copyright(c) 2005 Dirk Opfer
6 * Copyright(c) 2005 Ian Molton <spyro@f2s.com>
7 * Copyright(c) 2007 Dmitry Baryshkov
8 *
9 * Based on code written by Sharp/Lineo for 2.4 kernels
10 * Based on locomo.c
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/tmio.h>
26 #include <linux/mfd/tc6393xb.h>
27 #include <linux/gpio.h>
28
29 #define SCR_REVID 0x08 /* b Revision ID */
30 #define SCR_ISR 0x50 /* b Interrupt Status */
31 #define SCR_IMR 0x52 /* b Interrupt Mask */
32 #define SCR_IRR 0x54 /* b Interrupt Routing */
33 #define SCR_GPER 0x60 /* w GP Enable */
34 #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
35 #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
36 #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
37 #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
38 #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
39 #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
40 #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
41 #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
42 #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
43 #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
44 #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
45 #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
46 #define SCR_CCR 0x98 /* w Clock Control */
47 #define SCR_PLL2CR 0x9a /* w PLL2 Control */
48 #define SCR_PLL1CR 0x9c /* l PLL1 Control */
49 #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
50 #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
51 #define SCR_FER 0xe0 /* b Function Enable */
52 #define SCR_MCR 0xe4 /* w Mode Control */
53 #define SCR_CONFIG 0xfc /* b Configuration Control */
54 #define SCR_DEBUG 0xff /* b Debug */
55
56 #define SCR_CCR_CK32K BIT(0)
57 #define SCR_CCR_USBCK BIT(1)
58 #define SCR_CCR_UNK1 BIT(4)
59 #define SCR_CCR_MCLK_MASK (7 << 8)
60 #define SCR_CCR_MCLK_OFF (0 << 8)
61 #define SCR_CCR_MCLK_12 (1 << 8)
62 #define SCR_CCR_MCLK_24 (2 << 8)
63 #define SCR_CCR_MCLK_48 (3 << 8)
64 #define SCR_CCR_HCLK_MASK (3 << 12)
65 #define SCR_CCR_HCLK_24 (0 << 12)
66 #define SCR_CCR_HCLK_48 (1 << 12)
67
68 #define SCR_FER_USBEN BIT(0) /* USB host enable */
69 #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */
70 #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */
71
72 #define SCR_MCR_RDY_MASK (3 << 0)
73 #define SCR_MCR_RDY_OPENDRAIN (0 << 0)
74 #define SCR_MCR_RDY_TRISTATE (1 << 0)
75 #define SCR_MCR_RDY_PUSHPULL (2 << 0)
76 #define SCR_MCR_RDY_UNK BIT(2)
77 #define SCR_MCR_RDY_EN BIT(3)
78 #define SCR_MCR_INT_MASK (3 << 4)
79 #define SCR_MCR_INT_OPENDRAIN (0 << 4)
80 #define SCR_MCR_INT_TRISTATE (1 << 4)
81 #define SCR_MCR_INT_PUSHPULL (2 << 4)
82 #define SCR_MCR_INT_UNK BIT(6)
83 #define SCR_MCR_INT_EN BIT(7)
84 /* bits 8 - 16 are unknown */
85
86 #define TC_GPIO_BIT(i) (1 << (i & 0x7))
87
88 /*--------------------------------------------------------------------------*/
89
90 struct tc6393xb {
91 void __iomem *scr;
92
93 struct gpio_chip gpio;
94
95 struct clk *clk; /* 3,6 Mhz */
96
97 spinlock_t lock; /* protects RMW cycles */
98
99 struct {
100 u8 fer;
101 u16 ccr;
102 u8 gpi_bcr[3];
103 u8 gpo_dsr[3];
104 u8 gpo_doecr[3];
105 } suspend_state;
106
107 struct resource rscr;
108 struct resource *iomem;
109 int irq;
110 int irq_base;
111 };
112
113 enum {
114 TC6393XB_CELL_NAND,
115 TC6393XB_CELL_MMC,
116 TC6393XB_CELL_OHCI,
117 TC6393XB_CELL_FB,
118 };
119
120 /*--------------------------------------------------------------------------*/
121
122 static int tc6393xb_nand_enable(struct platform_device *nand)
123 {
124 struct platform_device *dev = to_platform_device(nand->dev.parent);
125 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
126 unsigned long flags;
127
128 spin_lock_irqsave(&tc6393xb->lock, flags);
129
130 /* SMD buffer on */
131 dev_dbg(&dev->dev, "SMD buffer on\n");
132 tmio_iowrite8(0xff, tc6393xb->scr + SCR_GPI_BCR(1));
133
134 spin_unlock_irqrestore(&tc6393xb->lock, flags);
135
136 return 0;
137 }
138
139 static struct resource __devinitdata tc6393xb_nand_resources[] = {
140 {
141 .start = 0x1000,
142 .end = 0x1007,
143 .flags = IORESOURCE_MEM,
144 },
145 {
146 .start = 0x0100,
147 .end = 0x01ff,
148 .flags = IORESOURCE_MEM,
149 },
150 {
151 .start = IRQ_TC6393_NAND,
152 .end = IRQ_TC6393_NAND,
153 .flags = IORESOURCE_IRQ,
154 },
155 };
156
157 static struct resource __devinitdata tc6393xb_mmc_resources[] = {
158 {
159 .start = 0x800,
160 .end = 0x9ff,
161 .flags = IORESOURCE_MEM,
162 },
163 {
164 .start = 0x200,
165 .end = 0x2ff,
166 .flags = IORESOURCE_MEM,
167 },
168 {
169 .start = IRQ_TC6393_MMC,
170 .end = IRQ_TC6393_MMC,
171 .flags = IORESOURCE_IRQ,
172 },
173 };
174
175 static const struct resource tc6393xb_ohci_resources[] = {
176 {
177 .start = 0x3000,
178 .end = 0x31ff,
179 .flags = IORESOURCE_MEM,
180 },
181 {
182 .start = 0x0300,
183 .end = 0x03ff,
184 .flags = IORESOURCE_MEM,
185 },
186 {
187 .start = 0x010000,
188 .end = 0x017fff,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .start = 0x018000,
193 .end = 0x01ffff,
194 .flags = IORESOURCE_MEM,
195 },
196 {
197 .start = IRQ_TC6393_OHCI,
198 .end = IRQ_TC6393_OHCI,
199 .flags = IORESOURCE_IRQ,
200 },
201 };
202
203 static struct resource __devinitdata tc6393xb_fb_resources[] = {
204 {
205 .start = 0x5000,
206 .end = 0x51ff,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .start = 0x0500,
211 .end = 0x05ff,
212 .flags = IORESOURCE_MEM,
213 },
214 {
215 .start = 0x100000,
216 .end = 0x1fffff,
217 .flags = IORESOURCE_MEM,
218 },
219 {
220 .start = IRQ_TC6393_FB,
221 .end = IRQ_TC6393_FB,
222 .flags = IORESOURCE_IRQ,
223 },
224 };
225
226 static int tc6393xb_ohci_enable(struct platform_device *dev)
227 {
228 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
229 unsigned long flags;
230 u16 ccr;
231 u8 fer;
232
233 spin_lock_irqsave(&tc6393xb->lock, flags);
234
235 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
236 ccr |= SCR_CCR_USBCK;
237 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
238
239 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
240 fer |= SCR_FER_USBEN;
241 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
242
243 spin_unlock_irqrestore(&tc6393xb->lock, flags);
244
245 return 0;
246 }
247
248 static int tc6393xb_ohci_disable(struct platform_device *dev)
249 {
250 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
251 unsigned long flags;
252 u16 ccr;
253 u8 fer;
254
255 spin_lock_irqsave(&tc6393xb->lock, flags);
256
257 fer = tmio_ioread8(tc6393xb->scr + SCR_FER);
258 fer &= ~SCR_FER_USBEN;
259 tmio_iowrite8(fer, tc6393xb->scr + SCR_FER);
260
261 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
262 ccr &= ~SCR_CCR_USBCK;
263 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
264
265 spin_unlock_irqrestore(&tc6393xb->lock, flags);
266
267 return 0;
268 }
269
270 static int tc6393xb_fb_enable(struct platform_device *dev)
271 {
272 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
273 unsigned long flags;
274 u16 ccr;
275
276 spin_lock_irqsave(&tc6393xb->lock, flags);
277
278 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
279 ccr &= ~SCR_CCR_MCLK_MASK;
280 ccr |= SCR_CCR_MCLK_48;
281 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
282
283 spin_unlock_irqrestore(&tc6393xb->lock, flags);
284
285 return 0;
286 }
287
288 static int tc6393xb_fb_disable(struct platform_device *dev)
289 {
290 struct tc6393xb *tc6393xb = dev_get_drvdata(dev->dev.parent);
291 unsigned long flags;
292 u16 ccr;
293
294 spin_lock_irqsave(&tc6393xb->lock, flags);
295
296 ccr = tmio_ioread16(tc6393xb->scr + SCR_CCR);
297 ccr &= ~SCR_CCR_MCLK_MASK;
298 ccr |= SCR_CCR_MCLK_OFF;
299 tmio_iowrite16(ccr, tc6393xb->scr + SCR_CCR);
300
301 spin_unlock_irqrestore(&tc6393xb->lock, flags);
302
303 return 0;
304 }
305
306 int tc6393xb_lcd_set_power(struct platform_device *fb, bool on)
307 {
308 struct platform_device *dev = to_platform_device(fb->dev.parent);
309 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
310 u8 fer;
311 unsigned long flags;
312
313 spin_lock_irqsave(&tc6393xb->lock, flags);
314
315 fer = ioread8(tc6393xb->scr + SCR_FER);
316 if (on)
317 fer |= SCR_FER_SLCDEN;
318 else
319 fer &= ~SCR_FER_SLCDEN;
320 iowrite8(fer, tc6393xb->scr + SCR_FER);
321
322 spin_unlock_irqrestore(&tc6393xb->lock, flags);
323
324 return 0;
325 }
326 EXPORT_SYMBOL(tc6393xb_lcd_set_power);
327
328 int tc6393xb_lcd_mode(struct platform_device *fb,
329 const struct fb_videomode *mode) {
330 struct platform_device *dev = to_platform_device(fb->dev.parent);
331 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
332 unsigned long flags;
333
334 spin_lock_irqsave(&tc6393xb->lock, flags);
335
336 iowrite16(mode->pixclock, tc6393xb->scr + SCR_PLL1CR + 0);
337 iowrite16(mode->pixclock >> 16, tc6393xb->scr + SCR_PLL1CR + 2);
338
339 spin_unlock_irqrestore(&tc6393xb->lock, flags);
340
341 return 0;
342 }
343 EXPORT_SYMBOL(tc6393xb_lcd_mode);
344
345 static struct mfd_cell __devinitdata tc6393xb_cells[] = {
346 [TC6393XB_CELL_NAND] = {
347 .name = "tmio-nand",
348 .enable = tc6393xb_nand_enable,
349 .num_resources = ARRAY_SIZE(tc6393xb_nand_resources),
350 .resources = tc6393xb_nand_resources,
351 },
352 [TC6393XB_CELL_MMC] = {
353 .name = "tmio-mmc",
354 .num_resources = ARRAY_SIZE(tc6393xb_mmc_resources),
355 .resources = tc6393xb_mmc_resources,
356 },
357 [TC6393XB_CELL_OHCI] = {
358 .name = "tmio-ohci",
359 .num_resources = ARRAY_SIZE(tc6393xb_ohci_resources),
360 .resources = tc6393xb_ohci_resources,
361 .enable = tc6393xb_ohci_enable,
362 .suspend = tc6393xb_ohci_disable,
363 .resume = tc6393xb_ohci_enable,
364 .disable = tc6393xb_ohci_disable,
365 },
366 [TC6393XB_CELL_FB] = {
367 .name = "tmio-fb",
368 .num_resources = ARRAY_SIZE(tc6393xb_fb_resources),
369 .resources = tc6393xb_fb_resources,
370 .enable = tc6393xb_fb_enable,
371 .suspend = tc6393xb_fb_disable,
372 .resume = tc6393xb_fb_enable,
373 .disable = tc6393xb_fb_disable,
374 },
375 };
376
377 /*--------------------------------------------------------------------------*/
378
379 static int tc6393xb_gpio_get(struct gpio_chip *chip,
380 unsigned offset)
381 {
382 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
383
384 /* XXX: does dsr also represent inputs? */
385 return tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8))
386 & TC_GPIO_BIT(offset);
387 }
388
389 static void __tc6393xb_gpio_set(struct gpio_chip *chip,
390 unsigned offset, int value)
391 {
392 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
393 u8 dsr;
394
395 dsr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8));
396 if (value)
397 dsr |= TC_GPIO_BIT(offset);
398 else
399 dsr &= ~TC_GPIO_BIT(offset);
400
401 tmio_iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8));
402 }
403
404 static void tc6393xb_gpio_set(struct gpio_chip *chip,
405 unsigned offset, int value)
406 {
407 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
408 unsigned long flags;
409
410 spin_lock_irqsave(&tc6393xb->lock, flags);
411
412 __tc6393xb_gpio_set(chip, offset, value);
413
414 spin_unlock_irqrestore(&tc6393xb->lock, flags);
415 }
416
417 static int tc6393xb_gpio_direction_input(struct gpio_chip *chip,
418 unsigned offset)
419 {
420 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
421 unsigned long flags;
422 u8 doecr;
423
424 spin_lock_irqsave(&tc6393xb->lock, flags);
425
426 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
427 doecr &= ~TC_GPIO_BIT(offset);
428 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
429
430 spin_unlock_irqrestore(&tc6393xb->lock, flags);
431
432 return 0;
433 }
434
435 static int tc6393xb_gpio_direction_output(struct gpio_chip *chip,
436 unsigned offset, int value)
437 {
438 struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio);
439 unsigned long flags;
440 u8 doecr;
441
442 spin_lock_irqsave(&tc6393xb->lock, flags);
443
444 __tc6393xb_gpio_set(chip, offset, value);
445
446 doecr = tmio_ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
447 doecr |= TC_GPIO_BIT(offset);
448 tmio_iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8));
449
450 spin_unlock_irqrestore(&tc6393xb->lock, flags);
451
452 return 0;
453 }
454
455 static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base)
456 {
457 tc6393xb->gpio.label = "tc6393xb";
458 tc6393xb->gpio.base = gpio_base;
459 tc6393xb->gpio.ngpio = 16;
460 tc6393xb->gpio.set = tc6393xb_gpio_set;
461 tc6393xb->gpio.get = tc6393xb_gpio_get;
462 tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input;
463 tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output;
464
465 return gpiochip_add(&tc6393xb->gpio);
466 }
467
468 /*--------------------------------------------------------------------------*/
469
470 static void
471 tc6393xb_irq(unsigned int irq, struct irq_desc *desc)
472 {
473 struct tc6393xb *tc6393xb = get_irq_data(irq);
474 unsigned int isr;
475 unsigned int i, irq_base;
476
477 irq_base = tc6393xb->irq_base;
478
479 while ((isr = tmio_ioread8(tc6393xb->scr + SCR_ISR) &
480 ~tmio_ioread8(tc6393xb->scr + SCR_IMR)))
481 for (i = 0; i < TC6393XB_NR_IRQS; i++) {
482 if (isr & (1 << i))
483 generic_handle_irq(irq_base + i);
484 }
485 }
486
487 static void tc6393xb_irq_ack(unsigned int irq)
488 {
489 }
490
491 static void tc6393xb_irq_mask(unsigned int irq)
492 {
493 struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
494 unsigned long flags;
495 u8 imr;
496
497 spin_lock_irqsave(&tc6393xb->lock, flags);
498 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
499 imr |= 1 << (irq - tc6393xb->irq_base);
500 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
501 spin_unlock_irqrestore(&tc6393xb->lock, flags);
502 }
503
504 static void tc6393xb_irq_unmask(unsigned int irq)
505 {
506 struct tc6393xb *tc6393xb = get_irq_chip_data(irq);
507 unsigned long flags;
508 u8 imr;
509
510 spin_lock_irqsave(&tc6393xb->lock, flags);
511 imr = tmio_ioread8(tc6393xb->scr + SCR_IMR);
512 imr &= ~(1 << (irq - tc6393xb->irq_base));
513 tmio_iowrite8(imr, tc6393xb->scr + SCR_IMR);
514 spin_unlock_irqrestore(&tc6393xb->lock, flags);
515 }
516
517 static struct irq_chip tc6393xb_chip = {
518 .name = "tc6393xb",
519 .ack = tc6393xb_irq_ack,
520 .mask = tc6393xb_irq_mask,
521 .unmask = tc6393xb_irq_unmask,
522 };
523
524 static void tc6393xb_attach_irq(struct platform_device *dev)
525 {
526 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
527 unsigned int irq, irq_base;
528
529 irq_base = tc6393xb->irq_base;
530
531 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
532 set_irq_chip(irq, &tc6393xb_chip);
533 set_irq_chip_data(irq, tc6393xb);
534 set_irq_handler(irq, handle_edge_irq);
535 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
536 }
537
538 set_irq_type(tc6393xb->irq, IRQ_TYPE_EDGE_FALLING);
539 set_irq_data(tc6393xb->irq, tc6393xb);
540 set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq);
541 }
542
543 static void tc6393xb_detach_irq(struct platform_device *dev)
544 {
545 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
546 unsigned int irq, irq_base;
547
548 set_irq_chained_handler(tc6393xb->irq, NULL);
549 set_irq_data(tc6393xb->irq, NULL);
550
551 irq_base = tc6393xb->irq_base;
552
553 for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) {
554 set_irq_flags(irq, 0);
555 set_irq_chip(irq, NULL);
556 set_irq_chip_data(irq, NULL);
557 }
558 }
559
560 /*--------------------------------------------------------------------------*/
561
562 static int __devinit tc6393xb_probe(struct platform_device *dev)
563 {
564 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
565 struct tc6393xb *tc6393xb;
566 struct resource *iomem, *rscr;
567 int ret, temp;
568
569 iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
570 if (!iomem)
571 return -EINVAL;
572
573 tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL);
574 if (!tc6393xb) {
575 ret = -ENOMEM;
576 goto err_kzalloc;
577 }
578
579 spin_lock_init(&tc6393xb->lock);
580
581 platform_set_drvdata(dev, tc6393xb);
582
583 ret = platform_get_irq(dev, 0);
584 if (ret >= 0)
585 tc6393xb->irq = ret;
586 else
587 goto err_noirq;
588
589 tc6393xb->iomem = iomem;
590 tc6393xb->irq_base = tcpd->irq_base;
591
592 tc6393xb->clk = clk_get(&dev->dev, "CLK_CK3P6MI");
593 if (IS_ERR(tc6393xb->clk)) {
594 ret = PTR_ERR(tc6393xb->clk);
595 goto err_clk_get;
596 }
597
598 rscr = &tc6393xb->rscr;
599 rscr->name = "tc6393xb-core";
600 rscr->start = iomem->start;
601 rscr->end = iomem->start + 0xff;
602 rscr->flags = IORESOURCE_MEM;
603
604 ret = request_resource(iomem, rscr);
605 if (ret)
606 goto err_request_scr;
607
608 tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1);
609 if (!tc6393xb->scr) {
610 ret = -ENOMEM;
611 goto err_ioremap;
612 }
613
614 ret = clk_enable(tc6393xb->clk);
615 if (ret)
616 goto err_clk_enable;
617
618 ret = tcpd->enable(dev);
619 if (ret)
620 goto err_enable;
621
622 iowrite8(0, tc6393xb->scr + SCR_FER);
623 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
624 iowrite16(SCR_CCR_UNK1 | SCR_CCR_HCLK_48,
625 tc6393xb->scr + SCR_CCR);
626 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
627 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
628 BIT(15), tc6393xb->scr + SCR_MCR);
629 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
630 iowrite8(0, tc6393xb->scr + SCR_IRR);
631 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
632
633 printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n",
634 tmio_ioread8(tc6393xb->scr + SCR_REVID),
635 (unsigned long) iomem->start, tc6393xb->irq);
636
637 tc6393xb->gpio.base = -1;
638
639 if (tcpd->gpio_base >= 0) {
640 ret = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base);
641 if (ret)
642 goto err_gpio_add;
643 }
644
645 tc6393xb_attach_irq(dev);
646
647 if (tcpd->setup) {
648 ret = tcpd->setup(dev);
649 if (ret)
650 goto err_setup;
651 }
652
653 tc6393xb_cells[TC6393XB_CELL_NAND].driver_data = tcpd->nand_data;
654 tc6393xb_cells[TC6393XB_CELL_NAND].platform_data =
655 &tc6393xb_cells[TC6393XB_CELL_NAND];
656 tc6393xb_cells[TC6393XB_CELL_NAND].data_size =
657 sizeof(tc6393xb_cells[TC6393XB_CELL_NAND]);
658
659 tc6393xb_cells[TC6393XB_CELL_MMC].platform_data =
660 &tc6393xb_cells[TC6393XB_CELL_MMC];
661 tc6393xb_cells[TC6393XB_CELL_MMC].data_size =
662 sizeof(tc6393xb_cells[TC6393XB_CELL_MMC]);
663
664 tc6393xb_cells[TC6393XB_CELL_OHCI].platform_data =
665 &tc6393xb_cells[TC6393XB_CELL_OHCI];
666 tc6393xb_cells[TC6393XB_CELL_OHCI].data_size =
667 sizeof(tc6393xb_cells[TC6393XB_CELL_OHCI]);
668
669 tc6393xb_cells[TC6393XB_CELL_FB].driver_data = tcpd->fb_data;
670 tc6393xb_cells[TC6393XB_CELL_FB].platform_data =
671 &tc6393xb_cells[TC6393XB_CELL_FB];
672 tc6393xb_cells[TC6393XB_CELL_FB].data_size =
673 sizeof(tc6393xb_cells[TC6393XB_CELL_FB]);
674
675 ret = mfd_add_devices(&dev->dev, dev->id,
676 tc6393xb_cells, ARRAY_SIZE(tc6393xb_cells),
677 iomem, tcpd->irq_base);
678
679 if (!ret)
680 return 0;
681
682 if (tcpd->teardown)
683 tcpd->teardown(dev);
684
685 err_setup:
686 tc6393xb_detach_irq(dev);
687
688 err_gpio_add:
689 if (tc6393xb->gpio.base != -1)
690 temp = gpiochip_remove(&tc6393xb->gpio);
691 tcpd->disable(dev);
692 err_clk_enable:
693 clk_disable(tc6393xb->clk);
694 err_enable:
695 iounmap(tc6393xb->scr);
696 err_ioremap:
697 release_resource(&tc6393xb->rscr);
698 err_request_scr:
699 clk_put(tc6393xb->clk);
700 err_noirq:
701 err_clk_get:
702 kfree(tc6393xb);
703 err_kzalloc:
704 return ret;
705 }
706
707 static int __devexit tc6393xb_remove(struct platform_device *dev)
708 {
709 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
710 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
711 int ret;
712
713 mfd_remove_devices(&dev->dev);
714
715 if (tcpd->teardown)
716 tcpd->teardown(dev);
717
718 tc6393xb_detach_irq(dev);
719
720 if (tc6393xb->gpio.base != -1) {
721 ret = gpiochip_remove(&tc6393xb->gpio);
722 if (ret) {
723 dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret);
724 return ret;
725 }
726 }
727
728 ret = tcpd->disable(dev);
729 clk_disable(tc6393xb->clk);
730 iounmap(tc6393xb->scr);
731 release_resource(&tc6393xb->rscr);
732 platform_set_drvdata(dev, NULL);
733 clk_put(tc6393xb->clk);
734 kfree(tc6393xb);
735
736 return ret;
737 }
738
739 #ifdef CONFIG_PM
740 static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state)
741 {
742 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
743 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
744 int i, ret;
745
746 tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR);
747 tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER);
748
749 for (i = 0; i < 3; i++) {
750 tc6393xb->suspend_state.gpo_dsr[i] =
751 ioread8(tc6393xb->scr + SCR_GPO_DSR(i));
752 tc6393xb->suspend_state.gpo_doecr[i] =
753 ioread8(tc6393xb->scr + SCR_GPO_DOECR(i));
754 tc6393xb->suspend_state.gpi_bcr[i] =
755 ioread8(tc6393xb->scr + SCR_GPI_BCR(i));
756 }
757 ret = tcpd->suspend(dev);
758 clk_disable(tc6393xb->clk);
759
760 return ret;
761 }
762
763 static int tc6393xb_resume(struct platform_device *dev)
764 {
765 struct tc6393xb_platform_data *tcpd = dev->dev.platform_data;
766 struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
767 int ret;
768 int i;
769
770 clk_enable(tc6393xb->clk);
771
772 ret = tcpd->resume(dev);
773 if (ret)
774 return ret;
775
776 if (!tcpd->resume_restore)
777 return 0;
778
779 iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER);
780 iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR);
781 iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR);
782 iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN |
783 SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN |
784 BIT(15), tc6393xb->scr + SCR_MCR);
785 iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER);
786 iowrite8(0, tc6393xb->scr + SCR_IRR);
787 iowrite8(0xbf, tc6393xb->scr + SCR_IMR);
788
789 for (i = 0; i < 3; i++) {
790 iowrite8(tc6393xb->suspend_state.gpo_dsr[i],
791 tc6393xb->scr + SCR_GPO_DSR(i));
792 iowrite8(tc6393xb->suspend_state.gpo_doecr[i],
793 tc6393xb->scr + SCR_GPO_DOECR(i));
794 iowrite8(tc6393xb->suspend_state.gpi_bcr[i],
795 tc6393xb->scr + SCR_GPI_BCR(i));
796 }
797
798 return 0;
799 }
800 #else
801 #define tc6393xb_suspend NULL
802 #define tc6393xb_resume NULL
803 #endif
804
805 static struct platform_driver tc6393xb_driver = {
806 .probe = tc6393xb_probe,
807 .remove = __devexit_p(tc6393xb_remove),
808 .suspend = tc6393xb_suspend,
809 .resume = tc6393xb_resume,
810
811 .driver = {
812 .name = "tc6393xb",
813 .owner = THIS_MODULE,
814 },
815 };
816
817 static int __init tc6393xb_init(void)
818 {
819 return platform_driver_register(&tc6393xb_driver);
820 }
821
822 static void __exit tc6393xb_exit(void)
823 {
824 platform_driver_unregister(&tc6393xb_driver);
825 }
826
827 subsys_initcall(tc6393xb_init);
828 module_exit(tc6393xb_exit);
829
830 MODULE_LICENSE("GPL v2");
831 MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer");
832 MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller");
833 MODULE_ALIAS("platform:tc6393xb");
Support for the Chinese Samsung S3C2440 based development boards