2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QE UCC Gigabit Ethernet Driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/mii.h>
29 #include <linux/phy.h>
30 #include <linux/workqueue.h>
31 #include <linux/of_platform.h>
33 #include <asm/uaccess.h>
36 #include <asm/immap_qe.h>
39 #include <asm/ucc_fast.h>
42 #include "ucc_geth_mii.h"
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
66 static DEFINE_SPINLOCK(ugeth_lock
);
72 module_param_named(debug
, debug
.msg_enable
, int, 0);
73 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 0xffff=all)");
75 static struct ucc_geth_info ugeth_primary_info
= {
77 .bd_mem_part
= MEM_PART_SYSTEM
,
78 .rtsm
= UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
,
79 .max_rx_buf_length
= 1536,
80 /* adjusted at startup if max-speed 1000 */
81 .urfs
= UCC_GETH_URFS_INIT
,
82 .urfet
= UCC_GETH_URFET_INIT
,
83 .urfset
= UCC_GETH_URFSET_INIT
,
84 .utfs
= UCC_GETH_UTFS_INIT
,
85 .utfet
= UCC_GETH_UTFET_INIT
,
86 .utftt
= UCC_GETH_UTFTT_INIT
,
88 .mode
= UCC_FAST_PROTOCOL_MODE_ETHERNET
,
89 .ttx_trx
= UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
,
90 .tenc
= UCC_FAST_TX_ENCODING_NRZ
,
91 .renc
= UCC_FAST_RX_ENCODING_NRZ
,
92 .tcrc
= UCC_FAST_16_BIT_CRC
,
93 .synl
= UCC_FAST_SYNC_LEN_NOT_USED
,
97 .extendedFilteringChainPointer
= ((uint32_t) NULL
),
98 .typeorlen
= 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1
= 0x40,
100 .nonBackToBackIfgPart2
= 0x60,
101 .miminumInterFrameGapEnforcement
= 0x50,
102 .backToBackInterFrameGap
= 0x60,
106 .strictpriorityq
= 0xff,
107 .altBebTruncation
= 0xa,
109 .maxRetransmission
= 0xf,
110 .collisionWindow
= 0x37,
111 .receiveFlowControl
= 1,
112 .transmitFlowControl
= 1,
113 .maxGroupAddrInHash
= 4,
114 .maxIndAddrInHash
= 4,
116 .maxFrameLength
= 1518,
117 .minFrameLength
= 64,
121 .ecamptr
= ((uint32_t) NULL
),
122 .eventRegMask
= UCCE_OTHER
,
123 .pausePeriod
= 0xf000,
124 .interruptcoalescingmaxvalue
= {1, 1, 1, 1, 1, 1, 1, 1},
145 .numStationAddresses
= UCC_GETH_NUM_OF_STATION_ADDRESSES_1
,
146 .largestexternallookupkeysize
=
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
,
148 .statisticsMode
= UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
|
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
|
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
,
151 .vlanOperationTagged
= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
,
152 .vlanOperationNonTagged
= UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
,
153 .rxQoSMode
= UCC_GETH_QOS_MODE_DEFAULT
,
154 .aufc
= UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
,
155 .padAndCrc
= MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
,
156 .numThreadsTx
= UCC_GETH_NUM_OF_THREADS_1
,
157 .numThreadsRx
= UCC_GETH_NUM_OF_THREADS_1
,
158 .riscTx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
159 .riscRx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
162 static struct ucc_geth_info ugeth_info
[8];
165 static void mem_disp(u8
*addr
, int size
)
168 int size16Aling
= (size
>> 4) << 4;
169 int size4Aling
= (size
>> 2) << 2;
174 for (i
= addr
; (u32
) i
< (u32
) addr
+ size16Aling
; i
+= 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
179 *((u32
*) (i
+ 8)), *((u32
*) (i
+ 12)));
181 printk("0x%08x: ", (u32
) i
);
182 for (; (u32
) i
< (u32
) addr
+ size4Aling
; i
+= 4)
183 printk("%08x ", *((u32
*) (i
)));
184 for (; (u32
) i
< (u32
) addr
+ size
; i
++)
185 printk("%02x", *((u8
*) (i
)));
191 static struct list_head
*dequeue(struct list_head
*lh
)
195 spin_lock_irqsave(&ugeth_lock
, flags
);
196 if (!list_empty(lh
)) {
197 struct list_head
*node
= lh
->next
;
199 spin_unlock_irqrestore(&ugeth_lock
, flags
);
202 spin_unlock_irqrestore(&ugeth_lock
, flags
);
207 static struct sk_buff
*get_new_skb(struct ucc_geth_private
*ugeth
,
210 struct sk_buff
*skb
= NULL
;
212 skb
= dev_alloc_skb(ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
213 UCC_GETH_RX_DATA_BUF_ALIGNMENT
);
218 /* We need the data buffer to be aligned properly. We will reserve
219 * as many bytes as needed to align the data properly
222 UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
223 (((unsigned)skb
->data
) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
226 skb
->dev
= ugeth
->dev
;
228 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
229 dma_map_single(&ugeth
->dev
->dev
,
231 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
232 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
235 out_be32((u32 __iomem
*)bd
,
236 (R_E
| R_I
| (in_be32((u32 __iomem
*)bd
) & R_W
)));
241 static int rx_bd_buffer_set(struct ucc_geth_private
*ugeth
, u8 rxQ
)
248 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
252 bd_status
= in_be32((u32 __iomem
*)bd
);
253 skb
= get_new_skb(ugeth
, bd
);
255 if (!skb
) /* If can not allocate data buffer,
256 abort. Cleanup will be elsewhere */
259 ugeth
->rx_skbuff
[rxQ
][i
] = skb
;
261 /* advance the BD pointer */
262 bd
+= sizeof(struct qe_bd
);
264 } while (!(bd_status
& R_W
));
269 static int fill_init_enet_entries(struct ucc_geth_private
*ugeth
,
273 u32 thread_alignment
,
274 enum qe_risc_allocation risc
,
275 int skip_page_for_first_entry
)
277 u32 init_enet_offset
;
281 for (i
= 0; i
< num_entries
; i
++) {
282 if ((snum
= qe_get_snum()) < 0) {
283 if (netif_msg_ifup(ugeth
))
284 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
287 if ((i
== 0) && skip_page_for_first_entry
)
288 /* First entry of Rx does not have page */
289 init_enet_offset
= 0;
292 qe_muram_alloc(thread_size
, thread_alignment
);
293 if (IS_ERR_VALUE(init_enet_offset
)) {
294 if (netif_msg_ifup(ugeth
))
295 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
296 qe_put_snum((u8
) snum
);
301 ((u8
) snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) | init_enet_offset
308 static int return_init_enet_entries(struct ucc_geth_private
*ugeth
,
311 enum qe_risc_allocation risc
,
312 int skip_page_for_first_entry
)
314 u32 init_enet_offset
;
318 for (i
= 0; i
< num_entries
; i
++) {
321 /* Check that this entry was actually valid --
322 needed in case failed in allocations */
323 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
325 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
326 ENET_INIT_PARAM_SNUM_SHIFT
;
327 qe_put_snum((u8
) snum
);
328 if (!((i
== 0) && skip_page_for_first_entry
)) {
329 /* First entry of Rx does not have page */
331 (val
& ENET_INIT_PARAM_PTR_MASK
);
332 qe_muram_free(init_enet_offset
);
342 static int dump_init_enet_entries(struct ucc_geth_private
*ugeth
,
343 u32 __iomem
*p_start
,
346 enum qe_risc_allocation risc
,
347 int skip_page_for_first_entry
)
349 u32 init_enet_offset
;
353 for (i
= 0; i
< num_entries
; i
++) {
354 u32 val
= in_be32(p_start
);
356 /* Check that this entry was actually valid --
357 needed in case failed in allocations */
358 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
360 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
361 ENET_INIT_PARAM_SNUM_SHIFT
;
362 qe_put_snum((u8
) snum
);
363 if (!((i
== 0) && skip_page_for_first_entry
)) {
364 /* First entry of Rx does not have page */
367 ENET_INIT_PARAM_PTR_MASK
);
368 ugeth_info("Init enet entry %d:", i
);
369 ugeth_info("Base address: 0x%08x",
371 qe_muram_addr(init_enet_offset
));
372 mem_disp(qe_muram_addr(init_enet_offset
),
383 static void put_enet_addr_container(struct enet_addr_container
*enet_addr_cont
)
385 kfree(enet_addr_cont
);
388 static void set_mac_addr(__be16 __iomem
*reg
, u8
*mac
)
390 out_be16(®
[0], ((u16
)mac
[5] << 8) | mac
[4]);
391 out_be16(®
[1], ((u16
)mac
[3] << 8) | mac
[2]);
392 out_be16(®
[2], ((u16
)mac
[1] << 8) | mac
[0]);
395 static int hw_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
, u8 paddr_num
)
397 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
399 if (!(paddr_num
< NUM_OF_PADDRS
)) {
400 ugeth_warn("%s: Illagel paddr_num.", __func__
);
405 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
408 /* Writing address ff.ff.ff.ff.ff.ff disables address
409 recognition for this register */
410 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, 0xffff);
411 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].m
, 0xffff);
412 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].l
, 0xffff);
417 static void hw_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
420 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
424 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
428 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
430 /* Ethernet frames are defined in Little Endian mode,
431 therefor to insert */
432 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
434 set_mac_addr(&p_82xx_addr_filt
->taddr
.h
, p_enet_addr
);
436 qe_issue_cmd(QE_SET_GROUP_ADDRESS
, cecr_subblock
,
437 QE_CR_PROTOCOL_ETHERNET
, 0);
440 #ifdef CONFIG_UGETH_MAGIC_PACKET
441 static void magic_packet_detection_enable(struct ucc_geth_private
*ugeth
)
443 struct ucc_fast_private
*uccf
;
444 struct ucc_geth __iomem
*ug_regs
;
447 ug_regs
= ugeth
->ug_regs
;
449 /* Enable interrupts for magic packet detection */
450 setbits32(uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
452 /* Enable magic packet detection */
453 setbits32(&ug_regs
->maccfg2
, MACCFG2_MPE
);
456 static void magic_packet_detection_disable(struct ucc_geth_private
*ugeth
)
458 struct ucc_fast_private
*uccf
;
459 struct ucc_geth __iomem
*ug_regs
;
462 ug_regs
= ugeth
->ug_regs
;
464 /* Disable interrupts for magic packet detection */
465 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
467 /* Disable magic packet detection */
468 clrbits32(&ug_regs
->maccfg2
, MACCFG2_MPE
);
470 #endif /* MAGIC_PACKET */
472 static inline int compare_addr(u8
**addr1
, u8
**addr2
)
474 return memcmp(addr1
, addr2
, ENET_NUM_OCTETS_PER_ADDRESS
);
478 static void get_statistics(struct ucc_geth_private
*ugeth
,
479 struct ucc_geth_tx_firmware_statistics
*
480 tx_firmware_statistics
,
481 struct ucc_geth_rx_firmware_statistics
*
482 rx_firmware_statistics
,
483 struct ucc_geth_hardware_statistics
*hardware_statistics
)
485 struct ucc_fast __iomem
*uf_regs
;
486 struct ucc_geth __iomem
*ug_regs
;
487 struct ucc_geth_tx_firmware_statistics_pram
*p_tx_fw_statistics_pram
;
488 struct ucc_geth_rx_firmware_statistics_pram
*p_rx_fw_statistics_pram
;
490 ug_regs
= ugeth
->ug_regs
;
491 uf_regs
= (struct ucc_fast __iomem
*) ug_regs
;
492 p_tx_fw_statistics_pram
= ugeth
->p_tx_fw_statistics_pram
;
493 p_rx_fw_statistics_pram
= ugeth
->p_rx_fw_statistics_pram
;
495 /* Tx firmware only if user handed pointer and driver actually
496 gathers Tx firmware statistics */
497 if (tx_firmware_statistics
&& p_tx_fw_statistics_pram
) {
498 tx_firmware_statistics
->sicoltx
=
499 in_be32(&p_tx_fw_statistics_pram
->sicoltx
);
500 tx_firmware_statistics
->mulcoltx
=
501 in_be32(&p_tx_fw_statistics_pram
->mulcoltx
);
502 tx_firmware_statistics
->latecoltxfr
=
503 in_be32(&p_tx_fw_statistics_pram
->latecoltxfr
);
504 tx_firmware_statistics
->frabortduecol
=
505 in_be32(&p_tx_fw_statistics_pram
->frabortduecol
);
506 tx_firmware_statistics
->frlostinmactxer
=
507 in_be32(&p_tx_fw_statistics_pram
->frlostinmactxer
);
508 tx_firmware_statistics
->carriersenseertx
=
509 in_be32(&p_tx_fw_statistics_pram
->carriersenseertx
);
510 tx_firmware_statistics
->frtxok
=
511 in_be32(&p_tx_fw_statistics_pram
->frtxok
);
512 tx_firmware_statistics
->txfrexcessivedefer
=
513 in_be32(&p_tx_fw_statistics_pram
->txfrexcessivedefer
);
514 tx_firmware_statistics
->txpkts256
=
515 in_be32(&p_tx_fw_statistics_pram
->txpkts256
);
516 tx_firmware_statistics
->txpkts512
=
517 in_be32(&p_tx_fw_statistics_pram
->txpkts512
);
518 tx_firmware_statistics
->txpkts1024
=
519 in_be32(&p_tx_fw_statistics_pram
->txpkts1024
);
520 tx_firmware_statistics
->txpktsjumbo
=
521 in_be32(&p_tx_fw_statistics_pram
->txpktsjumbo
);
524 /* Rx firmware only if user handed pointer and driver actually
525 * gathers Rx firmware statistics */
526 if (rx_firmware_statistics
&& p_rx_fw_statistics_pram
) {
528 rx_firmware_statistics
->frrxfcser
=
529 in_be32(&p_rx_fw_statistics_pram
->frrxfcser
);
530 rx_firmware_statistics
->fraligner
=
531 in_be32(&p_rx_fw_statistics_pram
->fraligner
);
532 rx_firmware_statistics
->inrangelenrxer
=
533 in_be32(&p_rx_fw_statistics_pram
->inrangelenrxer
);
534 rx_firmware_statistics
->outrangelenrxer
=
535 in_be32(&p_rx_fw_statistics_pram
->outrangelenrxer
);
536 rx_firmware_statistics
->frtoolong
=
537 in_be32(&p_rx_fw_statistics_pram
->frtoolong
);
538 rx_firmware_statistics
->runt
=
539 in_be32(&p_rx_fw_statistics_pram
->runt
);
540 rx_firmware_statistics
->verylongevent
=
541 in_be32(&p_rx_fw_statistics_pram
->verylongevent
);
542 rx_firmware_statistics
->symbolerror
=
543 in_be32(&p_rx_fw_statistics_pram
->symbolerror
);
544 rx_firmware_statistics
->dropbsy
=
545 in_be32(&p_rx_fw_statistics_pram
->dropbsy
);
546 for (i
= 0; i
< 0x8; i
++)
547 rx_firmware_statistics
->res0
[i
] =
548 p_rx_fw_statistics_pram
->res0
[i
];
549 rx_firmware_statistics
->mismatchdrop
=
550 in_be32(&p_rx_fw_statistics_pram
->mismatchdrop
);
551 rx_firmware_statistics
->underpkts
=
552 in_be32(&p_rx_fw_statistics_pram
->underpkts
);
553 rx_firmware_statistics
->pkts256
=
554 in_be32(&p_rx_fw_statistics_pram
->pkts256
);
555 rx_firmware_statistics
->pkts512
=
556 in_be32(&p_rx_fw_statistics_pram
->pkts512
);
557 rx_firmware_statistics
->pkts1024
=
558 in_be32(&p_rx_fw_statistics_pram
->pkts1024
);
559 rx_firmware_statistics
->pktsjumbo
=
560 in_be32(&p_rx_fw_statistics_pram
->pktsjumbo
);
561 rx_firmware_statistics
->frlossinmacer
=
562 in_be32(&p_rx_fw_statistics_pram
->frlossinmacer
);
563 rx_firmware_statistics
->pausefr
=
564 in_be32(&p_rx_fw_statistics_pram
->pausefr
);
565 for (i
= 0; i
< 0x4; i
++)
566 rx_firmware_statistics
->res1
[i
] =
567 p_rx_fw_statistics_pram
->res1
[i
];
568 rx_firmware_statistics
->removevlan
=
569 in_be32(&p_rx_fw_statistics_pram
->removevlan
);
570 rx_firmware_statistics
->replacevlan
=
571 in_be32(&p_rx_fw_statistics_pram
->replacevlan
);
572 rx_firmware_statistics
->insertvlan
=
573 in_be32(&p_rx_fw_statistics_pram
->insertvlan
);
576 /* Hardware only if user handed pointer and driver actually
577 gathers hardware statistics */
578 if (hardware_statistics
&&
579 (in_be32(&uf_regs
->upsmr
) & UCC_GETH_UPSMR_HSE
)) {
580 hardware_statistics
->tx64
= in_be32(&ug_regs
->tx64
);
581 hardware_statistics
->tx127
= in_be32(&ug_regs
->tx127
);
582 hardware_statistics
->tx255
= in_be32(&ug_regs
->tx255
);
583 hardware_statistics
->rx64
= in_be32(&ug_regs
->rx64
);
584 hardware_statistics
->rx127
= in_be32(&ug_regs
->rx127
);
585 hardware_statistics
->rx255
= in_be32(&ug_regs
->rx255
);
586 hardware_statistics
->txok
= in_be32(&ug_regs
->txok
);
587 hardware_statistics
->txcf
= in_be16(&ug_regs
->txcf
);
588 hardware_statistics
->tmca
= in_be32(&ug_regs
->tmca
);
589 hardware_statistics
->tbca
= in_be32(&ug_regs
->tbca
);
590 hardware_statistics
->rxfok
= in_be32(&ug_regs
->rxfok
);
591 hardware_statistics
->rxbok
= in_be32(&ug_regs
->rxbok
);
592 hardware_statistics
->rbyt
= in_be32(&ug_regs
->rbyt
);
593 hardware_statistics
->rmca
= in_be32(&ug_regs
->rmca
);
594 hardware_statistics
->rbca
= in_be32(&ug_regs
->rbca
);
598 static void dump_bds(struct ucc_geth_private
*ugeth
)
603 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
604 if (ugeth
->p_tx_bd_ring
[i
]) {
606 (ugeth
->ug_info
->bdRingLenTx
[i
] *
607 sizeof(struct qe_bd
));
608 ugeth_info("TX BDs[%d]", i
);
609 mem_disp(ugeth
->p_tx_bd_ring
[i
], length
);
612 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
613 if (ugeth
->p_rx_bd_ring
[i
]) {
615 (ugeth
->ug_info
->bdRingLenRx
[i
] *
616 sizeof(struct qe_bd
));
617 ugeth_info("RX BDs[%d]", i
);
618 mem_disp(ugeth
->p_rx_bd_ring
[i
], length
);
623 static void dump_regs(struct ucc_geth_private
*ugeth
)
627 ugeth_info("UCC%d Geth registers:", ugeth
->ug_info
->uf_info
.ucc_num
);
628 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->ug_regs
);
630 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
631 (u32
) & ugeth
->ug_regs
->maccfg1
,
632 in_be32(&ugeth
->ug_regs
->maccfg1
));
633 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
634 (u32
) & ugeth
->ug_regs
->maccfg2
,
635 in_be32(&ugeth
->ug_regs
->maccfg2
));
636 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
637 (u32
) & ugeth
->ug_regs
->ipgifg
,
638 in_be32(&ugeth
->ug_regs
->ipgifg
));
639 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
640 (u32
) & ugeth
->ug_regs
->hafdup
,
641 in_be32(&ugeth
->ug_regs
->hafdup
));
642 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
643 (u32
) & ugeth
->ug_regs
->ifctl
,
644 in_be32(&ugeth
->ug_regs
->ifctl
));
645 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
646 (u32
) & ugeth
->ug_regs
->ifstat
,
647 in_be32(&ugeth
->ug_regs
->ifstat
));
648 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
649 (u32
) & ugeth
->ug_regs
->macstnaddr1
,
650 in_be32(&ugeth
->ug_regs
->macstnaddr1
));
651 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
652 (u32
) & ugeth
->ug_regs
->macstnaddr2
,
653 in_be32(&ugeth
->ug_regs
->macstnaddr2
));
654 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
655 (u32
) & ugeth
->ug_regs
->uempr
,
656 in_be32(&ugeth
->ug_regs
->uempr
));
657 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
658 (u32
) & ugeth
->ug_regs
->utbipar
,
659 in_be32(&ugeth
->ug_regs
->utbipar
));
660 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
661 (u32
) & ugeth
->ug_regs
->uescr
,
662 in_be16(&ugeth
->ug_regs
->uescr
));
663 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
664 (u32
) & ugeth
->ug_regs
->tx64
,
665 in_be32(&ugeth
->ug_regs
->tx64
));
666 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
667 (u32
) & ugeth
->ug_regs
->tx127
,
668 in_be32(&ugeth
->ug_regs
->tx127
));
669 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
670 (u32
) & ugeth
->ug_regs
->tx255
,
671 in_be32(&ugeth
->ug_regs
->tx255
));
672 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
673 (u32
) & ugeth
->ug_regs
->rx64
,
674 in_be32(&ugeth
->ug_regs
->rx64
));
675 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
676 (u32
) & ugeth
->ug_regs
->rx127
,
677 in_be32(&ugeth
->ug_regs
->rx127
));
678 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
679 (u32
) & ugeth
->ug_regs
->rx255
,
680 in_be32(&ugeth
->ug_regs
->rx255
));
681 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
682 (u32
) & ugeth
->ug_regs
->txok
,
683 in_be32(&ugeth
->ug_regs
->txok
));
684 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
685 (u32
) & ugeth
->ug_regs
->txcf
,
686 in_be16(&ugeth
->ug_regs
->txcf
));
687 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
688 (u32
) & ugeth
->ug_regs
->tmca
,
689 in_be32(&ugeth
->ug_regs
->tmca
));
690 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
691 (u32
) & ugeth
->ug_regs
->tbca
,
692 in_be32(&ugeth
->ug_regs
->tbca
));
693 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
694 (u32
) & ugeth
->ug_regs
->rxfok
,
695 in_be32(&ugeth
->ug_regs
->rxfok
));
696 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
697 (u32
) & ugeth
->ug_regs
->rxbok
,
698 in_be32(&ugeth
->ug_regs
->rxbok
));
699 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
700 (u32
) & ugeth
->ug_regs
->rbyt
,
701 in_be32(&ugeth
->ug_regs
->rbyt
));
702 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
703 (u32
) & ugeth
->ug_regs
->rmca
,
704 in_be32(&ugeth
->ug_regs
->rmca
));
705 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
706 (u32
) & ugeth
->ug_regs
->rbca
,
707 in_be32(&ugeth
->ug_regs
->rbca
));
708 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
709 (u32
) & ugeth
->ug_regs
->scar
,
710 in_be32(&ugeth
->ug_regs
->scar
));
711 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
712 (u32
) & ugeth
->ug_regs
->scam
,
713 in_be32(&ugeth
->ug_regs
->scam
));
715 if (ugeth
->p_thread_data_tx
) {
716 int numThreadsTxNumerical
;
717 switch (ugeth
->ug_info
->numThreadsTx
) {
718 case UCC_GETH_NUM_OF_THREADS_1
:
719 numThreadsTxNumerical
= 1;
721 case UCC_GETH_NUM_OF_THREADS_2
:
722 numThreadsTxNumerical
= 2;
724 case UCC_GETH_NUM_OF_THREADS_4
:
725 numThreadsTxNumerical
= 4;
727 case UCC_GETH_NUM_OF_THREADS_6
:
728 numThreadsTxNumerical
= 6;
730 case UCC_GETH_NUM_OF_THREADS_8
:
731 numThreadsTxNumerical
= 8;
734 numThreadsTxNumerical
= 0;
738 ugeth_info("Thread data TXs:");
739 ugeth_info("Base address: 0x%08x",
740 (u32
) ugeth
->p_thread_data_tx
);
741 for (i
= 0; i
< numThreadsTxNumerical
; i
++) {
742 ugeth_info("Thread data TX[%d]:", i
);
743 ugeth_info("Base address: 0x%08x",
744 (u32
) & ugeth
->p_thread_data_tx
[i
]);
745 mem_disp((u8
*) & ugeth
->p_thread_data_tx
[i
],
746 sizeof(struct ucc_geth_thread_data_tx
));
749 if (ugeth
->p_thread_data_rx
) {
750 int numThreadsRxNumerical
;
751 switch (ugeth
->ug_info
->numThreadsRx
) {
752 case UCC_GETH_NUM_OF_THREADS_1
:
753 numThreadsRxNumerical
= 1;
755 case UCC_GETH_NUM_OF_THREADS_2
:
756 numThreadsRxNumerical
= 2;
758 case UCC_GETH_NUM_OF_THREADS_4
:
759 numThreadsRxNumerical
= 4;
761 case UCC_GETH_NUM_OF_THREADS_6
:
762 numThreadsRxNumerical
= 6;
764 case UCC_GETH_NUM_OF_THREADS_8
:
765 numThreadsRxNumerical
= 8;
768 numThreadsRxNumerical
= 0;
772 ugeth_info("Thread data RX:");
773 ugeth_info("Base address: 0x%08x",
774 (u32
) ugeth
->p_thread_data_rx
);
775 for (i
= 0; i
< numThreadsRxNumerical
; i
++) {
776 ugeth_info("Thread data RX[%d]:", i
);
777 ugeth_info("Base address: 0x%08x",
778 (u32
) & ugeth
->p_thread_data_rx
[i
]);
779 mem_disp((u8
*) & ugeth
->p_thread_data_rx
[i
],
780 sizeof(struct ucc_geth_thread_data_rx
));
783 if (ugeth
->p_exf_glbl_param
) {
784 ugeth_info("EXF global param:");
785 ugeth_info("Base address: 0x%08x",
786 (u32
) ugeth
->p_exf_glbl_param
);
787 mem_disp((u8
*) ugeth
->p_exf_glbl_param
,
788 sizeof(*ugeth
->p_exf_glbl_param
));
790 if (ugeth
->p_tx_glbl_pram
) {
791 ugeth_info("TX global param:");
792 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_tx_glbl_pram
);
793 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
794 (u32
) & ugeth
->p_tx_glbl_pram
->temoder
,
795 in_be16(&ugeth
->p_tx_glbl_pram
->temoder
));
796 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
797 (u32
) & ugeth
->p_tx_glbl_pram
->sqptr
,
798 in_be32(&ugeth
->p_tx_glbl_pram
->sqptr
));
799 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
800 (u32
) & ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
801 in_be32(&ugeth
->p_tx_glbl_pram
->
802 schedulerbasepointer
));
803 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
804 (u32
) & ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
805 in_be32(&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
));
806 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
807 (u32
) & ugeth
->p_tx_glbl_pram
->tstate
,
808 in_be32(&ugeth
->p_tx_glbl_pram
->tstate
));
809 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
810 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[0],
811 ugeth
->p_tx_glbl_pram
->iphoffset
[0]);
812 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
813 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[1],
814 ugeth
->p_tx_glbl_pram
->iphoffset
[1]);
815 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
816 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[2],
817 ugeth
->p_tx_glbl_pram
->iphoffset
[2]);
818 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
819 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[3],
820 ugeth
->p_tx_glbl_pram
->iphoffset
[3]);
821 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
822 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[4],
823 ugeth
->p_tx_glbl_pram
->iphoffset
[4]);
824 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
825 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[5],
826 ugeth
->p_tx_glbl_pram
->iphoffset
[5]);
827 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
828 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[6],
829 ugeth
->p_tx_glbl_pram
->iphoffset
[6]);
830 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
831 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[7],
832 ugeth
->p_tx_glbl_pram
->iphoffset
[7]);
833 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
834 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[0],
835 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[0]));
836 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
837 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[1],
838 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[1]));
839 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
840 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[2],
841 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[2]));
842 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
843 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[3],
844 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[3]));
845 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
846 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[4],
847 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[4]));
848 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
849 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[5],
850 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[5]));
851 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
852 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[6],
853 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[6]));
854 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
855 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[7],
856 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[7]));
857 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
858 (u32
) & ugeth
->p_tx_glbl_pram
->tqptr
,
859 in_be32(&ugeth
->p_tx_glbl_pram
->tqptr
));
861 if (ugeth
->p_rx_glbl_pram
) {
862 ugeth_info("RX global param:");
863 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_glbl_pram
);
864 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
865 (u32
) & ugeth
->p_rx_glbl_pram
->remoder
,
866 in_be32(&ugeth
->p_rx_glbl_pram
->remoder
));
867 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
868 (u32
) & ugeth
->p_rx_glbl_pram
->rqptr
,
869 in_be32(&ugeth
->p_rx_glbl_pram
->rqptr
));
870 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
871 (u32
) & ugeth
->p_rx_glbl_pram
->typeorlen
,
872 in_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
));
873 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
874 (u32
) & ugeth
->p_rx_glbl_pram
->rxgstpack
,
875 ugeth
->p_rx_glbl_pram
->rxgstpack
);
876 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
877 (u32
) & ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
878 in_be32(&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
));
879 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
880 (u32
) & ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
881 in_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
));
882 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
883 (u32
) & ugeth
->p_rx_glbl_pram
->rstate
,
884 ugeth
->p_rx_glbl_pram
->rstate
);
885 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
886 (u32
) & ugeth
->p_rx_glbl_pram
->mrblr
,
887 in_be16(&ugeth
->p_rx_glbl_pram
->mrblr
));
888 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
889 (u32
) & ugeth
->p_rx_glbl_pram
->rbdqptr
,
890 in_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
));
891 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
892 (u32
) & ugeth
->p_rx_glbl_pram
->mflr
,
893 in_be16(&ugeth
->p_rx_glbl_pram
->mflr
));
894 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
895 (u32
) & ugeth
->p_rx_glbl_pram
->minflr
,
896 in_be16(&ugeth
->p_rx_glbl_pram
->minflr
));
897 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
898 (u32
) & ugeth
->p_rx_glbl_pram
->maxd1
,
899 in_be16(&ugeth
->p_rx_glbl_pram
->maxd1
));
900 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
901 (u32
) & ugeth
->p_rx_glbl_pram
->maxd2
,
902 in_be16(&ugeth
->p_rx_glbl_pram
->maxd2
));
903 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
904 (u32
) & ugeth
->p_rx_glbl_pram
->ecamptr
,
905 in_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
));
906 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
907 (u32
) & ugeth
->p_rx_glbl_pram
->l2qt
,
908 in_be32(&ugeth
->p_rx_glbl_pram
->l2qt
));
909 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
910 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[0],
911 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[0]));
912 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
913 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[1],
914 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[1]));
915 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
916 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[2],
917 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[2]));
918 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
919 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[3],
920 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[3]));
921 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
922 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[4],
923 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[4]));
924 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
925 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[5],
926 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[5]));
927 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
928 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[6],
929 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[6]));
930 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
931 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[7],
932 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[7]));
933 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
934 (u32
) & ugeth
->p_rx_glbl_pram
->vlantype
,
935 in_be16(&ugeth
->p_rx_glbl_pram
->vlantype
));
936 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
937 (u32
) & ugeth
->p_rx_glbl_pram
->vlantci
,
938 in_be16(&ugeth
->p_rx_glbl_pram
->vlantci
));
939 for (i
= 0; i
< 64; i
++)
941 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
943 (u32
) & ugeth
->p_rx_glbl_pram
->addressfiltering
[i
],
944 ugeth
->p_rx_glbl_pram
->addressfiltering
[i
]);
945 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
946 (u32
) & ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
947 in_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
));
949 if (ugeth
->p_send_q_mem_reg
) {
950 ugeth_info("Send Q memory registers:");
951 ugeth_info("Base address: 0x%08x",
952 (u32
) ugeth
->p_send_q_mem_reg
);
953 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
954 ugeth_info("SQQD[%d]:", i
);
955 ugeth_info("Base address: 0x%08x",
956 (u32
) & ugeth
->p_send_q_mem_reg
->sqqd
[i
]);
957 mem_disp((u8
*) & ugeth
->p_send_q_mem_reg
->sqqd
[i
],
958 sizeof(struct ucc_geth_send_queue_qd
));
961 if (ugeth
->p_scheduler
) {
962 ugeth_info("Scheduler:");
963 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_scheduler
);
964 mem_disp((u8
*) ugeth
->p_scheduler
,
965 sizeof(*ugeth
->p_scheduler
));
967 if (ugeth
->p_tx_fw_statistics_pram
) {
968 ugeth_info("TX FW statistics pram:");
969 ugeth_info("Base address: 0x%08x",
970 (u32
) ugeth
->p_tx_fw_statistics_pram
);
971 mem_disp((u8
*) ugeth
->p_tx_fw_statistics_pram
,
972 sizeof(*ugeth
->p_tx_fw_statistics_pram
));
974 if (ugeth
->p_rx_fw_statistics_pram
) {
975 ugeth_info("RX FW statistics pram:");
976 ugeth_info("Base address: 0x%08x",
977 (u32
) ugeth
->p_rx_fw_statistics_pram
);
978 mem_disp((u8
*) ugeth
->p_rx_fw_statistics_pram
,
979 sizeof(*ugeth
->p_rx_fw_statistics_pram
));
981 if (ugeth
->p_rx_irq_coalescing_tbl
) {
982 ugeth_info("RX IRQ coalescing tables:");
983 ugeth_info("Base address: 0x%08x",
984 (u32
) ugeth
->p_rx_irq_coalescing_tbl
);
985 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
986 ugeth_info("RX IRQ coalescing table entry[%d]:", i
);
987 ugeth_info("Base address: 0x%08x",
988 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
991 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
992 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
993 coalescingentry
[i
].interruptcoalescingmaxvalue
,
994 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
996 interruptcoalescingmaxvalue
));
998 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
999 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1000 coalescingentry
[i
].interruptcoalescingcounter
,
1001 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1003 interruptcoalescingcounter
));
1006 if (ugeth
->p_rx_bd_qs_tbl
) {
1007 ugeth_info("RX BD QS tables:");
1008 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_bd_qs_tbl
);
1009 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1010 ugeth_info("RX BD QS table[%d]:", i
);
1011 ugeth_info("Base address: 0x%08x",
1012 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
]);
1014 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1015 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
,
1016 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
));
1018 ("bdptr : addr - 0x%08x, val - 0x%08x",
1019 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
,
1020 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
));
1022 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1023 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
1024 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].
1025 externalbdbaseptr
));
1027 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1028 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
,
1029 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
));
1030 ugeth_info("ucode RX Prefetched BDs:");
1031 ugeth_info("Base address: 0x%08x",
1033 qe_muram_addr(in_be32
1034 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1037 qe_muram_addr(in_be32
1038 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1040 sizeof(struct ucc_geth_rx_prefetched_bds
));
1043 if (ugeth
->p_init_enet_param_shadow
) {
1045 ugeth_info("Init enet param shadow:");
1046 ugeth_info("Base address: 0x%08x",
1047 (u32
) ugeth
->p_init_enet_param_shadow
);
1048 mem_disp((u8
*) ugeth
->p_init_enet_param_shadow
,
1049 sizeof(*ugeth
->p_init_enet_param_shadow
));
1051 size
= sizeof(struct ucc_geth_thread_rx_pram
);
1052 if (ugeth
->ug_info
->rxExtendedFiltering
) {
1054 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
1055 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1056 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
1058 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
1059 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1060 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
1062 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
1065 dump_init_enet_entries(ugeth
,
1066 &(ugeth
->p_init_enet_param_shadow
->
1068 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1069 sizeof(struct ucc_geth_thread_tx_pram
),
1070 ugeth
->ug_info
->riscTx
, 0);
1071 dump_init_enet_entries(ugeth
,
1072 &(ugeth
->p_init_enet_param_shadow
->
1074 ENET_INIT_PARAM_MAX_ENTRIES_RX
, size
,
1075 ugeth
->ug_info
->riscRx
, 1);
1080 static void init_default_reg_vals(u32 __iomem
*upsmr_register
,
1081 u32 __iomem
*maccfg1_register
,
1082 u32 __iomem
*maccfg2_register
)
1084 out_be32(upsmr_register
, UCC_GETH_UPSMR_INIT
);
1085 out_be32(maccfg1_register
, UCC_GETH_MACCFG1_INIT
);
1086 out_be32(maccfg2_register
, UCC_GETH_MACCFG2_INIT
);
1089 static int init_half_duplex_params(int alt_beb
,
1090 int back_pressure_no_backoff
,
1093 u8 alt_beb_truncation
,
1094 u8 max_retransmissions
,
1095 u8 collision_window
,
1096 u32 __iomem
*hafdup_register
)
1100 if ((alt_beb_truncation
> HALFDUP_ALT_BEB_TRUNCATION_MAX
) ||
1101 (max_retransmissions
> HALFDUP_MAX_RETRANSMISSION_MAX
) ||
1102 (collision_window
> HALFDUP_COLLISION_WINDOW_MAX
))
1105 value
= (u32
) (alt_beb_truncation
<< HALFDUP_ALT_BEB_TRUNCATION_SHIFT
);
1108 value
|= HALFDUP_ALT_BEB
;
1109 if (back_pressure_no_backoff
)
1110 value
|= HALFDUP_BACK_PRESSURE_NO_BACKOFF
;
1112 value
|= HALFDUP_NO_BACKOFF
;
1114 value
|= HALFDUP_EXCESSIVE_DEFER
;
1116 value
|= (max_retransmissions
<< HALFDUP_MAX_RETRANSMISSION_SHIFT
);
1118 value
|= collision_window
;
1120 out_be32(hafdup_register
, value
);
1124 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg
,
1128 u32 __iomem
*ipgifg_register
)
1132 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1134 if (non_btb_cs_ipg
> non_btb_ipg
)
1137 if ((non_btb_cs_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
) ||
1138 (non_btb_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
) ||
1139 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1140 (btb_ipg
> IPGIFG_BACK_TO_BACK_IFG_MAX
))
1144 ((non_btb_cs_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
) &
1145 IPGIFG_NBTB_CS_IPG_MASK
);
1147 ((non_btb_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
) &
1148 IPGIFG_NBTB_IPG_MASK
);
1150 ((min_ifg
<< IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
) &
1151 IPGIFG_MIN_IFG_MASK
);
1152 value
|= (btb_ipg
& IPGIFG_BTB_IPG_MASK
);
1154 out_be32(ipgifg_register
, value
);
1158 int init_flow_control_params(u32 automatic_flow_control_mode
,
1159 int rx_flow_control_enable
,
1160 int tx_flow_control_enable
,
1162 u16 extension_field
,
1163 u32 __iomem
*upsmr_register
,
1164 u32 __iomem
*uempr_register
,
1165 u32 __iomem
*maccfg1_register
)
1169 /* Set UEMPR register */
1170 value
= (u32
) pause_period
<< UEMPR_PAUSE_TIME_VALUE_SHIFT
;
1171 value
|= (u32
) extension_field
<< UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
;
1172 out_be32(uempr_register
, value
);
1174 /* Set UPSMR register */
1175 setbits32(upsmr_register
, automatic_flow_control_mode
);
1177 value
= in_be32(maccfg1_register
);
1178 if (rx_flow_control_enable
)
1179 value
|= MACCFG1_FLOW_RX
;
1180 if (tx_flow_control_enable
)
1181 value
|= MACCFG1_FLOW_TX
;
1182 out_be32(maccfg1_register
, value
);
1187 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics
,
1188 int auto_zero_hardware_statistics
,
1189 u32 __iomem
*upsmr_register
,
1190 u16 __iomem
*uescr_register
)
1192 u16 uescr_value
= 0;
1194 /* Enable hardware statistics gathering if requested */
1195 if (enable_hardware_statistics
)
1196 setbits32(upsmr_register
, UCC_GETH_UPSMR_HSE
);
1198 /* Clear hardware statistics counters */
1199 uescr_value
= in_be16(uescr_register
);
1200 uescr_value
|= UESCR_CLRCNT
;
1201 /* Automatically zero hardware statistics counters on read,
1203 if (auto_zero_hardware_statistics
)
1204 uescr_value
|= UESCR_AUTOZ
;
1205 out_be16(uescr_register
, uescr_value
);
1210 static int init_firmware_statistics_gathering_mode(int
1211 enable_tx_firmware_statistics
,
1212 int enable_rx_firmware_statistics
,
1213 u32 __iomem
*tx_rmon_base_ptr
,
1214 u32 tx_firmware_statistics_structure_address
,
1215 u32 __iomem
*rx_rmon_base_ptr
,
1216 u32 rx_firmware_statistics_structure_address
,
1217 u16 __iomem
*temoder_register
,
1218 u32 __iomem
*remoder_register
)
1220 /* Note: this function does not check if */
1221 /* the parameters it receives are NULL */
1223 if (enable_tx_firmware_statistics
) {
1224 out_be32(tx_rmon_base_ptr
,
1225 tx_firmware_statistics_structure_address
);
1226 setbits16(temoder_register
, TEMODER_TX_RMON_STATISTICS_ENABLE
);
1229 if (enable_rx_firmware_statistics
) {
1230 out_be32(rx_rmon_base_ptr
,
1231 rx_firmware_statistics_structure_address
);
1232 setbits32(remoder_register
, REMODER_RX_RMON_STATISTICS_ENABLE
);
1238 static int init_mac_station_addr_regs(u8 address_byte_0
,
1244 u32 __iomem
*macstnaddr1_register
,
1245 u32 __iomem
*macstnaddr2_register
)
1249 /* Example: for a station address of 0x12345678ABCD, */
1250 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1252 /* MACSTNADDR1 Register: */
1255 /* station address byte 5 station address byte 4 */
1257 /* station address byte 3 station address byte 2 */
1258 value
|= (u32
) ((address_byte_2
<< 0) & 0x000000FF);
1259 value
|= (u32
) ((address_byte_3
<< 8) & 0x0000FF00);
1260 value
|= (u32
) ((address_byte_4
<< 16) & 0x00FF0000);
1261 value
|= (u32
) ((address_byte_5
<< 24) & 0xFF000000);
1263 out_be32(macstnaddr1_register
, value
);
1265 /* MACSTNADDR2 Register: */
1268 /* station address byte 1 station address byte 0 */
1270 /* reserved reserved */
1272 value
|= (u32
) ((address_byte_0
<< 16) & 0x00FF0000);
1273 value
|= (u32
) ((address_byte_1
<< 24) & 0xFF000000);
1275 out_be32(macstnaddr2_register
, value
);
1280 static int init_check_frame_length_mode(int length_check
,
1281 u32 __iomem
*maccfg2_register
)
1285 value
= in_be32(maccfg2_register
);
1288 value
|= MACCFG2_LC
;
1290 value
&= ~MACCFG2_LC
;
1292 out_be32(maccfg2_register
, value
);
1296 static int init_preamble_length(u8 preamble_length
,
1297 u32 __iomem
*maccfg2_register
)
1299 if ((preamble_length
< 3) || (preamble_length
> 7))
1302 clrsetbits_be32(maccfg2_register
, MACCFG2_PREL_MASK
,
1303 preamble_length
<< MACCFG2_PREL_SHIFT
);
1308 static int init_rx_parameters(int reject_broadcast
,
1309 int receive_short_frames
,
1310 int promiscuous
, u32 __iomem
*upsmr_register
)
1314 value
= in_be32(upsmr_register
);
1316 if (reject_broadcast
)
1317 value
|= UCC_GETH_UPSMR_BRO
;
1319 value
&= ~UCC_GETH_UPSMR_BRO
;
1321 if (receive_short_frames
)
1322 value
|= UCC_GETH_UPSMR_RSH
;
1324 value
&= ~UCC_GETH_UPSMR_RSH
;
1327 value
|= UCC_GETH_UPSMR_PRO
;
1329 value
&= ~UCC_GETH_UPSMR_PRO
;
1331 out_be32(upsmr_register
, value
);
1336 static int init_max_rx_buff_len(u16 max_rx_buf_len
,
1337 u16 __iomem
*mrblr_register
)
1339 /* max_rx_buf_len value must be a multiple of 128 */
1340 if ((max_rx_buf_len
== 0)
1341 || (max_rx_buf_len
% UCC_GETH_MRBLR_ALIGNMENT
))
1344 out_be16(mrblr_register
, max_rx_buf_len
);
1348 static int init_min_frame_len(u16 min_frame_length
,
1349 u16 __iomem
*minflr_register
,
1350 u16 __iomem
*mrblr_register
)
1352 u16 mrblr_value
= 0;
1354 mrblr_value
= in_be16(mrblr_register
);
1355 if (min_frame_length
>= (mrblr_value
- 4))
1358 out_be16(minflr_register
, min_frame_length
);
1362 static int adjust_enet_interface(struct ucc_geth_private
*ugeth
)
1364 struct ucc_geth_info
*ug_info
;
1365 struct ucc_geth __iomem
*ug_regs
;
1366 struct ucc_fast __iomem
*uf_regs
;
1368 u32 upsmr
, maccfg2
, tbiBaseAddress
;
1371 ugeth_vdbg("%s: IN", __func__
);
1373 ug_info
= ugeth
->ug_info
;
1374 ug_regs
= ugeth
->ug_regs
;
1375 uf_regs
= ugeth
->uccf
->uf_regs
;
1378 maccfg2
= in_be32(&ug_regs
->maccfg2
);
1379 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
1380 if ((ugeth
->max_speed
== SPEED_10
) ||
1381 (ugeth
->max_speed
== SPEED_100
))
1382 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
1383 else if (ugeth
->max_speed
== SPEED_1000
)
1384 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
1385 maccfg2
|= ug_info
->padAndCrc
;
1386 out_be32(&ug_regs
->maccfg2
, maccfg2
);
1389 upsmr
= in_be32(&uf_regs
->upsmr
);
1390 upsmr
&= ~(UCC_GETH_UPSMR_RPM
| UCC_GETH_UPSMR_R10M
|
1391 UCC_GETH_UPSMR_TBIM
| UCC_GETH_UPSMR_RMM
);
1392 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1393 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1394 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1395 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1396 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1397 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1398 upsmr
|= UCC_GETH_UPSMR_RPM
;
1399 switch (ugeth
->max_speed
) {
1401 upsmr
|= UCC_GETH_UPSMR_R10M
;
1404 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RTBI
)
1405 upsmr
|= UCC_GETH_UPSMR_RMM
;
1408 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1409 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1410 upsmr
|= UCC_GETH_UPSMR_TBIM
;
1412 out_be32(&uf_regs
->upsmr
, upsmr
);
1414 /* Disable autonegotiation in tbi mode, because by default it
1415 comes up in autonegotiation mode. */
1416 /* Note that this depends on proper setting in utbipar register. */
1417 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1418 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1419 tbiBaseAddress
= in_be32(&ug_regs
->utbipar
);
1420 tbiBaseAddress
&= UTBIPAR_PHY_ADDRESS_MASK
;
1421 tbiBaseAddress
>>= UTBIPAR_PHY_ADDRESS_SHIFT
;
1422 value
= ugeth
->phydev
->bus
->read(ugeth
->phydev
->bus
,
1423 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
);
1424 value
&= ~0x1000; /* Turn off autonegotiation */
1425 ugeth
->phydev
->bus
->write(ugeth
->phydev
->bus
,
1426 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
, value
);
1429 init_check_frame_length_mode(ug_info
->lengthCheckRx
, &ug_regs
->maccfg2
);
1431 ret_val
= init_preamble_length(ug_info
->prel
, &ug_regs
->maccfg2
);
1433 if (netif_msg_probe(ugeth
))
1434 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1442 /* Called every time the controller might need to be made
1443 * aware of new link state. The PHY code conveys this
1444 * information through variables in the ugeth structure, and this
1445 * function converts those variables into the appropriate
1446 * register values, and can bring down the device if needed.
1449 static void adjust_link(struct net_device
*dev
)
1451 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1452 struct ucc_geth __iomem
*ug_regs
;
1453 struct ucc_fast __iomem
*uf_regs
;
1454 struct phy_device
*phydev
= ugeth
->phydev
;
1455 unsigned long flags
;
1458 ug_regs
= ugeth
->ug_regs
;
1459 uf_regs
= ugeth
->uccf
->uf_regs
;
1461 spin_lock_irqsave(&ugeth
->lock
, flags
);
1464 u32 tempval
= in_be32(&ug_regs
->maccfg2
);
1465 u32 upsmr
= in_be32(&uf_regs
->upsmr
);
1466 /* Now we make sure that we can be in full duplex mode.
1467 * If not, we operate in half-duplex mode. */
1468 if (phydev
->duplex
!= ugeth
->oldduplex
) {
1470 if (!(phydev
->duplex
))
1471 tempval
&= ~(MACCFG2_FDX
);
1473 tempval
|= MACCFG2_FDX
;
1474 ugeth
->oldduplex
= phydev
->duplex
;
1477 if (phydev
->speed
!= ugeth
->oldspeed
) {
1479 switch (phydev
->speed
) {
1481 tempval
= ((tempval
&
1482 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1483 MACCFG2_INTERFACE_MODE_BYTE
);
1487 tempval
= ((tempval
&
1488 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1489 MACCFG2_INTERFACE_MODE_NIBBLE
);
1490 /* if reduced mode, re-set UPSMR.R10M */
1491 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1492 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1493 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1494 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1495 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1496 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1497 if (phydev
->speed
== SPEED_10
)
1498 upsmr
|= UCC_GETH_UPSMR_R10M
;
1500 upsmr
&= ~UCC_GETH_UPSMR_R10M
;
1504 if (netif_msg_link(ugeth
))
1506 "%s: Ack! Speed (%d) is not 10/100/1000!",
1507 dev
->name
, phydev
->speed
);
1510 ugeth
->oldspeed
= phydev
->speed
;
1513 out_be32(&ug_regs
->maccfg2
, tempval
);
1514 out_be32(&uf_regs
->upsmr
, upsmr
);
1516 if (!ugeth
->oldlink
) {
1520 } else if (ugeth
->oldlink
) {
1523 ugeth
->oldspeed
= 0;
1524 ugeth
->oldduplex
= -1;
1527 if (new_state
&& netif_msg_link(ugeth
))
1528 phy_print_status(phydev
);
1530 spin_unlock_irqrestore(&ugeth
->lock
, flags
);
1533 /* Configure the PHY for dev.
1534 * returns 0 if success. -1 if failure
1536 static int init_phy(struct net_device
*dev
)
1538 struct ucc_geth_private
*priv
= netdev_priv(dev
);
1539 struct ucc_geth_info
*ug_info
= priv
->ug_info
;
1540 struct phy_device
*phydev
;
1544 priv
->oldduplex
= -1;
1546 phydev
= phy_connect(dev
, ug_info
->phy_bus_id
, &adjust_link
, 0,
1547 priv
->phy_interface
);
1549 if (IS_ERR(phydev
)) {
1550 printk("%s: Could not attach to PHY\n", dev
->name
);
1551 return PTR_ERR(phydev
);
1554 phydev
->supported
&= (ADVERTISED_10baseT_Half
|
1555 ADVERTISED_10baseT_Full
|
1556 ADVERTISED_100baseT_Half
|
1557 ADVERTISED_100baseT_Full
);
1559 if (priv
->max_speed
== SPEED_1000
)
1560 phydev
->supported
|= ADVERTISED_1000baseT_Full
;
1562 phydev
->advertising
= phydev
->supported
;
1564 priv
->phydev
= phydev
;
1571 static int ugeth_graceful_stop_tx(struct ucc_geth_private
*ugeth
)
1573 struct ucc_fast_private
*uccf
;
1580 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1581 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_GRA
);
1582 out_be32(uccf
->p_ucce
, UCC_GETH_UCCE_GRA
); /* clear by writing 1 */
1584 /* Issue host command */
1586 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1587 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
1588 QE_CR_PROTOCOL_ETHERNET
, 0);
1590 /* Wait for command to complete */
1593 temp
= in_be32(uccf
->p_ucce
);
1594 } while (!(temp
& UCC_GETH_UCCE_GRA
) && --i
);
1596 uccf
->stopped_tx
= 1;
1601 static int ugeth_graceful_stop_rx(struct ucc_geth_private
* ugeth
)
1603 struct ucc_fast_private
*uccf
;
1610 /* Clear acknowledge bit */
1611 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1612 temp
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
1613 out_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
, temp
);
1615 /* Keep issuing command and checking acknowledge bit until
1616 it is asserted, according to spec */
1618 /* Issue host command */
1620 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.
1622 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
1623 QE_CR_PROTOCOL_ETHERNET
, 0);
1625 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1626 } while (!(temp
& GRACEFUL_STOP_ACKNOWLEDGE_RX
) && --i
);
1628 uccf
->stopped_rx
= 1;
1633 static int ugeth_restart_tx(struct ucc_geth_private
*ugeth
)
1635 struct ucc_fast_private
*uccf
;
1641 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1642 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
, 0);
1643 uccf
->stopped_tx
= 0;
1648 static int ugeth_restart_rx(struct ucc_geth_private
*ugeth
)
1650 struct ucc_fast_private
*uccf
;
1656 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1657 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
1659 uccf
->stopped_rx
= 0;
1664 static int ugeth_enable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
1666 struct ucc_fast_private
*uccf
;
1667 int enabled_tx
, enabled_rx
;
1671 /* check if the UCC number is in range. */
1672 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1673 if (netif_msg_probe(ugeth
))
1674 ugeth_err("%s: ucc_num out of range.", __func__
);
1678 enabled_tx
= uccf
->enabled_tx
;
1679 enabled_rx
= uccf
->enabled_rx
;
1681 /* Get Tx and Rx going again, in case this channel was actively
1683 if ((mode
& COMM_DIR_TX
) && (!enabled_tx
) && uccf
->stopped_tx
)
1684 ugeth_restart_tx(ugeth
);
1685 if ((mode
& COMM_DIR_RX
) && (!enabled_rx
) && uccf
->stopped_rx
)
1686 ugeth_restart_rx(ugeth
);
1688 ucc_fast_enable(uccf
, mode
); /* OK to do even if not disabled */
1694 static int ugeth_disable(struct ucc_geth_private
* ugeth
, enum comm_dir mode
)
1696 struct ucc_fast_private
*uccf
;
1700 /* check if the UCC number is in range. */
1701 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1702 if (netif_msg_probe(ugeth
))
1703 ugeth_err("%s: ucc_num out of range.", __func__
);
1707 /* Stop any transmissions */
1708 if ((mode
& COMM_DIR_TX
) && uccf
->enabled_tx
&& !uccf
->stopped_tx
)
1709 ugeth_graceful_stop_tx(ugeth
);
1711 /* Stop any receptions */
1712 if ((mode
& COMM_DIR_RX
) && uccf
->enabled_rx
&& !uccf
->stopped_rx
)
1713 ugeth_graceful_stop_rx(ugeth
);
1715 ucc_fast_disable(ugeth
->uccf
, mode
); /* OK to do even if not enabled */
1720 static void ugeth_dump_regs(struct ucc_geth_private
*ugeth
)
1723 ucc_fast_dump_regs(ugeth
->uccf
);
1729 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private
*
1734 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1735 struct ucc_fast_private
*uccf
;
1736 enum comm_dir comm_dir
;
1737 struct list_head
*p_lh
;
1739 u32 __iomem
*addr_h
;
1740 u32 __iomem
*addr_l
;
1746 (struct ucc_geth_82xx_address_filtering_pram __iomem
*)
1747 ugeth
->p_rx_glbl_pram
->addressfiltering
;
1749 if (enet_addr_type
== ENET_ADDR_TYPE_GROUP
) {
1750 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
1751 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
1752 p_lh
= &ugeth
->group_hash_q
;
1753 p_counter
= &(ugeth
->numGroupAddrInHash
);
1754 } else if (enet_addr_type
== ENET_ADDR_TYPE_INDIVIDUAL
) {
1755 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
1756 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
1757 p_lh
= &ugeth
->ind_hash_q
;
1758 p_counter
= &(ugeth
->numIndAddrInHash
);
1763 if (uccf
->enabled_tx
)
1764 comm_dir
|= COMM_DIR_TX
;
1765 if (uccf
->enabled_rx
)
1766 comm_dir
|= COMM_DIR_RX
;
1768 ugeth_disable(ugeth
, comm_dir
);
1770 /* Clear the hash table. */
1771 out_be32(addr_h
, 0x00000000);
1772 out_be32(addr_l
, 0x00000000);
1779 /* Delete all remaining CQ elements */
1780 for (i
= 0; i
< num
; i
++)
1781 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh
)));
1786 ugeth_enable(ugeth
, comm_dir
);
1791 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
,
1794 ugeth
->indAddrRegUsed
[paddr_num
] = 0; /* mark this paddr as not used */
1795 return hw_clear_addr_in_paddr(ugeth
, paddr_num
);/* clear in hardware */
1798 static void ucc_geth_memclean(struct ucc_geth_private
*ugeth
)
1807 ucc_fast_free(ugeth
->uccf
);
1811 if (ugeth
->p_thread_data_tx
) {
1812 qe_muram_free(ugeth
->thread_dat_tx_offset
);
1813 ugeth
->p_thread_data_tx
= NULL
;
1815 if (ugeth
->p_thread_data_rx
) {
1816 qe_muram_free(ugeth
->thread_dat_rx_offset
);
1817 ugeth
->p_thread_data_rx
= NULL
;
1819 if (ugeth
->p_exf_glbl_param
) {
1820 qe_muram_free(ugeth
->exf_glbl_param_offset
);
1821 ugeth
->p_exf_glbl_param
= NULL
;
1823 if (ugeth
->p_rx_glbl_pram
) {
1824 qe_muram_free(ugeth
->rx_glbl_pram_offset
);
1825 ugeth
->p_rx_glbl_pram
= NULL
;
1827 if (ugeth
->p_tx_glbl_pram
) {
1828 qe_muram_free(ugeth
->tx_glbl_pram_offset
);
1829 ugeth
->p_tx_glbl_pram
= NULL
;
1831 if (ugeth
->p_send_q_mem_reg
) {
1832 qe_muram_free(ugeth
->send_q_mem_reg_offset
);
1833 ugeth
->p_send_q_mem_reg
= NULL
;
1835 if (ugeth
->p_scheduler
) {
1836 qe_muram_free(ugeth
->scheduler_offset
);
1837 ugeth
->p_scheduler
= NULL
;
1839 if (ugeth
->p_tx_fw_statistics_pram
) {
1840 qe_muram_free(ugeth
->tx_fw_statistics_pram_offset
);
1841 ugeth
->p_tx_fw_statistics_pram
= NULL
;
1843 if (ugeth
->p_rx_fw_statistics_pram
) {
1844 qe_muram_free(ugeth
->rx_fw_statistics_pram_offset
);
1845 ugeth
->p_rx_fw_statistics_pram
= NULL
;
1847 if (ugeth
->p_rx_irq_coalescing_tbl
) {
1848 qe_muram_free(ugeth
->rx_irq_coalescing_tbl_offset
);
1849 ugeth
->p_rx_irq_coalescing_tbl
= NULL
;
1851 if (ugeth
->p_rx_bd_qs_tbl
) {
1852 qe_muram_free(ugeth
->rx_bd_qs_tbl_offset
);
1853 ugeth
->p_rx_bd_qs_tbl
= NULL
;
1855 if (ugeth
->p_init_enet_param_shadow
) {
1856 return_init_enet_entries(ugeth
,
1857 &(ugeth
->p_init_enet_param_shadow
->
1859 ENET_INIT_PARAM_MAX_ENTRIES_RX
,
1860 ugeth
->ug_info
->riscRx
, 1);
1861 return_init_enet_entries(ugeth
,
1862 &(ugeth
->p_init_enet_param_shadow
->
1864 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1865 ugeth
->ug_info
->riscTx
, 0);
1866 kfree(ugeth
->p_init_enet_param_shadow
);
1867 ugeth
->p_init_enet_param_shadow
= NULL
;
1869 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
1870 bd
= ugeth
->p_tx_bd_ring
[i
];
1873 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenTx
[i
]; j
++) {
1874 if (ugeth
->tx_skbuff
[i
][j
]) {
1875 dma_unmap_single(&ugeth
->dev
->dev
,
1876 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1877 (in_be32((u32 __iomem
*)bd
) &
1880 dev_kfree_skb_any(ugeth
->tx_skbuff
[i
][j
]);
1881 ugeth
->tx_skbuff
[i
][j
] = NULL
;
1885 kfree(ugeth
->tx_skbuff
[i
]);
1887 if (ugeth
->p_tx_bd_ring
[i
]) {
1888 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1890 kfree((void *)ugeth
->tx_bd_ring_offset
[i
]);
1891 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1893 qe_muram_free(ugeth
->tx_bd_ring_offset
[i
]);
1894 ugeth
->p_tx_bd_ring
[i
] = NULL
;
1897 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1898 if (ugeth
->p_rx_bd_ring
[i
]) {
1899 /* Return existing data buffers in ring */
1900 bd
= ugeth
->p_rx_bd_ring
[i
];
1901 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenRx
[i
]; j
++) {
1902 if (ugeth
->rx_skbuff
[i
][j
]) {
1903 dma_unmap_single(&ugeth
->dev
->dev
,
1904 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1906 uf_info
.max_rx_buf_length
+
1907 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
1910 ugeth
->rx_skbuff
[i
][j
]);
1911 ugeth
->rx_skbuff
[i
][j
] = NULL
;
1913 bd
+= sizeof(struct qe_bd
);
1916 kfree(ugeth
->rx_skbuff
[i
]);
1918 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1920 kfree((void *)ugeth
->rx_bd_ring_offset
[i
]);
1921 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1923 qe_muram_free(ugeth
->rx_bd_ring_offset
[i
]);
1924 ugeth
->p_rx_bd_ring
[i
] = NULL
;
1927 while (!list_empty(&ugeth
->group_hash_q
))
1928 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1929 (dequeue(&ugeth
->group_hash_q
)));
1930 while (!list_empty(&ugeth
->ind_hash_q
))
1931 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1932 (dequeue(&ugeth
->ind_hash_q
)));
1933 if (ugeth
->ug_regs
) {
1934 iounmap(ugeth
->ug_regs
);
1935 ugeth
->ug_regs
= NULL
;
1939 static void ucc_geth_set_multi(struct net_device
*dev
)
1941 struct ucc_geth_private
*ugeth
;
1942 struct dev_mc_list
*dmi
;
1943 struct ucc_fast __iomem
*uf_regs
;
1944 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1947 ugeth
= netdev_priv(dev
);
1949 uf_regs
= ugeth
->uccf
->uf_regs
;
1951 if (dev
->flags
& IFF_PROMISC
) {
1952 setbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
1954 clrbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
1957 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
1958 p_rx_glbl_pram
->addressfiltering
;
1960 if (dev
->flags
& IFF_ALLMULTI
) {
1961 /* Catch all multicast addresses, so set the
1962 * filter to all 1's.
1964 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0xffffffff);
1965 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0xffffffff);
1967 /* Clear filter and add the addresses in the list.
1969 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0x0);
1970 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0x0);
1974 for (i
= 0; i
< dev
->mc_count
; i
++, dmi
= dmi
->next
) {
1976 /* Only support group multicast for now.
1978 if (!(dmi
->dmi_addr
[0] & 1))
1981 /* Ask CPM to run CRC and set bit in
1984 hw_add_addr_in_hash(ugeth
, dmi
->dmi_addr
);
1990 static void ucc_geth_stop(struct ucc_geth_private
*ugeth
)
1992 struct ucc_geth __iomem
*ug_regs
= ugeth
->ug_regs
;
1993 struct phy_device
*phydev
= ugeth
->phydev
;
1995 ugeth_vdbg("%s: IN", __func__
);
1997 /* Disable the controller */
1998 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
2000 /* Tell the kernel the link is down */
2003 /* Mask all interrupts */
2004 out_be32(ugeth
->uccf
->p_uccm
, 0x00000000);
2006 /* Clear all interrupts */
2007 out_be32(ugeth
->uccf
->p_ucce
, 0xffffffff);
2009 /* Disable Rx and Tx */
2010 clrbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2012 ucc_geth_memclean(ugeth
);
2015 static int ucc_struct_init(struct ucc_geth_private
*ugeth
)
2017 struct ucc_geth_info
*ug_info
;
2018 struct ucc_fast_info
*uf_info
;
2021 ug_info
= ugeth
->ug_info
;
2022 uf_info
= &ug_info
->uf_info
;
2024 if (!((uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) ||
2025 (uf_info
->bd_mem_part
== MEM_PART_MURAM
))) {
2026 if (netif_msg_probe(ugeth
))
2027 ugeth_err("%s: Bad memory partition value.",
2033 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2034 if ((ug_info
->bdRingLenRx
[i
] < UCC_GETH_RX_BD_RING_SIZE_MIN
) ||
2035 (ug_info
->bdRingLenRx
[i
] %
2036 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
)) {
2037 if (netif_msg_probe(ugeth
))
2039 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2046 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2047 if (ug_info
->bdRingLenTx
[i
] < UCC_GETH_TX_BD_RING_SIZE_MIN
) {
2048 if (netif_msg_probe(ugeth
))
2050 ("%s: Tx BD ring length must be no smaller than 2.",
2057 if ((uf_info
->max_rx_buf_length
== 0) ||
2058 (uf_info
->max_rx_buf_length
% UCC_GETH_MRBLR_ALIGNMENT
)) {
2059 if (netif_msg_probe(ugeth
))
2061 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2067 if (ug_info
->numQueuesTx
> NUM_TX_QUEUES
) {
2068 if (netif_msg_probe(ugeth
))
2069 ugeth_err("%s: number of tx queues too large.", __func__
);
2074 if (ug_info
->numQueuesRx
> NUM_RX_QUEUES
) {
2075 if (netif_msg_probe(ugeth
))
2076 ugeth_err("%s: number of rx queues too large.", __func__
);
2081 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++) {
2082 if (ug_info
->l2qt
[i
] >= ug_info
->numQueuesRx
) {
2083 if (netif_msg_probe(ugeth
))
2085 ("%s: VLAN priority table entry must not be"
2086 " larger than number of Rx queues.",
2093 for (i
= 0; i
< UCC_GETH_IP_PRIORITY_MAX
; i
++) {
2094 if (ug_info
->l3qt
[i
] >= ug_info
->numQueuesRx
) {
2095 if (netif_msg_probe(ugeth
))
2097 ("%s: IP priority table entry must not be"
2098 " larger than number of Rx queues.",
2104 if (ug_info
->cam
&& !ug_info
->ecamptr
) {
2105 if (netif_msg_probe(ugeth
))
2106 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2111 if ((ug_info
->numStationAddresses
!=
2112 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
)
2113 && ug_info
->rxExtendedFiltering
) {
2114 if (netif_msg_probe(ugeth
))
2115 ugeth_err("%s: Number of station addresses greater than 1 "
2116 "not allowed in extended parsing mode.",
2121 /* Generate uccm_mask for receive */
2122 uf_info
->uccm_mask
= ug_info
->eventRegMask
& UCCE_OTHER
;/* Errors */
2123 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
2124 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_RXF0
<< i
);
2126 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
2127 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_TXB0
<< i
);
2128 /* Initialize the general fast UCC block. */
2129 if (ucc_fast_init(uf_info
, &ugeth
->uccf
)) {
2130 if (netif_msg_probe(ugeth
))
2131 ugeth_err("%s: Failed to init uccf.", __func__
);
2135 ugeth
->ug_regs
= ioremap(uf_info
->regs
, sizeof(*ugeth
->ug_regs
));
2136 if (!ugeth
->ug_regs
) {
2137 if (netif_msg_probe(ugeth
))
2138 ugeth_err("%s: Failed to ioremap regs.", __func__
);
2145 static int ucc_geth_startup(struct ucc_geth_private
*ugeth
)
2147 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
2148 struct ucc_geth_init_pram __iomem
*p_init_enet_pram
;
2149 struct ucc_fast_private
*uccf
;
2150 struct ucc_geth_info
*ug_info
;
2151 struct ucc_fast_info
*uf_info
;
2152 struct ucc_fast __iomem
*uf_regs
;
2153 struct ucc_geth __iomem
*ug_regs
;
2154 int ret_val
= -EINVAL
;
2155 u32 remoder
= UCC_GETH_REMODER_INIT
;
2156 u32 init_enet_pram_offset
, cecr_subblock
, command
;
2157 u32 ifstat
, i
, j
, size
, l2qt
, l3qt
, length
;
2158 u16 temoder
= UCC_GETH_TEMODER_INIT
;
2160 u8 function_code
= 0;
2162 u8 __iomem
*endOfRing
;
2163 u8 numThreadsRxNumerical
, numThreadsTxNumerical
;
2165 ugeth_vdbg("%s: IN", __func__
);
2167 ug_info
= ugeth
->ug_info
;
2168 uf_info
= &ug_info
->uf_info
;
2169 uf_regs
= uccf
->uf_regs
;
2170 ug_regs
= ugeth
->ug_regs
;
2172 switch (ug_info
->numThreadsRx
) {
2173 case UCC_GETH_NUM_OF_THREADS_1
:
2174 numThreadsRxNumerical
= 1;
2176 case UCC_GETH_NUM_OF_THREADS_2
:
2177 numThreadsRxNumerical
= 2;
2179 case UCC_GETH_NUM_OF_THREADS_4
:
2180 numThreadsRxNumerical
= 4;
2182 case UCC_GETH_NUM_OF_THREADS_6
:
2183 numThreadsRxNumerical
= 6;
2185 case UCC_GETH_NUM_OF_THREADS_8
:
2186 numThreadsRxNumerical
= 8;
2189 if (netif_msg_ifup(ugeth
))
2190 ugeth_err("%s: Bad number of Rx threads value.",
2196 switch (ug_info
->numThreadsTx
) {
2197 case UCC_GETH_NUM_OF_THREADS_1
:
2198 numThreadsTxNumerical
= 1;
2200 case UCC_GETH_NUM_OF_THREADS_2
:
2201 numThreadsTxNumerical
= 2;
2203 case UCC_GETH_NUM_OF_THREADS_4
:
2204 numThreadsTxNumerical
= 4;
2206 case UCC_GETH_NUM_OF_THREADS_6
:
2207 numThreadsTxNumerical
= 6;
2209 case UCC_GETH_NUM_OF_THREADS_8
:
2210 numThreadsTxNumerical
= 8;
2213 if (netif_msg_ifup(ugeth
))
2214 ugeth_err("%s: Bad number of Tx threads value.",
2220 /* Calculate rx_extended_features */
2221 ugeth
->rx_non_dynamic_extended_features
= ug_info
->ipCheckSumCheck
||
2222 ug_info
->ipAddressAlignment
||
2223 (ug_info
->numStationAddresses
!=
2224 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
);
2226 ugeth
->rx_extended_features
= ugeth
->rx_non_dynamic_extended_features
||
2227 (ug_info
->vlanOperationTagged
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
2228 || (ug_info
->vlanOperationNonTagged
!=
2229 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
);
2231 init_default_reg_vals(&uf_regs
->upsmr
,
2232 &ug_regs
->maccfg1
, &ug_regs
->maccfg2
);
2235 /* For more details see the hardware spec. */
2236 init_rx_parameters(ug_info
->bro
,
2237 ug_info
->rsh
, ug_info
->pro
, &uf_regs
->upsmr
);
2239 /* We're going to ignore other registers for now, */
2240 /* except as needed to get up and running */
2243 /* For more details see the hardware spec. */
2244 init_flow_control_params(ug_info
->aufc
,
2245 ug_info
->receiveFlowControl
,
2246 ug_info
->transmitFlowControl
,
2247 ug_info
->pausePeriod
,
2248 ug_info
->extensionField
,
2250 &ug_regs
->uempr
, &ug_regs
->maccfg1
);
2252 setbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2255 /* For more details see the hardware spec. */
2256 ret_val
= init_inter_frame_gap_params(ug_info
->nonBackToBackIfgPart1
,
2257 ug_info
->nonBackToBackIfgPart2
,
2259 miminumInterFrameGapEnforcement
,
2260 ug_info
->backToBackInterFrameGap
,
2263 if (netif_msg_ifup(ugeth
))
2264 ugeth_err("%s: IPGIFG initialization parameter too large.",
2270 /* For more details see the hardware spec. */
2271 ret_val
= init_half_duplex_params(ug_info
->altBeb
,
2272 ug_info
->backPressureNoBackoff
,
2274 ug_info
->excessDefer
,
2275 ug_info
->altBebTruncation
,
2276 ug_info
->maxRetransmission
,
2277 ug_info
->collisionWindow
,
2280 if (netif_msg_ifup(ugeth
))
2281 ugeth_err("%s: Half Duplex initialization parameter too large.",
2287 /* For more details see the hardware spec. */
2288 /* Read only - resets upon read */
2289 ifstat
= in_be32(&ug_regs
->ifstat
);
2292 /* For more details see the hardware spec. */
2293 out_be32(&ug_regs
->uempr
, 0);
2296 /* For more details see the hardware spec. */
2297 init_hw_statistics_gathering_mode((ug_info
->statisticsMode
&
2298 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
),
2299 0, &uf_regs
->upsmr
, &ug_regs
->uescr
);
2301 /* Allocate Tx bds */
2302 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2303 /* Allocate in multiple of
2304 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2305 according to spec */
2306 length
= ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
))
2307 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2308 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2309 if ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)) %
2310 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2311 length
+= UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2312 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2314 if (UCC_GETH_TX_BD_RING_ALIGNMENT
> 4)
2315 align
= UCC_GETH_TX_BD_RING_ALIGNMENT
;
2316 ugeth
->tx_bd_ring_offset
[j
] =
2317 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2319 if (ugeth
->tx_bd_ring_offset
[j
] != 0)
2320 ugeth
->p_tx_bd_ring
[j
] =
2321 (u8 __iomem
*)((ugeth
->tx_bd_ring_offset
[j
] +
2322 align
) & ~(align
- 1));
2323 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2324 ugeth
->tx_bd_ring_offset
[j
] =
2325 qe_muram_alloc(length
,
2326 UCC_GETH_TX_BD_RING_ALIGNMENT
);
2327 if (!IS_ERR_VALUE(ugeth
->tx_bd_ring_offset
[j
]))
2328 ugeth
->p_tx_bd_ring
[j
] =
2329 (u8 __iomem
*) qe_muram_addr(ugeth
->
2330 tx_bd_ring_offset
[j
]);
2332 if (!ugeth
->p_tx_bd_ring
[j
]) {
2333 if (netif_msg_ifup(ugeth
))
2335 ("%s: Can not allocate memory for Tx bd rings.",
2339 /* Zero unused end of bd ring, according to spec */
2340 memset_io((void __iomem
*)(ugeth
->p_tx_bd_ring
[j
] +
2341 ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)), 0,
2342 length
- ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
));
2345 /* Allocate Rx bds */
2346 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2347 length
= ug_info
->bdRingLenRx
[j
] * sizeof(struct qe_bd
);
2348 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2350 if (UCC_GETH_RX_BD_RING_ALIGNMENT
> 4)
2351 align
= UCC_GETH_RX_BD_RING_ALIGNMENT
;
2352 ugeth
->rx_bd_ring_offset
[j
] =
2353 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2354 if (ugeth
->rx_bd_ring_offset
[j
] != 0)
2355 ugeth
->p_rx_bd_ring
[j
] =
2356 (u8 __iomem
*)((ugeth
->rx_bd_ring_offset
[j
] +
2357 align
) & ~(align
- 1));
2358 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2359 ugeth
->rx_bd_ring_offset
[j
] =
2360 qe_muram_alloc(length
,
2361 UCC_GETH_RX_BD_RING_ALIGNMENT
);
2362 if (!IS_ERR_VALUE(ugeth
->rx_bd_ring_offset
[j
]))
2363 ugeth
->p_rx_bd_ring
[j
] =
2364 (u8 __iomem
*) qe_muram_addr(ugeth
->
2365 rx_bd_ring_offset
[j
]);
2367 if (!ugeth
->p_rx_bd_ring
[j
]) {
2368 if (netif_msg_ifup(ugeth
))
2370 ("%s: Can not allocate memory for Rx bd rings.",
2377 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2378 /* Setup the skbuff rings */
2379 ugeth
->tx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2380 ugeth
->ug_info
->bdRingLenTx
[j
],
2383 if (ugeth
->tx_skbuff
[j
] == NULL
) {
2384 if (netif_msg_ifup(ugeth
))
2385 ugeth_err("%s: Could not allocate tx_skbuff",
2390 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenTx
[j
]; i
++)
2391 ugeth
->tx_skbuff
[j
][i
] = NULL
;
2393 ugeth
->skb_curtx
[j
] = ugeth
->skb_dirtytx
[j
] = 0;
2394 bd
= ugeth
->confBd
[j
] = ugeth
->txBd
[j
] = ugeth
->p_tx_bd_ring
[j
];
2395 for (i
= 0; i
< ug_info
->bdRingLenTx
[j
]; i
++) {
2396 /* clear bd buffer */
2397 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2398 /* set bd status and length */
2399 out_be32((u32 __iomem
*)bd
, 0);
2400 bd
+= sizeof(struct qe_bd
);
2402 bd
-= sizeof(struct qe_bd
);
2403 /* set bd status and length */
2404 out_be32((u32 __iomem
*)bd
, T_W
); /* for last BD set Wrap bit */
2408 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2409 /* Setup the skbuff rings */
2410 ugeth
->rx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2411 ugeth
->ug_info
->bdRingLenRx
[j
],
2414 if (ugeth
->rx_skbuff
[j
] == NULL
) {
2415 if (netif_msg_ifup(ugeth
))
2416 ugeth_err("%s: Could not allocate rx_skbuff",
2421 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenRx
[j
]; i
++)
2422 ugeth
->rx_skbuff
[j
][i
] = NULL
;
2424 ugeth
->skb_currx
[j
] = 0;
2425 bd
= ugeth
->rxBd
[j
] = ugeth
->p_rx_bd_ring
[j
];
2426 for (i
= 0; i
< ug_info
->bdRingLenRx
[j
]; i
++) {
2427 /* set bd status and length */
2428 out_be32((u32 __iomem
*)bd
, R_I
);
2429 /* clear bd buffer */
2430 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2431 bd
+= sizeof(struct qe_bd
);
2433 bd
-= sizeof(struct qe_bd
);
2434 /* set bd status and length */
2435 out_be32((u32 __iomem
*)bd
, R_W
); /* for last BD set Wrap bit */
2441 /* Tx global PRAM */
2442 /* Allocate global tx parameter RAM page */
2443 ugeth
->tx_glbl_pram_offset
=
2444 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram
),
2445 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
);
2446 if (IS_ERR_VALUE(ugeth
->tx_glbl_pram_offset
)) {
2447 if (netif_msg_ifup(ugeth
))
2449 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2453 ugeth
->p_tx_glbl_pram
=
2454 (struct ucc_geth_tx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2455 tx_glbl_pram_offset
);
2456 /* Zero out p_tx_glbl_pram */
2457 memset_io((void __iomem
*)ugeth
->p_tx_glbl_pram
, 0, sizeof(struct ucc_geth_tx_global_pram
));
2459 /* Fill global PRAM */
2462 /* Size varies with number of Tx threads */
2463 ugeth
->thread_dat_tx_offset
=
2464 qe_muram_alloc(numThreadsTxNumerical
*
2465 sizeof(struct ucc_geth_thread_data_tx
) +
2466 32 * (numThreadsTxNumerical
== 1),
2467 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2468 if (IS_ERR_VALUE(ugeth
->thread_dat_tx_offset
)) {
2469 if (netif_msg_ifup(ugeth
))
2471 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2476 ugeth
->p_thread_data_tx
=
2477 (struct ucc_geth_thread_data_tx __iomem
*) qe_muram_addr(ugeth
->
2478 thread_dat_tx_offset
);
2479 out_be32(&ugeth
->p_tx_glbl_pram
->tqptr
, ugeth
->thread_dat_tx_offset
);
2482 for (i
= 0; i
< UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
; i
++)
2483 out_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[i
],
2484 ug_info
->vtagtable
[i
]);
2487 for (i
= 0; i
< TX_IP_OFFSET_ENTRY_MAX
; i
++)
2488 out_8(&ugeth
->p_tx_glbl_pram
->iphoffset
[i
],
2489 ug_info
->iphoffset
[i
]);
2492 /* Size varies with number of Tx queues */
2493 ugeth
->send_q_mem_reg_offset
=
2494 qe_muram_alloc(ug_info
->numQueuesTx
*
2495 sizeof(struct ucc_geth_send_queue_qd
),
2496 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
2497 if (IS_ERR_VALUE(ugeth
->send_q_mem_reg_offset
)) {
2498 if (netif_msg_ifup(ugeth
))
2500 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2505 ugeth
->p_send_q_mem_reg
=
2506 (struct ucc_geth_send_queue_mem_region __iomem
*) qe_muram_addr(ugeth
->
2507 send_q_mem_reg_offset
);
2508 out_be32(&ugeth
->p_tx_glbl_pram
->sqptr
, ugeth
->send_q_mem_reg_offset
);
2510 /* Setup the table */
2511 /* Assume BD rings are already established */
2512 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2514 ugeth
->p_tx_bd_ring
[i
] + (ug_info
->bdRingLenTx
[i
] -
2515 1) * sizeof(struct qe_bd
);
2516 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2517 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2518 (u32
) virt_to_phys(ugeth
->p_tx_bd_ring
[i
]));
2519 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2520 last_bd_completed_address
,
2521 (u32
) virt_to_phys(endOfRing
));
2522 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2524 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2525 (u32
) immrbar_virt_to_phys(ugeth
->
2527 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2528 last_bd_completed_address
,
2529 (u32
) immrbar_virt_to_phys(endOfRing
));
2533 /* schedulerbasepointer */
2535 if (ug_info
->numQueuesTx
> 1) {
2536 /* scheduler exists only if more than 1 tx queue */
2537 ugeth
->scheduler_offset
=
2538 qe_muram_alloc(sizeof(struct ucc_geth_scheduler
),
2539 UCC_GETH_SCHEDULER_ALIGNMENT
);
2540 if (IS_ERR_VALUE(ugeth
->scheduler_offset
)) {
2541 if (netif_msg_ifup(ugeth
))
2543 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2548 ugeth
->p_scheduler
=
2549 (struct ucc_geth_scheduler __iomem
*) qe_muram_addr(ugeth
->
2551 out_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
2552 ugeth
->scheduler_offset
);
2553 /* Zero out p_scheduler */
2554 memset_io((void __iomem
*)ugeth
->p_scheduler
, 0, sizeof(struct ucc_geth_scheduler
));
2556 /* Set values in scheduler */
2557 out_be32(&ugeth
->p_scheduler
->mblinterval
,
2558 ug_info
->mblinterval
);
2559 out_be16(&ugeth
->p_scheduler
->nortsrbytetime
,
2560 ug_info
->nortsrbytetime
);
2561 out_8(&ugeth
->p_scheduler
->fracsiz
, ug_info
->fracsiz
);
2562 out_8(&ugeth
->p_scheduler
->strictpriorityq
,
2563 ug_info
->strictpriorityq
);
2564 out_8(&ugeth
->p_scheduler
->txasap
, ug_info
->txasap
);
2565 out_8(&ugeth
->p_scheduler
->extrabw
, ug_info
->extrabw
);
2566 for (i
= 0; i
< NUM_TX_QUEUES
; i
++)
2567 out_8(&ugeth
->p_scheduler
->weightfactor
[i
],
2568 ug_info
->weightfactor
[i
]);
2570 /* Set pointers to cpucount registers in scheduler */
2571 ugeth
->p_cpucount
[0] = &(ugeth
->p_scheduler
->cpucount0
);
2572 ugeth
->p_cpucount
[1] = &(ugeth
->p_scheduler
->cpucount1
);
2573 ugeth
->p_cpucount
[2] = &(ugeth
->p_scheduler
->cpucount2
);
2574 ugeth
->p_cpucount
[3] = &(ugeth
->p_scheduler
->cpucount3
);
2575 ugeth
->p_cpucount
[4] = &(ugeth
->p_scheduler
->cpucount4
);
2576 ugeth
->p_cpucount
[5] = &(ugeth
->p_scheduler
->cpucount5
);
2577 ugeth
->p_cpucount
[6] = &(ugeth
->p_scheduler
->cpucount6
);
2578 ugeth
->p_cpucount
[7] = &(ugeth
->p_scheduler
->cpucount7
);
2581 /* schedulerbasepointer */
2582 /* TxRMON_PTR (statistics) */
2584 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
) {
2585 ugeth
->tx_fw_statistics_pram_offset
=
2586 qe_muram_alloc(sizeof
2587 (struct ucc_geth_tx_firmware_statistics_pram
),
2588 UCC_GETH_TX_STATISTICS_ALIGNMENT
);
2589 if (IS_ERR_VALUE(ugeth
->tx_fw_statistics_pram_offset
)) {
2590 if (netif_msg_ifup(ugeth
))
2592 ("%s: Can not allocate DPRAM memory for"
2593 " p_tx_fw_statistics_pram.",
2597 ugeth
->p_tx_fw_statistics_pram
=
2598 (struct ucc_geth_tx_firmware_statistics_pram __iomem
*)
2599 qe_muram_addr(ugeth
->tx_fw_statistics_pram_offset
);
2600 /* Zero out p_tx_fw_statistics_pram */
2601 memset_io((void __iomem
*)ugeth
->p_tx_fw_statistics_pram
,
2602 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram
));
2606 /* Already has speed set */
2608 if (ug_info
->numQueuesTx
> 1)
2609 temoder
|= TEMODER_SCHEDULER_ENABLE
;
2610 if (ug_info
->ipCheckSumGenerate
)
2611 temoder
|= TEMODER_IP_CHECKSUM_GENERATE
;
2612 temoder
|= ((ug_info
->numQueuesTx
- 1) << TEMODER_NUM_OF_QUEUES_SHIFT
);
2613 out_be16(&ugeth
->p_tx_glbl_pram
->temoder
, temoder
);
2615 test
= in_be16(&ugeth
->p_tx_glbl_pram
->temoder
);
2617 /* Function code register value to be used later */
2618 function_code
= UCC_BMR_BO_BE
| UCC_BMR_GBL
;
2619 /* Required for QE */
2621 /* function code register */
2622 out_be32(&ugeth
->p_tx_glbl_pram
->tstate
, ((u32
) function_code
) << 24);
2624 /* Rx global PRAM */
2625 /* Allocate global rx parameter RAM page */
2626 ugeth
->rx_glbl_pram_offset
=
2627 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram
),
2628 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
);
2629 if (IS_ERR_VALUE(ugeth
->rx_glbl_pram_offset
)) {
2630 if (netif_msg_ifup(ugeth
))
2632 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2636 ugeth
->p_rx_glbl_pram
=
2637 (struct ucc_geth_rx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2638 rx_glbl_pram_offset
);
2639 /* Zero out p_rx_glbl_pram */
2640 memset_io((void __iomem
*)ugeth
->p_rx_glbl_pram
, 0, sizeof(struct ucc_geth_rx_global_pram
));
2642 /* Fill global PRAM */
2645 /* Size varies with number of Rx threads */
2646 ugeth
->thread_dat_rx_offset
=
2647 qe_muram_alloc(numThreadsRxNumerical
*
2648 sizeof(struct ucc_geth_thread_data_rx
),
2649 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2650 if (IS_ERR_VALUE(ugeth
->thread_dat_rx_offset
)) {
2651 if (netif_msg_ifup(ugeth
))
2653 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2658 ugeth
->p_thread_data_rx
=
2659 (struct ucc_geth_thread_data_rx __iomem
*) qe_muram_addr(ugeth
->
2660 thread_dat_rx_offset
);
2661 out_be32(&ugeth
->p_rx_glbl_pram
->rqptr
, ugeth
->thread_dat_rx_offset
);
2664 out_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
, ug_info
->typeorlen
);
2666 /* rxrmonbaseptr (statistics) */
2668 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
) {
2669 ugeth
->rx_fw_statistics_pram_offset
=
2670 qe_muram_alloc(sizeof
2671 (struct ucc_geth_rx_firmware_statistics_pram
),
2672 UCC_GETH_RX_STATISTICS_ALIGNMENT
);
2673 if (IS_ERR_VALUE(ugeth
->rx_fw_statistics_pram_offset
)) {
2674 if (netif_msg_ifup(ugeth
))
2676 ("%s: Can not allocate DPRAM memory for"
2677 " p_rx_fw_statistics_pram.", __func__
);
2680 ugeth
->p_rx_fw_statistics_pram
=
2681 (struct ucc_geth_rx_firmware_statistics_pram __iomem
*)
2682 qe_muram_addr(ugeth
->rx_fw_statistics_pram_offset
);
2683 /* Zero out p_rx_fw_statistics_pram */
2684 memset_io((void __iomem
*)ugeth
->p_rx_fw_statistics_pram
, 0,
2685 sizeof(struct ucc_geth_rx_firmware_statistics_pram
));
2688 /* intCoalescingPtr */
2690 /* Size varies with number of Rx queues */
2691 ugeth
->rx_irq_coalescing_tbl_offset
=
2692 qe_muram_alloc(ug_info
->numQueuesRx
*
2693 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry
)
2694 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
);
2695 if (IS_ERR_VALUE(ugeth
->rx_irq_coalescing_tbl_offset
)) {
2696 if (netif_msg_ifup(ugeth
))
2698 ("%s: Can not allocate DPRAM memory for"
2699 " p_rx_irq_coalescing_tbl.", __func__
);
2703 ugeth
->p_rx_irq_coalescing_tbl
=
2704 (struct ucc_geth_rx_interrupt_coalescing_table __iomem
*)
2705 qe_muram_addr(ugeth
->rx_irq_coalescing_tbl_offset
);
2706 out_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
2707 ugeth
->rx_irq_coalescing_tbl_offset
);
2709 /* Fill interrupt coalescing table */
2710 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2711 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2712 interruptcoalescingmaxvalue
,
2713 ug_info
->interruptcoalescingmaxvalue
[i
]);
2714 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2715 interruptcoalescingcounter
,
2716 ug_info
->interruptcoalescingmaxvalue
[i
]);
2720 init_max_rx_buff_len(uf_info
->max_rx_buf_length
,
2721 &ugeth
->p_rx_glbl_pram
->mrblr
);
2723 out_be16(&ugeth
->p_rx_glbl_pram
->mflr
, ug_info
->maxFrameLength
);
2725 init_min_frame_len(ug_info
->minFrameLength
,
2726 &ugeth
->p_rx_glbl_pram
->minflr
,
2727 &ugeth
->p_rx_glbl_pram
->mrblr
);
2729 out_be16(&ugeth
->p_rx_glbl_pram
->maxd1
, ug_info
->maxD1Length
);
2731 out_be16(&ugeth
->p_rx_glbl_pram
->maxd2
, ug_info
->maxD2Length
);
2735 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++)
2736 l2qt
|= (ug_info
->l2qt
[i
] << (28 - 4 * i
));
2737 out_be32(&ugeth
->p_rx_glbl_pram
->l2qt
, l2qt
);
2740 for (j
= 0; j
< UCC_GETH_IP_PRIORITY_MAX
; j
+= 8) {
2742 for (i
= 0; i
< 8; i
++)
2743 l3qt
|= (ug_info
->l3qt
[j
+ i
] << (28 - 4 * i
));
2744 out_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[j
/8], l3qt
);
2748 out_be16(&ugeth
->p_rx_glbl_pram
->vlantype
, ug_info
->vlantype
);
2751 out_be16(&ugeth
->p_rx_glbl_pram
->vlantci
, ug_info
->vlantci
);
2754 out_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
, ug_info
->ecamptr
);
2757 /* Size varies with number of Rx queues */
2758 ugeth
->rx_bd_qs_tbl_offset
=
2759 qe_muram_alloc(ug_info
->numQueuesRx
*
2760 (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2761 sizeof(struct ucc_geth_rx_prefetched_bds
)),
2762 UCC_GETH_RX_BD_QUEUES_ALIGNMENT
);
2763 if (IS_ERR_VALUE(ugeth
->rx_bd_qs_tbl_offset
)) {
2764 if (netif_msg_ifup(ugeth
))
2766 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2771 ugeth
->p_rx_bd_qs_tbl
=
2772 (struct ucc_geth_rx_bd_queues_entry __iomem
*) qe_muram_addr(ugeth
->
2773 rx_bd_qs_tbl_offset
);
2774 out_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
, ugeth
->rx_bd_qs_tbl_offset
);
2775 /* Zero out p_rx_bd_qs_tbl */
2776 memset_io((void __iomem
*)ugeth
->p_rx_bd_qs_tbl
,
2778 ug_info
->numQueuesRx
* (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2779 sizeof(struct ucc_geth_rx_prefetched_bds
)));
2781 /* Setup the table */
2782 /* Assume BD rings are already established */
2783 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2784 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2785 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2786 (u32
) virt_to_phys(ugeth
->p_rx_bd_ring
[i
]));
2787 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2789 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2790 (u32
) immrbar_virt_to_phys(ugeth
->
2793 /* rest of fields handled by QE */
2797 /* Already has speed set */
2799 if (ugeth
->rx_extended_features
)
2800 remoder
|= REMODER_RX_EXTENDED_FEATURES
;
2801 if (ug_info
->rxExtendedFiltering
)
2802 remoder
|= REMODER_RX_EXTENDED_FILTERING
;
2803 if (ug_info
->dynamicMaxFrameLength
)
2804 remoder
|= REMODER_DYNAMIC_MAX_FRAME_LENGTH
;
2805 if (ug_info
->dynamicMinFrameLength
)
2806 remoder
|= REMODER_DYNAMIC_MIN_FRAME_LENGTH
;
2808 ug_info
->vlanOperationTagged
<< REMODER_VLAN_OPERATION_TAGGED_SHIFT
;
2811 vlanOperationNonTagged
<< REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
;
2812 remoder
|= ug_info
->rxQoSMode
<< REMODER_RX_QOS_MODE_SHIFT
;
2813 remoder
|= ((ug_info
->numQueuesRx
- 1) << REMODER_NUM_OF_QUEUES_SHIFT
);
2814 if (ug_info
->ipCheckSumCheck
)
2815 remoder
|= REMODER_IP_CHECKSUM_CHECK
;
2816 if (ug_info
->ipAddressAlignment
)
2817 remoder
|= REMODER_IP_ADDRESS_ALIGNMENT
;
2818 out_be32(&ugeth
->p_rx_glbl_pram
->remoder
, remoder
);
2820 /* Note that this function must be called */
2821 /* ONLY AFTER p_tx_fw_statistics_pram */
2822 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2823 init_firmware_statistics_gathering_mode((ug_info
->
2825 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
),
2826 (ug_info
->statisticsMode
&
2827 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
),
2828 &ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
2829 ugeth
->tx_fw_statistics_pram_offset
,
2830 &ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
2831 ugeth
->rx_fw_statistics_pram_offset
,
2832 &ugeth
->p_tx_glbl_pram
->temoder
,
2833 &ugeth
->p_rx_glbl_pram
->remoder
);
2835 /* function code register */
2836 out_8(&ugeth
->p_rx_glbl_pram
->rstate
, function_code
);
2838 /* initialize extended filtering */
2839 if (ug_info
->rxExtendedFiltering
) {
2840 if (!ug_info
->extendedFilteringChainPointer
) {
2841 if (netif_msg_ifup(ugeth
))
2842 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2847 /* Allocate memory for extended filtering Mode Global
2849 ugeth
->exf_glbl_param_offset
=
2850 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram
),
2851 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
);
2852 if (IS_ERR_VALUE(ugeth
->exf_glbl_param_offset
)) {
2853 if (netif_msg_ifup(ugeth
))
2855 ("%s: Can not allocate DPRAM memory for"
2856 " p_exf_glbl_param.", __func__
);
2860 ugeth
->p_exf_glbl_param
=
2861 (struct ucc_geth_exf_global_pram __iomem
*) qe_muram_addr(ugeth
->
2862 exf_glbl_param_offset
);
2863 out_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
2864 ugeth
->exf_glbl_param_offset
);
2865 out_be32(&ugeth
->p_exf_glbl_param
->l2pcdptr
,
2866 (u32
) ug_info
->extendedFilteringChainPointer
);
2868 } else { /* initialize 82xx style address filtering */
2870 /* Init individual address recognition registers to disabled */
2872 for (j
= 0; j
< NUM_OF_PADDRS
; j
++)
2873 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth
, (u8
) j
);
2876 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
2877 p_rx_glbl_pram
->addressfiltering
;
2879 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2880 ENET_ADDR_TYPE_GROUP
);
2881 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2882 ENET_ADDR_TYPE_INDIVIDUAL
);
2886 * Initialize UCC at QE level
2889 command
= QE_INIT_TX_RX
;
2891 /* Allocate shadow InitEnet command parameter structure.
2892 * This is needed because after the InitEnet command is executed,
2893 * the structure in DPRAM is released, because DPRAM is a premium
2895 * This shadow structure keeps a copy of what was done so that the
2896 * allocated resources can be released when the channel is freed.
2898 if (!(ugeth
->p_init_enet_param_shadow
=
2899 kmalloc(sizeof(struct ucc_geth_init_pram
), GFP_KERNEL
))) {
2900 if (netif_msg_ifup(ugeth
))
2902 ("%s: Can not allocate memory for"
2903 " p_UccInitEnetParamShadows.", __func__
);
2906 /* Zero out *p_init_enet_param_shadow */
2907 memset((char *)ugeth
->p_init_enet_param_shadow
,
2908 0, sizeof(struct ucc_geth_init_pram
));
2910 /* Fill shadow InitEnet command parameter structure */
2912 ugeth
->p_init_enet_param_shadow
->resinit1
=
2913 ENET_INIT_PARAM_MAGIC_RES_INIT1
;
2914 ugeth
->p_init_enet_param_shadow
->resinit2
=
2915 ENET_INIT_PARAM_MAGIC_RES_INIT2
;
2916 ugeth
->p_init_enet_param_shadow
->resinit3
=
2917 ENET_INIT_PARAM_MAGIC_RES_INIT3
;
2918 ugeth
->p_init_enet_param_shadow
->resinit4
=
2919 ENET_INIT_PARAM_MAGIC_RES_INIT4
;
2920 ugeth
->p_init_enet_param_shadow
->resinit5
=
2921 ENET_INIT_PARAM_MAGIC_RES_INIT5
;
2922 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2923 ((u32
) ug_info
->numThreadsRx
) << ENET_INIT_PARAM_RGF_SHIFT
;
2924 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2925 ((u32
) ug_info
->numThreadsTx
) << ENET_INIT_PARAM_TGF_SHIFT
;
2927 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2928 ugeth
->rx_glbl_pram_offset
| ug_info
->riscRx
;
2929 if ((ug_info
->largestexternallookupkeysize
!=
2930 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
)
2931 && (ug_info
->largestexternallookupkeysize
!=
2932 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2933 && (ug_info
->largestexternallookupkeysize
!=
2934 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)) {
2935 if (netif_msg_ifup(ugeth
))
2936 ugeth_err("%s: Invalid largest External Lookup Key Size.",
2940 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
=
2941 ug_info
->largestexternallookupkeysize
;
2942 size
= sizeof(struct ucc_geth_thread_rx_pram
);
2943 if (ug_info
->rxExtendedFiltering
) {
2944 size
+= THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
2945 if (ug_info
->largestexternallookupkeysize
==
2946 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2948 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
2949 if (ug_info
->largestexternallookupkeysize
==
2950 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
2952 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
2955 if ((ret_val
= fill_init_enet_entries(ugeth
, &(ugeth
->
2956 p_init_enet_param_shadow
->rxthread
[0]),
2957 (u8
) (numThreadsRxNumerical
+ 1)
2958 /* Rx needs one extra for terminator */
2959 , size
, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
,
2960 ug_info
->riscRx
, 1)) != 0) {
2961 if (netif_msg_ifup(ugeth
))
2962 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2967 ugeth
->p_init_enet_param_shadow
->txglobal
=
2968 ugeth
->tx_glbl_pram_offset
| ug_info
->riscTx
;
2970 fill_init_enet_entries(ugeth
,
2971 &(ugeth
->p_init_enet_param_shadow
->
2972 txthread
[0]), numThreadsTxNumerical
,
2973 sizeof(struct ucc_geth_thread_tx_pram
),
2974 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
,
2975 ug_info
->riscTx
, 0)) != 0) {
2976 if (netif_msg_ifup(ugeth
))
2977 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2982 /* Load Rx bds with buffers */
2983 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2984 if ((ret_val
= rx_bd_buffer_set(ugeth
, (u8
) i
)) != 0) {
2985 if (netif_msg_ifup(ugeth
))
2986 ugeth_err("%s: Can not fill Rx bds with buffers.",
2992 /* Allocate InitEnet command parameter structure */
2993 init_enet_pram_offset
= qe_muram_alloc(sizeof(struct ucc_geth_init_pram
), 4);
2994 if (IS_ERR_VALUE(init_enet_pram_offset
)) {
2995 if (netif_msg_ifup(ugeth
))
2997 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3002 (struct ucc_geth_init_pram __iomem
*) qe_muram_addr(init_enet_pram_offset
);
3004 /* Copy shadow InitEnet command parameter structure into PRAM */
3005 out_8(&p_init_enet_pram
->resinit1
,
3006 ugeth
->p_init_enet_param_shadow
->resinit1
);
3007 out_8(&p_init_enet_pram
->resinit2
,
3008 ugeth
->p_init_enet_param_shadow
->resinit2
);
3009 out_8(&p_init_enet_pram
->resinit3
,
3010 ugeth
->p_init_enet_param_shadow
->resinit3
);
3011 out_8(&p_init_enet_pram
->resinit4
,
3012 ugeth
->p_init_enet_param_shadow
->resinit4
);
3013 out_be16(&p_init_enet_pram
->resinit5
,
3014 ugeth
->p_init_enet_param_shadow
->resinit5
);
3015 out_8(&p_init_enet_pram
->largestexternallookupkeysize
,
3016 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
);
3017 out_be32(&p_init_enet_pram
->rgftgfrxglobal
,
3018 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
);
3019 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_RX
; i
++)
3020 out_be32(&p_init_enet_pram
->rxthread
[i
],
3021 ugeth
->p_init_enet_param_shadow
->rxthread
[i
]);
3022 out_be32(&p_init_enet_pram
->txglobal
,
3023 ugeth
->p_init_enet_param_shadow
->txglobal
);
3024 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_TX
; i
++)
3025 out_be32(&p_init_enet_pram
->txthread
[i
],
3026 ugeth
->p_init_enet_param_shadow
->txthread
[i
]);
3028 /* Issue QE command */
3030 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
3031 qe_issue_cmd(command
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
3032 init_enet_pram_offset
);
3034 /* Free InitEnet command parameter */
3035 qe_muram_free(init_enet_pram_offset
);
3040 /* This is called by the kernel when a frame is ready for transmission. */
3041 /* It is pointed to by the dev->hard_start_xmit function pointer */
3042 static int ucc_geth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3044 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3045 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3046 struct ucc_fast_private
*uccf
;
3048 u8 __iomem
*bd
; /* BD pointer */
3052 ugeth_vdbg("%s: IN", __func__
);
3054 spin_lock_irq(&ugeth
->lock
);
3056 dev
->stats
.tx_bytes
+= skb
->len
;
3058 /* Start from the next BD that should be filled */
3059 bd
= ugeth
->txBd
[txQ
];
3060 bd_status
= in_be32((u32 __iomem
*)bd
);
3061 /* Save the skb pointer so we can free it later */
3062 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_curtx
[txQ
]] = skb
;
3064 /* Update the current skb pointer (wrapping if this was the last) */
3065 ugeth
->skb_curtx
[txQ
] =
3066 (ugeth
->skb_curtx
[txQ
] +
3067 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3069 /* set up the buffer descriptor */
3070 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
3071 dma_map_single(&ugeth
->dev
->dev
, skb
->data
,
3072 skb
->len
, DMA_TO_DEVICE
));
3074 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3076 bd_status
= (bd_status
& T_W
) | T_R
| T_I
| T_L
| skb
->len
;
3078 /* set bd status and length */
3079 out_be32((u32 __iomem
*)bd
, bd_status
);
3081 dev
->trans_start
= jiffies
;
3083 /* Move to next BD in the ring */
3084 if (!(bd_status
& T_W
))
3085 bd
+= sizeof(struct qe_bd
);
3087 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3089 /* If the next BD still needs to be cleaned up, then the bds
3090 are full. We need to tell the kernel to stop sending us stuff. */
3091 if (bd
== ugeth
->confBd
[txQ
]) {
3092 if (!netif_queue_stopped(dev
))
3093 netif_stop_queue(dev
);
3096 ugeth
->txBd
[txQ
] = bd
;
3098 if (ugeth
->p_scheduler
) {
3099 ugeth
->cpucount
[txQ
]++;
3100 /* Indicate to QE that there are more Tx bds ready for
3102 /* This is done by writing a running counter of the bd
3103 count to the scheduler PRAM. */
3104 out_be16(ugeth
->p_cpucount
[txQ
], ugeth
->cpucount
[txQ
]);
3107 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3109 out_be16(uccf
->p_utodr
, UCC_FAST_TOD
);
3111 spin_unlock_irq(&ugeth
->lock
);
3116 static int ucc_geth_rx(struct ucc_geth_private
*ugeth
, u8 rxQ
, int rx_work_limit
)
3118 struct sk_buff
*skb
;
3120 u16 length
, howmany
= 0;
3123 struct net_device
*dev
;
3125 ugeth_vdbg("%s: IN", __func__
);
3129 /* collect received buffers */
3130 bd
= ugeth
->rxBd
[rxQ
];
3132 bd_status
= in_be32((u32 __iomem
*)bd
);
3134 /* while there are received buffers and BD is full (~R_E) */
3135 while (!((bd_status
& (R_E
)) || (--rx_work_limit
< 0))) {
3136 bdBuffer
= (u8
*) in_be32(&((struct qe_bd __iomem
*)bd
)->buf
);
3137 length
= (u16
) ((bd_status
& BD_LENGTH_MASK
) - 4);
3138 skb
= ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]];
3140 /* determine whether buffer is first, last, first and last
3141 (single buffer frame) or middle (not first and not last) */
3143 (!(bd_status
& (R_F
| R_L
))) ||
3144 (bd_status
& R_ERRORS_FATAL
)) {
3145 if (netif_msg_rx_err(ugeth
))
3146 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3147 __func__
, __LINE__
, (u32
) skb
);
3149 dev_kfree_skb_any(skb
);
3151 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = NULL
;
3152 dev
->stats
.rx_dropped
++;
3154 dev
->stats
.rx_packets
++;
3157 /* Prep the skb for the packet */
3158 skb_put(skb
, length
);
3160 /* Tell the skb what kind of packet this is */
3161 skb
->protocol
= eth_type_trans(skb
, ugeth
->dev
);
3163 dev
->stats
.rx_bytes
+= length
;
3164 /* Send the packet up the stack */
3165 netif_receive_skb(skb
);
3168 skb
= get_new_skb(ugeth
, bd
);
3170 if (netif_msg_rx_err(ugeth
))
3171 ugeth_warn("%s: No Rx Data Buffer", __func__
);
3172 dev
->stats
.rx_dropped
++;
3176 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = skb
;
3178 /* update to point at the next skb */
3179 ugeth
->skb_currx
[rxQ
] =
3180 (ugeth
->skb_currx
[rxQ
] +
3181 1) & RX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenRx
[rxQ
]);
3183 if (bd_status
& R_W
)
3184 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
3186 bd
+= sizeof(struct qe_bd
);
3188 bd_status
= in_be32((u32 __iomem
*)bd
);
3191 ugeth
->rxBd
[rxQ
] = bd
;
3195 static int ucc_geth_tx(struct net_device
*dev
, u8 txQ
)
3197 /* Start from the next BD that should be filled */
3198 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3199 u8 __iomem
*bd
; /* BD pointer */
3202 bd
= ugeth
->confBd
[txQ
];
3203 bd_status
= in_be32((u32 __iomem
*)bd
);
3205 /* Normal processing. */
3206 while ((bd_status
& T_R
) == 0) {
3207 /* BD contains already transmitted buffer. */
3208 /* Handle the transmitted buffer and release */
3209 /* the BD to be used with the current frame */
3211 if ((bd
== ugeth
->txBd
[txQ
]) && (netif_queue_stopped(dev
) == 0))
3214 dev
->stats
.tx_packets
++;
3216 /* Free the sk buffer associated with this TxBD */
3217 dev_kfree_skb_irq(ugeth
->
3218 tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]]);
3219 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]] = NULL
;
3220 ugeth
->skb_dirtytx
[txQ
] =
3221 (ugeth
->skb_dirtytx
[txQ
] +
3222 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3224 /* We freed a buffer, so now we can restart transmission */
3225 if (netif_queue_stopped(dev
))
3226 netif_wake_queue(dev
);
3228 /* Advance the confirmation BD pointer */
3229 if (!(bd_status
& T_W
))
3230 bd
+= sizeof(struct qe_bd
);
3232 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3233 bd_status
= in_be32((u32 __iomem
*)bd
);
3235 ugeth
->confBd
[txQ
] = bd
;
3239 static int ucc_geth_poll(struct napi_struct
*napi
, int budget
)
3241 struct ucc_geth_private
*ugeth
= container_of(napi
, struct ucc_geth_private
, napi
);
3242 struct ucc_geth_info
*ug_info
;
3245 ug_info
= ugeth
->ug_info
;
3248 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
3249 howmany
+= ucc_geth_rx(ugeth
, i
, budget
- howmany
);
3251 if (howmany
< budget
) {
3252 netif_rx_complete(napi
);
3253 setbits32(ugeth
->uccf
->p_uccm
, UCCE_RX_EVENTS
);
3259 static irqreturn_t
ucc_geth_irq_handler(int irq
, void *info
)
3261 struct net_device
*dev
= info
;
3262 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3263 struct ucc_fast_private
*uccf
;
3264 struct ucc_geth_info
*ug_info
;
3267 register u32 tx_mask
;
3270 ugeth_vdbg("%s: IN", __func__
);
3273 ug_info
= ugeth
->ug_info
;
3275 /* read and clear events */
3276 ucce
= (u32
) in_be32(uccf
->p_ucce
);
3277 uccm
= (u32
) in_be32(uccf
->p_uccm
);
3279 out_be32(uccf
->p_ucce
, ucce
);
3281 /* check for receive events that require processing */
3282 if (ucce
& UCCE_RX_EVENTS
) {
3283 if (netif_rx_schedule_prep(&ugeth
->napi
)) {
3284 uccm
&= ~UCCE_RX_EVENTS
;
3285 out_be32(uccf
->p_uccm
, uccm
);
3286 __netif_rx_schedule(&ugeth
->napi
);
3290 /* Tx event processing */
3291 if (ucce
& UCCE_TX_EVENTS
) {
3292 spin_lock(&ugeth
->lock
);
3293 tx_mask
= UCC_GETH_UCCE_TXB0
;
3294 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
3296 ucc_geth_tx(dev
, i
);
3300 spin_unlock(&ugeth
->lock
);
3303 /* Errors and other events */
3304 if (ucce
& UCCE_OTHER
) {
3305 if (ucce
& UCC_GETH_UCCE_BSY
)
3306 dev
->stats
.rx_errors
++;
3307 if (ucce
& UCC_GETH_UCCE_TXE
)
3308 dev
->stats
.tx_errors
++;
3314 #ifdef CONFIG_NET_POLL_CONTROLLER
3316 * Polling 'interrupt' - used by things like netconsole to send skbs
3317 * without having to re-enable interrupts. It's not called while
3318 * the interrupt routine is executing.
3320 static void ucc_netpoll(struct net_device
*dev
)
3322 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3323 int irq
= ugeth
->ug_info
->uf_info
.irq
;
3326 ucc_geth_irq_handler(irq
, dev
);
3329 #endif /* CONFIG_NET_POLL_CONTROLLER */
3331 /* Called when something needs to use the ethernet device */
3332 /* Returns 0 for success. */
3333 static int ucc_geth_open(struct net_device
*dev
)
3335 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3338 ugeth_vdbg("%s: IN", __func__
);
3340 /* Test station address */
3341 if (dev
->dev_addr
[0] & ENET_GROUP_ADDR
) {
3342 if (netif_msg_ifup(ugeth
))
3343 ugeth_err("%s: Multicast address used for station address"
3344 " - is this what you wanted?", __func__
);
3348 err
= ucc_struct_init(ugeth
);
3350 if (netif_msg_ifup(ugeth
))
3351 ugeth_err("%s: Cannot configure internal struct, aborting.", dev
->name
);
3355 napi_enable(&ugeth
->napi
);
3357 err
= ucc_geth_startup(ugeth
);
3359 if (netif_msg_ifup(ugeth
))
3360 ugeth_err("%s: Cannot configure net device, aborting.",
3365 err
= adjust_enet_interface(ugeth
);
3367 if (netif_msg_ifup(ugeth
))
3368 ugeth_err("%s: Cannot configure net device, aborting.",
3373 /* Set MACSTNADDR1, MACSTNADDR2 */
3374 /* For more details see the hardware spec. */
3375 init_mac_station_addr_regs(dev
->dev_addr
[0],
3381 &ugeth
->ug_regs
->macstnaddr1
,
3382 &ugeth
->ug_regs
->macstnaddr2
);
3384 err
= init_phy(dev
);
3386 if (netif_msg_ifup(ugeth
))
3387 ugeth_err("%s: Cannot initialize PHY, aborting.", dev
->name
);
3391 phy_start(ugeth
->phydev
);
3393 err
= ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
3395 if (netif_msg_ifup(ugeth
))
3396 ugeth_err("%s: Cannot enable net device, aborting.", dev
->name
);
3400 err
= request_irq(ugeth
->ug_info
->uf_info
.irq
, ucc_geth_irq_handler
,
3401 0, "UCC Geth", dev
);
3403 if (netif_msg_ifup(ugeth
))
3404 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3409 netif_start_queue(dev
);
3414 napi_disable(&ugeth
->napi
);
3416 ucc_geth_stop(ugeth
);
3420 /* Stops the kernel queue, and halts the controller */
3421 static int ucc_geth_close(struct net_device
*dev
)
3423 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3425 ugeth_vdbg("%s: IN", __func__
);
3427 napi_disable(&ugeth
->napi
);
3429 ucc_geth_stop(ugeth
);
3431 free_irq(ugeth
->ug_info
->uf_info
.irq
, ugeth
->dev
);
3433 phy_disconnect(ugeth
->phydev
);
3434 ugeth
->phydev
= NULL
;
3436 netif_stop_queue(dev
);
3441 /* Reopen device. This will reset the MAC and PHY. */
3442 static void ucc_geth_timeout_work(struct work_struct
*work
)
3444 struct ucc_geth_private
*ugeth
;
3445 struct net_device
*dev
;
3447 ugeth
= container_of(work
, struct ucc_geth_private
, timeout_work
);
3450 ugeth_vdbg("%s: IN", __func__
);
3452 dev
->stats
.tx_errors
++;
3454 ugeth_dump_regs(ugeth
);
3456 if (dev
->flags
& IFF_UP
) {
3458 * Must reset MAC *and* PHY. This is done by reopening
3461 ucc_geth_close(dev
);
3465 netif_tx_schedule_all(dev
);
3469 * ucc_geth_timeout gets called when a packet has not been
3470 * transmitted after a set amount of time.
3472 static void ucc_geth_timeout(struct net_device
*dev
)
3474 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3476 netif_carrier_off(dev
);
3477 schedule_work(&ugeth
->timeout_work
);
3480 static phy_interface_t
to_phy_interface(const char *phy_connection_type
)
3482 if (strcasecmp(phy_connection_type
, "mii") == 0)
3483 return PHY_INTERFACE_MODE_MII
;
3484 if (strcasecmp(phy_connection_type
, "gmii") == 0)
3485 return PHY_INTERFACE_MODE_GMII
;
3486 if (strcasecmp(phy_connection_type
, "tbi") == 0)
3487 return PHY_INTERFACE_MODE_TBI
;
3488 if (strcasecmp(phy_connection_type
, "rmii") == 0)
3489 return PHY_INTERFACE_MODE_RMII
;
3490 if (strcasecmp(phy_connection_type
, "rgmii") == 0)
3491 return PHY_INTERFACE_MODE_RGMII
;
3492 if (strcasecmp(phy_connection_type
, "rgmii-id") == 0)
3493 return PHY_INTERFACE_MODE_RGMII_ID
;
3494 if (strcasecmp(phy_connection_type
, "rgmii-txid") == 0)
3495 return PHY_INTERFACE_MODE_RGMII_TXID
;
3496 if (strcasecmp(phy_connection_type
, "rgmii-rxid") == 0)
3497 return PHY_INTERFACE_MODE_RGMII_RXID
;
3498 if (strcasecmp(phy_connection_type
, "rtbi") == 0)
3499 return PHY_INTERFACE_MODE_RTBI
;
3501 return PHY_INTERFACE_MODE_MII
;
3504 static int ucc_geth_probe(struct of_device
* ofdev
, const struct of_device_id
*match
)
3506 struct device
*device
= &ofdev
->dev
;
3507 struct device_node
*np
= ofdev
->node
;
3508 struct device_node
*mdio
;
3509 struct net_device
*dev
= NULL
;
3510 struct ucc_geth_private
*ugeth
= NULL
;
3511 struct ucc_geth_info
*ug_info
;
3512 struct resource res
;
3513 struct device_node
*phy
;
3514 int err
, ucc_num
, max_speed
= 0;
3516 const u32
*fixed_link
;
3517 const unsigned int *prop
;
3519 const void *mac_addr
;
3520 phy_interface_t phy_interface
;
3521 static const int enet_to_speed
[] = {
3522 SPEED_10
, SPEED_10
, SPEED_10
,
3523 SPEED_100
, SPEED_100
, SPEED_100
,
3524 SPEED_1000
, SPEED_1000
, SPEED_1000
, SPEED_1000
,
3526 static const phy_interface_t enet_to_phy_interface
[] = {
3527 PHY_INTERFACE_MODE_MII
, PHY_INTERFACE_MODE_RMII
,
3528 PHY_INTERFACE_MODE_RGMII
, PHY_INTERFACE_MODE_MII
,
3529 PHY_INTERFACE_MODE_RMII
, PHY_INTERFACE_MODE_RGMII
,
3530 PHY_INTERFACE_MODE_GMII
, PHY_INTERFACE_MODE_RGMII
,
3531 PHY_INTERFACE_MODE_TBI
, PHY_INTERFACE_MODE_RTBI
,
3534 ugeth_vdbg("%s: IN", __func__
);
3536 prop
= of_get_property(np
, "cell-index", NULL
);
3538 prop
= of_get_property(np
, "device-id", NULL
);
3543 ucc_num
= *prop
- 1;
3544 if ((ucc_num
< 0) || (ucc_num
> 7))
3547 ug_info
= &ugeth_info
[ucc_num
];
3548 if (ug_info
== NULL
) {
3549 if (netif_msg_probe(&debug
))
3550 ugeth_err("%s: [%d] Missing additional data!",
3555 ug_info
->uf_info
.ucc_num
= ucc_num
;
3557 sprop
= of_get_property(np
, "rx-clock-name", NULL
);
3559 ug_info
->uf_info
.rx_clock
= qe_clock_source(sprop
);
3560 if ((ug_info
->uf_info
.rx_clock
< QE_CLK_NONE
) ||
3561 (ug_info
->uf_info
.rx_clock
> QE_CLK24
)) {
3563 "ucc_geth: invalid rx-clock-name property\n");
3567 prop
= of_get_property(np
, "rx-clock", NULL
);
3569 /* If both rx-clock-name and rx-clock are missing,
3570 we want to tell people to use rx-clock-name. */
3572 "ucc_geth: missing rx-clock-name property\n");
3575 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3577 "ucc_geth: invalid rx-clock propperty\n");
3580 ug_info
->uf_info
.rx_clock
= *prop
;
3583 sprop
= of_get_property(np
, "tx-clock-name", NULL
);
3585 ug_info
->uf_info
.tx_clock
= qe_clock_source(sprop
);
3586 if ((ug_info
->uf_info
.tx_clock
< QE_CLK_NONE
) ||
3587 (ug_info
->uf_info
.tx_clock
> QE_CLK24
)) {
3589 "ucc_geth: invalid tx-clock-name property\n");
3593 prop
= of_get_property(np
, "tx-clock", NULL
);
3596 "ucc_geth: mising tx-clock-name property\n");
3599 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3601 "ucc_geth: invalid tx-clock property\n");
3604 ug_info
->uf_info
.tx_clock
= *prop
;
3607 err
= of_address_to_resource(np
, 0, &res
);
3611 ug_info
->uf_info
.regs
= res
.start
;
3612 ug_info
->uf_info
.irq
= irq_of_parse_and_map(np
, 0);
3613 fixed_link
= of_get_property(np
, "fixed-link", NULL
);
3615 snprintf(ug_info
->phy_bus_id
, sizeof(ug_info
->phy_bus_id
),
3616 PHY_ID_FMT
, "0", fixed_link
[0]);
3619 char bus_name
[MII_BUS_ID_SIZE
];
3621 ph
= of_get_property(np
, "phy-handle", NULL
);
3622 phy
= of_find_node_by_phandle(*ph
);
3627 /* set the PHY address */
3628 prop
= of_get_property(phy
, "reg", NULL
);
3632 /* Set the bus id */
3633 mdio
= of_get_parent(phy
);
3638 err
= of_address_to_resource(mdio
, 0, &res
);
3644 uec_mdio_bus_name(bus_name
, mdio
);
3645 snprintf(ug_info
->phy_bus_id
, sizeof(ug_info
->phy_bus_id
),
3646 "%s:%02x", bus_name
, *prop
);
3649 /* get the phy interface type, or default to MII */
3650 prop
= of_get_property(np
, "phy-connection-type", NULL
);
3652 /* handle interface property present in old trees */
3653 prop
= of_get_property(phy
, "interface", NULL
);
3655 phy_interface
= enet_to_phy_interface
[*prop
];
3656 max_speed
= enet_to_speed
[*prop
];
3658 phy_interface
= PHY_INTERFACE_MODE_MII
;
3660 phy_interface
= to_phy_interface((const char *)prop
);
3663 /* get speed, or derive from PHY interface */
3665 switch (phy_interface
) {
3666 case PHY_INTERFACE_MODE_GMII
:
3667 case PHY_INTERFACE_MODE_RGMII
:
3668 case PHY_INTERFACE_MODE_RGMII_ID
:
3669 case PHY_INTERFACE_MODE_RGMII_RXID
:
3670 case PHY_INTERFACE_MODE_RGMII_TXID
:
3671 case PHY_INTERFACE_MODE_TBI
:
3672 case PHY_INTERFACE_MODE_RTBI
:
3673 max_speed
= SPEED_1000
;
3676 max_speed
= SPEED_100
;
3680 if (max_speed
== SPEED_1000
) {
3681 /* configure muram FIFOs for gigabit operation */
3682 ug_info
->uf_info
.urfs
= UCC_GETH_URFS_GIGA_INIT
;
3683 ug_info
->uf_info
.urfet
= UCC_GETH_URFET_GIGA_INIT
;
3684 ug_info
->uf_info
.urfset
= UCC_GETH_URFSET_GIGA_INIT
;
3685 ug_info
->uf_info
.utfs
= UCC_GETH_UTFS_GIGA_INIT
;
3686 ug_info
->uf_info
.utfet
= UCC_GETH_UTFET_GIGA_INIT
;
3687 ug_info
->uf_info
.utftt
= UCC_GETH_UTFTT_GIGA_INIT
;
3688 ug_info
->numThreadsTx
= UCC_GETH_NUM_OF_THREADS_4
;
3689 ug_info
->numThreadsRx
= UCC_GETH_NUM_OF_THREADS_4
;
3692 if (netif_msg_probe(&debug
))
3693 printk(KERN_INFO
"ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3694 ug_info
->uf_info
.ucc_num
+ 1, ug_info
->uf_info
.regs
,
3695 ug_info
->uf_info
.irq
);
3697 /* Create an ethernet device instance */
3698 dev
= alloc_etherdev(sizeof(*ugeth
));
3703 ugeth
= netdev_priv(dev
);
3704 spin_lock_init(&ugeth
->lock
);
3706 /* Create CQs for hash tables */
3707 INIT_LIST_HEAD(&ugeth
->group_hash_q
);
3708 INIT_LIST_HEAD(&ugeth
->ind_hash_q
);
3710 dev_set_drvdata(device
, dev
);
3712 /* Set the dev->base_addr to the gfar reg region */
3713 dev
->base_addr
= (unsigned long)(ug_info
->uf_info
.regs
);
3715 SET_NETDEV_DEV(dev
, device
);
3717 /* Fill in the dev structure */
3718 uec_set_ethtool_ops(dev
);
3719 dev
->open
= ucc_geth_open
;
3720 dev
->hard_start_xmit
= ucc_geth_start_xmit
;
3721 dev
->tx_timeout
= ucc_geth_timeout
;
3722 dev
->watchdog_timeo
= TX_TIMEOUT
;
3723 INIT_WORK(&ugeth
->timeout_work
, ucc_geth_timeout_work
);
3724 netif_napi_add(dev
, &ugeth
->napi
, ucc_geth_poll
, UCC_GETH_DEV_WEIGHT
);
3725 #ifdef CONFIG_NET_POLL_CONTROLLER
3726 dev
->poll_controller
= ucc_netpoll
;
3728 dev
->stop
= ucc_geth_close
;
3729 // dev->change_mtu = ucc_geth_change_mtu;
3731 dev
->set_multicast_list
= ucc_geth_set_multi
;
3733 ugeth
->msg_enable
= netif_msg_init(debug
.msg_enable
, UGETH_MSG_DEFAULT
);
3734 ugeth
->phy_interface
= phy_interface
;
3735 ugeth
->max_speed
= max_speed
;
3737 err
= register_netdev(dev
);
3739 if (netif_msg_probe(ugeth
))
3740 ugeth_err("%s: Cannot register net device, aborting.",
3746 mac_addr
= of_get_mac_address(np
);
3748 memcpy(dev
->dev_addr
, mac_addr
, 6);
3750 ugeth
->ug_info
= ug_info
;
3757 static int ucc_geth_remove(struct of_device
* ofdev
)
3759 struct device
*device
= &ofdev
->dev
;
3760 struct net_device
*dev
= dev_get_drvdata(device
);
3761 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3763 unregister_netdev(dev
);
3765 ucc_geth_memclean(ugeth
);
3766 dev_set_drvdata(device
, NULL
);
3771 static struct of_device_id ucc_geth_match
[] = {
3774 .compatible
= "ucc_geth",
3779 MODULE_DEVICE_TABLE(of
, ucc_geth_match
);
3781 static struct of_platform_driver ucc_geth_driver
= {
3783 .match_table
= ucc_geth_match
,
3784 .probe
= ucc_geth_probe
,
3785 .remove
= ucc_geth_remove
,
3788 static int __init
ucc_geth_init(void)
3792 ret
= uec_mdio_init();
3797 if (netif_msg_drv(&debug
))
3798 printk(KERN_INFO
"ucc_geth: " DRV_DESC
"\n");
3799 for (i
= 0; i
< 8; i
++)
3800 memcpy(&(ugeth_info
[i
]), &ugeth_primary_info
,
3801 sizeof(ugeth_primary_info
));
3803 ret
= of_register_platform_driver(&ucc_geth_driver
);
3811 static void __exit
ucc_geth_exit(void)
3813 of_unregister_platform_driver(&ucc_geth_driver
);
3817 module_init(ucc_geth_init
);
3818 module_exit(ucc_geth_exit
);
3820 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3821 MODULE_DESCRIPTION(DRV_DESC
);
3822 MODULE_VERSION(DRV_VERSION
);
3823 MODULE_LICENSE("GPL");