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ASoC: TWL4030: Change DAPM routings and controls for DACs and PGAs
[linux-2.6/mini2440.git] / sound / soc / codecs / twl4030.c
blob99fe44f70507f0b2df8c152ad19d3bfb02af7427
1 /*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/i2c/twl4030.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/initval.h>
36 #include <sound/tlv.h>
37
38 #include "twl4030.h"
39
40 /*
41 * twl4030 register cache & default register settings
42 */
43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
45 0x91, /* REG_CODEC_MODE (0x1) */
46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118 };
119
120 /* codec private data */
121 struct twl4030_priv {
122 unsigned int bypass_state;
123 unsigned int codec_powered;
124 unsigned int codec_muted;
125
126 struct snd_pcm_substream *master_substream;
127 struct snd_pcm_substream *slave_substream;
128
129 unsigned int configured;
130 unsigned int rate;
131 unsigned int sample_bits;
132 unsigned int channels;
133 };
134
135 /*
136 * read twl4030 register cache
137 */
138 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
139 unsigned int reg)
140 {
141 u8 *cache = codec->reg_cache;
142
143 if (reg >= TWL4030_CACHEREGNUM)
144 return -EIO;
145
146 return cache[reg];
147 }
148
149 /*
150 * write twl4030 register cache
151 */
152 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
153 u8 reg, u8 value)
154 {
155 u8 *cache = codec->reg_cache;
156
157 if (reg >= TWL4030_CACHEREGNUM)
158 return;
159 cache[reg] = value;
160 }
161
162 /*
163 * write to the twl4030 register space
164 */
165 static int twl4030_write(struct snd_soc_codec *codec,
166 unsigned int reg, unsigned int value)
167 {
168 twl4030_write_reg_cache(codec, reg, value);
169 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
170 }
171
172 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
173 {
174 struct twl4030_priv *twl4030 = codec->private_data;
175 u8 mode;
176
177 if (enable == twl4030->codec_powered)
178 return;
179
180 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
181 if (enable)
182 mode |= TWL4030_CODECPDZ;
183 else
184 mode &= ~TWL4030_CODECPDZ;
185
186 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
187 twl4030->codec_powered = enable;
188
189 /* REVISIT: this delay is present in TI sample drivers */
190 /* but there seems to be no TRM requirement for it */
191 udelay(10);
192 }
193
194 static void twl4030_init_chip(struct snd_soc_codec *codec)
195 {
196 int i;
197
198 /* clear CODECPDZ prior to setting register defaults */
199 twl4030_codec_enable(codec, 0);
200
201 /* set all audio section registers to reasonable defaults */
202 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
203 twl4030_write(codec, i, twl4030_reg[i]);
204
205 }
206
207 static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
208 {
209 struct twl4030_priv *twl4030 = codec->private_data;
210 u8 reg_val;
211
212 if (mute == twl4030->codec_muted)
213 return;
214
215 if (mute) {
216 /* Bypass the reg_cache and mute the volumes
217 * Headset mute is done in it's own event handler
218 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
219 */
220 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
221 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
222 reg_val & (~TWL4030_EAR_GAIN),
223 TWL4030_REG_EAR_CTL);
224
225 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
226 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 reg_val & (~TWL4030_PREDL_GAIN),
228 TWL4030_REG_PREDL_CTL);
229 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
230 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 reg_val & (~TWL4030_PREDR_GAIN),
232 TWL4030_REG_PREDL_CTL);
233
234 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
235 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
236 reg_val & (~TWL4030_PRECKL_GAIN),
237 TWL4030_REG_PRECKL_CTL);
238 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
239 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
240 reg_val & (~TWL4030_PRECKR_GAIN),
241 TWL4030_REG_PRECKR_CTL);
242
243 /* Disable PLL */
244 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
245 reg_val &= ~TWL4030_APLL_EN;
246 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
247 } else {
248 /* Restore the volumes
249 * Headset mute is done in it's own event handler
250 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
251 */
252 twl4030_write(codec, TWL4030_REG_EAR_CTL,
253 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
254
255 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
256 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
257 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
258 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
259
260 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
261 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
262 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
263 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
264
265 /* Enable PLL */
266 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
267 reg_val |= TWL4030_APLL_EN;
268 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
269 }
270
271 twl4030->codec_muted = mute;
272 }
273
274 static void twl4030_power_up(struct snd_soc_codec *codec)
275 {
276 struct twl4030_priv *twl4030 = codec->private_data;
277 u8 anamicl, regmisc1, byte;
278 int i = 0;
279
280 if (twl4030->codec_powered)
281 return;
282
283 /* set CODECPDZ to turn on codec */
284 twl4030_codec_enable(codec, 1);
285
286 /* initiate offset cancellation */
287 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
288 twl4030_write(codec, TWL4030_REG_ANAMICL,
289 anamicl | TWL4030_CNCL_OFFSET_START);
290
291 /* wait for offset cancellation to complete */
292 do {
293 /* this takes a little while, so don't slam i2c */
294 udelay(2000);
295 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
296 TWL4030_REG_ANAMICL);
297 } while ((i++ < 100) &&
298 ((byte & TWL4030_CNCL_OFFSET_START) ==
299 TWL4030_CNCL_OFFSET_START));
300
301 /* Make sure that the reg_cache has the same value as the HW */
302 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
303
304 /* anti-pop when changing analog gain */
305 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
306 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
307 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
308
309 /* toggle CODECPDZ as per TRM */
310 twl4030_codec_enable(codec, 0);
311 twl4030_codec_enable(codec, 1);
312 }
313
314 /*
315 * Unconditional power down
316 */
317 static void twl4030_power_down(struct snd_soc_codec *codec)
318 {
319 /* power down */
320 twl4030_codec_enable(codec, 0);
321 }
322
323 /* Earpiece */
324 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
325 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
326 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
327 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
328 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
329 };
330
331 /* PreDrive Left */
332 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
333 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
334 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
335 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
336 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
337 };
338
339 /* PreDrive Right */
340 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
341 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
342 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
343 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
344 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
345 };
346
347 /* Headset Left */
348 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
349 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
350 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
351 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
352 };
353
354 /* Headset Right */
355 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
356 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
357 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
358 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
359 };
360
361 /* Carkit Left */
362 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
363 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
364 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
365 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
366 };
367
368 /* Carkit Right */
369 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
370 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
371 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
372 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
373 };
374
375 /* Handsfree Left */
376 static const char *twl4030_handsfreel_texts[] =
377 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
378
379 static const struct soc_enum twl4030_handsfreel_enum =
380 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
381 ARRAY_SIZE(twl4030_handsfreel_texts),
382 twl4030_handsfreel_texts);
383
384 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
385 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
386
387 /* Handsfree Right */
388 static const char *twl4030_handsfreer_texts[] =
389 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
390
391 static const struct soc_enum twl4030_handsfreer_enum =
392 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
393 ARRAY_SIZE(twl4030_handsfreer_texts),
394 twl4030_handsfreer_texts);
395
396 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
397 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
398
399 /* Vibra */
400 /* Vibra audio path selection */
401 static const char *twl4030_vibra_texts[] =
402 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
403
404 static const struct soc_enum twl4030_vibra_enum =
405 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
406 ARRAY_SIZE(twl4030_vibra_texts),
407 twl4030_vibra_texts);
408
409 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
410 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
411
412 /* Vibra path selection: local vibrator (PWM) or audio driven */
413 static const char *twl4030_vibrapath_texts[] =
414 {"Local vibrator", "Audio"};
415
416 static const struct soc_enum twl4030_vibrapath_enum =
417 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
418 ARRAY_SIZE(twl4030_vibrapath_texts),
419 twl4030_vibrapath_texts);
420
421 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
422 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
423
424 /* Left analog microphone selection */
425 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
426 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
427 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
428 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
429 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
430 };
431
432 /* Right analog microphone selection */
433 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
434 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
435 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
436 };
437
438 /* TX1 L/R Analog/Digital microphone selection */
439 static const char *twl4030_micpathtx1_texts[] =
440 {"Analog", "Digimic0"};
441
442 static const struct soc_enum twl4030_micpathtx1_enum =
443 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
444 ARRAY_SIZE(twl4030_micpathtx1_texts),
445 twl4030_micpathtx1_texts);
446
447 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
448 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
449
450 /* TX2 L/R Analog/Digital microphone selection */
451 static const char *twl4030_micpathtx2_texts[] =
452 {"Analog", "Digimic1"};
453
454 static const struct soc_enum twl4030_micpathtx2_enum =
455 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
456 ARRAY_SIZE(twl4030_micpathtx2_texts),
457 twl4030_micpathtx2_texts);
458
459 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
460 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
461
462 /* Analog bypass for AudioR1 */
463 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
464 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
465
466 /* Analog bypass for AudioL1 */
467 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
468 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
469
470 /* Analog bypass for AudioR2 */
471 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
472 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
473
474 /* Analog bypass for AudioL2 */
475 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
476 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
477
478 /* Analog bypass for Voice */
479 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
480 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
481
482 /* Digital bypass gain, 0 mutes the bypass */
483 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
484 TLV_DB_RANGE_HEAD(2),
485 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
486 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
487 };
488
489 /* Digital bypass left (TX1L -> RX2L) */
490 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
491 SOC_DAPM_SINGLE_TLV("Volume",
492 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
493 twl4030_dapm_dbypass_tlv);
494
495 /* Digital bypass right (TX1R -> RX2R) */
496 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
497 SOC_DAPM_SINGLE_TLV("Volume",
498 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
499 twl4030_dapm_dbypass_tlv);
500
501 /*
502 * Voice Sidetone GAIN volume control:
503 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
504 */
505 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
506
507 /* Digital bypass voice: sidetone (VUL -> VDL)*/
508 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
509 SOC_DAPM_SINGLE_TLV("Volume",
510 TWL4030_REG_VSTPGA, 0, 0x29, 0,
511 twl4030_dapm_dbypassv_tlv);
512
513 static int micpath_event(struct snd_soc_dapm_widget *w,
514 struct snd_kcontrol *kcontrol, int event)
515 {
516 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
517 unsigned char adcmicsel, micbias_ctl;
518
519 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
520 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
521 /* Prepare the bits for the given TX path:
522 * shift_l == 0: TX1 microphone path
523 * shift_l == 2: TX2 microphone path */
524 if (e->shift_l) {
525 /* TX2 microphone path */
526 if (adcmicsel & TWL4030_TX2IN_SEL)
527 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
528 else
529 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
530 } else {
531 /* TX1 microphone path */
532 if (adcmicsel & TWL4030_TX1IN_SEL)
533 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
534 else
535 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
536 }
537
538 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
539
540 return 0;
541 }
542
543 static int handsfree_event(struct snd_soc_dapm_widget *w,
544 struct snd_kcontrol *kcontrol, int event)
545 {
546 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
547 unsigned char hs_ctl;
548
549 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
550
551 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
552 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
553 twl4030_write(w->codec, e->reg, hs_ctl);
554 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
555 twl4030_write(w->codec, e->reg, hs_ctl);
556 hs_ctl |= TWL4030_HF_CTL_HB_EN;
557 twl4030_write(w->codec, e->reg, hs_ctl);
558 } else {
559 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
560 | TWL4030_HF_CTL_HB_EN);
561 twl4030_write(w->codec, e->reg, hs_ctl);
562 }
563
564 return 0;
565 }
566
567 static int headsetl_event(struct snd_soc_dapm_widget *w,
568 struct snd_kcontrol *kcontrol, int event)
569 {
570 unsigned char hs_gain, hs_pop;
571
572 /* Save the current volume */
573 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
574 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
575
576 switch (event) {
577 case SND_SOC_DAPM_POST_PMU:
578 /* Do the anti-pop/bias ramp enable according to the TRM */
579 hs_pop |= TWL4030_VMID_EN;
580 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
581 /* Is this needed? Can we just use whatever gain here? */
582 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
583 (hs_gain & (~0x0f)) | 0x0a);
584 hs_pop |= TWL4030_RAMP_EN;
585 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
586
587 /* Restore the original volume */
588 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
589 break;
590 case SND_SOC_DAPM_POST_PMD:
591 /* Do the anti-pop/bias ramp disable according to the TRM */
592 hs_pop &= ~TWL4030_RAMP_EN;
593 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
594 /* Bypass the reg_cache to mute the headset */
595 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
596 hs_gain & (~0x0f),
597 TWL4030_REG_HS_GAIN_SET);
598 hs_pop &= ~TWL4030_VMID_EN;
599 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
600 break;
601 }
602 return 0;
603 }
604
605 static int bypass_event(struct snd_soc_dapm_widget *w,
606 struct snd_kcontrol *kcontrol, int event)
607 {
608 struct soc_mixer_control *m =
609 (struct soc_mixer_control *)w->kcontrols->private_value;
610 struct twl4030_priv *twl4030 = w->codec->private_data;
611 unsigned char reg, misc;
612
613 reg = twl4030_read_reg_cache(w->codec, m->reg);
614
615 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
616 /* Analog bypass */
617 if (reg & (1 << m->shift))
618 twl4030->bypass_state |=
619 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
620 else
621 twl4030->bypass_state &=
622 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
623 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
624 /* Analog voice bypass */
625 if (reg & (1 << m->shift))
626 twl4030->bypass_state |= (1 << 4);
627 else
628 twl4030->bypass_state &= ~(1 << 4);
629 } else if (m->reg == TWL4030_REG_VSTPGA) {
630 /* Voice digital bypass */
631 if (reg)
632 twl4030->bypass_state |= (1 << 5);
633 else
634 twl4030->bypass_state &= ~(1 << 5);
635 } else {
636 /* Digital bypass */
637 if (reg & (0x7 << m->shift))
638 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
639 else
640 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
641 }
642
643 /* Enable master analog loopback mode if any analog switch is enabled*/
644 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
645 if (twl4030->bypass_state & 0x1F)
646 misc |= TWL4030_FMLOOP_EN;
647 else
648 misc &= ~TWL4030_FMLOOP_EN;
649 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
650
651 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
652 if (twl4030->bypass_state)
653 twl4030_codec_mute(w->codec, 0);
654 else
655 twl4030_codec_mute(w->codec, 1);
656 }
657 return 0;
658 }
659
660 /*
661 * Some of the gain controls in TWL (mostly those which are associated with
662 * the outputs) are implemented in an interesting way:
663 * 0x0 : Power down (mute)
664 * 0x1 : 6dB
665 * 0x2 : 0 dB
666 * 0x3 : -6 dB
667 * Inverting not going to help with these.
668 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
669 */
670 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
671 xinvert, tlv_array) \
672 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
673 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
674 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
675 .tlv.p = (tlv_array), \
676 .info = snd_soc_info_volsw, \
677 .get = snd_soc_get_volsw_twl4030, \
678 .put = snd_soc_put_volsw_twl4030, \
679 .private_value = (unsigned long)&(struct soc_mixer_control) \
680 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
681 .max = xmax, .invert = xinvert} }
682 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
683 xinvert, tlv_array) \
684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
685 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
686 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
687 .tlv.p = (tlv_array), \
688 .info = snd_soc_info_volsw_2r, \
689 .get = snd_soc_get_volsw_r2_twl4030,\
690 .put = snd_soc_put_volsw_r2_twl4030, \
691 .private_value = (unsigned long)&(struct soc_mixer_control) \
692 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
693 .rshift = xshift, .max = xmax, .invert = xinvert} }
694 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
695 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
696 xinvert, tlv_array)
697
698 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
699 struct snd_ctl_elem_value *ucontrol)
700 {
701 struct soc_mixer_control *mc =
702 (struct soc_mixer_control *)kcontrol->private_value;
703 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
704 unsigned int reg = mc->reg;
705 unsigned int shift = mc->shift;
706 unsigned int rshift = mc->rshift;
707 int max = mc->max;
708 int mask = (1 << fls(max)) - 1;
709
710 ucontrol->value.integer.value[0] =
711 (snd_soc_read(codec, reg) >> shift) & mask;
712 if (ucontrol->value.integer.value[0])
713 ucontrol->value.integer.value[0] =
714 max + 1 - ucontrol->value.integer.value[0];
715
716 if (shift != rshift) {
717 ucontrol->value.integer.value[1] =
718 (snd_soc_read(codec, reg) >> rshift) & mask;
719 if (ucontrol->value.integer.value[1])
720 ucontrol->value.integer.value[1] =
721 max + 1 - ucontrol->value.integer.value[1];
722 }
723
724 return 0;
725 }
726
727 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_value *ucontrol)
729 {
730 struct soc_mixer_control *mc =
731 (struct soc_mixer_control *)kcontrol->private_value;
732 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
733 unsigned int reg = mc->reg;
734 unsigned int shift = mc->shift;
735 unsigned int rshift = mc->rshift;
736 int max = mc->max;
737 int mask = (1 << fls(max)) - 1;
738 unsigned short val, val2, val_mask;
739
740 val = (ucontrol->value.integer.value[0] & mask);
741
742 val_mask = mask << shift;
743 if (val)
744 val = max + 1 - val;
745 val = val << shift;
746 if (shift != rshift) {
747 val2 = (ucontrol->value.integer.value[1] & mask);
748 val_mask |= mask << rshift;
749 if (val2)
750 val2 = max + 1 - val2;
751 val |= val2 << rshift;
752 }
753 return snd_soc_update_bits(codec, reg, val_mask, val);
754 }
755
756 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
757 struct snd_ctl_elem_value *ucontrol)
758 {
759 struct soc_mixer_control *mc =
760 (struct soc_mixer_control *)kcontrol->private_value;
761 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
762 unsigned int reg = mc->reg;
763 unsigned int reg2 = mc->rreg;
764 unsigned int shift = mc->shift;
765 int max = mc->max;
766 int mask = (1<<fls(max))-1;
767
768 ucontrol->value.integer.value[0] =
769 (snd_soc_read(codec, reg) >> shift) & mask;
770 ucontrol->value.integer.value[1] =
771 (snd_soc_read(codec, reg2) >> shift) & mask;
772
773 if (ucontrol->value.integer.value[0])
774 ucontrol->value.integer.value[0] =
775 max + 1 - ucontrol->value.integer.value[0];
776 if (ucontrol->value.integer.value[1])
777 ucontrol->value.integer.value[1] =
778 max + 1 - ucontrol->value.integer.value[1];
779
780 return 0;
781 }
782
783 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
785 {
786 struct soc_mixer_control *mc =
787 (struct soc_mixer_control *)kcontrol->private_value;
788 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
789 unsigned int reg = mc->reg;
790 unsigned int reg2 = mc->rreg;
791 unsigned int shift = mc->shift;
792 int max = mc->max;
793 int mask = (1 << fls(max)) - 1;
794 int err;
795 unsigned short val, val2, val_mask;
796
797 val_mask = mask << shift;
798 val = (ucontrol->value.integer.value[0] & mask);
799 val2 = (ucontrol->value.integer.value[1] & mask);
800
801 if (val)
802 val = max + 1 - val;
803 if (val2)
804 val2 = max + 1 - val2;
805
806 val = val << shift;
807 val2 = val2 << shift;
808
809 err = snd_soc_update_bits(codec, reg, val_mask, val);
810 if (err < 0)
811 return err;
812
813 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
814 return err;
815 }
816
817 /* Codec operation modes */
818 static const char *twl4030_op_modes_texts[] = {
819 "Option 2 (voice/audio)", "Option 1 (audio)"
820 };
821
822 static const struct soc_enum twl4030_op_modes_enum =
823 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
824 ARRAY_SIZE(twl4030_op_modes_texts),
825 twl4030_op_modes_texts);
826
827 int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
828 struct snd_ctl_elem_value *ucontrol)
829 {
830 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
831 struct twl4030_priv *twl4030 = codec->private_data;
832 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
833 unsigned short val;
834 unsigned short mask, bitmask;
835
836 if (twl4030->configured) {
837 printk(KERN_ERR "twl4030 operation mode cannot be "
838 "changed on-the-fly\n");
839 return -EBUSY;
840 }
841
842 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
843 ;
844 if (ucontrol->value.enumerated.item[0] > e->max - 1)
845 return -EINVAL;
846
847 val = ucontrol->value.enumerated.item[0] << e->shift_l;
848 mask = (bitmask - 1) << e->shift_l;
849 if (e->shift_l != e->shift_r) {
850 if (ucontrol->value.enumerated.item[1] > e->max - 1)
851 return -EINVAL;
852 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
853 mask |= (bitmask - 1) << e->shift_r;
854 }
855
856 return snd_soc_update_bits(codec, e->reg, mask, val);
857 }
858
859 /*
860 * FGAIN volume control:
861 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
862 */
863 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
864
865 /*
866 * CGAIN volume control:
867 * 0 dB to 12 dB in 6 dB steps
868 * value 2 and 3 means 12 dB
869 */
870 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
871
872 /*
873 * Voice Downlink GAIN volume control:
874 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
875 */
876 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
877
878 /*
879 * Analog playback gain
880 * -24 dB to 12 dB in 2 dB steps
881 */
882 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
883
884 /*
885 * Gain controls tied to outputs
886 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
887 */
888 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
889
890 /*
891 * Gain control for earpiece amplifier
892 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
893 */
894 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
895
896 /*
897 * Capture gain after the ADCs
898 * from 0 dB to 31 dB in 1 dB steps
899 */
900 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
901
902 /*
903 * Gain control for input amplifiers
904 * 0 dB to 30 dB in 6 dB steps
905 */
906 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
907
908 static const char *twl4030_rampdelay_texts[] = {
909 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
910 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
911 "3495/2581/1748 ms"
912 };
913
914 static const struct soc_enum twl4030_rampdelay_enum =
915 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
916 ARRAY_SIZE(twl4030_rampdelay_texts),
917 twl4030_rampdelay_texts);
918
919 /* Vibra H-bridge direction mode */
920 static const char *twl4030_vibradirmode_texts[] = {
921 "Vibra H-bridge direction", "Audio data MSB",
922 };
923
924 static const struct soc_enum twl4030_vibradirmode_enum =
925 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
926 ARRAY_SIZE(twl4030_vibradirmode_texts),
927 twl4030_vibradirmode_texts);
928
929 /* Vibra H-bridge direction */
930 static const char *twl4030_vibradir_texts[] = {
931 "Positive polarity", "Negative polarity",
932 };
933
934 static const struct soc_enum twl4030_vibradir_enum =
935 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
936 ARRAY_SIZE(twl4030_vibradir_texts),
937 twl4030_vibradir_texts);
938
939 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
940 /* Codec operation mode control */
941 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
942 snd_soc_get_enum_double,
943 snd_soc_put_twl4030_opmode_enum_double),
944
945 /* Common playback gain controls */
946 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
947 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
948 0, 0x3f, 0, digital_fine_tlv),
949 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
950 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
951 0, 0x3f, 0, digital_fine_tlv),
952
953 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
954 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
955 6, 0x2, 0, digital_coarse_tlv),
956 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
957 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
958 6, 0x2, 0, digital_coarse_tlv),
959
960 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
961 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
962 3, 0x12, 1, analog_tlv),
963 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
964 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
965 3, 0x12, 1, analog_tlv),
966 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
967 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
968 1, 1, 0),
969 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
970 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
971 1, 1, 0),
972
973 /* Common voice downlink gain controls */
974 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
975 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
976
977 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
978 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
979
980 SOC_SINGLE("DAC Voice Analog Downlink Switch",
981 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
982
983 /* Separate output gain controls */
984 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
985 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
986 4, 3, 0, output_tvl),
987
988 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
989 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
990
991 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
992 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
993 4, 3, 0, output_tvl),
994
995 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
996 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
997
998 /* Common capture gain controls */
999 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1000 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1001 0, 0x1f, 0, digital_capture_tlv),
1002 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1003 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1004 0, 0x1f, 0, digital_capture_tlv),
1005
1006 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1007 0, 3, 5, 0, input_gain_tlv),
1008
1009 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1010
1011 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1012 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1013 };
1014
1015 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1016 /* Left channel inputs */
1017 SND_SOC_DAPM_INPUT("MAINMIC"),
1018 SND_SOC_DAPM_INPUT("HSMIC"),
1019 SND_SOC_DAPM_INPUT("AUXL"),
1020 SND_SOC_DAPM_INPUT("CARKITMIC"),
1021 /* Right channel inputs */
1022 SND_SOC_DAPM_INPUT("SUBMIC"),
1023 SND_SOC_DAPM_INPUT("AUXR"),
1024 /* Digital microphones (Stereo) */
1025 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1026 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1027
1028 /* Outputs */
1029 SND_SOC_DAPM_OUTPUT("OUTL"),
1030 SND_SOC_DAPM_OUTPUT("OUTR"),
1031 SND_SOC_DAPM_OUTPUT("EARPIECE"),
1032 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1033 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1034 SND_SOC_DAPM_OUTPUT("HSOL"),
1035 SND_SOC_DAPM_OUTPUT("HSOR"),
1036 SND_SOC_DAPM_OUTPUT("CARKITL"),
1037 SND_SOC_DAPM_OUTPUT("CARKITR"),
1038 SND_SOC_DAPM_OUTPUT("HFL"),
1039 SND_SOC_DAPM_OUTPUT("HFR"),
1040 SND_SOC_DAPM_OUTPUT("VIBRA"),
1041
1042 /* DACs */
1043 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
1044 SND_SOC_NOPM, 0, 0),
1045 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
1046 SND_SOC_NOPM, 0, 0),
1047 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
1048 SND_SOC_NOPM, 0, 0),
1049 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
1050 SND_SOC_NOPM, 0, 0),
1051 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
1052 SND_SOC_NOPM, 0, 0),
1053
1054 /* Analog bypasses */
1055 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1056 &twl4030_dapm_abypassr1_control, bypass_event,
1057 SND_SOC_DAPM_POST_REG),
1058 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1059 &twl4030_dapm_abypassl1_control,
1060 bypass_event, SND_SOC_DAPM_POST_REG),
1061 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1062 &twl4030_dapm_abypassr2_control,
1063 bypass_event, SND_SOC_DAPM_POST_REG),
1064 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1065 &twl4030_dapm_abypassl2_control,
1066 bypass_event, SND_SOC_DAPM_POST_REG),
1067 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1068 &twl4030_dapm_abypassv_control,
1069 bypass_event, SND_SOC_DAPM_POST_REG),
1070
1071 /* Digital bypasses */
1072 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1073 &twl4030_dapm_dbypassl_control, bypass_event,
1074 SND_SOC_DAPM_POST_REG),
1075 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1076 &twl4030_dapm_dbypassr_control, bypass_event,
1077 SND_SOC_DAPM_POST_REG),
1078 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1079 &twl4030_dapm_dbypassv_control, bypass_event,
1080 SND_SOC_DAPM_POST_REG),
1081
1082 /* Digital mixers, power control for the physical DACs */
1083 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1084 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1085 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1086 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1087 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1088 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1089 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1090 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1091 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1092 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1093
1094 /* Analog mixers, power control for the physical PGAs */
1095 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1096 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1097 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1098 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1099 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1100 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1101 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1102 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1103 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1104 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1105
1106 /* Output MIXER controls */
1107 /* Earpiece */
1108 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1109 &twl4030_dapm_earpiece_controls[0],
1110 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1111 /* PreDrivL/R */
1112 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1113 &twl4030_dapm_predrivel_controls[0],
1114 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1115 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1116 &twl4030_dapm_predriver_controls[0],
1117 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1118 /* HeadsetL/R */
1119 SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1120 &twl4030_dapm_hsol_controls[0],
1121 ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
1122 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1123 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1124 &twl4030_dapm_hsor_controls[0],
1125 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1126 /* CarkitL/R */
1127 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1128 &twl4030_dapm_carkitl_controls[0],
1129 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1130 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1131 &twl4030_dapm_carkitr_controls[0],
1132 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1133
1134 /* Output MUX controls */
1135 /* HandsfreeL/R */
1136 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
1137 &twl4030_dapm_handsfreel_control, handsfree_event,
1138 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1139 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
1140 &twl4030_dapm_handsfreer_control, handsfree_event,
1141 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1142 /* Vibra */
1143 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1144 &twl4030_dapm_vibra_control),
1145 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1146 &twl4030_dapm_vibrapath_control),
1147
1148 /* Introducing four virtual ADC, since TWL4030 have four channel for
1149 capture */
1150 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1151 SND_SOC_NOPM, 0, 0),
1152 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1153 SND_SOC_NOPM, 0, 0),
1154 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1155 SND_SOC_NOPM, 0, 0),
1156 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1157 SND_SOC_NOPM, 0, 0),
1158
1159 /* Analog/Digital mic path selection.
1160 TX1 Left/Right: either analog Left/Right or Digimic0
1161 TX2 Left/Right: either analog Left/Right or Digimic1 */
1162 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1163 &twl4030_dapm_micpathtx1_control, micpath_event,
1164 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1165 SND_SOC_DAPM_POST_REG),
1166 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1167 &twl4030_dapm_micpathtx2_control, micpath_event,
1168 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1169 SND_SOC_DAPM_POST_REG),
1170
1171 /* Analog input mixers for the capture amplifiers */
1172 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1173 TWL4030_REG_ANAMICL, 4, 0,
1174 &twl4030_dapm_analoglmic_controls[0],
1175 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1176 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1177 TWL4030_REG_ANAMICR, 4, 0,
1178 &twl4030_dapm_analogrmic_controls[0],
1179 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1180
1181 SND_SOC_DAPM_PGA("ADC Physical Left",
1182 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1183 SND_SOC_DAPM_PGA("ADC Physical Right",
1184 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1185
1186 SND_SOC_DAPM_PGA("Digimic0 Enable",
1187 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1188 SND_SOC_DAPM_PGA("Digimic1 Enable",
1189 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1190
1191 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1192 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1193 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1194
1195 };
1196
1197 static const struct snd_soc_dapm_route intercon[] = {
1198 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1199 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1200 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1201 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1202 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1203
1204 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1205 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1206 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1207 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1208 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1209
1210 /* Internal playback routings */
1211 /* Earpiece */
1212 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1213 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1214 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1215 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1216 /* PreDrivL */
1217 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1218 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1219 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1220 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1221 /* PreDrivR */
1222 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1223 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1224 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1225 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1226 /* HeadsetL */
1227 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1228 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1229 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1230 /* HeadsetR */
1231 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1232 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1233 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1234 /* CarkitL */
1235 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1236 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1237 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1238 /* CarkitR */
1239 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1240 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1241 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1242 /* HandsfreeL */
1243 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1244 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1245 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1246 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1247 /* HandsfreeR */
1248 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1249 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1250 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1251 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1252 /* Vibra */
1253 {"Vibra Mux", "AudioL1", "DAC Left1"},
1254 {"Vibra Mux", "AudioR1", "DAC Right1"},
1255 {"Vibra Mux", "AudioL2", "DAC Left2"},
1256 {"Vibra Mux", "AudioR2", "DAC Right2"},
1257
1258 /* outputs */
1259 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1260 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1261 {"EARPIECE", NULL, "Earpiece Mixer"},
1262 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1263 {"PREDRIVER", NULL, "PredriveR Mixer"},
1264 {"HSOL", NULL, "HeadsetL Mixer"},
1265 {"HSOR", NULL, "HeadsetR Mixer"},
1266 {"CARKITL", NULL, "CarkitL Mixer"},
1267 {"CARKITR", NULL, "CarkitR Mixer"},
1268 {"HFL", NULL, "HandsfreeL Mux"},
1269 {"HFR", NULL, "HandsfreeR Mux"},
1270 {"Vibra Route", "Audio", "Vibra Mux"},
1271 {"VIBRA", NULL, "Vibra Route"},
1272
1273 /* Capture path */
1274 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1275 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1276 {"Analog Left Capture Route", "AUXL", "AUXL"},
1277 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1278
1279 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1280 {"Analog Right Capture Route", "AUXR", "AUXR"},
1281
1282 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1283 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
1284
1285 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1286 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1287
1288 /* TX1 Left capture path */
1289 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1290 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1291 /* TX1 Right capture path */
1292 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1293 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1294 /* TX2 Left capture path */
1295 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1296 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1297 /* TX2 Right capture path */
1298 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1299 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1300
1301 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1302 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1303 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1304 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1305
1306 /* Analog bypass routes */
1307 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1308 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1309 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1310 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
1311 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
1312
1313 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1314 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1315 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1316 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1317 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1318
1319 /* Digital bypass routes */
1320 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1321 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1322 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1323
1324 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1325 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1326 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1327
1328 };
1329
1330 static int twl4030_add_widgets(struct snd_soc_codec *codec)
1331 {
1332 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1333 ARRAY_SIZE(twl4030_dapm_widgets));
1334
1335 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1336
1337 snd_soc_dapm_new_widgets(codec);
1338 return 0;
1339 }
1340
1341 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1342 enum snd_soc_bias_level level)
1343 {
1344 struct twl4030_priv *twl4030 = codec->private_data;
1345
1346 switch (level) {
1347 case SND_SOC_BIAS_ON:
1348 twl4030_codec_mute(codec, 0);
1349 break;
1350 case SND_SOC_BIAS_PREPARE:
1351 twl4030_power_up(codec);
1352 if (twl4030->bypass_state)
1353 twl4030_codec_mute(codec, 0);
1354 else
1355 twl4030_codec_mute(codec, 1);
1356 break;
1357 case SND_SOC_BIAS_STANDBY:
1358 twl4030_power_up(codec);
1359 if (twl4030->bypass_state)
1360 twl4030_codec_mute(codec, 0);
1361 else
1362 twl4030_codec_mute(codec, 1);
1363 break;
1364 case SND_SOC_BIAS_OFF:
1365 twl4030_power_down(codec);
1366 break;
1367 }
1368 codec->bias_level = level;
1369
1370 return 0;
1371 }
1372
1373 static void twl4030_constraints(struct twl4030_priv *twl4030,
1374 struct snd_pcm_substream *mst_substream)
1375 {
1376 struct snd_pcm_substream *slv_substream;
1377
1378 /* Pick the stream, which need to be constrained */
1379 if (mst_substream == twl4030->master_substream)
1380 slv_substream = twl4030->slave_substream;
1381 else if (mst_substream == twl4030->slave_substream)
1382 slv_substream = twl4030->master_substream;
1383 else /* This should not happen.. */
1384 return;
1385
1386 /* Set the constraints according to the already configured stream */
1387 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1388 SNDRV_PCM_HW_PARAM_RATE,
1389 twl4030->rate,
1390 twl4030->rate);
1391
1392 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1393 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1394 twl4030->sample_bits,
1395 twl4030->sample_bits);
1396
1397 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1398 SNDRV_PCM_HW_PARAM_CHANNELS,
1399 twl4030->channels,
1400 twl4030->channels);
1401 }
1402
1403 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1404 * capture has to be enabled/disabled. */
1405 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1406 int enable)
1407 {
1408 u8 reg, mask;
1409
1410 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1411
1412 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1413 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1414 else
1415 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1416
1417 if (enable)
1418 reg |= mask;
1419 else
1420 reg &= ~mask;
1421
1422 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1423 }
1424
1425 static int twl4030_startup(struct snd_pcm_substream *substream,
1426 struct snd_soc_dai *dai)
1427 {
1428 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1429 struct snd_soc_device *socdev = rtd->socdev;
1430 struct snd_soc_codec *codec = socdev->card->codec;
1431 struct twl4030_priv *twl4030 = codec->private_data;
1432
1433 if (twl4030->master_substream) {
1434 twl4030->slave_substream = substream;
1435 /* The DAI has one configuration for playback and capture, so
1436 * if the DAI has been already configured then constrain this
1437 * substream to match it. */
1438 if (twl4030->configured)
1439 twl4030_constraints(twl4030, twl4030->master_substream);
1440 } else {
1441 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1442 TWL4030_OPTION_1)) {
1443 /* In option2 4 channel is not supported, set the
1444 * constraint for the first stream for channels, the
1445 * second stream will 'inherit' this cosntraint */
1446 snd_pcm_hw_constraint_minmax(substream->runtime,
1447 SNDRV_PCM_HW_PARAM_CHANNELS,
1448 2, 2);
1449 }
1450 twl4030->master_substream = substream;
1451 }
1452
1453 return 0;
1454 }
1455
1456 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1457 struct snd_soc_dai *dai)
1458 {
1459 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1460 struct snd_soc_device *socdev = rtd->socdev;
1461 struct snd_soc_codec *codec = socdev->card->codec;
1462 struct twl4030_priv *twl4030 = codec->private_data;
1463
1464 if (twl4030->master_substream == substream)
1465 twl4030->master_substream = twl4030->slave_substream;
1466
1467 twl4030->slave_substream = NULL;
1468
1469 /* If all streams are closed, or the remaining stream has not yet
1470 * been configured than set the DAI as not configured. */
1471 if (!twl4030->master_substream)
1472 twl4030->configured = 0;
1473 else if (!twl4030->master_substream->runtime->channels)
1474 twl4030->configured = 0;
1475
1476 /* If the closing substream had 4 channel, do the necessary cleanup */
1477 if (substream->runtime->channels == 4)
1478 twl4030_tdm_enable(codec, substream->stream, 0);
1479 }
1480
1481 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1482 struct snd_pcm_hw_params *params,
1483 struct snd_soc_dai *dai)
1484 {
1485 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1486 struct snd_soc_device *socdev = rtd->socdev;
1487 struct snd_soc_codec *codec = socdev->card->codec;
1488 struct twl4030_priv *twl4030 = codec->private_data;
1489 u8 mode, old_mode, format, old_format;
1490
1491 /* If the substream has 4 channel, do the necessary setup */
1492 if (params_channels(params) == 4) {
1493 /* Safety check: are we in the correct operating mode? */
1494 if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1495 TWL4030_OPTION_1))
1496 twl4030_tdm_enable(codec, substream->stream, 1);
1497 else
1498 return -EINVAL;
1499 }
1500
1501 if (twl4030->configured)
1502 /* Ignoring hw_params for already configured DAI */
1503 return 0;
1504
1505 /* bit rate */
1506 old_mode = twl4030_read_reg_cache(codec,
1507 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1508 mode = old_mode & ~TWL4030_APLL_RATE;
1509
1510 switch (params_rate(params)) {
1511 case 8000:
1512 mode |= TWL4030_APLL_RATE_8000;
1513 break;
1514 case 11025:
1515 mode |= TWL4030_APLL_RATE_11025;
1516 break;
1517 case 12000:
1518 mode |= TWL4030_APLL_RATE_12000;
1519 break;
1520 case 16000:
1521 mode |= TWL4030_APLL_RATE_16000;
1522 break;
1523 case 22050:
1524 mode |= TWL4030_APLL_RATE_22050;
1525 break;
1526 case 24000:
1527 mode |= TWL4030_APLL_RATE_24000;
1528 break;
1529 case 32000:
1530 mode |= TWL4030_APLL_RATE_32000;
1531 break;
1532 case 44100:
1533 mode |= TWL4030_APLL_RATE_44100;
1534 break;
1535 case 48000:
1536 mode |= TWL4030_APLL_RATE_48000;
1537 break;
1538 case 96000:
1539 mode |= TWL4030_APLL_RATE_96000;
1540 break;
1541 default:
1542 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1543 params_rate(params));
1544 return -EINVAL;
1545 }
1546
1547 if (mode != old_mode) {
1548 /* change rate and set CODECPDZ */
1549 twl4030_codec_enable(codec, 0);
1550 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1551 twl4030_codec_enable(codec, 1);
1552 }
1553
1554 /* sample size */
1555 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1556 format = old_format;
1557 format &= ~TWL4030_DATA_WIDTH;
1558 switch (params_format(params)) {
1559 case SNDRV_PCM_FORMAT_S16_LE:
1560 format |= TWL4030_DATA_WIDTH_16S_16W;
1561 break;
1562 case SNDRV_PCM_FORMAT_S24_LE:
1563 format |= TWL4030_DATA_WIDTH_32S_24W;
1564 break;
1565 default:
1566 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1567 params_format(params));
1568 return -EINVAL;
1569 }
1570
1571 if (format != old_format) {
1572
1573 /* clear CODECPDZ before changing format (codec requirement) */
1574 twl4030_codec_enable(codec, 0);
1575
1576 /* change format */
1577 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1578
1579 /* set CODECPDZ afterwards */
1580 twl4030_codec_enable(codec, 1);
1581 }
1582
1583 /* Store the important parameters for the DAI configuration and set
1584 * the DAI as configured */
1585 twl4030->configured = 1;
1586 twl4030->rate = params_rate(params);
1587 twl4030->sample_bits = hw_param_interval(params,
1588 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1589 twl4030->channels = params_channels(params);
1590
1591 /* If both playback and capture streams are open, and one of them
1592 * is setting the hw parameters right now (since we are here), set
1593 * constraints to the other stream to match the current one. */
1594 if (twl4030->slave_substream)
1595 twl4030_constraints(twl4030, substream);
1596
1597 return 0;
1598 }
1599
1600 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1601 int clk_id, unsigned int freq, int dir)
1602 {
1603 struct snd_soc_codec *codec = codec_dai->codec;
1604 u8 infreq;
1605
1606 switch (freq) {
1607 case 19200000:
1608 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1609 break;
1610 case 26000000:
1611 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1612 break;
1613 case 38400000:
1614 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1615 break;
1616 default:
1617 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1618 freq);
1619 return -EINVAL;
1620 }
1621
1622 infreq |= TWL4030_APLL_EN;
1623 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1624
1625 return 0;
1626 }
1627
1628 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1629 unsigned int fmt)
1630 {
1631 struct snd_soc_codec *codec = codec_dai->codec;
1632 u8 old_format, format;
1633
1634 /* get format */
1635 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1636 format = old_format;
1637
1638 /* set master/slave audio interface */
1639 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1640 case SND_SOC_DAIFMT_CBM_CFM:
1641 format &= ~(TWL4030_AIF_SLAVE_EN);
1642 format &= ~(TWL4030_CLK256FS_EN);
1643 break;
1644 case SND_SOC_DAIFMT_CBS_CFS:
1645 format |= TWL4030_AIF_SLAVE_EN;
1646 format |= TWL4030_CLK256FS_EN;
1647 break;
1648 default:
1649 return -EINVAL;
1650 }
1651
1652 /* interface format */
1653 format &= ~TWL4030_AIF_FORMAT;
1654 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1655 case SND_SOC_DAIFMT_I2S:
1656 format |= TWL4030_AIF_FORMAT_CODEC;
1657 break;
1658 case SND_SOC_DAIFMT_DSP_A:
1659 format |= TWL4030_AIF_FORMAT_TDM;
1660 break;
1661 default:
1662 return -EINVAL;
1663 }
1664
1665 if (format != old_format) {
1666
1667 /* clear CODECPDZ before changing format (codec requirement) */
1668 twl4030_codec_enable(codec, 0);
1669
1670 /* change format */
1671 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1672
1673 /* set CODECPDZ afterwards */
1674 twl4030_codec_enable(codec, 1);
1675 }
1676
1677 return 0;
1678 }
1679
1680 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1681 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1682 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1683 int enable)
1684 {
1685 u8 reg, mask;
1686
1687 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1688
1689 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1690 mask = TWL4030_ARXL1_VRX_EN;
1691 else
1692 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1693
1694 if (enable)
1695 reg |= mask;
1696 else
1697 reg &= ~mask;
1698
1699 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1700 }
1701
1702 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1703 struct snd_soc_dai *dai)
1704 {
1705 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1706 struct snd_soc_device *socdev = rtd->socdev;
1707 struct snd_soc_codec *codec = socdev->card->codec;
1708 u8 infreq;
1709 u8 mode;
1710
1711 /* If the system master clock is not 26MHz, the voice PCM interface is
1712 * not avilable.
1713 */
1714 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1715 & TWL4030_APLL_INFREQ;
1716
1717 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1718 printk(KERN_ERR "TWL4030 voice startup: "
1719 "MCLK is not 26MHz, call set_sysclk() on init\n");
1720 return -EINVAL;
1721 }
1722
1723 /* If the codec mode is not option2, the voice PCM interface is not
1724 * avilable.
1725 */
1726 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1727 & TWL4030_OPT_MODE;
1728
1729 if (mode != TWL4030_OPTION_2) {
1730 printk(KERN_ERR "TWL4030 voice startup: "
1731 "the codec mode is not option2\n");
1732 return -EINVAL;
1733 }
1734
1735 return 0;
1736 }
1737
1738 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1739 struct snd_soc_dai *dai)
1740 {
1741 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1742 struct snd_soc_device *socdev = rtd->socdev;
1743 struct snd_soc_codec *codec = socdev->card->codec;
1744
1745 /* Enable voice digital filters */
1746 twl4030_voice_enable(codec, substream->stream, 0);
1747 }
1748
1749 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1750 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1751 {
1752 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1753 struct snd_soc_device *socdev = rtd->socdev;
1754 struct snd_soc_codec *codec = socdev->card->codec;
1755 u8 old_mode, mode;
1756
1757 /* Enable voice digital filters */
1758 twl4030_voice_enable(codec, substream->stream, 1);
1759
1760 /* bit rate */
1761 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1762 & ~(TWL4030_CODECPDZ);
1763 mode = old_mode;
1764
1765 switch (params_rate(params)) {
1766 case 8000:
1767 mode &= ~(TWL4030_SEL_16K);
1768 break;
1769 case 16000:
1770 mode |= TWL4030_SEL_16K;
1771 break;
1772 default:
1773 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1774 params_rate(params));
1775 return -EINVAL;
1776 }
1777
1778 if (mode != old_mode) {
1779 /* change rate and set CODECPDZ */
1780 twl4030_codec_enable(codec, 0);
1781 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1782 twl4030_codec_enable(codec, 1);
1783 }
1784
1785 return 0;
1786 }
1787
1788 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1789 int clk_id, unsigned int freq, int dir)
1790 {
1791 struct snd_soc_codec *codec = codec_dai->codec;
1792 u8 infreq;
1793
1794 switch (freq) {
1795 case 26000000:
1796 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1797 break;
1798 default:
1799 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1800 freq);
1801 return -EINVAL;
1802 }
1803
1804 infreq |= TWL4030_APLL_EN;
1805 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1806
1807 return 0;
1808 }
1809
1810 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1811 unsigned int fmt)
1812 {
1813 struct snd_soc_codec *codec = codec_dai->codec;
1814 u8 old_format, format;
1815
1816 /* get format */
1817 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1818 format = old_format;
1819
1820 /* set master/slave audio interface */
1821 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1822 case SND_SOC_DAIFMT_CBS_CFM:
1823 format &= ~(TWL4030_VIF_SLAVE_EN);
1824 break;
1825 case SND_SOC_DAIFMT_CBS_CFS:
1826 format |= TWL4030_VIF_SLAVE_EN;
1827 break;
1828 default:
1829 return -EINVAL;
1830 }
1831
1832 /* clock inversion */
1833 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1834 case SND_SOC_DAIFMT_IB_NF:
1835 format &= ~(TWL4030_VIF_FORMAT);
1836 break;
1837 case SND_SOC_DAIFMT_NB_IF:
1838 format |= TWL4030_VIF_FORMAT;
1839 break;
1840 default:
1841 return -EINVAL;
1842 }
1843
1844 if (format != old_format) {
1845 /* change format and set CODECPDZ */
1846 twl4030_codec_enable(codec, 0);
1847 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1848 twl4030_codec_enable(codec, 1);
1849 }
1850
1851 return 0;
1852 }
1853
1854 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
1855 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1856
1857 static struct snd_soc_dai_ops twl4030_dai_ops = {
1858 .startup = twl4030_startup,
1859 .shutdown = twl4030_shutdown,
1860 .hw_params = twl4030_hw_params,
1861 .set_sysclk = twl4030_set_dai_sysclk,
1862 .set_fmt = twl4030_set_dai_fmt,
1863 };
1864
1865 static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1866 .startup = twl4030_voice_startup,
1867 .shutdown = twl4030_voice_shutdown,
1868 .hw_params = twl4030_voice_hw_params,
1869 .set_sysclk = twl4030_voice_set_dai_sysclk,
1870 .set_fmt = twl4030_voice_set_dai_fmt,
1871 };
1872
1873 struct snd_soc_dai twl4030_dai[] = {
1874 {
1875 .name = "twl4030",
1876 .playback = {
1877 .stream_name = "Playback",
1878 .channels_min = 2,
1879 .channels_max = 4,
1880 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
1881 .formats = TWL4030_FORMATS,},
1882 .capture = {
1883 .stream_name = "Capture",
1884 .channels_min = 2,
1885 .channels_max = 4,
1886 .rates = TWL4030_RATES,
1887 .formats = TWL4030_FORMATS,},
1888 .ops = &twl4030_dai_ops,
1889 },
1890 {
1891 .name = "twl4030 Voice",
1892 .playback = {
1893 .stream_name = "Playback",
1894 .channels_min = 1,
1895 .channels_max = 1,
1896 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1897 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1898 .capture = {
1899 .stream_name = "Capture",
1900 .channels_min = 1,
1901 .channels_max = 2,
1902 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
1903 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
1904 .ops = &twl4030_dai_voice_ops,
1905 },
1906 };
1907 EXPORT_SYMBOL_GPL(twl4030_dai);
1908
1909 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1910 {
1911 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1912 struct snd_soc_codec *codec = socdev->card->codec;
1913
1914 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1915
1916 return 0;
1917 }
1918
1919 static int twl4030_resume(struct platform_device *pdev)
1920 {
1921 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1922 struct snd_soc_codec *codec = socdev->card->codec;
1923
1924 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1925 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1926 return 0;
1927 }
1928
1929 /*
1930 * initialize the driver
1931 * register the mixer and dsp interfaces with the kernel
1932 */
1933
1934 static int twl4030_init(struct snd_soc_device *socdev)
1935 {
1936 struct snd_soc_codec *codec = socdev->card->codec;
1937 int ret = 0;
1938
1939 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1940
1941 codec->name = "twl4030";
1942 codec->owner = THIS_MODULE;
1943 codec->read = twl4030_read_reg_cache;
1944 codec->write = twl4030_write;
1945 codec->set_bias_level = twl4030_set_bias_level;
1946 codec->dai = twl4030_dai;
1947 codec->num_dai = ARRAY_SIZE(twl4030_dai),
1948 codec->reg_cache_size = sizeof(twl4030_reg);
1949 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1950 GFP_KERNEL);
1951 if (codec->reg_cache == NULL)
1952 return -ENOMEM;
1953
1954 /* register pcms */
1955 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1956 if (ret < 0) {
1957 printk(KERN_ERR "twl4030: failed to create pcms\n");
1958 goto pcm_err;
1959 }
1960
1961 twl4030_init_chip(codec);
1962
1963 /* power on device */
1964 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1965
1966 snd_soc_add_controls(codec, twl4030_snd_controls,
1967 ARRAY_SIZE(twl4030_snd_controls));
1968 twl4030_add_widgets(codec);
1969
1970 ret = snd_soc_init_card(socdev);
1971 if (ret < 0) {
1972 printk(KERN_ERR "twl4030: failed to register card\n");
1973 goto card_err;
1974 }
1975
1976 return ret;
1977
1978 card_err:
1979 snd_soc_free_pcms(socdev);
1980 snd_soc_dapm_free(socdev);
1981 pcm_err:
1982 kfree(codec->reg_cache);
1983 return ret;
1984 }
1985
1986 static struct snd_soc_device *twl4030_socdev;
1987
1988 static int twl4030_probe(struct platform_device *pdev)
1989 {
1990 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1991 struct snd_soc_codec *codec;
1992 struct twl4030_priv *twl4030;
1993
1994 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1995 if (codec == NULL)
1996 return -ENOMEM;
1997
1998 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
1999 if (twl4030 == NULL) {
2000 kfree(codec);
2001 return -ENOMEM;
2002 }
2003
2004 codec->private_data = twl4030;
2005 socdev->card->codec = codec;
2006 mutex_init(&codec->mutex);
2007 INIT_LIST_HEAD(&codec->dapm_widgets);
2008 INIT_LIST_HEAD(&codec->dapm_paths);
2009
2010 twl4030_socdev = socdev;
2011 twl4030_init(socdev);
2012
2013 return 0;
2014 }
2015
2016 static int twl4030_remove(struct platform_device *pdev)
2017 {
2018 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2019 struct snd_soc_codec *codec = socdev->card->codec;
2020
2021 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
2022 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2023 snd_soc_free_pcms(socdev);
2024 snd_soc_dapm_free(socdev);
2025 kfree(codec->private_data);
2026 kfree(codec);
2027
2028 return 0;
2029 }
2030
2031 struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2032 .probe = twl4030_probe,
2033 .remove = twl4030_remove,
2034 .suspend = twl4030_suspend,
2035 .resume = twl4030_resume,
2036 };
2037 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2038
2039 static int __init twl4030_modinit(void)
2040 {
2041 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2042 }
2043 module_init(twl4030_modinit);
2044
2045 static void __exit twl4030_exit(void)
2046 {
2047 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
2048 }
2049 module_exit(twl4030_exit);
2050
2051 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2052 MODULE_AUTHOR("Steve Sakoman");
2053 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards