arch/x86/pci/pci.h

   1 /*
   2  *      Low-Level PCI Access for i386 machines.
   3  *
   4  *      (c) 1999 Martin Mares <mj@ucw.cz>
   5  */
   6
   7 #undef DEBUG
   8
   9 #ifdef DEBUG
  10 #define DBG(x...) printk(x)
  11 #else
  12 #define DBG(x...)
  13 #endif
  14
  15 #define PCI_PROBE_BIOS          0x0001
  16 #define PCI_PROBE_CONF1         0x0002
  17 #define PCI_PROBE_CONF2         0x0004
  18 #define PCI_PROBE_MMCONF        0x0008
  19 #define PCI_PROBE_MASK          0x000f
  20 #define PCI_PROBE_NOEARLY       0x0010
  21
  22 #define PCI_NO_CHECKS           0x0400
  23 #define PCI_USE_PIRQ_MASK       0x0800
  24 #define PCI_ASSIGN_ROMS         0x1000
  25 #define PCI_BIOS_IRQ_SCAN       0x2000
  26 #define PCI_ASSIGN_ALL_BUSSES   0x4000
  27 #define PCI_CAN_SKIP_ISA_ALIGN  0x8000
  28 #define PCI_USE__CRS            0x10000
  29 #define PCI_CHECK_ENABLE_AMD_MMCONF     0x20000
  30 #define PCI_HAS_IO_ECS          0x40000
  31
  32 extern unsigned int pci_probe;
  33 extern unsigned long pirq_table_addr;
  34
  35 enum pci_bf_sort_state {
  36         pci_bf_sort_default,
  37         pci_force_nobf,
  38         pci_force_bf,
  39         pci_dmi_bf,
  40 };
  41
  42 /* pci-i386.c */
  43
  44 extern unsigned int pcibios_max_latency;
  45
  46 void pcibios_resource_survey(void);
  47
  48 /* pci-pc.c */
  49
  50 extern int pcibios_last_bus;
  51 extern struct pci_bus *pci_root_bus;
  52 extern struct pci_ops pci_root_ops;
  53
  54 /* pci-irq.c */
  55
  56 struct irq_info {
  57         u8 bus, devfn;                  /* Bus, device and function */
  58         struct {
  59                 u8 link;                /* IRQ line ID, chipset dependent, 0=not routed */
  60                 u16 bitmap;             /* Available IRQs */
  61         } __attribute__((packed)) irq[4];
  62         u8 slot;                        /* Slot number, 0=onboard */
  63         u8 rfu;
  64 } __attribute__((packed));
  65
  66 struct irq_routing_table {
  67         u32 signature;                  /* PIRQ_SIGNATURE should be here */
  68         u16 version;                    /* PIRQ_VERSION */
  69         u16 size;                       /* Table size in bytes */
  70         u8 rtr_bus, rtr_devfn;          /* Where the interrupt router lies */
  71         u16 exclusive_irqs;             /* IRQs devoted exclusively to PCI usage */
  72         u16 rtr_vendor, rtr_device;     /* Vendor and device ID of interrupt router */
  73         u32 miniport_data;              /* Crap */
  74         u8 rfu[11];
  75         u8 checksum;                    /* Modulo 256 checksum must give zero */
  76         struct irq_info slots[0];
  77 } __attribute__((packed));
  78
  79 extern unsigned int pcibios_irq_mask;
  80
  81 extern int pcibios_scanned;
  82 extern spinlock_t pci_config_lock;
  83
  84 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
  85 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
  86
  87 struct pci_raw_ops {
  88         int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
  89                                                 int reg, int len, u32 *val);
  90         int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
  91                                                 int reg, int len, u32 val);
  92 };
  93
  94 extern struct pci_raw_ops *raw_pci_ops;
  95 extern struct pci_raw_ops *raw_pci_ext_ops;
  96
  97 extern struct pci_raw_ops pci_direct_conf1;
  98
  99 /* arch_initcall level */
 100 extern int pci_direct_probe(void);
 101 extern void pci_direct_init(int type);
 102 extern void pci_pcbios_init(void);
 103 extern int pci_olpc_init(void);
 104 extern void __init dmi_check_pciprobe(void);
 105 extern void __init dmi_check_skip_isa_align(void);
 106
 107 /* some common used subsys_initcalls */
 108 extern int __init pci_acpi_init(void);
 109 extern int __init pcibios_irq_init(void);
 110 extern int __init pci_numa_init(void);
 111 extern int __init pcibios_init(void);
 112
 113 /* pci-mmconfig.c */
 114
 115 extern int __init pci_mmcfg_arch_init(void);
 116 extern void __init pci_mmcfg_arch_free(void);
 117
 118 /*
 119  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 120  * on their northbrige except through the * %eax register. As such, you MUST
 121  * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 122  * accessor functions.
 123  * In fact just use pci_config_*, nothing else please.
 124  */
 125 static inline unsigned char mmio_config_readb(void __iomem *pos)
 126 {
 127         u8 val;
 128         asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
 129         return val;
 130 }
 131
 132 static inline unsigned short mmio_config_readw(void __iomem *pos)
 133 {
 134         u16 val;
 135         asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
 136         return val;
 137 }
 138
 139 static inline unsigned int mmio_config_readl(void __iomem *pos)
 140 {
 141         u32 val;
 142         asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
 143         return val;
 144 }
 145
 146 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
 147 {
 148         asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
 149 }
 150
 151 static inline void mmio_config_writew(void __iomem *pos, u16 val)
 152 {
 153         asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
 154 }
 155
 156 static inline void mmio_config_writel(void __iomem *pos, u32 val)
 157 {
 158         asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
 159 }