2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 void arch_disable_smp_support(void)
106 noioapicreroute
= -1;
108 skip_ioapic_setup
= 1;
111 static int __init
parse_noapic(char *str
)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic
);
122 * This is performance-critical, we want to do it O(1)
124 * the indexing order of this array favors 1:1 mappings
125 * between pins and IRQs.
128 struct irq_pin_list
{
130 struct irq_pin_list
*next
;
133 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
135 struct irq_pin_list
*pin
;
137 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
143 struct irq_pin_list
*irq_2_pin
;
144 cpumask_var_t domain
;
145 cpumask_var_t old_domain
;
146 unsigned move_cleanup_count
;
148 u8 move_in_progress
: 1;
151 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
152 #ifdef CONFIG_SPARSE_IRQ
153 static struct irq_cfg irq_cfgx
[] = {
155 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
157 [0] = { .vector
= IRQ0_VECTOR
, },
158 [1] = { .vector
= IRQ1_VECTOR
, },
159 [2] = { .vector
= IRQ2_VECTOR
, },
160 [3] = { .vector
= IRQ3_VECTOR
, },
161 [4] = { .vector
= IRQ4_VECTOR
, },
162 [5] = { .vector
= IRQ5_VECTOR
, },
163 [6] = { .vector
= IRQ6_VECTOR
, },
164 [7] = { .vector
= IRQ7_VECTOR
, },
165 [8] = { .vector
= IRQ8_VECTOR
, },
166 [9] = { .vector
= IRQ9_VECTOR
, },
167 [10] = { .vector
= IRQ10_VECTOR
, },
168 [11] = { .vector
= IRQ11_VECTOR
, },
169 [12] = { .vector
= IRQ12_VECTOR
, },
170 [13] = { .vector
= IRQ13_VECTOR
, },
171 [14] = { .vector
= IRQ14_VECTOR
, },
172 [15] = { .vector
= IRQ15_VECTOR
, },
175 int __init
arch_early_irq_init(void)
178 struct irq_desc
*desc
;
184 count
= ARRAY_SIZE(irq_cfgx
);
185 node
= cpu_to_node(boot_cpu_id
);
187 for (i
= 0; i
< count
; i
++) {
188 desc
= irq_to_desc(i
);
189 desc
->chip_data
= &cfg
[i
];
190 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
191 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
192 if (i
< NR_IRQS_LEGACY
)
193 cpumask_setall(cfg
[i
].domain
);
199 #ifdef CONFIG_SPARSE_IRQ
200 static struct irq_cfg
*irq_cfg(unsigned int irq
)
202 struct irq_cfg
*cfg
= NULL
;
203 struct irq_desc
*desc
;
205 desc
= irq_to_desc(irq
);
207 cfg
= desc
->chip_data
;
212 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
216 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
218 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
221 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
223 free_cpumask_var(cfg
->domain
);
227 cpumask_clear(cfg
->domain
);
228 cpumask_clear(cfg
->old_domain
);
235 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
239 cfg
= desc
->chip_data
;
241 desc
->chip_data
= get_one_free_irq_cfg(node
);
242 if (!desc
->chip_data
) {
243 printk(KERN_ERR
"can not alloc irq_cfg\n");
251 /* for move_irq_desc */
253 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
255 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
257 cfg
->irq_2_pin
= NULL
;
258 old_entry
= old_cfg
->irq_2_pin
;
262 entry
= get_one_free_irq_2_pin(node
);
266 entry
->apic
= old_entry
->apic
;
267 entry
->pin
= old_entry
->pin
;
270 old_entry
= old_entry
->next
;
272 entry
= get_one_free_irq_2_pin(node
);
280 /* still use the old one */
283 entry
->apic
= old_entry
->apic
;
284 entry
->pin
= old_entry
->pin
;
287 old_entry
= old_entry
->next
;
291 cfg
->irq_2_pin
= head
;
294 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
296 struct irq_pin_list
*entry
, *next
;
298 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
301 entry
= old_cfg
->irq_2_pin
;
308 old_cfg
->irq_2_pin
= NULL
;
311 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
312 struct irq_desc
*desc
, int node
)
315 struct irq_cfg
*old_cfg
;
317 cfg
= get_one_free_irq_cfg(node
);
322 desc
->chip_data
= cfg
;
324 old_cfg
= old_desc
->chip_data
;
326 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
328 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
331 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
336 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
338 struct irq_cfg
*old_cfg
, *cfg
;
340 old_cfg
= old_desc
->chip_data
;
341 cfg
= desc
->chip_data
;
347 free_irq_2_pin(old_cfg
, cfg
);
348 free_irq_cfg(old_cfg
);
349 old_desc
->chip_data
= NULL
;
352 /* end for move_irq_desc */
355 static struct irq_cfg
*irq_cfg(unsigned int irq
)
357 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
364 unsigned int unused
[3];
366 unsigned int unused2
[11];
370 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
372 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
373 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
376 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
378 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
379 writel(vector
, &io_apic
->eoi
);
382 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
384 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
385 writel(reg
, &io_apic
->index
);
386 return readl(&io_apic
->data
);
389 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
391 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
392 writel(reg
, &io_apic
->index
);
393 writel(value
, &io_apic
->data
);
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
400 * Older SiS APIC requires we rewrite the index register
402 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
404 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
407 writel(reg
, &io_apic
->index
);
408 writel(value
, &io_apic
->data
);
411 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
413 struct irq_pin_list
*entry
;
416 spin_lock_irqsave(&ioapic_lock
, flags
);
417 entry
= cfg
->irq_2_pin
;
425 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
426 /* Is the remote IRR bit set? */
427 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
428 spin_unlock_irqrestore(&ioapic_lock
, flags
);
435 spin_unlock_irqrestore(&ioapic_lock
, flags
);
441 struct { u32 w1
, w2
; };
442 struct IO_APIC_route_entry entry
;
445 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
447 union entry_union eu
;
449 spin_lock_irqsave(&ioapic_lock
, flags
);
450 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
451 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
452 spin_unlock_irqrestore(&ioapic_lock
, flags
);
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
463 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
465 union entry_union eu
= {{0, 0}};
468 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
469 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
472 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
475 spin_lock_irqsave(&ioapic_lock
, flags
);
476 __ioapic_write_entry(apic
, pin
, e
);
477 spin_unlock_irqrestore(&ioapic_lock
, flags
);
481 * When we mask an IO APIC routing entry, we need to write the low
482 * word first, in order to set the mask bit before we change the
485 static void ioapic_mask_entry(int apic
, int pin
)
488 union entry_union eu
= { .entry
.mask
= 1 };
490 spin_lock_irqsave(&ioapic_lock
, flags
);
491 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
492 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
493 spin_unlock_irqrestore(&ioapic_lock
, flags
);
497 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
498 * shared ISA-space IRQs, so we have to support them. We are super
499 * fast in the common case, and fast for shared ISA-space IRQs.
501 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
503 struct irq_pin_list
*entry
;
505 entry
= cfg
->irq_2_pin
;
507 entry
= get_one_free_irq_2_pin(node
);
509 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
513 cfg
->irq_2_pin
= entry
;
519 while (entry
->next
) {
520 /* not again, please */
521 if (entry
->apic
== apic
&& entry
->pin
== pin
)
527 entry
->next
= get_one_free_irq_2_pin(node
);
534 * Reroute an IRQ to a different pin.
536 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
537 int oldapic
, int oldpin
,
538 int newapic
, int newpin
)
540 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
544 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
545 entry
->apic
= newapic
;
548 /* every one is different, right? */
554 /* why? call replace before add? */
556 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
559 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
560 int mask_and
, int mask_or
,
561 void (*final
)(struct irq_pin_list
*entry
))
564 struct irq_pin_list
*entry
;
566 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
569 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
572 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
578 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
580 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
584 static void io_apic_sync(struct irq_pin_list
*entry
)
587 * Synchronize the IO-APIC and the CPU by doing
588 * a dummy read from the IO-APIC
590 struct io_apic __iomem
*io_apic
;
591 io_apic
= io_apic_base(entry
->apic
);
592 readl(&io_apic
->data
);
595 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
597 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
599 #else /* CONFIG_X86_32 */
600 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
602 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
605 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
607 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
608 IO_APIC_REDIR_MASKED
, NULL
);
611 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
613 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
614 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
616 #endif /* CONFIG_X86_32 */
618 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
620 struct irq_cfg
*cfg
= desc
->chip_data
;
625 spin_lock_irqsave(&ioapic_lock
, flags
);
626 __mask_IO_APIC_irq(cfg
);
627 spin_unlock_irqrestore(&ioapic_lock
, flags
);
630 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
632 struct irq_cfg
*cfg
= desc
->chip_data
;
635 spin_lock_irqsave(&ioapic_lock
, flags
);
636 __unmask_IO_APIC_irq(cfg
);
637 spin_unlock_irqrestore(&ioapic_lock
, flags
);
640 static void mask_IO_APIC_irq(unsigned int irq
)
642 struct irq_desc
*desc
= irq_to_desc(irq
);
644 mask_IO_APIC_irq_desc(desc
);
646 static void unmask_IO_APIC_irq(unsigned int irq
)
648 struct irq_desc
*desc
= irq_to_desc(irq
);
650 unmask_IO_APIC_irq_desc(desc
);
653 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
655 struct IO_APIC_route_entry entry
;
657 /* Check delivery_mode to be sure we're not clearing an SMI pin */
658 entry
= ioapic_read_entry(apic
, pin
);
659 if (entry
.delivery_mode
== dest_SMI
)
662 * Disable it in the IO-APIC irq-routing table:
664 ioapic_mask_entry(apic
, pin
);
667 static void clear_IO_APIC (void)
671 for (apic
= 0; apic
< nr_ioapics
; apic
++)
672 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
673 clear_IO_APIC_pin(apic
, pin
);
678 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
679 * specific CPU-side IRQs.
683 static int pirq_entries
[MAX_PIRQS
] = {
684 [0 ... MAX_PIRQS
- 1] = -1
687 static int __init
ioapic_pirq_setup(char *str
)
690 int ints
[MAX_PIRQS
+1];
692 get_options(str
, ARRAY_SIZE(ints
), ints
);
694 apic_printk(APIC_VERBOSE
, KERN_INFO
695 "PIRQ redirection, working around broken MP-BIOS.\n");
697 if (ints
[0] < MAX_PIRQS
)
700 for (i
= 0; i
< max
; i
++) {
701 apic_printk(APIC_VERBOSE
, KERN_DEBUG
702 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
704 * PIRQs are mapped upside down, usually.
706 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
711 __setup("pirq=", ioapic_pirq_setup
);
712 #endif /* CONFIG_X86_32 */
714 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
717 struct IO_APIC_route_entry
**ioapic_entries
;
719 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
724 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
725 ioapic_entries
[apic
] =
726 kzalloc(sizeof(struct IO_APIC_route_entry
) *
727 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
728 if (!ioapic_entries
[apic
])
732 return ioapic_entries
;
736 kfree(ioapic_entries
[apic
]);
737 kfree(ioapic_entries
);
743 * Saves all the IO-APIC RTE's
745 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
752 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
753 if (!ioapic_entries
[apic
])
756 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
757 ioapic_entries
[apic
][pin
] =
758 ioapic_read_entry(apic
, pin
);
765 * Mask all IO APIC entries.
767 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
774 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
775 if (!ioapic_entries
[apic
])
778 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
779 struct IO_APIC_route_entry entry
;
781 entry
= ioapic_entries
[apic
][pin
];
784 ioapic_write_entry(apic
, pin
, entry
);
791 * Restore IO APIC entries which was saved in ioapic_entries.
793 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
800 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
801 if (!ioapic_entries
[apic
])
804 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
805 ioapic_write_entry(apic
, pin
,
806 ioapic_entries
[apic
][pin
]);
811 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
815 for (apic
= 0; apic
< nr_ioapics
; apic
++)
816 kfree(ioapic_entries
[apic
]);
818 kfree(ioapic_entries
);
822 * Find the IRQ entry number of a certain pin.
824 static int find_irq_entry(int apic
, int pin
, int type
)
828 for (i
= 0; i
< mp_irq_entries
; i
++)
829 if (mp_irqs
[i
].irqtype
== type
&&
830 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
831 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
832 mp_irqs
[i
].dstirq
== pin
)
839 * Find the pin to which IRQ[irq] (ISA) is connected
841 static int __init
find_isa_irq_pin(int irq
, int type
)
845 for (i
= 0; i
< mp_irq_entries
; i
++) {
846 int lbus
= mp_irqs
[i
].srcbus
;
848 if (test_bit(lbus
, mp_bus_not_pci
) &&
849 (mp_irqs
[i
].irqtype
== type
) &&
850 (mp_irqs
[i
].srcbusirq
== irq
))
852 return mp_irqs
[i
].dstirq
;
857 static int __init
find_isa_irq_apic(int irq
, int type
)
861 for (i
= 0; i
< mp_irq_entries
; i
++) {
862 int lbus
= mp_irqs
[i
].srcbus
;
864 if (test_bit(lbus
, mp_bus_not_pci
) &&
865 (mp_irqs
[i
].irqtype
== type
) &&
866 (mp_irqs
[i
].srcbusirq
== irq
))
869 if (i
< mp_irq_entries
) {
871 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
872 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
880 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
882 * EISA Edge/Level control register, ELCR
884 static int EISA_ELCR(unsigned int irq
)
886 if (irq
< NR_IRQS_LEGACY
) {
887 unsigned int port
= 0x4d0 + (irq
>> 3);
888 return (inb(port
) >> (irq
& 7)) & 1;
890 apic_printk(APIC_VERBOSE
, KERN_INFO
891 "Broken MPtable reports ISA irq %d\n", irq
);
897 /* ISA interrupts are always polarity zero edge triggered,
898 * when listed as conforming in the MP table. */
900 #define default_ISA_trigger(idx) (0)
901 #define default_ISA_polarity(idx) (0)
903 /* EISA interrupts are always polarity zero and can be edge or level
904 * trigger depending on the ELCR value. If an interrupt is listed as
905 * EISA conforming in the MP table, that means its trigger type must
906 * be read in from the ELCR */
908 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
909 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
911 /* PCI interrupts are always polarity one level triggered,
912 * when listed as conforming in the MP table. */
914 #define default_PCI_trigger(idx) (1)
915 #define default_PCI_polarity(idx) (1)
917 /* MCA interrupts are always polarity zero level triggered,
918 * when listed as conforming in the MP table. */
920 #define default_MCA_trigger(idx) (1)
921 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
923 static int MPBIOS_polarity(int idx
)
925 int bus
= mp_irqs
[idx
].srcbus
;
929 * Determine IRQ line polarity (high active or low active):
931 switch (mp_irqs
[idx
].irqflag
& 3)
933 case 0: /* conforms, ie. bus-type dependent polarity */
934 if (test_bit(bus
, mp_bus_not_pci
))
935 polarity
= default_ISA_polarity(idx
);
937 polarity
= default_PCI_polarity(idx
);
939 case 1: /* high active */
944 case 2: /* reserved */
946 printk(KERN_WARNING
"broken BIOS!!\n");
950 case 3: /* low active */
955 default: /* invalid */
957 printk(KERN_WARNING
"broken BIOS!!\n");
965 static int MPBIOS_trigger(int idx
)
967 int bus
= mp_irqs
[idx
].srcbus
;
971 * Determine IRQ trigger mode (edge or level sensitive):
973 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
975 case 0: /* conforms, ie. bus-type dependent */
976 if (test_bit(bus
, mp_bus_not_pci
))
977 trigger
= default_ISA_trigger(idx
);
979 trigger
= default_PCI_trigger(idx
);
980 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
981 switch (mp_bus_id_to_type
[bus
]) {
982 case MP_BUS_ISA
: /* ISA pin */
984 /* set before the switch */
987 case MP_BUS_EISA
: /* EISA pin */
989 trigger
= default_EISA_trigger(idx
);
992 case MP_BUS_PCI
: /* PCI pin */
994 /* set before the switch */
997 case MP_BUS_MCA
: /* MCA pin */
999 trigger
= default_MCA_trigger(idx
);
1004 printk(KERN_WARNING
"broken BIOS!!\n");
1016 case 2: /* reserved */
1018 printk(KERN_WARNING
"broken BIOS!!\n");
1027 default: /* invalid */
1029 printk(KERN_WARNING
"broken BIOS!!\n");
1037 static inline int irq_polarity(int idx
)
1039 return MPBIOS_polarity(idx
);
1042 static inline int irq_trigger(int idx
)
1044 return MPBIOS_trigger(idx
);
1047 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1048 static int pin_2_irq(int idx
, int apic
, int pin
)
1051 int bus
= mp_irqs
[idx
].srcbus
;
1054 * Debugging check, we are in big trouble if this message pops up!
1056 if (mp_irqs
[idx
].dstirq
!= pin
)
1057 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1059 if (test_bit(bus
, mp_bus_not_pci
)) {
1060 irq
= mp_irqs
[idx
].srcbusirq
;
1063 * PCI IRQs are mapped in order
1067 irq
+= nr_ioapic_registers
[i
++];
1070 * For MPS mode, so far only needed by ES7000 platform
1072 if (ioapic_renumber_irq
)
1073 irq
= ioapic_renumber_irq(apic
, irq
);
1076 #ifdef CONFIG_X86_32
1078 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1080 if ((pin
>= 16) && (pin
<= 23)) {
1081 if (pirq_entries
[pin
-16] != -1) {
1082 if (!pirq_entries
[pin
-16]) {
1083 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1084 "disabling PIRQ%d\n", pin
-16);
1086 irq
= pirq_entries
[pin
-16];
1087 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1088 "using PIRQ%d -> IRQ %d\n",
1099 * Find a specific PCI IRQ entry.
1100 * Not an __init, possibly needed by modules
1102 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1103 struct io_apic_irq_attr
*irq_attr
)
1105 int apic
, i
, best_guess
= -1;
1107 apic_printk(APIC_DEBUG
,
1108 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1110 if (test_bit(bus
, mp_bus_not_pci
)) {
1111 apic_printk(APIC_VERBOSE
,
1112 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1115 for (i
= 0; i
< mp_irq_entries
; i
++) {
1116 int lbus
= mp_irqs
[i
].srcbus
;
1118 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1119 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1120 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1123 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1124 !mp_irqs
[i
].irqtype
&&
1126 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1127 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1129 if (!(apic
|| IO_APIC_IRQ(irq
)))
1132 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1133 set_io_apic_irq_attr(irq_attr
, apic
,
1140 * Use the first all-but-pin matching entry as a
1141 * best-guess fuzzy result for broken mptables.
1143 if (best_guess
< 0) {
1144 set_io_apic_irq_attr(irq_attr
, apic
,
1154 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1156 void lock_vector_lock(void)
1158 /* Used to the online set of cpus does not change
1159 * during assign_irq_vector.
1161 spin_lock(&vector_lock
);
1164 void unlock_vector_lock(void)
1166 spin_unlock(&vector_lock
);
1170 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1173 * NOTE! The local APIC isn't very good at handling
1174 * multiple interrupts at the same interrupt level.
1175 * As the interrupt level is determined by taking the
1176 * vector number and shifting that right by 4, we
1177 * want to spread these out a bit so that they don't
1178 * all fall in the same interrupt level.
1180 * Also, we've got to be careful not to trash gate
1181 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1183 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1184 unsigned int old_vector
;
1186 cpumask_var_t tmp_mask
;
1188 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1191 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1194 old_vector
= cfg
->vector
;
1196 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1197 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1198 if (!cpumask_empty(tmp_mask
)) {
1199 free_cpumask_var(tmp_mask
);
1204 /* Only try and allocate irqs on cpus that are present */
1206 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1210 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1212 vector
= current_vector
;
1213 offset
= current_offset
;
1216 if (vector
>= first_system_vector
) {
1217 /* If out of vectors on large boxen, must share them. */
1218 offset
= (offset
+ 1) % 8;
1219 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1221 if (unlikely(current_vector
== vector
))
1224 if (test_bit(vector
, used_vectors
))
1227 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1228 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1231 current_vector
= vector
;
1232 current_offset
= offset
;
1234 cfg
->move_in_progress
= 1;
1235 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1237 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1238 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1239 cfg
->vector
= vector
;
1240 cpumask_copy(cfg
->domain
, tmp_mask
);
1244 free_cpumask_var(tmp_mask
);
1249 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1252 unsigned long flags
;
1254 spin_lock_irqsave(&vector_lock
, flags
);
1255 err
= __assign_irq_vector(irq
, cfg
, mask
);
1256 spin_unlock_irqrestore(&vector_lock
, flags
);
1260 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1264 BUG_ON(!cfg
->vector
);
1266 vector
= cfg
->vector
;
1267 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1268 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1271 cpumask_clear(cfg
->domain
);
1273 if (likely(!cfg
->move_in_progress
))
1275 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1276 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1278 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1280 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1284 cfg
->move_in_progress
= 0;
1287 void __setup_vector_irq(int cpu
)
1289 /* Initialize vector_irq on a new cpu */
1290 /* This function must be called with vector_lock held */
1292 struct irq_cfg
*cfg
;
1293 struct irq_desc
*desc
;
1295 /* Mark the inuse vectors */
1296 for_each_irq_desc(irq
, desc
) {
1297 cfg
= desc
->chip_data
;
1298 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1300 vector
= cfg
->vector
;
1301 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1303 /* Mark the free vectors */
1304 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1305 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1310 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1311 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1315 static struct irq_chip ioapic_chip
;
1316 static struct irq_chip ir_ioapic_chip
;
1318 #define IOAPIC_AUTO -1
1319 #define IOAPIC_EDGE 0
1320 #define IOAPIC_LEVEL 1
1322 #ifdef CONFIG_X86_32
1323 static inline int IO_APIC_irq_trigger(int irq
)
1327 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1328 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1329 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1330 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1331 return irq_trigger(idx
);
1335 * nonexistent IRQs are edge default
1340 static inline int IO_APIC_irq_trigger(int irq
)
1346 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1349 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1350 trigger
== IOAPIC_LEVEL
)
1351 desc
->status
|= IRQ_LEVEL
;
1353 desc
->status
&= ~IRQ_LEVEL
;
1355 if (irq_remapped(irq
)) {
1356 desc
->status
|= IRQ_MOVE_PCNTXT
;
1358 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1362 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1363 handle_edge_irq
, "edge");
1367 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1368 trigger
== IOAPIC_LEVEL
)
1369 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1373 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1374 handle_edge_irq
, "edge");
1377 int setup_ioapic_entry(int apic_id
, int irq
,
1378 struct IO_APIC_route_entry
*entry
,
1379 unsigned int destination
, int trigger
,
1380 int polarity
, int vector
, int pin
)
1383 * add it to the IO-APIC irq-routing table:
1385 memset(entry
,0,sizeof(*entry
));
1387 if (intr_remapping_enabled
) {
1388 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1390 struct IR_IO_APIC_route_entry
*ir_entry
=
1391 (struct IR_IO_APIC_route_entry
*) entry
;
1395 panic("No mapping iommu for ioapic %d\n", apic_id
);
1397 index
= alloc_irte(iommu
, irq
, 1);
1399 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1401 memset(&irte
, 0, sizeof(irte
));
1404 irte
.dst_mode
= apic
->irq_dest_mode
;
1406 * Trigger mode in the IRTE will always be edge, and the
1407 * actual level or edge trigger will be setup in the IO-APIC
1408 * RTE. This will help simplify level triggered irq migration.
1409 * For more details, see the comments above explainig IO-APIC
1410 * irq migration in the presence of interrupt-remapping.
1412 irte
.trigger_mode
= 0;
1413 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1414 irte
.vector
= vector
;
1415 irte
.dest_id
= IRTE_DEST(destination
);
1417 modify_irte(irq
, &irte
);
1419 ir_entry
->index2
= (index
>> 15) & 0x1;
1421 ir_entry
->format
= 1;
1422 ir_entry
->index
= (index
& 0x7fff);
1424 * IO-APIC RTE will be configured with virtual vector.
1425 * irq handler will do the explicit EOI to the io-apic.
1427 ir_entry
->vector
= pin
;
1429 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1430 entry
->dest_mode
= apic
->irq_dest_mode
;
1431 entry
->dest
= destination
;
1432 entry
->vector
= vector
;
1435 entry
->mask
= 0; /* enable IRQ */
1436 entry
->trigger
= trigger
;
1437 entry
->polarity
= polarity
;
1439 /* Mask level triggered irqs.
1440 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1447 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1448 int trigger
, int polarity
)
1450 struct irq_cfg
*cfg
;
1451 struct IO_APIC_route_entry entry
;
1454 if (!IO_APIC_IRQ(irq
))
1457 cfg
= desc
->chip_data
;
1459 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1462 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1464 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1465 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1466 "IRQ %d Mode:%i Active:%i)\n",
1467 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1468 irq
, trigger
, polarity
);
1471 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1472 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1473 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1474 mp_ioapics
[apic_id
].apicid
, pin
);
1475 __clear_irq_vector(irq
, cfg
);
1479 ioapic_register_intr(irq
, desc
, trigger
);
1480 if (irq
< NR_IRQS_LEGACY
)
1481 disable_8259A_irq(irq
);
1483 ioapic_write_entry(apic_id
, pin
, entry
);
1487 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1488 } mp_ioapic_routing
[MAX_IO_APICS
];
1490 static void __init
setup_IO_APIC_irqs(void)
1492 int apic_id
= 0, pin
, idx
, irq
;
1494 struct irq_desc
*desc
;
1495 struct irq_cfg
*cfg
;
1496 int node
= cpu_to_node(boot_cpu_id
);
1498 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1501 if (!acpi_disabled
&& acpi_ioapic
) {
1502 apic_id
= mp_find_ioapic(0);
1508 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1509 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1513 apic_printk(APIC_VERBOSE
,
1514 KERN_DEBUG
" %d-%d",
1515 mp_ioapics
[apic_id
].apicid
, pin
);
1517 apic_printk(APIC_VERBOSE
, " %d-%d",
1518 mp_ioapics
[apic_id
].apicid
, pin
);
1522 apic_printk(APIC_VERBOSE
,
1523 " (apicid-pin) not connected\n");
1527 irq
= pin_2_irq(idx
, apic_id
, pin
);
1530 * Skip the timer IRQ if there's a quirk handler
1531 * installed and if it returns 1:
1533 if (apic
->multi_timer_check
&&
1534 apic
->multi_timer_check(apic_id
, irq
))
1537 desc
= irq_to_desc_alloc_node(irq
, node
);
1539 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1542 cfg
= desc
->chip_data
;
1543 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1545 * don't mark it in pin_programmed, so later acpi could
1546 * set it correctly when irq < 16
1548 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1549 irq_trigger(idx
), irq_polarity(idx
));
1553 apic_printk(APIC_VERBOSE
,
1554 " (apicid-pin) not connected\n");
1558 * Set up the timer pin, possibly with the 8259A-master behind.
1560 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1563 struct IO_APIC_route_entry entry
;
1565 if (intr_remapping_enabled
)
1568 memset(&entry
, 0, sizeof(entry
));
1571 * We use logical delivery to get the timer IRQ
1574 entry
.dest_mode
= apic
->irq_dest_mode
;
1575 entry
.mask
= 0; /* don't mask IRQ for edge */
1576 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1577 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1580 entry
.vector
= vector
;
1583 * The timer IRQ doesn't have to know that behind the
1584 * scene we may have a 8259A-master in AEOI mode ...
1586 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1589 * Add it to the IO-APIC irq-routing table:
1591 ioapic_write_entry(apic_id
, pin
, entry
);
1595 __apicdebuginit(void) print_IO_APIC(void)
1598 union IO_APIC_reg_00 reg_00
;
1599 union IO_APIC_reg_01 reg_01
;
1600 union IO_APIC_reg_02 reg_02
;
1601 union IO_APIC_reg_03 reg_03
;
1602 unsigned long flags
;
1603 struct irq_cfg
*cfg
;
1604 struct irq_desc
*desc
;
1607 if (apic_verbosity
== APIC_QUIET
)
1610 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1611 for (i
= 0; i
< nr_ioapics
; i
++)
1612 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1613 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1616 * We are a bit conservative about what we expect. We have to
1617 * know about every hardware change ASAP.
1619 printk(KERN_INFO
"testing the IO APIC.......................\n");
1621 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1623 spin_lock_irqsave(&ioapic_lock
, flags
);
1624 reg_00
.raw
= io_apic_read(apic
, 0);
1625 reg_01
.raw
= io_apic_read(apic
, 1);
1626 if (reg_01
.bits
.version
>= 0x10)
1627 reg_02
.raw
= io_apic_read(apic
, 2);
1628 if (reg_01
.bits
.version
>= 0x20)
1629 reg_03
.raw
= io_apic_read(apic
, 3);
1630 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1633 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1634 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1635 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1636 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1637 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1639 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1640 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1642 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1643 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1646 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1647 * but the value of reg_02 is read as the previous read register
1648 * value, so ignore it if reg_02 == reg_01.
1650 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1651 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1652 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1656 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1657 * or reg_03, but the value of reg_0[23] is read as the previous read
1658 * register value, so ignore it if reg_03 == reg_0[12].
1660 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1661 reg_03
.raw
!= reg_01
.raw
) {
1662 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1663 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1666 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1668 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1669 " Stat Dmod Deli Vect: \n");
1671 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1672 struct IO_APIC_route_entry entry
;
1674 entry
= ioapic_read_entry(apic
, i
);
1676 printk(KERN_DEBUG
" %02x %03X ",
1681 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1686 entry
.delivery_status
,
1688 entry
.delivery_mode
,
1693 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1694 for_each_irq_desc(irq
, desc
) {
1695 struct irq_pin_list
*entry
;
1697 cfg
= desc
->chip_data
;
1698 entry
= cfg
->irq_2_pin
;
1701 printk(KERN_DEBUG
"IRQ%d ", irq
);
1703 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1706 entry
= entry
->next
;
1711 printk(KERN_INFO
".................................... done.\n");
1716 __apicdebuginit(void) print_APIC_bitfield(int base
)
1721 if (apic_verbosity
== APIC_QUIET
)
1724 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1725 for (i
= 0; i
< 8; i
++) {
1726 v
= apic_read(base
+ i
*0x10);
1727 for (j
= 0; j
< 32; j
++) {
1737 __apicdebuginit(void) print_local_APIC(void *dummy
)
1739 unsigned int i
, v
, ver
, maxlvt
;
1742 if (apic_verbosity
== APIC_QUIET
)
1745 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1746 smp_processor_id(), hard_smp_processor_id());
1747 v
= apic_read(APIC_ID
);
1748 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1749 v
= apic_read(APIC_LVR
);
1750 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1751 ver
= GET_APIC_VERSION(v
);
1752 maxlvt
= lapic_get_maxlvt();
1754 v
= apic_read(APIC_TASKPRI
);
1755 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1757 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1758 if (!APIC_XAPIC(ver
)) {
1759 v
= apic_read(APIC_ARBPRI
);
1760 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1761 v
& APIC_ARBPRI_MASK
);
1763 v
= apic_read(APIC_PROCPRI
);
1764 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1768 * Remote read supported only in the 82489DX and local APIC for
1769 * Pentium processors.
1771 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1772 v
= apic_read(APIC_RRR
);
1773 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1776 v
= apic_read(APIC_LDR
);
1777 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1778 if (!x2apic_enabled()) {
1779 v
= apic_read(APIC_DFR
);
1780 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1782 v
= apic_read(APIC_SPIV
);
1783 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1785 printk(KERN_DEBUG
"... APIC ISR field:\n");
1786 print_APIC_bitfield(APIC_ISR
);
1787 printk(KERN_DEBUG
"... APIC TMR field:\n");
1788 print_APIC_bitfield(APIC_TMR
);
1789 printk(KERN_DEBUG
"... APIC IRR field:\n");
1790 print_APIC_bitfield(APIC_IRR
);
1792 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1793 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1794 apic_write(APIC_ESR
, 0);
1796 v
= apic_read(APIC_ESR
);
1797 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1800 icr
= apic_icr_read();
1801 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1802 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1804 v
= apic_read(APIC_LVTT
);
1805 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1807 if (maxlvt
> 3) { /* PC is LVT#4. */
1808 v
= apic_read(APIC_LVTPC
);
1809 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1811 v
= apic_read(APIC_LVT0
);
1812 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1813 v
= apic_read(APIC_LVT1
);
1814 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1816 if (maxlvt
> 2) { /* ERR is LVT#3. */
1817 v
= apic_read(APIC_LVTERR
);
1818 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1821 v
= apic_read(APIC_TMICT
);
1822 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1823 v
= apic_read(APIC_TMCCT
);
1824 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1825 v
= apic_read(APIC_TDCR
);
1826 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1828 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1829 v
= apic_read(APIC_EFEAT
);
1830 maxlvt
= (v
>> 16) & 0xff;
1831 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1832 v
= apic_read(APIC_ECTRL
);
1833 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1834 for (i
= 0; i
< maxlvt
; i
++) {
1835 v
= apic_read(APIC_EILVTn(i
));
1836 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1842 __apicdebuginit(void) print_all_local_APICs(void)
1847 for_each_online_cpu(cpu
)
1848 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1852 __apicdebuginit(void) print_PIC(void)
1855 unsigned long flags
;
1857 if (apic_verbosity
== APIC_QUIET
)
1860 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1862 spin_lock_irqsave(&i8259A_lock
, flags
);
1864 v
= inb(0xa1) << 8 | inb(0x21);
1865 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1867 v
= inb(0xa0) << 8 | inb(0x20);
1868 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1872 v
= inb(0xa0) << 8 | inb(0x20);
1876 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1878 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1880 v
= inb(0x4d1) << 8 | inb(0x4d0);
1881 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1884 __apicdebuginit(int) print_all_ICs(void)
1888 /* don't print out if apic is not there */
1889 if (!cpu_has_apic
|| disable_apic
)
1892 print_all_local_APICs();
1898 fs_initcall(print_all_ICs
);
1901 /* Where if anywhere is the i8259 connect in external int mode */
1902 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1904 void __init
enable_IO_APIC(void)
1906 union IO_APIC_reg_01 reg_01
;
1907 int i8259_apic
, i8259_pin
;
1909 unsigned long flags
;
1912 * The number of IO-APIC IRQ registers (== #pins):
1914 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1915 spin_lock_irqsave(&ioapic_lock
, flags
);
1916 reg_01
.raw
= io_apic_read(apic
, 1);
1917 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1918 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1920 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1922 /* See if any of the pins is in ExtINT mode */
1923 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1924 struct IO_APIC_route_entry entry
;
1925 entry
= ioapic_read_entry(apic
, pin
);
1927 /* If the interrupt line is enabled and in ExtInt mode
1928 * I have found the pin where the i8259 is connected.
1930 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1931 ioapic_i8259
.apic
= apic
;
1932 ioapic_i8259
.pin
= pin
;
1938 /* Look to see what if the MP table has reported the ExtINT */
1939 /* If we could not find the appropriate pin by looking at the ioapic
1940 * the i8259 probably is not connected the ioapic but give the
1941 * mptable a chance anyway.
1943 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1944 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1945 /* Trust the MP table if nothing is setup in the hardware */
1946 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1947 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1948 ioapic_i8259
.pin
= i8259_pin
;
1949 ioapic_i8259
.apic
= i8259_apic
;
1951 /* Complain if the MP table and the hardware disagree */
1952 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1953 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1955 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1959 * Do not trust the IO-APIC being empty at bootup
1965 * Not an __init, needed by the reboot code
1967 void disable_IO_APIC(void)
1970 * Clear the IO-APIC before rebooting:
1975 * If the i8259 is routed through an IOAPIC
1976 * Put that IOAPIC in virtual wire mode
1977 * so legacy interrupts can be delivered.
1979 * With interrupt-remapping, for now we will use virtual wire A mode,
1980 * as virtual wire B is little complex (need to configure both
1981 * IOAPIC RTE aswell as interrupt-remapping table entry).
1982 * As this gets called during crash dump, keep this simple for now.
1984 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
1985 struct IO_APIC_route_entry entry
;
1987 memset(&entry
, 0, sizeof(entry
));
1988 entry
.mask
= 0; /* Enabled */
1989 entry
.trigger
= 0; /* Edge */
1991 entry
.polarity
= 0; /* High */
1992 entry
.delivery_status
= 0;
1993 entry
.dest_mode
= 0; /* Physical */
1994 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1996 entry
.dest
= read_apic_id();
1999 * Add it to the IO-APIC irq-routing table:
2001 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2005 * Use virtual wire A mode when interrupt remapping is enabled.
2008 disconnect_bsp_APIC(!intr_remapping_enabled
&&
2009 ioapic_i8259
.pin
!= -1);
2012 #ifdef CONFIG_X86_32
2014 * function to set the IO-APIC physical IDs based on the
2015 * values stored in the MPC table.
2017 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2020 static void __init
setup_ioapic_ids_from_mpc(void)
2022 union IO_APIC_reg_00 reg_00
;
2023 physid_mask_t phys_id_present_map
;
2026 unsigned char old_id
;
2027 unsigned long flags
;
2029 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2033 * Don't check I/O APIC IDs for xAPIC systems. They have
2034 * no meaning without the serial APIC bus.
2036 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2037 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2040 * This is broken; anything with a real cpu count has to
2041 * circumvent this idiocy regardless.
2043 phys_id_present_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
2046 * Set the IOAPIC ID to the value stored in the MPC table.
2048 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2050 /* Read the register 0 value */
2051 spin_lock_irqsave(&ioapic_lock
, flags
);
2052 reg_00
.raw
= io_apic_read(apic_id
, 0);
2053 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2055 old_id
= mp_ioapics
[apic_id
].apicid
;
2057 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2058 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2059 apic_id
, mp_ioapics
[apic_id
].apicid
);
2060 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2062 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2066 * Sanity check, is the ID really free? Every APIC in a
2067 * system must have a unique ID or we get lots of nice
2068 * 'stuck on smp_invalidate_needed IPI wait' messages.
2070 if (apic
->check_apicid_used(phys_id_present_map
,
2071 mp_ioapics
[apic_id
].apicid
)) {
2072 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2073 apic_id
, mp_ioapics
[apic_id
].apicid
);
2074 for (i
= 0; i
< get_physical_broadcast(); i
++)
2075 if (!physid_isset(i
, phys_id_present_map
))
2077 if (i
>= get_physical_broadcast())
2078 panic("Max APIC ID exceeded!\n");
2079 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2081 physid_set(i
, phys_id_present_map
);
2082 mp_ioapics
[apic_id
].apicid
= i
;
2085 tmp
= apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
);
2086 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2087 "phys_id_present_map\n",
2088 mp_ioapics
[apic_id
].apicid
);
2089 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2094 * We need to adjust the IRQ routing table
2095 * if the ID changed.
2097 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2098 for (i
= 0; i
< mp_irq_entries
; i
++)
2099 if (mp_irqs
[i
].dstapic
== old_id
)
2101 = mp_ioapics
[apic_id
].apicid
;
2104 * Read the right value from the MPC table and
2105 * write it into the ID register.
2107 apic_printk(APIC_VERBOSE
, KERN_INFO
2108 "...changing IO-APIC physical APIC ID to %d ...",
2109 mp_ioapics
[apic_id
].apicid
);
2111 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2112 spin_lock_irqsave(&ioapic_lock
, flags
);
2113 io_apic_write(apic_id
, 0, reg_00
.raw
);
2114 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2119 spin_lock_irqsave(&ioapic_lock
, flags
);
2120 reg_00
.raw
= io_apic_read(apic_id
, 0);
2121 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2122 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2123 printk("could not set ID!\n");
2125 apic_printk(APIC_VERBOSE
, " ok.\n");
2130 int no_timer_check __initdata
;
2132 static int __init
notimercheck(char *s
)
2137 __setup("no_timer_check", notimercheck
);
2140 * There is a nasty bug in some older SMP boards, their mptable lies
2141 * about the timer IRQ. We do the following to work around the situation:
2143 * - timer IRQ defaults to IO-APIC IRQ
2144 * - if this function detects that timer IRQs are defunct, then we fall
2145 * back to ISA timer IRQs
2147 static int __init
timer_irq_works(void)
2149 unsigned long t1
= jiffies
;
2150 unsigned long flags
;
2155 local_save_flags(flags
);
2157 /* Let ten ticks pass... */
2158 mdelay((10 * 1000) / HZ
);
2159 local_irq_restore(flags
);
2162 * Expect a few ticks at least, to be sure some possible
2163 * glue logic does not lock up after one or two first
2164 * ticks in a non-ExtINT mode. Also the local APIC
2165 * might have cached one ExtINT interrupt. Finally, at
2166 * least one tick may be lost due to delays.
2170 if (time_after(jiffies
, t1
+ 4))
2176 * In the SMP+IOAPIC case it might happen that there are an unspecified
2177 * number of pending IRQ events unhandled. These cases are very rare,
2178 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2179 * better to do it this way as thus we do not have to be aware of
2180 * 'pending' interrupts in the IRQ path, except at this point.
2183 * Edge triggered needs to resend any interrupt
2184 * that was delayed but this is now handled in the device
2189 * Starting up a edge-triggered IO-APIC interrupt is
2190 * nasty - we need to make sure that we get the edge.
2191 * If it is already asserted for some reason, we need
2192 * return 1 to indicate that is was pending.
2194 * This is not complete - we should be able to fake
2195 * an edge even if it isn't on the 8259A...
2198 static unsigned int startup_ioapic_irq(unsigned int irq
)
2200 int was_pending
= 0;
2201 unsigned long flags
;
2202 struct irq_cfg
*cfg
;
2204 spin_lock_irqsave(&ioapic_lock
, flags
);
2205 if (irq
< NR_IRQS_LEGACY
) {
2206 disable_8259A_irq(irq
);
2207 if (i8259A_irq_pending(irq
))
2211 __unmask_IO_APIC_irq(cfg
);
2212 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2217 #ifdef CONFIG_X86_64
2218 static int ioapic_retrigger_irq(unsigned int irq
)
2221 struct irq_cfg
*cfg
= irq_cfg(irq
);
2222 unsigned long flags
;
2224 spin_lock_irqsave(&vector_lock
, flags
);
2225 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2226 spin_unlock_irqrestore(&vector_lock
, flags
);
2231 static int ioapic_retrigger_irq(unsigned int irq
)
2233 apic
->send_IPI_self(irq_cfg(irq
)->vector
);
2240 * Level and edge triggered IO-APIC interrupts need different handling,
2241 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2242 * handled with the level-triggered descriptor, but that one has slightly
2243 * more overhead. Level-triggered interrupts cannot be handled with the
2244 * edge-triggered handler, without risking IRQ storms and other ugly
2249 static void send_cleanup_vector(struct irq_cfg
*cfg
)
2251 cpumask_var_t cleanup_mask
;
2253 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2255 cfg
->move_cleanup_count
= 0;
2256 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2257 cfg
->move_cleanup_count
++;
2258 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2259 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2261 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2262 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
2263 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2264 free_cpumask_var(cleanup_mask
);
2266 cfg
->move_in_progress
= 0;
2269 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2272 struct irq_pin_list
*entry
;
2273 u8 vector
= cfg
->vector
;
2275 entry
= cfg
->irq_2_pin
;
2285 * With interrupt-remapping, destination information comes
2286 * from interrupt-remapping table entry.
2288 if (!irq_remapped(irq
))
2289 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2290 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2291 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2293 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2296 entry
= entry
->next
;
2301 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
2304 * Either sets desc->affinity to a valid value, and returns
2305 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2306 * leaves desc->affinity untouched.
2309 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
2311 struct irq_cfg
*cfg
;
2314 if (!cpumask_intersects(mask
, cpu_online_mask
))
2318 cfg
= desc
->chip_data
;
2319 if (assign_irq_vector(irq
, cfg
, mask
))
2322 cpumask_copy(desc
->affinity
, mask
);
2324 return apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2328 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2330 struct irq_cfg
*cfg
;
2331 unsigned long flags
;
2337 cfg
= desc
->chip_data
;
2339 spin_lock_irqsave(&ioapic_lock
, flags
);
2340 dest
= set_desc_affinity(desc
, mask
);
2341 if (dest
!= BAD_APICID
) {
2342 /* Only the high 8 bits are valid. */
2343 dest
= SET_APIC_LOGICAL_ID(dest
);
2344 __target_IO_APIC_irq(irq
, dest
, cfg
);
2347 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2353 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2355 struct irq_desc
*desc
;
2357 desc
= irq_to_desc(irq
);
2359 return set_ioapic_affinity_irq_desc(desc
, mask
);
2362 #ifdef CONFIG_INTR_REMAP
2365 * Migrate the IO-APIC irq in the presence of intr-remapping.
2367 * For both level and edge triggered, irq migration is a simple atomic
2368 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2370 * For level triggered, we eliminate the io-apic RTE modification (with the
2371 * updated vector information), by using a virtual vector (io-apic pin number).
2372 * Real vector that is used for interrupting cpu will be coming from
2373 * the interrupt-remapping table entry.
2376 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2378 struct irq_cfg
*cfg
;
2384 if (!cpumask_intersects(mask
, cpu_online_mask
))
2388 if (get_irte(irq
, &irte
))
2391 cfg
= desc
->chip_data
;
2392 if (assign_irq_vector(irq
, cfg
, mask
))
2395 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2397 irte
.vector
= cfg
->vector
;
2398 irte
.dest_id
= IRTE_DEST(dest
);
2401 * Modified the IRTE and flushes the Interrupt entry cache.
2403 modify_irte(irq
, &irte
);
2405 if (cfg
->move_in_progress
)
2406 send_cleanup_vector(cfg
);
2408 cpumask_copy(desc
->affinity
, mask
);
2414 * Migrates the IRQ destination in the process context.
2416 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2417 const struct cpumask
*mask
)
2419 return migrate_ioapic_irq_desc(desc
, mask
);
2421 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2422 const struct cpumask
*mask
)
2424 struct irq_desc
*desc
= irq_to_desc(irq
);
2426 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2429 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2430 const struct cpumask
*mask
)
2436 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2438 unsigned vector
, me
;
2444 me
= smp_processor_id();
2445 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2448 struct irq_desc
*desc
;
2449 struct irq_cfg
*cfg
;
2450 irq
= __get_cpu_var(vector_irq
)[vector
];
2455 desc
= irq_to_desc(irq
);
2460 spin_lock(&desc
->lock
);
2461 if (!cfg
->move_cleanup_count
)
2464 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2467 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2469 * Check if the vector that needs to be cleanedup is
2470 * registered at the cpu's IRR. If so, then this is not
2471 * the best time to clean it up. Lets clean it up in the
2472 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2475 if (irr
& (1 << (vector
% 32))) {
2476 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2479 __get_cpu_var(vector_irq
)[vector
] = -1;
2480 cfg
->move_cleanup_count
--;
2482 spin_unlock(&desc
->lock
);
2488 static void irq_complete_move(struct irq_desc
**descp
)
2490 struct irq_desc
*desc
= *descp
;
2491 struct irq_cfg
*cfg
= desc
->chip_data
;
2492 unsigned vector
, me
;
2494 if (likely(!cfg
->move_in_progress
))
2497 vector
= ~get_irq_regs()->orig_ax
;
2498 me
= smp_processor_id();
2500 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2501 send_cleanup_vector(cfg
);
2504 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2507 static void ack_apic_edge(unsigned int irq
)
2509 struct irq_desc
*desc
= irq_to_desc(irq
);
2511 irq_complete_move(&desc
);
2512 move_native_irq(irq
);
2516 atomic_t irq_mis_count
;
2518 static void ack_apic_level(unsigned int irq
)
2520 struct irq_desc
*desc
= irq_to_desc(irq
);
2522 #ifdef CONFIG_X86_32
2526 struct irq_cfg
*cfg
;
2527 int do_unmask_irq
= 0;
2529 irq_complete_move(&desc
);
2530 #ifdef CONFIG_GENERIC_PENDING_IRQ
2531 /* If we are moving the irq we need to mask it */
2532 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2534 mask_IO_APIC_irq_desc(desc
);
2538 #ifdef CONFIG_X86_32
2540 * It appears there is an erratum which affects at least version 0x11
2541 * of I/O APIC (that's the 82093AA and cores integrated into various
2542 * chipsets). Under certain conditions a level-triggered interrupt is
2543 * erroneously delivered as edge-triggered one but the respective IRR
2544 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2545 * message but it will never arrive and further interrupts are blocked
2546 * from the source. The exact reason is so far unknown, but the
2547 * phenomenon was observed when two consecutive interrupt requests
2548 * from a given source get delivered to the same CPU and the source is
2549 * temporarily disabled in between.
2551 * A workaround is to simulate an EOI message manually. We achieve it
2552 * by setting the trigger mode to edge and then to level when the edge
2553 * trigger mode gets detected in the TMR of a local APIC for a
2554 * level-triggered interrupt. We mask the source for the time of the
2555 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2556 * The idea is from Manfred Spraul. --macro
2558 cfg
= desc
->chip_data
;
2561 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2565 * We must acknowledge the irq before we move it or the acknowledge will
2566 * not propagate properly.
2570 /* Now we can move and renable the irq */
2571 if (unlikely(do_unmask_irq
)) {
2572 /* Only migrate the irq if the ack has been received.
2574 * On rare occasions the broadcast level triggered ack gets
2575 * delayed going to ioapics, and if we reprogram the
2576 * vector while Remote IRR is still set the irq will never
2579 * To prevent this scenario we read the Remote IRR bit
2580 * of the ioapic. This has two effects.
2581 * - On any sane system the read of the ioapic will
2582 * flush writes (and acks) going to the ioapic from
2584 * - We get to see if the ACK has actually been delivered.
2586 * Based on failed experiments of reprogramming the
2587 * ioapic entry from outside of irq context starting
2588 * with masking the ioapic entry and then polling until
2589 * Remote IRR was clear before reprogramming the
2590 * ioapic I don't trust the Remote IRR bit to be
2591 * completey accurate.
2593 * However there appears to be no other way to plug
2594 * this race, so if the Remote IRR bit is not
2595 * accurate and is causing problems then it is a hardware bug
2596 * and you can go talk to the chipset vendor about it.
2598 cfg
= desc
->chip_data
;
2599 if (!io_apic_level_ack_pending(cfg
))
2600 move_masked_irq(irq
);
2601 unmask_IO_APIC_irq_desc(desc
);
2604 #ifdef CONFIG_X86_32
2605 if (!(v
& (1 << (i
& 0x1f)))) {
2606 atomic_inc(&irq_mis_count
);
2607 spin_lock(&ioapic_lock
);
2608 __mask_and_edge_IO_APIC_irq(cfg
);
2609 __unmask_and_level_IO_APIC_irq(cfg
);
2610 spin_unlock(&ioapic_lock
);
2615 #ifdef CONFIG_INTR_REMAP
2616 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2619 struct irq_pin_list
*entry
;
2621 entry
= cfg
->irq_2_pin
;
2629 io_apic_eoi(apic
, pin
);
2630 entry
= entry
->next
;
2635 eoi_ioapic_irq(struct irq_desc
*desc
)
2637 struct irq_cfg
*cfg
;
2638 unsigned long flags
;
2642 cfg
= desc
->chip_data
;
2644 spin_lock_irqsave(&ioapic_lock
, flags
);
2645 __eoi_ioapic_irq(irq
, cfg
);
2646 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2649 static void ir_ack_apic_edge(unsigned int irq
)
2654 static void ir_ack_apic_level(unsigned int irq
)
2656 struct irq_desc
*desc
= irq_to_desc(irq
);
2659 eoi_ioapic_irq(desc
);
2661 #endif /* CONFIG_INTR_REMAP */
2663 static struct irq_chip ioapic_chip __read_mostly
= {
2665 .startup
= startup_ioapic_irq
,
2666 .mask
= mask_IO_APIC_irq
,
2667 .unmask
= unmask_IO_APIC_irq
,
2668 .ack
= ack_apic_edge
,
2669 .eoi
= ack_apic_level
,
2671 .set_affinity
= set_ioapic_affinity_irq
,
2673 .retrigger
= ioapic_retrigger_irq
,
2676 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2677 .name
= "IR-IO-APIC",
2678 .startup
= startup_ioapic_irq
,
2679 .mask
= mask_IO_APIC_irq
,
2680 .unmask
= unmask_IO_APIC_irq
,
2681 #ifdef CONFIG_INTR_REMAP
2682 .ack
= ir_ack_apic_edge
,
2683 .eoi
= ir_ack_apic_level
,
2685 .set_affinity
= set_ir_ioapic_affinity_irq
,
2688 .retrigger
= ioapic_retrigger_irq
,
2691 static inline void init_IO_APIC_traps(void)
2694 struct irq_desc
*desc
;
2695 struct irq_cfg
*cfg
;
2698 * NOTE! The local APIC isn't very good at handling
2699 * multiple interrupts at the same interrupt level.
2700 * As the interrupt level is determined by taking the
2701 * vector number and shifting that right by 4, we
2702 * want to spread these out a bit so that they don't
2703 * all fall in the same interrupt level.
2705 * Also, we've got to be careful not to trash gate
2706 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2708 for_each_irq_desc(irq
, desc
) {
2709 cfg
= desc
->chip_data
;
2710 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2712 * Hmm.. We don't have an entry for this,
2713 * so default to an old-fashioned 8259
2714 * interrupt if we can..
2716 if (irq
< NR_IRQS_LEGACY
)
2717 make_8259A_irq(irq
);
2719 /* Strange. Oh, well.. */
2720 desc
->chip
= &no_irq_chip
;
2726 * The local APIC irq-chip implementation:
2729 static void mask_lapic_irq(unsigned int irq
)
2733 v
= apic_read(APIC_LVT0
);
2734 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2737 static void unmask_lapic_irq(unsigned int irq
)
2741 v
= apic_read(APIC_LVT0
);
2742 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2745 static void ack_lapic_irq(unsigned int irq
)
2750 static struct irq_chip lapic_chip __read_mostly
= {
2751 .name
= "local-APIC",
2752 .mask
= mask_lapic_irq
,
2753 .unmask
= unmask_lapic_irq
,
2754 .ack
= ack_lapic_irq
,
2757 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2759 desc
->status
&= ~IRQ_LEVEL
;
2760 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2764 static void __init
setup_nmi(void)
2767 * Dirty trick to enable the NMI watchdog ...
2768 * We put the 8259A master into AEOI mode and
2769 * unmask on all local APICs LVT0 as NMI.
2771 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2772 * is from Maciej W. Rozycki - so we do not have to EOI from
2773 * the NMI handler or the timer interrupt.
2775 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2777 enable_NMI_through_LVT0();
2779 apic_printk(APIC_VERBOSE
, " done.\n");
2783 * This looks a bit hackish but it's about the only one way of sending
2784 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2785 * not support the ExtINT mode, unfortunately. We need to send these
2786 * cycles as some i82489DX-based boards have glue logic that keeps the
2787 * 8259A interrupt line asserted until INTA. --macro
2789 static inline void __init
unlock_ExtINT_logic(void)
2792 struct IO_APIC_route_entry entry0
, entry1
;
2793 unsigned char save_control
, save_freq_select
;
2795 pin
= find_isa_irq_pin(8, mp_INT
);
2800 apic
= find_isa_irq_apic(8, mp_INT
);
2806 entry0
= ioapic_read_entry(apic
, pin
);
2807 clear_IO_APIC_pin(apic
, pin
);
2809 memset(&entry1
, 0, sizeof(entry1
));
2811 entry1
.dest_mode
= 0; /* physical delivery */
2812 entry1
.mask
= 0; /* unmask IRQ now */
2813 entry1
.dest
= hard_smp_processor_id();
2814 entry1
.delivery_mode
= dest_ExtINT
;
2815 entry1
.polarity
= entry0
.polarity
;
2819 ioapic_write_entry(apic
, pin
, entry1
);
2821 save_control
= CMOS_READ(RTC_CONTROL
);
2822 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2823 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2825 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2830 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2834 CMOS_WRITE(save_control
, RTC_CONTROL
);
2835 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2836 clear_IO_APIC_pin(apic
, pin
);
2838 ioapic_write_entry(apic
, pin
, entry0
);
2841 static int disable_timer_pin_1 __initdata
;
2842 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2843 static int __init
disable_timer_pin_setup(char *arg
)
2845 disable_timer_pin_1
= 1;
2848 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2850 int timer_through_8259 __initdata
;
2853 * This code may look a bit paranoid, but it's supposed to cooperate with
2854 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2855 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2856 * fanatically on his truly buggy board.
2858 * FIXME: really need to revamp this for all platforms.
2860 static inline void __init
check_timer(void)
2862 struct irq_desc
*desc
= irq_to_desc(0);
2863 struct irq_cfg
*cfg
= desc
->chip_data
;
2864 int node
= cpu_to_node(boot_cpu_id
);
2865 int apic1
, pin1
, apic2
, pin2
;
2866 unsigned long flags
;
2869 local_irq_save(flags
);
2872 * get/set the timer IRQ vector:
2874 disable_8259A_irq(0);
2875 assign_irq_vector(0, cfg
, apic
->target_cpus());
2878 * As IRQ0 is to be enabled in the 8259A, the virtual
2879 * wire has to be disabled in the local APIC. Also
2880 * timer interrupts need to be acknowledged manually in
2881 * the 8259A for the i82489DX when using the NMI
2882 * watchdog as that APIC treats NMIs as level-triggered.
2883 * The AEOI mode will finish them in the 8259A
2886 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2888 #ifdef CONFIG_X86_32
2892 ver
= apic_read(APIC_LVR
);
2893 ver
= GET_APIC_VERSION(ver
);
2894 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2898 pin1
= find_isa_irq_pin(0, mp_INT
);
2899 apic1
= find_isa_irq_apic(0, mp_INT
);
2900 pin2
= ioapic_i8259
.pin
;
2901 apic2
= ioapic_i8259
.apic
;
2903 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2904 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2905 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2908 * Some BIOS writers are clueless and report the ExtINTA
2909 * I/O APIC input from the cascaded 8259A as the timer
2910 * interrupt input. So just in case, if only one pin
2911 * was found above, try it both directly and through the
2915 if (intr_remapping_enabled
)
2916 panic("BIOS bug: timer not connected to IO-APIC");
2920 } else if (pin2
== -1) {
2927 * Ok, does IRQ0 through the IOAPIC work?
2930 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2931 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2933 /* for edge trigger, setup_IO_APIC_irq already
2934 * leave it unmasked.
2935 * so only need to unmask if it is level-trigger
2936 * do we really have level trigger timer?
2939 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2940 if (idx
!= -1 && irq_trigger(idx
))
2941 unmask_IO_APIC_irq_desc(desc
);
2943 if (timer_irq_works()) {
2944 if (nmi_watchdog
== NMI_IO_APIC
) {
2946 enable_8259A_irq(0);
2948 if (disable_timer_pin_1
> 0)
2949 clear_IO_APIC_pin(0, pin1
);
2952 if (intr_remapping_enabled
)
2953 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2954 local_irq_disable();
2955 clear_IO_APIC_pin(apic1
, pin1
);
2957 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2958 "8254 timer not connected to IO-APIC\n");
2960 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2961 "(IRQ0) through the 8259A ...\n");
2962 apic_printk(APIC_QUIET
, KERN_INFO
2963 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2965 * legacy devices should be connected to IO APIC #0
2967 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2968 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2969 enable_8259A_irq(0);
2970 if (timer_irq_works()) {
2971 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2972 timer_through_8259
= 1;
2973 if (nmi_watchdog
== NMI_IO_APIC
) {
2974 disable_8259A_irq(0);
2976 enable_8259A_irq(0);
2981 * Cleanup, just in case ...
2983 local_irq_disable();
2984 disable_8259A_irq(0);
2985 clear_IO_APIC_pin(apic2
, pin2
);
2986 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2989 if (nmi_watchdog
== NMI_IO_APIC
) {
2990 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2991 "through the IO-APIC - disabling NMI Watchdog!\n");
2992 nmi_watchdog
= NMI_NONE
;
2994 #ifdef CONFIG_X86_32
2998 apic_printk(APIC_QUIET
, KERN_INFO
2999 "...trying to set up timer as Virtual Wire IRQ...\n");
3001 lapic_register_intr(0, desc
);
3002 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3003 enable_8259A_irq(0);
3005 if (timer_irq_works()) {
3006 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3009 local_irq_disable();
3010 disable_8259A_irq(0);
3011 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3012 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3014 apic_printk(APIC_QUIET
, KERN_INFO
3015 "...trying to set up timer as ExtINT IRQ...\n");
3019 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3021 unlock_ExtINT_logic();
3023 if (timer_irq_works()) {
3024 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3027 local_irq_disable();
3028 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3029 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3030 "report. Then try booting with the 'noapic' option.\n");
3032 local_irq_restore(flags
);
3036 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3037 * to devices. However there may be an I/O APIC pin available for
3038 * this interrupt regardless. The pin may be left unconnected, but
3039 * typically it will be reused as an ExtINT cascade interrupt for
3040 * the master 8259A. In the MPS case such a pin will normally be
3041 * reported as an ExtINT interrupt in the MP table. With ACPI
3042 * there is no provision for ExtINT interrupts, and in the absence
3043 * of an override it would be treated as an ordinary ISA I/O APIC
3044 * interrupt, that is edge-triggered and unmasked by default. We
3045 * used to do this, but it caused problems on some systems because
3046 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3047 * the same ExtINT cascade interrupt to drive the local APIC of the
3048 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3049 * the I/O APIC in all cases now. No actual device should request
3050 * it anyway. --macro
3052 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3054 void __init
setup_IO_APIC(void)
3058 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3061 io_apic_irqs
= ~PIC_IRQS
;
3063 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3065 * Set up IO-APIC IRQ routing.
3067 #ifdef CONFIG_X86_32
3069 setup_ioapic_ids_from_mpc();
3072 setup_IO_APIC_irqs();
3073 init_IO_APIC_traps();
3078 * Called after all the initialization is done. If we didnt find any
3079 * APIC bugs then we can allow the modify fast path
3082 static int __init
io_apic_bug_finalize(void)
3084 if (sis_apic_bug
== -1)
3089 late_initcall(io_apic_bug_finalize
);
3091 struct sysfs_ioapic_data
{
3092 struct sys_device dev
;
3093 struct IO_APIC_route_entry entry
[0];
3095 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3097 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3099 struct IO_APIC_route_entry
*entry
;
3100 struct sysfs_ioapic_data
*data
;
3103 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3104 entry
= data
->entry
;
3105 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3106 *entry
= ioapic_read_entry(dev
->id
, i
);
3111 static int ioapic_resume(struct sys_device
*dev
)
3113 struct IO_APIC_route_entry
*entry
;
3114 struct sysfs_ioapic_data
*data
;
3115 unsigned long flags
;
3116 union IO_APIC_reg_00 reg_00
;
3119 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3120 entry
= data
->entry
;
3122 spin_lock_irqsave(&ioapic_lock
, flags
);
3123 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3124 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3125 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3126 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3128 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3129 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3130 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3135 static struct sysdev_class ioapic_sysdev_class
= {
3137 .suspend
= ioapic_suspend
,
3138 .resume
= ioapic_resume
,
3141 static int __init
ioapic_init_sysfs(void)
3143 struct sys_device
* dev
;
3146 error
= sysdev_class_register(&ioapic_sysdev_class
);
3150 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3151 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3152 * sizeof(struct IO_APIC_route_entry
);
3153 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3154 if (!mp_ioapic_data
[i
]) {
3155 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3158 dev
= &mp_ioapic_data
[i
]->dev
;
3160 dev
->cls
= &ioapic_sysdev_class
;
3161 error
= sysdev_register(dev
);
3163 kfree(mp_ioapic_data
[i
]);
3164 mp_ioapic_data
[i
] = NULL
;
3165 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3173 device_initcall(ioapic_init_sysfs
);
3175 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3177 * Dynamic irq allocate and deallocation
3179 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3181 /* Allocate an unused irq */
3184 unsigned long flags
;
3185 struct irq_cfg
*cfg_new
= NULL
;
3186 struct irq_desc
*desc_new
= NULL
;
3189 if (irq_want
< nr_irqs_gsi
)
3190 irq_want
= nr_irqs_gsi
;
3192 spin_lock_irqsave(&vector_lock
, flags
);
3193 for (new = irq_want
; new < nr_irqs
; new++) {
3194 desc_new
= irq_to_desc_alloc_node(new, node
);
3196 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3199 cfg_new
= desc_new
->chip_data
;
3201 if (cfg_new
->vector
!= 0)
3204 desc_new
= move_irq_desc(desc_new
, node
);
3206 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3210 spin_unlock_irqrestore(&vector_lock
, flags
);
3213 dynamic_irq_init(irq
);
3214 /* restore it, in case dynamic_irq_init clear it */
3216 desc_new
->chip_data
= cfg_new
;
3221 int create_irq(void)
3223 int node
= cpu_to_node(boot_cpu_id
);
3224 unsigned int irq_want
;
3227 irq_want
= nr_irqs_gsi
;
3228 irq
= create_irq_nr(irq_want
, node
);
3236 void destroy_irq(unsigned int irq
)
3238 unsigned long flags
;
3239 struct irq_cfg
*cfg
;
3240 struct irq_desc
*desc
;
3242 /* store it, in case dynamic_irq_cleanup clear it */
3243 desc
= irq_to_desc(irq
);
3244 cfg
= desc
->chip_data
;
3245 dynamic_irq_cleanup(irq
);
3246 /* connect back irq_cfg */
3248 desc
->chip_data
= cfg
;
3251 spin_lock_irqsave(&vector_lock
, flags
);
3252 __clear_irq_vector(irq
, cfg
);
3253 spin_unlock_irqrestore(&vector_lock
, flags
);
3257 * MSI message composition
3259 #ifdef CONFIG_PCI_MSI
3260 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3262 struct irq_cfg
*cfg
;
3270 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3274 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3276 if (irq_remapped(irq
)) {
3281 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3282 BUG_ON(ir_index
== -1);
3284 memset (&irte
, 0, sizeof(irte
));
3287 irte
.dst_mode
= apic
->irq_dest_mode
;
3288 irte
.trigger_mode
= 0; /* edge */
3289 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3290 irte
.vector
= cfg
->vector
;
3291 irte
.dest_id
= IRTE_DEST(dest
);
3293 modify_irte(irq
, &irte
);
3295 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3296 msg
->data
= sub_handle
;
3297 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3299 MSI_ADDR_IR_INDEX1(ir_index
) |
3300 MSI_ADDR_IR_INDEX2(ir_index
);
3302 if (x2apic_enabled())
3303 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3304 MSI_ADDR_EXT_DEST_ID(dest
);
3306 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3310 ((apic
->irq_dest_mode
== 0) ?
3311 MSI_ADDR_DEST_MODE_PHYSICAL
:
3312 MSI_ADDR_DEST_MODE_LOGICAL
) |
3313 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3314 MSI_ADDR_REDIRECTION_CPU
:
3315 MSI_ADDR_REDIRECTION_LOWPRI
) |
3316 MSI_ADDR_DEST_ID(dest
);
3319 MSI_DATA_TRIGGER_EDGE
|
3320 MSI_DATA_LEVEL_ASSERT
|
3321 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3322 MSI_DATA_DELIVERY_FIXED
:
3323 MSI_DATA_DELIVERY_LOWPRI
) |
3324 MSI_DATA_VECTOR(cfg
->vector
);
3330 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3332 struct irq_desc
*desc
= irq_to_desc(irq
);
3333 struct irq_cfg
*cfg
;
3337 dest
= set_desc_affinity(desc
, mask
);
3338 if (dest
== BAD_APICID
)
3341 cfg
= desc
->chip_data
;
3343 read_msi_msg_desc(desc
, &msg
);
3345 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3346 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3347 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3348 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3350 write_msi_msg_desc(desc
, &msg
);
3354 #ifdef CONFIG_INTR_REMAP
3356 * Migrate the MSI irq to another cpumask. This migration is
3357 * done in the process context using interrupt-remapping hardware.
3360 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3362 struct irq_desc
*desc
= irq_to_desc(irq
);
3363 struct irq_cfg
*cfg
= desc
->chip_data
;
3367 if (get_irte(irq
, &irte
))
3370 dest
= set_desc_affinity(desc
, mask
);
3371 if (dest
== BAD_APICID
)
3374 irte
.vector
= cfg
->vector
;
3375 irte
.dest_id
= IRTE_DEST(dest
);
3378 * atomically update the IRTE with the new destination and vector.
3380 modify_irte(irq
, &irte
);
3383 * After this point, all the interrupts will start arriving
3384 * at the new destination. So, time to cleanup the previous
3385 * vector allocation.
3387 if (cfg
->move_in_progress
)
3388 send_cleanup_vector(cfg
);
3394 #endif /* CONFIG_SMP */
3397 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3398 * which implement the MSI or MSI-X Capability Structure.
3400 static struct irq_chip msi_chip
= {
3402 .unmask
= unmask_msi_irq
,
3403 .mask
= mask_msi_irq
,
3404 .ack
= ack_apic_edge
,
3406 .set_affinity
= set_msi_irq_affinity
,
3408 .retrigger
= ioapic_retrigger_irq
,
3411 static struct irq_chip msi_ir_chip
= {
3412 .name
= "IR-PCI-MSI",
3413 .unmask
= unmask_msi_irq
,
3414 .mask
= mask_msi_irq
,
3415 #ifdef CONFIG_INTR_REMAP
3416 .ack
= ir_ack_apic_edge
,
3418 .set_affinity
= ir_set_msi_irq_affinity
,
3421 .retrigger
= ioapic_retrigger_irq
,
3425 * Map the PCI dev to the corresponding remapping hardware unit
3426 * and allocate 'nvec' consecutive interrupt-remapping table entries
3429 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3431 struct intel_iommu
*iommu
;
3434 iommu
= map_dev_to_ir(dev
);
3437 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3441 index
= alloc_irte(iommu
, irq
, nvec
);
3444 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3451 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3456 ret
= msi_compose_msg(dev
, irq
, &msg
);
3460 set_irq_msi(irq
, msidesc
);
3461 write_msi_msg(irq
, &msg
);
3463 if (irq_remapped(irq
)) {
3464 struct irq_desc
*desc
= irq_to_desc(irq
);
3466 * irq migration in process context
3468 desc
->status
|= IRQ_MOVE_PCNTXT
;
3469 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3471 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3473 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3478 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3481 int ret
, sub_handle
;
3482 struct msi_desc
*msidesc
;
3483 unsigned int irq_want
;
3484 struct intel_iommu
*iommu
= NULL
;
3488 /* x86 doesn't support multiple MSI yet */
3489 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3492 node
= dev_to_node(&dev
->dev
);
3493 irq_want
= nr_irqs_gsi
;
3495 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3496 irq
= create_irq_nr(irq_want
, node
);
3500 if (!intr_remapping_enabled
)
3505 * allocate the consecutive block of IRTE's
3508 index
= msi_alloc_irte(dev
, irq
, nvec
);
3514 iommu
= map_dev_to_ir(dev
);
3520 * setup the mapping between the irq and the IRTE
3521 * base index, the sub_handle pointing to the
3522 * appropriate interrupt remap table entry.
3524 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3527 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3539 void arch_teardown_msi_irq(unsigned int irq
)
3544 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3546 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3548 struct irq_desc
*desc
= irq_to_desc(irq
);
3549 struct irq_cfg
*cfg
;
3553 dest
= set_desc_affinity(desc
, mask
);
3554 if (dest
== BAD_APICID
)
3557 cfg
= desc
->chip_data
;
3559 dmar_msi_read(irq
, &msg
);
3561 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3562 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3563 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3564 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3566 dmar_msi_write(irq
, &msg
);
3571 #endif /* CONFIG_SMP */
3573 static struct irq_chip dmar_msi_type
= {
3575 .unmask
= dmar_msi_unmask
,
3576 .mask
= dmar_msi_mask
,
3577 .ack
= ack_apic_edge
,
3579 .set_affinity
= dmar_msi_set_affinity
,
3581 .retrigger
= ioapic_retrigger_irq
,
3584 int arch_setup_dmar_msi(unsigned int irq
)
3589 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3592 dmar_msi_write(irq
, &msg
);
3593 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3599 #ifdef CONFIG_HPET_TIMER
3602 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3604 struct irq_desc
*desc
= irq_to_desc(irq
);
3605 struct irq_cfg
*cfg
;
3609 dest
= set_desc_affinity(desc
, mask
);
3610 if (dest
== BAD_APICID
)
3613 cfg
= desc
->chip_data
;
3615 hpet_msi_read(irq
, &msg
);
3617 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3618 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3619 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3620 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3622 hpet_msi_write(irq
, &msg
);
3627 #endif /* CONFIG_SMP */
3629 static struct irq_chip hpet_msi_type
= {
3631 .unmask
= hpet_msi_unmask
,
3632 .mask
= hpet_msi_mask
,
3633 .ack
= ack_apic_edge
,
3635 .set_affinity
= hpet_msi_set_affinity
,
3637 .retrigger
= ioapic_retrigger_irq
,
3640 int arch_setup_hpet_msi(unsigned int irq
)
3644 struct irq_desc
*desc
= irq_to_desc(irq
);
3646 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3650 hpet_msi_write(irq
, &msg
);
3651 desc
->status
|= IRQ_MOVE_PCNTXT
;
3652 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3659 #endif /* CONFIG_PCI_MSI */
3661 * Hypertransport interrupt support
3663 #ifdef CONFIG_HT_IRQ
3667 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3669 struct ht_irq_msg msg
;
3670 fetch_ht_irq_msg(irq
, &msg
);
3672 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3673 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3675 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3676 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3678 write_ht_irq_msg(irq
, &msg
);
3681 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3683 struct irq_desc
*desc
= irq_to_desc(irq
);
3684 struct irq_cfg
*cfg
;
3687 dest
= set_desc_affinity(desc
, mask
);
3688 if (dest
== BAD_APICID
)
3691 cfg
= desc
->chip_data
;
3693 target_ht_irq(irq
, dest
, cfg
->vector
);
3700 static struct irq_chip ht_irq_chip
= {
3702 .mask
= mask_ht_irq
,
3703 .unmask
= unmask_ht_irq
,
3704 .ack
= ack_apic_edge
,
3706 .set_affinity
= set_ht_irq_affinity
,
3708 .retrigger
= ioapic_retrigger_irq
,
3711 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3713 struct irq_cfg
*cfg
;
3720 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3722 struct ht_irq_msg msg
;
3725 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3726 apic
->target_cpus());
3728 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3732 HT_IRQ_LOW_DEST_ID(dest
) |
3733 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3734 ((apic
->irq_dest_mode
== 0) ?
3735 HT_IRQ_LOW_DM_PHYSICAL
:
3736 HT_IRQ_LOW_DM_LOGICAL
) |
3737 HT_IRQ_LOW_RQEOI_EDGE
|
3738 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3739 HT_IRQ_LOW_MT_FIXED
:
3740 HT_IRQ_LOW_MT_ARBITRATED
) |
3741 HT_IRQ_LOW_IRQ_MASKED
;
3743 write_ht_irq_msg(irq
, &msg
);
3745 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3746 handle_edge_irq
, "edge");
3748 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3752 #endif /* CONFIG_HT_IRQ */
3754 #ifdef CONFIG_X86_UV
3756 * Re-target the irq to the specified CPU and enable the specified MMR located
3757 * on the specified blade to allow the sending of MSIs to the specified CPU.
3759 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3760 unsigned long mmr_offset
)
3762 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3763 struct irq_cfg
*cfg
;
3765 unsigned long mmr_value
;
3766 struct uv_IO_APIC_route_entry
*entry
;
3767 unsigned long flags
;
3770 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3774 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3778 spin_lock_irqsave(&vector_lock
, flags
);
3779 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3781 spin_unlock_irqrestore(&vector_lock
, flags
);
3784 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3785 entry
->vector
= cfg
->vector
;
3786 entry
->delivery_mode
= apic
->irq_delivery_mode
;
3787 entry
->dest_mode
= apic
->irq_dest_mode
;
3788 entry
->polarity
= 0;
3791 entry
->dest
= apic
->cpu_mask_to_apicid(eligible_cpu
);
3793 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3794 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3800 * Disable the specified MMR located on the specified blade so that MSIs are
3801 * longer allowed to be sent.
3803 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3805 unsigned long mmr_value
;
3806 struct uv_IO_APIC_route_entry
*entry
;
3809 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3812 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3815 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3816 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3818 #endif /* CONFIG_X86_64 */
3820 int __init
io_apic_get_redir_entries (int ioapic
)
3822 union IO_APIC_reg_01 reg_01
;
3823 unsigned long flags
;
3825 spin_lock_irqsave(&ioapic_lock
, flags
);
3826 reg_01
.raw
= io_apic_read(ioapic
, 1);
3827 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3829 return reg_01
.bits
.entries
;
3832 void __init
probe_nr_irqs_gsi(void)
3836 nr
= acpi_probe_gsi();
3837 if (nr
> nr_irqs_gsi
) {
3840 /* for acpi=off or acpi is not compiled in */
3844 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3845 nr
+= io_apic_get_redir_entries(idx
) + 1;
3847 if (nr
> nr_irqs_gsi
)
3851 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3854 #ifdef CONFIG_SPARSE_IRQ
3855 int __init
arch_probe_nr_irqs(void)
3859 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3860 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3862 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3863 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3865 * for MSI and HT dyn irq
3867 nr
+= nr_irqs_gsi
* 16;
3876 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3877 struct io_apic_irq_attr
*irq_attr
)
3879 struct irq_desc
*desc
;
3880 struct irq_cfg
*cfg
;
3883 int trigger
, polarity
;
3885 ioapic
= irq_attr
->ioapic
;
3886 if (!IO_APIC_IRQ(irq
)) {
3887 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3893 node
= dev_to_node(dev
);
3895 node
= cpu_to_node(boot_cpu_id
);
3897 desc
= irq_to_desc_alloc_node(irq
, node
);
3899 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3903 pin
= irq_attr
->ioapic_pin
;
3904 trigger
= irq_attr
->trigger
;
3905 polarity
= irq_attr
->polarity
;
3908 * IRQs < 16 are already in the irq_2_pin[] map
3910 if (irq
>= NR_IRQS_LEGACY
) {
3911 cfg
= desc
->chip_data
;
3912 add_pin_to_irq_node(cfg
, node
, ioapic
, pin
);
3915 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3920 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3921 struct io_apic_irq_attr
*irq_attr
)
3925 * Avoid pin reprogramming. PRTs typically include entries
3926 * with redundant pin->gsi mappings (but unique PCI devices);
3927 * we only program the IOAPIC on the first.
3929 ioapic
= irq_attr
->ioapic
;
3930 pin
= irq_attr
->ioapic_pin
;
3931 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3932 pr_debug("Pin %d-%d already programmed\n",
3933 mp_ioapics
[ioapic
].apicid
, pin
);
3936 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3938 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3941 /* --------------------------------------------------------------------------
3942 ACPI-based IOAPIC Configuration
3943 -------------------------------------------------------------------------- */
3947 #ifdef CONFIG_X86_32
3948 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3950 union IO_APIC_reg_00 reg_00
;
3951 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3953 unsigned long flags
;
3957 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3958 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3959 * supports up to 16 on one shared APIC bus.
3961 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3962 * advantage of new APIC bus architecture.
3965 if (physids_empty(apic_id_map
))
3966 apic_id_map
= apic
->ioapic_phys_id_map(phys_cpu_present_map
);
3968 spin_lock_irqsave(&ioapic_lock
, flags
);
3969 reg_00
.raw
= io_apic_read(ioapic
, 0);
3970 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3972 if (apic_id
>= get_physical_broadcast()) {
3973 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3974 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3975 apic_id
= reg_00
.bits
.ID
;
3979 * Every APIC in a system must have a unique ID or we get lots of nice
3980 * 'stuck on smp_invalidate_needed IPI wait' messages.
3982 if (apic
->check_apicid_used(apic_id_map
, apic_id
)) {
3984 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3985 if (!apic
->check_apicid_used(apic_id_map
, i
))
3989 if (i
== get_physical_broadcast())
3990 panic("Max apic_id exceeded!\n");
3992 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3993 "trying %d\n", ioapic
, apic_id
, i
);
3998 tmp
= apic
->apicid_to_cpu_present(apic_id
);
3999 physids_or(apic_id_map
, apic_id_map
, tmp
);
4001 if (reg_00
.bits
.ID
!= apic_id
) {
4002 reg_00
.bits
.ID
= apic_id
;
4004 spin_lock_irqsave(&ioapic_lock
, flags
);
4005 io_apic_write(ioapic
, 0, reg_00
.raw
);
4006 reg_00
.raw
= io_apic_read(ioapic
, 0);
4007 spin_unlock_irqrestore(&ioapic_lock
, flags
);
4010 if (reg_00
.bits
.ID
!= apic_id
) {
4011 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4016 apic_printk(APIC_VERBOSE
, KERN_INFO
4017 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4023 int __init
io_apic_get_version(int ioapic
)
4025 union IO_APIC_reg_01 reg_01
;
4026 unsigned long flags
;
4028 spin_lock_irqsave(&ioapic_lock
, flags
);
4029 reg_01
.raw
= io_apic_read(ioapic
, 1);
4030 spin_unlock_irqrestore(&ioapic_lock
, flags
);
4032 return reg_01
.bits
.version
;
4035 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4039 if (skip_ioapic_setup
)
4042 for (i
= 0; i
< mp_irq_entries
; i
++)
4043 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4044 mp_irqs
[i
].srcbusirq
== bus_irq
)
4046 if (i
>= mp_irq_entries
)
4049 *trigger
= irq_trigger(i
);
4050 *polarity
= irq_polarity(i
);
4054 #endif /* CONFIG_ACPI */
4057 * This function currently is only a helper for the i386 smp boot process where
4058 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4059 * so mask in all cases should simply be apic->target_cpus()
4062 void __init
setup_ioapic_dest(void)
4064 int pin
, ioapic
= 0, irq
, irq_entry
;
4065 struct irq_desc
*desc
;
4066 const struct cpumask
*mask
;
4068 if (skip_ioapic_setup
== 1)
4072 if (!acpi_disabled
&& acpi_ioapic
) {
4073 ioapic
= mp_find_ioapic(0);
4079 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4080 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4081 if (irq_entry
== -1)
4083 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4085 desc
= irq_to_desc(irq
);
4088 * Honour affinities which have been set in early boot
4091 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4092 mask
= desc
->affinity
;
4094 mask
= apic
->target_cpus();
4096 if (intr_remapping_enabled
)
4097 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4099 set_ioapic_affinity_irq_desc(desc
, mask
);
4105 #define IOAPIC_RESOURCE_NAME_SIZE 11
4107 static struct resource
*ioapic_resources
;
4109 static struct resource
* __init
ioapic_setup_resources(void)
4112 struct resource
*res
;
4116 if (nr_ioapics
<= 0)
4119 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4122 mem
= alloc_bootmem(n
);
4126 mem
+= sizeof(struct resource
) * nr_ioapics
;
4128 for (i
= 0; i
< nr_ioapics
; i
++) {
4130 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4131 sprintf(mem
, "IOAPIC %u", i
);
4132 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4136 ioapic_resources
= res
;
4141 void __init
ioapic_init_mappings(void)
4143 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4144 struct resource
*ioapic_res
;
4147 ioapic_res
= ioapic_setup_resources();
4148 for (i
= 0; i
< nr_ioapics
; i
++) {
4149 if (smp_found_config
) {
4150 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4151 #ifdef CONFIG_X86_32
4154 "WARNING: bogus zero IO-APIC "
4155 "address found in MPTABLE, "
4156 "disabling IO/APIC support!\n");
4157 smp_found_config
= 0;
4158 skip_ioapic_setup
= 1;
4159 goto fake_ioapic_page
;
4163 #ifdef CONFIG_X86_32
4166 ioapic_phys
= (unsigned long)
4167 alloc_bootmem_pages(PAGE_SIZE
);
4168 ioapic_phys
= __pa(ioapic_phys
);
4170 set_fixmap_nocache(idx
, ioapic_phys
);
4171 apic_printk(APIC_VERBOSE
,
4172 "mapped IOAPIC to %08lx (%08lx)\n",
4173 __fix_to_virt(idx
), ioapic_phys
);
4176 if (ioapic_res
!= NULL
) {
4177 ioapic_res
->start
= ioapic_phys
;
4178 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4184 static int __init
ioapic_insert_resources(void)
4187 struct resource
*r
= ioapic_resources
;
4190 if (nr_ioapics
> 0) {
4192 "IO APIC resources couldn't be allocated.\n");
4198 for (i
= 0; i
< nr_ioapics
; i
++) {
4199 insert_resource(&iomem_resource
, r
);
4206 /* Insert the IO APIC resources after PCI initialization has occured to handle
4207 * IO APICS that are mapped in on a BAR in PCI space. */
4208 late_initcall(ioapic_insert_resources
);