sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/module.h>
  26 #include <linux/device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/initval.h>
  31 #include <sound/soc.h>
  32
  33 #include <mach/control.h>
  34 #include <mach/dma.h>
  35 #include <mach/mcbsp.h>
  36 #include "omap-mcbsp.h"
  37 #include "omap-pcm.h"
  38
  39 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_44100 | \
  40                                  SNDRV_PCM_RATE_48000 | \
  41                                  SNDRV_PCM_RATE_KNOT)
  42
  43 struct omap_mcbsp_data {
  44         unsigned int                    bus_id;
  45         struct omap_mcbsp_reg_cfg       regs;
  46         /*
  47          * Flags indicating is the bus already activated and configured by
  48          * another substream
  49          */
  50         int                             active;
  51         int                             configured;
  52 };
  53
  54 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  55
  56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  57
  58 /*
  59  * Stream DMA parameters. DMA request line and port address are set runtime
  60  * since they are different between OMAP1 and later OMAPs
  61  */
  62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  63
  64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  65 static const int omap1_dma_reqs[][2] = {
  66         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  67         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  68         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  69 };
  70 static const unsigned long omap1_mcbsp_port[][2] = {
  71         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  72           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  73         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  74           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  75         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  76           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  77 };
  78 #else
  79 static const int omap1_dma_reqs[][2] = {};
  80 static const unsigned long omap1_mcbsp_port[][2] = {};
  81 #endif
  82
  83 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  84 static const int omap24xx_dma_reqs[][2] = {
  85         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  86         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  87 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
  88         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  89         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  90         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  91 #endif
  92 };
  93 #else
  94 static const int omap24xx_dma_reqs[][2] = {};
  95 #endif
  96
  97 #if defined(CONFIG_ARCH_OMAP2420)
  98 static const unsigned long omap2420_mcbsp_port[][2] = {
  99         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 100           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 101         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 102           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 103 };
 104 #else
 105 static const unsigned long omap2420_mcbsp_port[][2] = {};
 106 #endif
 107
 108 #if defined(CONFIG_ARCH_OMAP2430)
 109 static const unsigned long omap2430_mcbsp_port[][2] = {
 110         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 111           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 112         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 113           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 114         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 115           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 116         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 117           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 118         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 119           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 120 };
 121 #else
 122 static const unsigned long omap2430_mcbsp_port[][2] = {};
 123 #endif
 124
 125 #if defined(CONFIG_ARCH_OMAP34XX)
 126 static const unsigned long omap34xx_mcbsp_port[][2] = {
 127         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 128           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 129         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 131         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 132           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 133         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 134           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 135         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 136           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 137 };
 138 #else
 139 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 140 #endif
 141
 142 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream)
 143 {
 144         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 145         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 146         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 147         int err = 0;
 148
 149         if (!cpu_dai->active)
 150                 err = omap_mcbsp_request(mcbsp_data->bus_id);
 151
 152         return err;
 153 }
 154
 155 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream)
 156 {
 157         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 158         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 159         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 160
 161         if (!cpu_dai->active) {
 162                 omap_mcbsp_free(mcbsp_data->bus_id);
 163                 mcbsp_data->configured = 0;
 164         }
 165 }
 166
 167 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd)
 168 {
 169         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 170         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 171         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 172         int err = 0;
 173
 174         switch (cmd) {
 175         case SNDRV_PCM_TRIGGER_START:
 176         case SNDRV_PCM_TRIGGER_RESUME:
 177         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 178                 if (!mcbsp_data->active++)
 179                         omap_mcbsp_start(mcbsp_data->bus_id);
 180                 break;
 181
 182         case SNDRV_PCM_TRIGGER_STOP:
 183         case SNDRV_PCM_TRIGGER_SUSPEND:
 184         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 185                 if (!--mcbsp_data->active)
 186                         omap_mcbsp_stop(mcbsp_data->bus_id);
 187                 break;
 188         default:
 189                 err = -EINVAL;
 190         }
 191
 192         return err;
 193 }
 194
 195 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 196                                     struct snd_pcm_hw_params *params)
 197 {
 198         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 199         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 200         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 201         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 202         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 203         unsigned long port;
 204
 205         if (cpu_class_is_omap1()) {
 206                 dma = omap1_dma_reqs[bus_id][substream->stream];
 207                 port = omap1_mcbsp_port[bus_id][substream->stream];
 208         } else if (cpu_is_omap2420()) {
 209                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 210                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 211         } else if (cpu_is_omap2430()) {
 212                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 213                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 214         } else if (cpu_is_omap343x()) {
 215                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 216                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 217         } else {
 218                 return -ENODEV;
 219         }
 220         omap_mcbsp_dai_dma_params[id][substream->stream].name =
 221                 substream->stream ? "Audio Capture" : "Audio Playback";
 222         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 223         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 224         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 225
 226         if (mcbsp_data->configured) {
 227                 /* McBSP already configured by another stream */
 228                 return 0;
 229         }
 230
 231         switch (params_channels(params)) {
 232         case 2:
 233                 /* Set 1 word per (McBPSP) frame and use dual-phase frames */
 234                 regs->rcr2      |= RFRLEN2(1 - 1) | RPHASE;
 235                 regs->rcr1      |= RFRLEN1(1 - 1);
 236                 regs->xcr2      |= XFRLEN2(1 - 1) | XPHASE;
 237                 regs->xcr1      |= XFRLEN1(1 - 1);
 238                 break;
 239         default:
 240                 /* Unsupported number of channels */
 241                 return -EINVAL;
 242         }
 243
 244         switch (params_format(params)) {
 245         case SNDRV_PCM_FORMAT_S16_LE:
 246                 /* Set word lengths */
 247                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 248                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 249                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 250                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 251                 /* Set FS period and length in terms of bit clock periods */
 252                 regs->srgr2     |= FPER(16 * 2 - 1);
 253                 regs->srgr1     |= FWID(16 - 1);
 254                 break;
 255         default:
 256                 /* Unsupported PCM format */
 257                 return -EINVAL;
 258         }
 259
 260         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 261         mcbsp_data->configured = 1;
 262
 263         return 0;
 264 }
 265
 266 /*
 267  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 268  * cache is initialized here
 269  */
 270 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 271                                       unsigned int fmt)
 272 {
 273         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 274         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 275
 276         if (mcbsp_data->configured)
 277                 return 0;
 278
 279         memset(regs, 0, sizeof(*regs));
 280         /* Generic McBSP register settings */
 281         regs->spcr2     |= XINTM(3) | FREE;
 282         regs->spcr1     |= RINTM(3);
 283         regs->rcr2      |= RFIG;
 284         regs->xcr2      |= XFIG;
 285
 286         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 287         case SND_SOC_DAIFMT_I2S:
 288                 /* 1-bit data delay */
 289                 regs->rcr2      |= RDATDLY(1);
 290                 regs->xcr2      |= XDATDLY(1);
 291                 break;
 292         case SND_SOC_DAIFMT_DSP_A:
 293                 /* 0-bit data delay */
 294                 regs->rcr2      |= RDATDLY(0);
 295                 regs->xcr2      |= XDATDLY(0);
 296                 break;
 297         default:
 298                 /* Unsupported data format */
 299                 return -EINVAL;
 300         }
 301
 302         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 303         case SND_SOC_DAIFMT_CBS_CFS:
 304                 /* McBSP master. Set FS and bit clocks as outputs */
 305                 regs->pcr0      |= FSXM | FSRM |
 306                                    CLKXM | CLKRM;
 307                 /* Sample rate generator drives the FS */
 308                 regs->srgr2     |= FSGM;
 309                 break;
 310         case SND_SOC_DAIFMT_CBM_CFM:
 311                 /* McBSP slave */
 312                 break;
 313         default:
 314                 /* Unsupported master/slave configuration */
 315                 return -EINVAL;
 316         }
 317
 318         /* Set bit clock (CLKX/CLKR) and FS polarities */
 319         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 320         case SND_SOC_DAIFMT_NB_NF:
 321                 /*
 322                  * Normal BCLK + FS.
 323                  * FS active low. TX data driven on falling edge of bit clock
 324                  * and RX data sampled on rising edge of bit clock.
 325                  */
 326                 regs->pcr0      |= FSXP | FSRP |
 327                                    CLKXP | CLKRP;
 328                 break;
 329         case SND_SOC_DAIFMT_NB_IF:
 330                 regs->pcr0      |= CLKXP | CLKRP;
 331                 break;
 332         case SND_SOC_DAIFMT_IB_NF:
 333                 regs->pcr0      |= FSXP | FSRP;
 334                 break;
 335         case SND_SOC_DAIFMT_IB_IF:
 336                 break;
 337         default:
 338                 return -EINVAL;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 345                                      int div_id, int div)
 346 {
 347         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 348         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 349
 350         if (div_id != OMAP_MCBSP_CLKGDV)
 351                 return -ENODEV;
 352
 353         regs->srgr1     |= CLKGDV(div - 1);
 354
 355         return 0;
 356 }
 357
 358 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 359                                        int clk_id)
 360 {
 361         int sel_bit;
 362         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 363
 364         if (cpu_class_is_omap1()) {
 365                 /* OMAP1's can use only external source clock */
 366                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 367                         return -EINVAL;
 368                 else
 369                         return 0;
 370         }
 371
 372         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 373                 return -EINVAL;
 374
 375         if (cpu_is_omap343x())
 376                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 377
 378         switch (mcbsp_data->bus_id) {
 379         case 0:
 380                 reg = OMAP2_CONTROL_DEVCONF0;
 381                 sel_bit = 2;
 382                 break;
 383         case 1:
 384                 reg = OMAP2_CONTROL_DEVCONF0;
 385                 sel_bit = 6;
 386                 break;
 387         case 2:
 388                 reg = reg_devconf1;
 389                 sel_bit = 0;
 390                 break;
 391         case 3:
 392                 reg = reg_devconf1;
 393                 sel_bit = 2;
 394                 break;
 395         case 4:
 396                 reg = reg_devconf1;
 397                 sel_bit = 4;
 398                 break;
 399         default:
 400                 return -EINVAL;
 401         }
 402
 403         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 404                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 405         else
 406                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 407
 408         return 0;
 409 }
 410
 411 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 412                                          int clk_id, unsigned int freq,
 413                                          int dir)
 414 {
 415         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 416         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 417         int err = 0;
 418
 419         switch (clk_id) {
 420         case OMAP_MCBSP_SYSCLK_CLK:
 421                 regs->srgr2     |= CLKSM;
 422                 break;
 423         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 424         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 425                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 426                 break;
 427
 428         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 429                 regs->srgr2     |= CLKSM;
 430         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 431                 regs->pcr0      |= SCLKME;
 432                 break;
 433         default:
 434                 err = -ENODEV;
 435         }
 436
 437         return err;
 438 }
 439
 440 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 441 {                                                               \
 442         .name = "omap-mcbsp-dai-(link_id)",                     \
 443         .id = (link_id),                                        \
 444         .type = SND_SOC_DAI_I2S,                                \
 445         .playback = {                                           \
 446                 .channels_min = 2,                              \
 447                 .channels_max = 2,                              \
 448                 .rates = OMAP_MCBSP_RATES,                      \
 449                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 450         },                                                      \
 451         .capture = {                                            \
 452                 .channels_min = 2,                              \
 453                 .channels_max = 2,                              \
 454                 .rates = OMAP_MCBSP_RATES,                      \
 455                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 456         },                                                      \
 457         .ops = {                                                \
 458                 .startup = omap_mcbsp_dai_startup,              \
 459                 .shutdown = omap_mcbsp_dai_shutdown,            \
 460                 .trigger = omap_mcbsp_dai_trigger,              \
 461                 .hw_params = omap_mcbsp_dai_hw_params,          \
 462         },                                                      \
 463         .dai_ops = {                                            \
 464                 .set_fmt = omap_mcbsp_dai_set_dai_fmt,          \
 465                 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,        \
 466                 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,    \
 467         },                                                      \
 468         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 469 }
 470
 471 struct snd_soc_dai omap_mcbsp_dai[] = {
 472         OMAP_MCBSP_DAI_BUILDER(0),
 473         OMAP_MCBSP_DAI_BUILDER(1),
 474 #if NUM_LINKS >= 3
 475         OMAP_MCBSP_DAI_BUILDER(2),
 476 #endif
 477 #if NUM_LINKS == 5
 478         OMAP_MCBSP_DAI_BUILDER(3),
 479         OMAP_MCBSP_DAI_BUILDER(4),
 480 #endif
 481 };
 482
 483 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 484
 485 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
 486 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 487 MODULE_LICENSE("GPL");