2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
34 #include <linux/smp.h>
35 #include <linux/nmi.h>
36 #include <linux/timex.h>
38 #include <asm/atomic.h>
40 #include <asm/mpspec.h>
42 #include <asm/arch_hooks.h>
44 #include <asm/pgalloc.h>
45 #include <asm/i8253.h>
47 #include <asm/proto.h>
49 #include <asm/i8259.h>
52 #include <asm/genapic.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
61 unsigned int num_processors
;
62 unsigned disabled_cpus __cpuinitdata
;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid
= -1U;
65 EXPORT_SYMBOL(boot_cpu_physical_apicid
);
66 unsigned int max_physical_apicid
;
68 /* Bitmask of physically existing CPUs */
69 physid_mask_t phys_cpu_present_map
;
72 * Map cpu index to physical APIC ID
74 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
75 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
76 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
77 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
81 * Knob to control our willingness to enable the local APIC.
85 static int force_enable_local_apic
;
87 * APIC command line parameters
89 static int __init
parse_lapic(char *arg
)
91 force_enable_local_apic
= 1;
94 early_param("lapic", parse_lapic
);
95 /* Local APIC was disabled by the BIOS and enabled by the kernel */
96 static int enabled_via_apicbase
;
101 static int apic_calibrate_pmtmr __initdata
;
102 static __init
int setup_apicpmtimer(char *s
)
104 apic_calibrate_pmtmr
= 1;
108 __setup("apicpmtimer", setup_apicpmtimer
);
117 /* x2apic enabled before OS handover */
118 static int x2apic_preenabled
;
119 static int disable_x2apic
;
120 static __init
int setup_nox2apic(char *str
)
123 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
126 early_param("nox2apic", setup_nox2apic
);
129 unsigned long mp_lapic_addr
;
131 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
132 static int disable_apic_timer __cpuinitdata
;
133 /* Local APIC timer works in C2 */
134 int local_apic_timer_c2_ok
;
135 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
137 int first_system_vector
= 0xfe;
140 * Debug level, exported for io_apic.c
142 unsigned int apic_verbosity
;
146 /* Have we found an MP table */
147 int smp_found_config
;
149 static struct resource lapic_resource
= {
150 .name
= "Local APIC",
151 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
154 static unsigned int calibration_result
;
156 static int lapic_next_event(unsigned long delta
,
157 struct clock_event_device
*evt
);
158 static void lapic_timer_setup(enum clock_event_mode mode
,
159 struct clock_event_device
*evt
);
160 static void lapic_timer_broadcast(const struct cpumask
*mask
);
161 static void apic_pm_activate(void);
164 * The local apic timer can be used for any function which is CPU local.
166 static struct clock_event_device lapic_clockevent
= {
168 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
169 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
171 .set_mode
= lapic_timer_setup
,
172 .set_next_event
= lapic_next_event
,
173 .broadcast
= lapic_timer_broadcast
,
177 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
179 static unsigned long apic_phys
;
182 * Get the LAPIC version
184 static inline int lapic_get_version(void)
186 return GET_APIC_VERSION(apic_read(APIC_LVR
));
190 * Check, if the APIC is integrated or a separate chip
192 static inline int lapic_is_integrated(void)
197 return APIC_INTEGRATED(lapic_get_version());
202 * Check, whether this is a modern or a first generation APIC
204 static int modern_apic(void)
206 /* AMD systems use old APIC versions, so check the CPU */
207 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
208 boot_cpu_data
.x86
>= 0xf)
210 return lapic_get_version() >= 0x14;
214 * Paravirt kernels also might be using these below ops. So we still
215 * use generic apic_read()/apic_write(), which might be pointing to different
216 * ops in PARAVIRT case.
218 void xapic_wait_icr_idle(void)
220 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
224 u32
safe_xapic_wait_icr_idle(void)
231 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
235 } while (timeout
++ < 1000);
240 void xapic_icr_write(u32 low
, u32 id
)
242 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
243 apic_write(APIC_ICR
, low
);
246 static u64
xapic_icr_read(void)
250 icr2
= apic_read(APIC_ICR2
);
251 icr1
= apic_read(APIC_ICR
);
253 return icr1
| ((u64
)icr2
<< 32);
256 static struct apic_ops xapic_ops
= {
257 .read
= native_apic_mem_read
,
258 .write
= native_apic_mem_write
,
259 .icr_read
= xapic_icr_read
,
260 .icr_write
= xapic_icr_write
,
261 .wait_icr_idle
= xapic_wait_icr_idle
,
262 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
265 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
266 EXPORT_SYMBOL_GPL(apic_ops
);
269 static void x2apic_wait_icr_idle(void)
271 /* no need to wait for icr idle in x2apic */
275 static u32
safe_x2apic_wait_icr_idle(void)
277 /* no need to wait for icr idle in x2apic */
281 void x2apic_icr_write(u32 low
, u32 id
)
283 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
286 static u64
x2apic_icr_read(void)
290 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
294 static struct apic_ops x2apic_ops
= {
295 .read
= native_apic_msr_read
,
296 .write
= native_apic_msr_write
,
297 .icr_read
= x2apic_icr_read
,
298 .icr_write
= x2apic_icr_write
,
299 .wait_icr_idle
= x2apic_wait_icr_idle
,
300 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
305 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
307 void __cpuinit
enable_NMI_through_LVT0(void)
311 /* unmask and set to NMI */
314 /* Level triggered for 82489DX (32bit mode) */
315 if (!lapic_is_integrated())
316 v
|= APIC_LVT_LEVEL_TRIGGER
;
318 apic_write(APIC_LVT0
, v
);
323 * get_physical_broadcast - Get number of physical broadcast IDs
325 int get_physical_broadcast(void)
327 return modern_apic() ? 0xff : 0xf;
332 * lapic_get_maxlvt - get the maximum number of local vector table entries
334 int lapic_get_maxlvt(void)
338 v
= apic_read(APIC_LVR
);
340 * - we always have APIC integrated on 64bit mode
341 * - 82489DXs do not report # of LVT entries
343 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
351 #define APIC_DIVISOR 16
354 * This function sets up the local APIC timer, with a timeout of
355 * 'clocks' APIC bus clock. During calibration we actually call
356 * this function twice on the boot CPU, once with a bogus timeout
357 * value, second time for real. The other (noncalibrating) CPUs
358 * call this function only once, with the real, calibrated value.
360 * We do reads before writes even if unnecessary, to get around the
361 * P5 APIC double write bug.
363 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
365 unsigned int lvtt_value
, tmp_value
;
367 lvtt_value
= LOCAL_TIMER_VECTOR
;
369 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
370 if (!lapic_is_integrated())
371 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
374 lvtt_value
|= APIC_LVT_MASKED
;
376 apic_write(APIC_LVTT
, lvtt_value
);
381 tmp_value
= apic_read(APIC_TDCR
);
382 apic_write(APIC_TDCR
,
383 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
387 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
391 * Setup extended LVT, AMD specific (K8, family 10h)
393 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
394 * MCE interrupts are supported. Thus MCE offset must be set to 0.
396 * If mask=1, the LVT entry does not generate interrupts while mask=0
397 * enables the vector. See also the BKDGs.
400 #define APIC_EILVT_LVTOFF_MCE 0
401 #define APIC_EILVT_LVTOFF_IBS 1
403 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
405 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
406 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
411 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
413 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
414 return APIC_EILVT_LVTOFF_MCE
;
417 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
419 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
420 return APIC_EILVT_LVTOFF_IBS
;
422 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
425 * Program the next event, relative to now
427 static int lapic_next_event(unsigned long delta
,
428 struct clock_event_device
*evt
)
430 apic_write(APIC_TMICT
, delta
);
435 * Setup the lapic timer in periodic or oneshot mode
437 static void lapic_timer_setup(enum clock_event_mode mode
,
438 struct clock_event_device
*evt
)
443 /* Lapic used as dummy for broadcast ? */
444 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
447 local_irq_save(flags
);
450 case CLOCK_EVT_MODE_PERIODIC
:
451 case CLOCK_EVT_MODE_ONESHOT
:
452 __setup_APIC_LVTT(calibration_result
,
453 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
455 case CLOCK_EVT_MODE_UNUSED
:
456 case CLOCK_EVT_MODE_SHUTDOWN
:
457 v
= apic_read(APIC_LVTT
);
458 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
459 apic_write(APIC_LVTT
, v
);
460 apic_write(APIC_TMICT
, 0xffffffff);
462 case CLOCK_EVT_MODE_RESUME
:
463 /* Nothing to do here */
467 local_irq_restore(flags
);
471 * Local APIC timer broadcast function
473 static void lapic_timer_broadcast(const struct cpumask
*mask
)
476 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
481 * Setup the local APIC timer for this CPU. Copy the initilized values
482 * of the boot CPU and register the clock event in the framework.
484 static void __cpuinit
setup_APIC_timer(void)
486 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
488 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
489 levt
->cpumask
= cpumask_of(smp_processor_id());
491 clockevents_register_device(levt
);
495 * In this functions we calibrate APIC bus clocks to the external timer.
497 * We want to do the calibration only once since we want to have local timer
498 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
501 * This was previously done by reading the PIT/HPET and waiting for a wrap
502 * around to find out, that a tick has elapsed. I have a box, where the PIT
503 * readout is broken, so it never gets out of the wait loop again. This was
504 * also reported by others.
506 * Monitoring the jiffies value is inaccurate and the clockevents
507 * infrastructure allows us to do a simple substitution of the interrupt
510 * The calibration routine also uses the pm_timer when possible, as the PIT
511 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
512 * back to normal later in the boot process).
515 #define LAPIC_CAL_LOOPS (HZ/10)
517 static __initdata
int lapic_cal_loops
= -1;
518 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
519 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
520 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
521 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
524 * Temporary interrupt handler.
526 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
528 unsigned long long tsc
= 0;
529 long tapic
= apic_read(APIC_TMCCT
);
530 unsigned long pm
= acpi_pm_read_early();
535 switch (lapic_cal_loops
++) {
537 lapic_cal_t1
= tapic
;
538 lapic_cal_tsc1
= tsc
;
540 lapic_cal_j1
= jiffies
;
543 case LAPIC_CAL_LOOPS
:
544 lapic_cal_t2
= tapic
;
545 lapic_cal_tsc2
= tsc
;
546 if (pm
< lapic_cal_pm1
)
547 pm
+= ACPI_PM_OVRRUN
;
549 lapic_cal_j2
= jiffies
;
554 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
556 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
557 const long pm_thresh
= pm_100ms
/ 100;
561 #ifndef CONFIG_X86_PM_TIMER
565 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
567 /* Check, if the PM timer is available */
571 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
573 if (deltapm
> (pm_100ms
- pm_thresh
) &&
574 deltapm
< (pm_100ms
+ pm_thresh
)) {
575 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
577 res
= (((u64
)deltapm
) * mult
) >> 22;
578 do_div(res
, 1000000);
579 pr_warning("APIC calibration not consistent "
580 "with PM Timer: %ldms instead of 100ms\n",
582 /* Correct the lapic counter value */
583 res
= (((u64
)(*delta
)) * pm_100ms
);
584 do_div(res
, deltapm
);
585 pr_info("APIC delta adjusted to PM-Timer: "
586 "%lu (%ld)\n", (unsigned long)res
, *delta
);
593 static int __init
calibrate_APIC_clock(void)
595 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
596 void (*real_handler
)(struct clock_event_device
*dev
);
597 unsigned long deltaj
;
599 int pm_referenced
= 0;
603 /* Replace the global interrupt handler */
604 real_handler
= global_clock_event
->event_handler
;
605 global_clock_event
->event_handler
= lapic_cal_handler
;
608 * Setup the APIC counter to maximum. There is no way the lapic
609 * can underflow in the 100ms detection time frame
611 __setup_APIC_LVTT(0xffffffff, 0, 0);
613 /* Let the interrupts run */
616 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
621 /* Restore the real event handler */
622 global_clock_event
->event_handler
= real_handler
;
624 /* Build delta t1-t2 as apic timer counts down */
625 delta
= lapic_cal_t1
- lapic_cal_t2
;
626 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
628 /* we trust the PM based calibration if possible */
629 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
632 /* Calculate the scaled math multiplication factor */
633 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
634 lapic_clockevent
.shift
);
635 lapic_clockevent
.max_delta_ns
=
636 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
637 lapic_clockevent
.min_delta_ns
=
638 clockevent_delta2ns(0xF, &lapic_clockevent
);
640 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
642 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
643 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
644 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
648 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
649 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
651 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
652 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
655 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
657 calibration_result
/ (1000000 / HZ
),
658 calibration_result
% (1000000 / HZ
));
661 * Do a sanity check on the APIC calibration result
663 if (calibration_result
< (1000000 / HZ
)) {
665 pr_warning("APIC frequency too slow, disabling apic timer\n");
669 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
672 * PM timer calibration failed or not turned on
673 * so lets try APIC timer based calibration
675 if (!pm_referenced
) {
676 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
679 * Setup the apic timer manually
681 levt
->event_handler
= lapic_cal_handler
;
682 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
683 lapic_cal_loops
= -1;
685 /* Let the interrupts run */
688 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
691 /* Stop the lapic timer */
692 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
695 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
696 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
698 /* Check, if the jiffies result is consistent */
699 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
700 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
702 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
706 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
707 pr_warning("APIC timer disabled due to verification failure\n");
715 * Setup the boot APIC
717 * Calibrate and verify the result.
719 void __init
setup_boot_APIC_clock(void)
722 * The local apic timer can be disabled via the kernel
723 * commandline or from the CPU detection code. Register the lapic
724 * timer as a dummy clock event source on SMP systems, so the
725 * broadcast mechanism is used. On UP systems simply ignore it.
727 if (disable_apic_timer
) {
728 pr_info("Disabling APIC timer\n");
729 /* No broadcast on UP ! */
730 if (num_possible_cpus() > 1) {
731 lapic_clockevent
.mult
= 1;
737 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
738 "calibrating APIC timer ...\n");
740 if (calibrate_APIC_clock()) {
741 /* No broadcast on UP ! */
742 if (num_possible_cpus() > 1)
748 * If nmi_watchdog is set to IO_APIC, we need the
749 * PIT/HPET going. Otherwise register lapic as a dummy
752 if (nmi_watchdog
!= NMI_IO_APIC
)
753 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
755 pr_warning("APIC timer registered as dummy,"
756 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
758 /* Setup the lapic or request the broadcast */
762 void __cpuinit
setup_secondary_APIC_clock(void)
768 * The guts of the apic timer interrupt
770 static void local_apic_timer_interrupt(void)
772 int cpu
= smp_processor_id();
773 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
776 * Normally we should not be here till LAPIC has been initialized but
777 * in some cases like kdump, its possible that there is a pending LAPIC
778 * timer interrupt from previous kernel's context and is delivered in
779 * new kernel the moment interrupts are enabled.
781 * Interrupts are enabled early and LAPIC is setup much later, hence
782 * its possible that when we get here evt->event_handler is NULL.
783 * Check for event_handler being NULL and discard the interrupt as
786 if (!evt
->event_handler
) {
787 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
789 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
794 * the NMI deadlock-detector uses this.
796 inc_irq_stat(apic_timer_irqs
);
798 evt
->event_handler(evt
);
802 * Local APIC timer interrupt. This is the most natural way for doing
803 * local interrupts, but local timer interrupts can be emulated by
804 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
806 * [ if a single-CPU system runs an SMP kernel then we call the local
807 * interrupt as well. Thus we cannot inline the local irq ... ]
809 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
811 struct pt_regs
*old_regs
= set_irq_regs(regs
);
814 * NOTE! We'd better ACK the irq immediately,
815 * because timer handling can be slow.
819 * update_process_times() expects us to have done irq_enter().
820 * Besides, if we don't timer interrupts ignore the global
821 * interrupt lock, which is the WrongThing (tm) to do.
825 local_apic_timer_interrupt();
828 set_irq_regs(old_regs
);
831 int setup_profiling_timer(unsigned int multiplier
)
837 * Local APIC start and shutdown
841 * clear_local_APIC - shutdown the local APIC
843 * This is called, when a CPU is disabled and before rebooting, so the state of
844 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
845 * leftovers during boot.
847 void clear_local_APIC(void)
852 /* APIC hasn't been mapped yet */
856 maxlvt
= lapic_get_maxlvt();
858 * Masking an LVT entry can trigger a local APIC error
859 * if the vector is zero. Mask LVTERR first to prevent this.
862 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
863 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
866 * Careful: we have to set masks only first to deassert
867 * any level-triggered sources.
869 v
= apic_read(APIC_LVTT
);
870 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
871 v
= apic_read(APIC_LVT0
);
872 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
873 v
= apic_read(APIC_LVT1
);
874 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
876 v
= apic_read(APIC_LVTPC
);
877 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
880 /* lets not touch this if we didn't frob it */
881 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
883 v
= apic_read(APIC_LVTTHMR
);
884 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
888 * Clean APIC state for other OSs:
890 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
891 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
892 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
894 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
896 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
898 /* Integrated APIC (!82489DX) ? */
899 if (lapic_is_integrated()) {
901 /* Clear ESR due to Pentium errata 3AP and 11AP */
902 apic_write(APIC_ESR
, 0);
908 * disable_local_APIC - clear and disable the local APIC
910 void disable_local_APIC(void)
914 /* APIC hasn't been mapped yet */
921 * Disable APIC (implies clearing of registers
924 value
= apic_read(APIC_SPIV
);
925 value
&= ~APIC_SPIV_APIC_ENABLED
;
926 apic_write(APIC_SPIV
, value
);
930 * When LAPIC was disabled by the BIOS and enabled by the kernel,
931 * restore the disabled state.
933 if (enabled_via_apicbase
) {
936 rdmsr(MSR_IA32_APICBASE
, l
, h
);
937 l
&= ~MSR_IA32_APICBASE_ENABLE
;
938 wrmsr(MSR_IA32_APICBASE
, l
, h
);
944 * If Linux enabled the LAPIC against the BIOS default disable it down before
945 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
946 * not power-off. Additionally clear all LVT entries before disable_local_APIC
947 * for the case where Linux didn't enable the LAPIC.
949 void lapic_shutdown(void)
956 local_irq_save(flags
);
959 if (!enabled_via_apicbase
)
963 disable_local_APIC();
966 local_irq_restore(flags
);
970 * This is to verify that we're looking at a real local APIC.
971 * Check these against your board if the CPUs aren't getting
972 * started for no apparent reason.
974 int __init
verify_local_APIC(void)
976 unsigned int reg0
, reg1
;
979 * The version register is read-only in a real APIC.
981 reg0
= apic_read(APIC_LVR
);
982 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
983 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
984 reg1
= apic_read(APIC_LVR
);
985 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
988 * The two version reads above should print the same
989 * numbers. If the second one is different, then we
990 * poke at a non-APIC.
996 * Check if the version looks reasonably.
998 reg1
= GET_APIC_VERSION(reg0
);
999 if (reg1
== 0x00 || reg1
== 0xff)
1001 reg1
= lapic_get_maxlvt();
1002 if (reg1
< 0x02 || reg1
== 0xff)
1006 * The ID register is read/write in a real APIC.
1008 reg0
= apic_read(APIC_ID
);
1009 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1010 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1011 reg1
= apic_read(APIC_ID
);
1012 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1013 apic_write(APIC_ID
, reg0
);
1014 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1018 * The next two are just to see if we have sane values.
1019 * They're only really relevant if we're in Virtual Wire
1020 * compatibility mode, but most boxes are anymore.
1022 reg0
= apic_read(APIC_LVT0
);
1023 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1024 reg1
= apic_read(APIC_LVT1
);
1025 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1031 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1033 void __init
sync_Arb_IDs(void)
1036 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1039 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1045 apic_wait_icr_idle();
1047 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1048 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1049 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1053 * An initial setup of the virtual wire mode.
1055 void __init
init_bsp_APIC(void)
1060 * Don't do the setup now if we have a SMP BIOS as the
1061 * through-I/O-APIC virtual wire mode might be active.
1063 if (smp_found_config
|| !cpu_has_apic
)
1067 * Do not trust the local APIC being empty at bootup.
1074 value
= apic_read(APIC_SPIV
);
1075 value
&= ~APIC_VECTOR_MASK
;
1076 value
|= APIC_SPIV_APIC_ENABLED
;
1078 #ifdef CONFIG_X86_32
1079 /* This bit is reserved on P4/Xeon and should be cleared */
1080 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1081 (boot_cpu_data
.x86
== 15))
1082 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1085 value
|= APIC_SPIV_FOCUS_DISABLED
;
1086 value
|= SPURIOUS_APIC_VECTOR
;
1087 apic_write(APIC_SPIV
, value
);
1090 * Set up the virtual wire mode.
1092 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1093 value
= APIC_DM_NMI
;
1094 if (!lapic_is_integrated()) /* 82489DX */
1095 value
|= APIC_LVT_LEVEL_TRIGGER
;
1096 apic_write(APIC_LVT1
, value
);
1099 static void __cpuinit
lapic_setup_esr(void)
1101 unsigned int oldvalue
, value
, maxlvt
;
1103 if (!lapic_is_integrated()) {
1104 pr_info("No ESR for 82489DX.\n");
1108 if (apic
->disable_esr
) {
1110 * Something untraceable is creating bad interrupts on
1111 * secondary quads ... for the moment, just leave the
1112 * ESR disabled - we can't do anything useful with the
1113 * errors anyway - mbligh
1115 pr_info("Leaving ESR disabled.\n");
1119 maxlvt
= lapic_get_maxlvt();
1120 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1121 apic_write(APIC_ESR
, 0);
1122 oldvalue
= apic_read(APIC_ESR
);
1124 /* enables sending errors */
1125 value
= ERROR_APIC_VECTOR
;
1126 apic_write(APIC_LVTERR
, value
);
1129 * spec says clear errors after enabling vector.
1132 apic_write(APIC_ESR
, 0);
1133 value
= apic_read(APIC_ESR
);
1134 if (value
!= oldvalue
)
1135 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1136 "vector: 0x%08x after: 0x%08x\n",
1142 * setup_local_APIC - setup the local APIC
1144 void __cpuinit
setup_local_APIC(void)
1150 #ifdef CONFIG_X86_IO_APIC
1151 disable_ioapic_setup();
1156 #ifdef CONFIG_X86_32
1157 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1158 if (lapic_is_integrated() && apic
->disable_esr
) {
1159 apic_write(APIC_ESR
, 0);
1160 apic_write(APIC_ESR
, 0);
1161 apic_write(APIC_ESR
, 0);
1162 apic_write(APIC_ESR
, 0);
1169 * Double-check whether this APIC is really registered.
1170 * This is meaningless in clustered apic mode, so we skip it.
1172 if (!apic
->apic_id_registered())
1176 * Intel recommends to set DFR, LDR and TPR before enabling
1177 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1178 * document number 292116). So here it goes...
1180 apic
->init_apic_ldr();
1183 * Set Task Priority to 'accept all'. We never change this
1186 value
= apic_read(APIC_TASKPRI
);
1187 value
&= ~APIC_TPRI_MASK
;
1188 apic_write(APIC_TASKPRI
, value
);
1191 * After a crash, we no longer service the interrupts and a pending
1192 * interrupt from previous kernel might still have ISR bit set.
1194 * Most probably by now CPU has serviced that pending interrupt and
1195 * it might not have done the ack_APIC_irq() because it thought,
1196 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1197 * does not clear the ISR bit and cpu thinks it has already serivced
1198 * the interrupt. Hence a vector might get locked. It was noticed
1199 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1201 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1202 value
= apic_read(APIC_ISR
+ i
*0x10);
1203 for (j
= 31; j
>= 0; j
--) {
1210 * Now that we are all set up, enable the APIC
1212 value
= apic_read(APIC_SPIV
);
1213 value
&= ~APIC_VECTOR_MASK
;
1217 value
|= APIC_SPIV_APIC_ENABLED
;
1219 #ifdef CONFIG_X86_32
1221 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1222 * certain networking cards. If high frequency interrupts are
1223 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1224 * entry is masked/unmasked at a high rate as well then sooner or
1225 * later IOAPIC line gets 'stuck', no more interrupts are received
1226 * from the device. If focus CPU is disabled then the hang goes
1229 * [ This bug can be reproduced easily with a level-triggered
1230 * PCI Ne2000 networking cards and PII/PIII processors, dual
1234 * Actually disabling the focus CPU check just makes the hang less
1235 * frequent as it makes the interrupt distributon model be more
1236 * like LRU than MRU (the short-term load is more even across CPUs).
1237 * See also the comment in end_level_ioapic_irq(). --macro
1241 * - enable focus processor (bit==0)
1242 * - 64bit mode always use processor focus
1243 * so no need to set it
1245 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1249 * Set spurious IRQ vector
1251 value
|= SPURIOUS_APIC_VECTOR
;
1252 apic_write(APIC_SPIV
, value
);
1255 * Set up LVT0, LVT1:
1257 * set up through-local-APIC on the BP's LINT0. This is not
1258 * strictly necessary in pure symmetric-IO mode, but sometimes
1259 * we delegate interrupts to the 8259A.
1262 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1264 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1265 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1266 value
= APIC_DM_EXTINT
;
1267 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1268 smp_processor_id());
1270 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1271 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1272 smp_processor_id());
1274 apic_write(APIC_LVT0
, value
);
1277 * only the BP should see the LINT1 NMI signal, obviously.
1279 if (!smp_processor_id())
1280 value
= APIC_DM_NMI
;
1282 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1283 if (!lapic_is_integrated()) /* 82489DX */
1284 value
|= APIC_LVT_LEVEL_TRIGGER
;
1285 apic_write(APIC_LVT1
, value
);
1290 void __cpuinit
end_local_APIC_setup(void)
1294 #ifdef CONFIG_X86_32
1297 /* Disable the local apic timer */
1298 value
= apic_read(APIC_LVTT
);
1299 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1300 apic_write(APIC_LVTT
, value
);
1304 setup_apic_nmi_watchdog(NULL
);
1309 void check_x2apic(void)
1313 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1315 if (msr
& X2APIC_ENABLE
) {
1316 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1317 x2apic_preenabled
= x2apic
= 1;
1318 apic_ops
= &x2apic_ops
;
1322 void enable_x2apic(void)
1326 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1327 if (!(msr
& X2APIC_ENABLE
)) {
1328 pr_info("Enabling x2apic\n");
1329 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1333 void __init
enable_IR_x2apic(void)
1335 #ifdef CONFIG_INTR_REMAP
1337 unsigned long flags
;
1339 if (!cpu_has_x2apic
)
1342 if (!x2apic_preenabled
&& disable_x2apic
) {
1343 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1344 "because of nox2apic\n");
1348 if (x2apic_preenabled
&& disable_x2apic
)
1349 panic("Bios already enabled x2apic, can't enforce nox2apic");
1351 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1352 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1353 "because of skipping io-apic setup\n");
1357 ret
= dmar_table_init();
1359 pr_info("dmar_table_init() failed with %d:\n", ret
);
1361 if (x2apic_preenabled
)
1362 panic("x2apic enabled by bios. But IR enabling failed");
1364 pr_info("Not enabling x2apic,Intr-remapping\n");
1368 local_irq_save(flags
);
1371 ret
= save_mask_IO_APIC_setup();
1373 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1377 ret
= enable_intr_remapping(1);
1379 if (ret
&& x2apic_preenabled
) {
1380 local_irq_restore(flags
);
1381 panic("x2apic enabled by bios. But IR enabling failed");
1389 apic_ops
= &x2apic_ops
;
1396 * IR enabling failed
1398 restore_IO_APIC_setup();
1400 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1404 local_irq_restore(flags
);
1407 if (!x2apic_preenabled
)
1408 pr_info("Enabled x2apic and interrupt-remapping\n");
1410 pr_info("Enabled Interrupt-remapping\n");
1412 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1414 if (!cpu_has_x2apic
)
1417 if (x2apic_preenabled
)
1418 panic("x2apic enabled prior OS handover,"
1419 " enable CONFIG_INTR_REMAP");
1421 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1427 #endif /* HAVE_X2APIC */
1429 #ifdef CONFIG_X86_64
1431 * Detect and enable local APICs on non-SMP boards.
1432 * Original code written by Keir Fraser.
1433 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1434 * not correctly set up (usually the APIC timer won't work etc.)
1436 static int __init
detect_init_APIC(void)
1438 if (!cpu_has_apic
) {
1439 pr_info("No local APIC present\n");
1443 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1444 boot_cpu_physical_apicid
= 0;
1449 * Detect and initialize APIC
1451 static int __init
detect_init_APIC(void)
1455 /* Disabled by kernel option? */
1459 switch (boot_cpu_data
.x86_vendor
) {
1460 case X86_VENDOR_AMD
:
1461 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1462 (boot_cpu_data
.x86
== 15))
1465 case X86_VENDOR_INTEL
:
1466 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1467 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1474 if (!cpu_has_apic
) {
1476 * Over-ride BIOS and try to enable the local APIC only if
1477 * "lapic" specified.
1479 if (!force_enable_local_apic
) {
1480 pr_info("Local APIC disabled by BIOS -- "
1481 "you can enable it with \"lapic\"\n");
1485 * Some BIOSes disable the local APIC in the APIC_BASE
1486 * MSR. This can only be done in software for Intel P6 or later
1487 * and AMD K7 (Model > 1) or later.
1489 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1490 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1491 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1492 l
&= ~MSR_IA32_APICBASE_BASE
;
1493 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1494 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1495 enabled_via_apicbase
= 1;
1499 * The APIC feature bit should now be enabled
1502 features
= cpuid_edx(1);
1503 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1504 pr_warning("Could not enable APIC!\n");
1507 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1508 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1510 /* The BIOS may have set up the APIC at some other address */
1511 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1512 if (l
& MSR_IA32_APICBASE_ENABLE
)
1513 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1515 pr_info("Found and enabled local APIC!\n");
1522 pr_info("No local APIC present or hardware disabled\n");
1527 #ifdef CONFIG_X86_64
1528 void __init
early_init_lapic_mapping(void)
1530 unsigned long phys_addr
;
1533 * If no local APIC can be found then go out
1534 * : it means there is no mpatable and MADT
1536 if (!smp_found_config
)
1539 phys_addr
= mp_lapic_addr
;
1541 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1542 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1543 APIC_BASE
, phys_addr
);
1546 * Fetch the APIC ID of the BSP in case we have a
1547 * default configuration (or the MP table is broken).
1549 boot_cpu_physical_apicid
= read_apic_id();
1554 * init_apic_mappings - initialize APIC mappings
1556 void __init
init_apic_mappings(void)
1560 boot_cpu_physical_apicid
= read_apic_id();
1566 * If no local APIC can be found then set up a fake all
1567 * zeroes page to simulate the local APIC and another
1568 * one for the IO-APIC.
1570 if (!smp_found_config
&& detect_init_APIC()) {
1571 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1572 apic_phys
= __pa(apic_phys
);
1574 apic_phys
= mp_lapic_addr
;
1576 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1577 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1578 APIC_BASE
, apic_phys
);
1581 * Fetch the APIC ID of the BSP in case we have a
1582 * default configuration (or the MP table is broken).
1584 if (boot_cpu_physical_apicid
== -1U)
1585 boot_cpu_physical_apicid
= read_apic_id();
1589 * This initializes the IO-APIC and APIC hardware if this is
1592 int apic_version
[MAX_APICS
];
1594 int __init
APIC_init_uniprocessor(void)
1597 pr_info("Apic disabled\n");
1600 #ifdef CONFIG_X86_64
1601 if (!cpu_has_apic
) {
1603 pr_info("Apic disabled by BIOS\n");
1607 if (!smp_found_config
&& !cpu_has_apic
)
1611 * Complain if the BIOS pretends there is one.
1613 if (!cpu_has_apic
&&
1614 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1615 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1616 boot_cpu_physical_apicid
);
1617 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1625 #ifdef CONFIG_X86_64
1626 default_setup_apic_routing();
1629 verify_local_APIC();
1632 #ifdef CONFIG_X86_64
1633 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1636 * Hack: In case of kdump, after a crash, kernel might be booting
1637 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1638 * might be zero if read from MP tables. Get it from LAPIC.
1640 # ifdef CONFIG_CRASH_DUMP
1641 boot_cpu_physical_apicid
= read_apic_id();
1644 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1647 #ifdef CONFIG_X86_64
1649 * Now enable IO-APICs, actually call clear_IO_APIC
1650 * We need clear_IO_APIC before enabling vector on BP
1652 if (!skip_ioapic_setup
&& nr_ioapics
)
1656 #ifdef CONFIG_X86_IO_APIC
1657 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1659 localise_nmi_watchdog();
1660 end_local_APIC_setup();
1662 #ifdef CONFIG_X86_IO_APIC
1663 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1665 # ifdef CONFIG_X86_64
1671 #ifdef CONFIG_X86_64
1672 setup_boot_APIC_clock();
1673 check_nmi_watchdog();
1682 * Local APIC interrupts
1686 * This interrupt should _never_ happen with our APIC/SMP architecture
1688 void smp_spurious_interrupt(struct pt_regs
*regs
)
1695 * Check if this really is a spurious interrupt and ACK it
1696 * if it is a vectored one. Just in case...
1697 * Spurious interrupts should not be ACKed.
1699 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1700 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1703 inc_irq_stat(irq_spurious_count
);
1705 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1706 pr_info("spurious APIC interrupt on CPU#%d, "
1707 "should never happen.\n", smp_processor_id());
1712 * This interrupt should never happen with our APIC/SMP architecture
1714 void smp_error_interrupt(struct pt_regs
*regs
)
1720 /* First tickle the hardware, only then report what went on. -- REW */
1721 v
= apic_read(APIC_ESR
);
1722 apic_write(APIC_ESR
, 0);
1723 v1
= apic_read(APIC_ESR
);
1725 atomic_inc(&irq_err_count
);
1728 * Here is what the APIC error bits mean:
1730 * 1: Receive CS error
1731 * 2: Send accept error
1732 * 3: Receive accept error
1734 * 5: Send illegal vector
1735 * 6: Received illegal vector
1736 * 7: Illegal register address
1738 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1739 smp_processor_id(), v
, v1
);
1744 * connect_bsp_APIC - attach the APIC to the interrupt system
1746 void __init
connect_bsp_APIC(void)
1748 #ifdef CONFIG_X86_32
1751 * Do not trust the local APIC being empty at bootup.
1755 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1756 * local APIC to INT and NMI lines.
1758 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1759 "enabling APIC mode.\n");
1764 if (apic
->enable_apic_mode
)
1765 apic
->enable_apic_mode();
1769 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1770 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1772 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1775 void disconnect_bsp_APIC(int virt_wire_setup
)
1779 #ifdef CONFIG_X86_32
1782 * Put the board back into PIC mode (has an effect only on
1783 * certain older boards). Note that APIC interrupts, including
1784 * IPIs, won't work beyond this point! The only exception are
1787 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1788 "entering PIC mode.\n");
1795 /* Go back to Virtual Wire compatibility mode */
1797 /* For the spurious interrupt use vector F, and enable it */
1798 value
= apic_read(APIC_SPIV
);
1799 value
&= ~APIC_VECTOR_MASK
;
1800 value
|= APIC_SPIV_APIC_ENABLED
;
1802 apic_write(APIC_SPIV
, value
);
1804 if (!virt_wire_setup
) {
1806 * For LVT0 make it edge triggered, active high,
1807 * external and enabled
1809 value
= apic_read(APIC_LVT0
);
1810 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1811 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1812 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1813 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1814 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1815 apic_write(APIC_LVT0
, value
);
1818 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1822 * For LVT1 make it edge triggered, active high,
1825 value
= apic_read(APIC_LVT1
);
1826 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1827 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1828 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1829 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1830 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1831 apic_write(APIC_LVT1
, value
);
1834 void __cpuinit
generic_processor_info(int apicid
, int version
)
1841 if (version
== 0x0) {
1842 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1843 "fixing up to 0x10. (tell your hw vendor)\n",
1847 apic_version
[apicid
] = version
;
1849 if (num_processors
>= nr_cpu_ids
) {
1850 int max
= nr_cpu_ids
;
1851 int thiscpu
= max
+ disabled_cpus
;
1854 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1855 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1862 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1864 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1866 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1867 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1869 physid_set(apicid
, phys_cpu_present_map
);
1870 if (apicid
== boot_cpu_physical_apicid
) {
1872 * x86_bios_cpu_apicid is required to have processors listed
1873 * in same order as logical cpu numbers. Hence the first
1874 * entry is BSP, and so on.
1878 if (apicid
> max_physical_apicid
)
1879 max_physical_apicid
= apicid
;
1881 #ifdef CONFIG_X86_32
1883 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1884 * but we need to work other dependencies like SMP_SUSPEND etc
1885 * before this can be done without some confusion.
1886 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1887 * - Ashok Raj <ashok.raj@intel.com>
1889 if (max_physical_apicid
>= 8) {
1890 switch (boot_cpu_data
.x86_vendor
) {
1891 case X86_VENDOR_INTEL
:
1892 if (!APIC_XAPIC(version
)) {
1896 /* If P4 and above fall through */
1897 case X86_VENDOR_AMD
:
1903 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1904 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1905 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1908 set_cpu_possible(cpu
, true);
1909 set_cpu_present(cpu
, true);
1912 int hard_smp_processor_id(void)
1914 return read_apic_id();
1917 void default_init_apic_ldr(void)
1921 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1922 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1923 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1924 apic_write(APIC_LDR
, val
);
1927 #ifdef CONFIG_X86_32
1928 int default_apicid_to_node(int logical_apicid
)
1931 return apicid_2_node
[hard_smp_processor_id()];
1945 * 'active' is true if the local APIC was enabled by us and
1946 * not the BIOS; this signifies that we are also responsible
1947 * for disabling it before entering apm/acpi suspend
1950 /* r/w apic fields */
1951 unsigned int apic_id
;
1952 unsigned int apic_taskpri
;
1953 unsigned int apic_ldr
;
1954 unsigned int apic_dfr
;
1955 unsigned int apic_spiv
;
1956 unsigned int apic_lvtt
;
1957 unsigned int apic_lvtpc
;
1958 unsigned int apic_lvt0
;
1959 unsigned int apic_lvt1
;
1960 unsigned int apic_lvterr
;
1961 unsigned int apic_tmict
;
1962 unsigned int apic_tdcr
;
1963 unsigned int apic_thmr
;
1966 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1968 unsigned long flags
;
1971 if (!apic_pm_state
.active
)
1974 maxlvt
= lapic_get_maxlvt();
1976 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1977 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1978 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1979 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1980 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1981 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1983 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1984 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1985 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1986 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1987 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1988 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1989 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1991 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1994 local_irq_save(flags
);
1995 disable_local_APIC();
1996 local_irq_restore(flags
);
2000 static int lapic_resume(struct sys_device
*dev
)
2003 unsigned long flags
;
2006 if (!apic_pm_state
.active
)
2009 maxlvt
= lapic_get_maxlvt();
2011 local_irq_save(flags
);
2020 * Make sure the APICBASE points to the right address
2022 * FIXME! This will be wrong if we ever support suspend on
2023 * SMP! We'll need to do this as part of the CPU restore!
2025 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2026 l
&= ~MSR_IA32_APICBASE_BASE
;
2027 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2028 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2031 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2032 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2033 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2034 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2035 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2036 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2037 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2038 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2039 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2041 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2044 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2045 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2046 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2047 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2048 apic_write(APIC_ESR
, 0);
2049 apic_read(APIC_ESR
);
2050 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2051 apic_write(APIC_ESR
, 0);
2052 apic_read(APIC_ESR
);
2054 local_irq_restore(flags
);
2060 * This device has no shutdown method - fully functioning local APICs
2061 * are needed on every CPU up until machine_halt/restart/poweroff.
2064 static struct sysdev_class lapic_sysclass
= {
2066 .resume
= lapic_resume
,
2067 .suspend
= lapic_suspend
,
2070 static struct sys_device device_lapic
= {
2072 .cls
= &lapic_sysclass
,
2075 static void __cpuinit
apic_pm_activate(void)
2077 apic_pm_state
.active
= 1;
2080 static int __init
init_lapic_sysfs(void)
2086 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2088 error
= sysdev_class_register(&lapic_sysclass
);
2090 error
= sysdev_register(&device_lapic
);
2093 device_initcall(init_lapic_sysfs
);
2095 #else /* CONFIG_PM */
2097 static void apic_pm_activate(void) { }
2099 #endif /* CONFIG_PM */
2101 #ifdef CONFIG_X86_64
2103 * apic_is_clustered_box() -- Check if we can expect good TSC
2105 * Thus far, the major user of this is IBM's Summit2 series:
2107 * Clustered boxes may have unsynced TSC problems if they are
2108 * multi-chassis. Use available data to take a good guess.
2109 * If in doubt, go HPET.
2111 __cpuinit
int apic_is_clustered_box(void)
2113 int i
, clusters
, zeros
;
2115 u16
*bios_cpu_apicid
;
2116 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2119 * there is not this kind of box with AMD CPU yet.
2120 * Some AMD box with quadcore cpu and 8 sockets apicid
2121 * will be [4, 0x23] or [8, 0x27] could be thought to
2122 * vsmp box still need checking...
2124 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2127 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2128 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2130 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2131 /* are we being called early in kernel startup? */
2132 if (bios_cpu_apicid
) {
2133 id
= bios_cpu_apicid
[i
];
2134 } else if (i
< nr_cpu_ids
) {
2136 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2142 if (id
!= BAD_APICID
)
2143 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2146 /* Problem: Partially populated chassis may not have CPUs in some of
2147 * the APIC clusters they have been allocated. Only present CPUs have
2148 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2149 * Since clusters are allocated sequentially, count zeros only if
2150 * they are bounded by ones.
2154 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2155 if (test_bit(i
, clustermap
)) {
2156 clusters
+= 1 + zeros
;
2162 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2163 * not guaranteed to be synced between boards
2165 if (is_vsmp_box() && clusters
> 1)
2169 * If clusters > 2, then should be multi-chassis.
2170 * May have to revisit this when multi-core + hyperthreaded CPUs come
2171 * out, but AFAIK this will work even for them.
2173 return (clusters
> 2);
2178 * APIC command line parameters
2180 static int __init
setup_disableapic(char *arg
)
2183 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2186 early_param("disableapic", setup_disableapic
);
2188 /* same as disableapic, for compatibility */
2189 static int __init
setup_nolapic(char *arg
)
2191 return setup_disableapic(arg
);
2193 early_param("nolapic", setup_nolapic
);
2195 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2197 local_apic_timer_c2_ok
= 1;
2200 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2202 static int __init
parse_disable_apic_timer(char *arg
)
2204 disable_apic_timer
= 1;
2207 early_param("noapictimer", parse_disable_apic_timer
);
2209 static int __init
parse_nolapic_timer(char *arg
)
2211 disable_apic_timer
= 1;
2214 early_param("nolapic_timer", parse_nolapic_timer
);
2216 static int __init
apic_set_verbosity(char *arg
)
2219 #ifdef CONFIG_X86_64
2220 skip_ioapic_setup
= 0;
2226 if (strcmp("debug", arg
) == 0)
2227 apic_verbosity
= APIC_DEBUG
;
2228 else if (strcmp("verbose", arg
) == 0)
2229 apic_verbosity
= APIC_VERBOSE
;
2231 pr_warning("APIC Verbosity level %s not recognised"
2232 " use apic=verbose or apic=debug\n", arg
);
2238 early_param("apic", apic_set_verbosity
);
2240 static int __init
lapic_insert_resource(void)
2245 /* Put local APIC into the resource map. */
2246 lapic_resource
.start
= apic_phys
;
2247 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2248 insert_resource(&iomem_resource
, &lapic_resource
);
2254 * need call insert after e820_reserve_resources()
2255 * that is using request_resource
2257 late_initcall(lapic_insert_resource
);