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[SCSI] qla2xxx: Add checks for a valid fcport in dev-loss-tmo/terminate_rport_io...
[linux-2.6/mini2440.git] / drivers / serial / samsung.c
blob41ac94872b8d952a6b3250cacf3f12432e5ed107
1 /* linux/drivers/serial/samsuing.c
2 *
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 /* Hote on 2410 error handling
14 *
15 * The s3c2410 manual has a love/hate affair with the contents of the
16 * UERSTAT register in the UART blocks, and keeps marking some of the
17 * error bits as reserved. Having checked with the s3c2410x01,
18 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
19 * feature from the latter versions of the manual.
20 *
21 * If it becomes aparrent that latter versions of the 2410 remove these
22 * bits, then action will have to be taken to differentiate the versions
23 * and change the policy on BREAK
24 *
25 * BJD, 04-Nov-2004
26 */
27
28 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
29 #define SUPPORT_SYSRQ
30 #endif
31
32 #include <linux/module.h>
33 #include <linux/ioport.h>
34 #include <linux/io.h>
35 #include <linux/platform_device.h>
36 #include <linux/init.h>
37 #include <linux/sysrq.h>
38 #include <linux/console.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
46
47 #include <asm/irq.h>
48
49 #include <mach/hardware.h>
50 #include <mach/map.h>
51
52 #include <plat/regs-serial.h>
53
54 #include "samsung.h"
55
56 /* UART name and device definitions */
57
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
61
62 /* macros to change one thing to another */
63
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
66
67 /* flag to ignore all characters comming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
69
70 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71 {
72 return container_of(port, struct s3c24xx_uart_port, port);
73 }
74
75 /* translate a port to the device name */
76
77 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78 {
79 return to_platform_device(port->dev)->name;
80 }
81
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83 {
84 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
85 }
86
87 static void s3c24xx_serial_rx_enable(struct uart_port *port)
88 {
89 unsigned long flags;
90 unsigned int ucon, ufcon;
91 int count = 10000;
92
93 spin_lock_irqsave(&port->lock, flags);
94
95 while (--count && !s3c24xx_serial_txempty_nofifo(port))
96 udelay(100);
97
98 ufcon = rd_regl(port, S3C2410_UFCON);
99 ufcon |= S3C2410_UFCON_RESETRX;
100 wr_regl(port, S3C2410_UFCON, ufcon);
101
102 ucon = rd_regl(port, S3C2410_UCON);
103 ucon |= S3C2410_UCON_RXIRQMODE;
104 wr_regl(port, S3C2410_UCON, ucon);
105
106 rx_enabled(port) = 1;
107 spin_unlock_irqrestore(&port->lock, flags);
108 }
109
110 static void s3c24xx_serial_rx_disable(struct uart_port *port)
111 {
112 unsigned long flags;
113 unsigned int ucon;
114
115 spin_lock_irqsave(&port->lock, flags);
116
117 ucon = rd_regl(port, S3C2410_UCON);
118 ucon &= ~S3C2410_UCON_RXIRQMODE;
119 wr_regl(port, S3C2410_UCON, ucon);
120
121 rx_enabled(port) = 0;
122 spin_unlock_irqrestore(&port->lock, flags);
123 }
124
125 static void s3c24xx_serial_stop_tx(struct uart_port *port)
126 {
127 struct s3c24xx_uart_port *ourport = to_ourport(port);
128
129 if (tx_enabled(port)) {
130 disable_irq(ourport->tx_irq);
131 tx_enabled(port) = 0;
132 if (port->flags & UPF_CONS_FLOW)
133 s3c24xx_serial_rx_enable(port);
134 }
135 }
136
137 static void s3c24xx_serial_start_tx(struct uart_port *port)
138 {
139 struct s3c24xx_uart_port *ourport = to_ourport(port);
140
141 if (!tx_enabled(port)) {
142 if (port->flags & UPF_CONS_FLOW)
143 s3c24xx_serial_rx_disable(port);
144
145 enable_irq(ourport->tx_irq);
146 tx_enabled(port) = 1;
147 }
148 }
149
150
151 static void s3c24xx_serial_stop_rx(struct uart_port *port)
152 {
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
155 if (rx_enabled(port)) {
156 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
157 disable_irq(ourport->rx_irq);
158 rx_enabled(port) = 0;
159 }
160 }
161
162 static void s3c24xx_serial_enable_ms(struct uart_port *port)
163 {
164 }
165
166 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
167 {
168 return to_ourport(port)->info;
169 }
170
171 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
172 {
173 if (port->dev == NULL)
174 return NULL;
175
176 return (struct s3c2410_uartcfg *)port->dev->platform_data;
177 }
178
179 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
180 unsigned long ufstat)
181 {
182 struct s3c24xx_uart_info *info = ourport->info;
183
184 if (ufstat & info->rx_fifofull)
185 return info->fifosize;
186
187 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
188 }
189
190
191 /* ? - where has parity gone?? */
192 #define S3C2410_UERSTAT_PARITY (0x1000)
193
194 static irqreturn_t
195 s3c24xx_serial_rx_chars(int irq, void *dev_id)
196 {
197 struct s3c24xx_uart_port *ourport = dev_id;
198 struct uart_port *port = &ourport->port;
199 struct tty_struct *tty = port->info->port.tty;
200 unsigned int ufcon, ch, flag, ufstat, uerstat;
201 int max_count = 64;
202
203 while (max_count-- > 0) {
204 ufcon = rd_regl(port, S3C2410_UFCON);
205 ufstat = rd_regl(port, S3C2410_UFSTAT);
206
207 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
208 break;
209
210 uerstat = rd_regl(port, S3C2410_UERSTAT);
211 ch = rd_regb(port, S3C2410_URXH);
212
213 if (port->flags & UPF_CONS_FLOW) {
214 int txe = s3c24xx_serial_txempty_nofifo(port);
215
216 if (rx_enabled(port)) {
217 if (!txe) {
218 rx_enabled(port) = 0;
219 continue;
220 }
221 } else {
222 if (txe) {
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
225 rx_enabled(port) = 1;
226 goto out;
227 }
228 continue;
229 }
230 }
231
232 /* insert the character into the buffer */
233
234 flag = TTY_NORMAL;
235 port->icount.rx++;
236
237 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
238 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
239 ch, uerstat);
240
241 /* check for break */
242 if (uerstat & S3C2410_UERSTAT_BREAK) {
243 dbg("break!\n");
244 port->icount.brk++;
245 if (uart_handle_break(port))
246 goto ignore_char;
247 }
248
249 if (uerstat & S3C2410_UERSTAT_FRAME)
250 port->icount.frame++;
251 if (uerstat & S3C2410_UERSTAT_OVERRUN)
252 port->icount.overrun++;
253
254 uerstat &= port->read_status_mask;
255
256 if (uerstat & S3C2410_UERSTAT_BREAK)
257 flag = TTY_BREAK;
258 else if (uerstat & S3C2410_UERSTAT_PARITY)
259 flag = TTY_PARITY;
260 else if (uerstat & (S3C2410_UERSTAT_FRAME |
261 S3C2410_UERSTAT_OVERRUN))
262 flag = TTY_FRAME;
263 }
264
265 if (uart_handle_sysrq_char(port, ch))
266 goto ignore_char;
267
268 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
269 ch, flag);
270
271 ignore_char:
272 continue;
273 }
274 tty_flip_buffer_push(tty);
275
276 out:
277 return IRQ_HANDLED;
278 }
279
280 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
281 {
282 struct s3c24xx_uart_port *ourport = id;
283 struct uart_port *port = &ourport->port;
284 struct circ_buf *xmit = &port->info->xmit;
285 int count = 256;
286
287 if (port->x_char) {
288 wr_regb(port, S3C2410_UTXH, port->x_char);
289 port->icount.tx++;
290 port->x_char = 0;
291 goto out;
292 }
293
294 /* if there isnt anything more to transmit, or the uart is now
295 * stopped, disable the uart and exit
296 */
297
298 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
299 s3c24xx_serial_stop_tx(port);
300 goto out;
301 }
302
303 /* try and drain the buffer... */
304
305 while (!uart_circ_empty(xmit) && count-- > 0) {
306 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
307 break;
308
309 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
310 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
311 port->icount.tx++;
312 }
313
314 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
315 uart_write_wakeup(port);
316
317 if (uart_circ_empty(xmit))
318 s3c24xx_serial_stop_tx(port);
319
320 out:
321 return IRQ_HANDLED;
322 }
323
324 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
325 {
326 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
327 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
328 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
329
330 if (ufcon & S3C2410_UFCON_FIFOMODE) {
331 if ((ufstat & info->tx_fifomask) != 0 ||
332 (ufstat & info->tx_fifofull))
333 return 0;
334
335 return 1;
336 }
337
338 return s3c24xx_serial_txempty_nofifo(port);
339 }
340
341 /* no modem control lines */
342 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
343 {
344 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
345
346 if (umstat & S3C2410_UMSTAT_CTS)
347 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
348 else
349 return TIOCM_CAR | TIOCM_DSR;
350 }
351
352 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
353 {
354 /* todo - possibly remove AFC and do manual CTS */
355 }
356
357 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
358 {
359 unsigned long flags;
360 unsigned int ucon;
361
362 spin_lock_irqsave(&port->lock, flags);
363
364 ucon = rd_regl(port, S3C2410_UCON);
365
366 if (break_state)
367 ucon |= S3C2410_UCON_SBREAK;
368 else
369 ucon &= ~S3C2410_UCON_SBREAK;
370
371 wr_regl(port, S3C2410_UCON, ucon);
372
373 spin_unlock_irqrestore(&port->lock, flags);
374 }
375
376 static void s3c24xx_serial_shutdown(struct uart_port *port)
377 {
378 struct s3c24xx_uart_port *ourport = to_ourport(port);
379
380 if (ourport->tx_claimed) {
381 free_irq(ourport->tx_irq, ourport);
382 tx_enabled(port) = 0;
383 ourport->tx_claimed = 0;
384 }
385
386 if (ourport->rx_claimed) {
387 free_irq(ourport->rx_irq, ourport);
388 ourport->rx_claimed = 0;
389 rx_enabled(port) = 0;
390 }
391 }
392
393
394 static int s3c24xx_serial_startup(struct uart_port *port)
395 {
396 struct s3c24xx_uart_port *ourport = to_ourport(port);
397 int ret;
398
399 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
400 port->mapbase, port->membase);
401
402 rx_enabled(port) = 1;
403
404 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
405 s3c24xx_serial_portname(port), ourport);
406
407 if (ret != 0) {
408 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
409 return ret;
410 }
411
412 ourport->rx_claimed = 1;
413
414 dbg("requesting tx irq...\n");
415
416 tx_enabled(port) = 1;
417
418 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
419 s3c24xx_serial_portname(port), ourport);
420
421 if (ret) {
422 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
423 goto err;
424 }
425
426 ourport->tx_claimed = 1;
427
428 dbg("s3c24xx_serial_startup ok\n");
429
430 /* the port reset code should have done the correct
431 * register setup for the port controls */
432
433 return ret;
434
435 err:
436 s3c24xx_serial_shutdown(port);
437 return ret;
438 }
439
440 /* power power management control */
441
442 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
443 unsigned int old)
444 {
445 struct s3c24xx_uart_port *ourport = to_ourport(port);
446
447 ourport->pm_level = level;
448
449 switch (level) {
450 case 3:
451 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
452 clk_disable(ourport->baudclk);
453
454 clk_disable(ourport->clk);
455 break;
456
457 case 0:
458 clk_enable(ourport->clk);
459
460 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
461 clk_enable(ourport->baudclk);
462
463 break;
464 default:
465 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
466 }
467 }
468
469 /* baud rate calculation
470 *
471 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
472 * of different sources, including the peripheral clock ("pclk") and an
473 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
474 * with a programmable extra divisor.
475 *
476 * The following code goes through the clock sources, and calculates the
477 * baud clocks (and the resultant actual baud rates) and then tries to
478 * pick the closest one and select that.
479 *
480 */
481
482
483 #define MAX_CLKS (8)
484
485 static struct s3c24xx_uart_clksrc tmp_clksrc = {
486 .name = "pclk",
487 .min_baud = 0,
488 .max_baud = 0,
489 .divisor = 1,
490 };
491
492 static inline int
493 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
494 {
495 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
496
497 return (info->get_clksrc)(port, c);
498 }
499
500 static inline int
501 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
502 {
503 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
504
505 return (info->set_clksrc)(port, c);
506 }
507
508 struct baud_calc {
509 struct s3c24xx_uart_clksrc *clksrc;
510 unsigned int calc;
511 unsigned int quot;
512 struct clk *src;
513 };
514
515 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
516 struct uart_port *port,
517 struct s3c24xx_uart_clksrc *clksrc,
518 unsigned int baud)
519 {
520 unsigned long rate;
521
522 calc->src = clk_get(port->dev, clksrc->name);
523 if (calc->src == NULL || IS_ERR(calc->src))
524 return 0;
525
526 rate = clk_get_rate(calc->src);
527 rate /= clksrc->divisor;
528
529 calc->clksrc = clksrc;
530 calc->quot = (rate + (8 * baud)) / (16 * baud);
531 calc->calc = (rate / (calc->quot * 16));
532
533 calc->quot--;
534 return 1;
535 }
536
537 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
538 struct s3c24xx_uart_clksrc **clksrc,
539 struct clk **clk,
540 unsigned int baud)
541 {
542 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
543 struct s3c24xx_uart_clksrc *clkp;
544 struct baud_calc res[MAX_CLKS];
545 struct baud_calc *resptr, *best, *sptr;
546 int i;
547
548 clkp = cfg->clocks;
549 best = NULL;
550
551 if (cfg->clocks_size < 2) {
552 if (cfg->clocks_size == 0)
553 clkp = &tmp_clksrc;
554
555 /* check to see if we're sourcing fclk, and if so we're
556 * going to have to update the clock source
557 */
558
559 if (strcmp(clkp->name, "fclk") == 0) {
560 struct s3c24xx_uart_clksrc src;
561
562 s3c24xx_serial_getsource(port, &src);
563
564 /* check that the port already using fclk, and if
565 * not, then re-select fclk
566 */
567
568 if (strcmp(src.name, clkp->name) == 0) {
569 s3c24xx_serial_setsource(port, clkp);
570 s3c24xx_serial_getsource(port, &src);
571 }
572
573 clkp->divisor = src.divisor;
574 }
575
576 s3c24xx_serial_calcbaud(res, port, clkp, baud);
577 best = res;
578 resptr = best + 1;
579 } else {
580 resptr = res;
581
582 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
583 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
584 resptr++;
585 }
586 }
587
588 /* ok, we now need to select the best clock we found */
589
590 if (!best) {
591 unsigned int deviation = (1<<30)|((1<<30)-1);
592 int calc_deviation;
593
594 for (sptr = res; sptr < resptr; sptr++) {
595 calc_deviation = baud - sptr->calc;
596 if (calc_deviation < 0)
597 calc_deviation = -calc_deviation;
598
599 if (calc_deviation < deviation) {
600 best = sptr;
601 deviation = calc_deviation;
602 }
603 }
604 }
605
606 /* store results to pass back */
607
608 *clksrc = best->clksrc;
609 *clk = best->src;
610
611 return best->quot;
612 }
613
614 static void s3c24xx_serial_set_termios(struct uart_port *port,
615 struct ktermios *termios,
616 struct ktermios *old)
617 {
618 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
619 struct s3c24xx_uart_port *ourport = to_ourport(port);
620 struct s3c24xx_uart_clksrc *clksrc = NULL;
621 struct clk *clk = NULL;
622 unsigned long flags;
623 unsigned int baud, quot;
624 unsigned int ulcon;
625 unsigned int umcon;
626
627 /*
628 * We don't support modem control lines.
629 */
630 termios->c_cflag &= ~(HUPCL | CMSPAR);
631 termios->c_cflag |= CLOCAL;
632
633 /*
634 * Ask the core to calculate the divisor for us.
635 */
636
637 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
638
639 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
640 quot = port->custom_divisor;
641 else
642 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
643
644 /* check to see if we need to change clock source */
645
646 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
647 s3c24xx_serial_setsource(port, clksrc);
648
649 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
650 clk_disable(ourport->baudclk);
651 ourport->baudclk = NULL;
652 }
653
654 clk_enable(clk);
655
656 ourport->clksrc = clksrc;
657 ourport->baudclk = clk;
658 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
659 }
660
661 switch (termios->c_cflag & CSIZE) {
662 case CS5:
663 dbg("config: 5bits/char\n");
664 ulcon = S3C2410_LCON_CS5;
665 break;
666 case CS6:
667 dbg("config: 6bits/char\n");
668 ulcon = S3C2410_LCON_CS6;
669 break;
670 case CS7:
671 dbg("config: 7bits/char\n");
672 ulcon = S3C2410_LCON_CS7;
673 break;
674 case CS8:
675 default:
676 dbg("config: 8bits/char\n");
677 ulcon = S3C2410_LCON_CS8;
678 break;
679 }
680
681 /* preserve original lcon IR settings */
682 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
683
684 if (termios->c_cflag & CSTOPB)
685 ulcon |= S3C2410_LCON_STOPB;
686
687 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
688
689 if (termios->c_cflag & PARENB) {
690 if (termios->c_cflag & PARODD)
691 ulcon |= S3C2410_LCON_PODD;
692 else
693 ulcon |= S3C2410_LCON_PEVEN;
694 } else {
695 ulcon |= S3C2410_LCON_PNONE;
696 }
697
698 spin_lock_irqsave(&port->lock, flags);
699
700 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
701
702 wr_regl(port, S3C2410_ULCON, ulcon);
703 wr_regl(port, S3C2410_UBRDIV, quot);
704 wr_regl(port, S3C2410_UMCON, umcon);
705
706 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
707 rd_regl(port, S3C2410_ULCON),
708 rd_regl(port, S3C2410_UCON),
709 rd_regl(port, S3C2410_UFCON));
710
711 /*
712 * Update the per-port timeout.
713 */
714 uart_update_timeout(port, termios->c_cflag, baud);
715
716 /*
717 * Which character status flags are we interested in?
718 */
719 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
720 if (termios->c_iflag & INPCK)
721 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
722
723 /*
724 * Which character status flags should we ignore?
725 */
726 port->ignore_status_mask = 0;
727 if (termios->c_iflag & IGNPAR)
728 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
729 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
730 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
731
732 /*
733 * Ignore all characters if CREAD is not set.
734 */
735 if ((termios->c_cflag & CREAD) == 0)
736 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
737
738 spin_unlock_irqrestore(&port->lock, flags);
739 }
740
741 static const char *s3c24xx_serial_type(struct uart_port *port)
742 {
743 switch (port->type) {
744 case PORT_S3C2410:
745 return "S3C2410";
746 case PORT_S3C2440:
747 return "S3C2440";
748 case PORT_S3C2412:
749 return "S3C2412";
750 case PORT_S3C6400:
751 return "S3C6400/10";
752 default:
753 return NULL;
754 }
755 }
756
757 #define MAP_SIZE (0x100)
758
759 static void s3c24xx_serial_release_port(struct uart_port *port)
760 {
761 release_mem_region(port->mapbase, MAP_SIZE);
762 }
763
764 static int s3c24xx_serial_request_port(struct uart_port *port)
765 {
766 const char *name = s3c24xx_serial_portname(port);
767 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
768 }
769
770 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
771 {
772 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
773
774 if (flags & UART_CONFIG_TYPE &&
775 s3c24xx_serial_request_port(port) == 0)
776 port->type = info->type;
777 }
778
779 /*
780 * verify the new serial_struct (for TIOCSSERIAL).
781 */
782 static int
783 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
784 {
785 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
786
787 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
788 return -EINVAL;
789
790 return 0;
791 }
792
793
794 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
795
796 static struct console s3c24xx_serial_console;
797
798 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
799 #else
800 #define S3C24XX_SERIAL_CONSOLE NULL
801 #endif
802
803 static struct uart_ops s3c24xx_serial_ops = {
804 .pm = s3c24xx_serial_pm,
805 .tx_empty = s3c24xx_serial_tx_empty,
806 .get_mctrl = s3c24xx_serial_get_mctrl,
807 .set_mctrl = s3c24xx_serial_set_mctrl,
808 .stop_tx = s3c24xx_serial_stop_tx,
809 .start_tx = s3c24xx_serial_start_tx,
810 .stop_rx = s3c24xx_serial_stop_rx,
811 .enable_ms = s3c24xx_serial_enable_ms,
812 .break_ctl = s3c24xx_serial_break_ctl,
813 .startup = s3c24xx_serial_startup,
814 .shutdown = s3c24xx_serial_shutdown,
815 .set_termios = s3c24xx_serial_set_termios,
816 .type = s3c24xx_serial_type,
817 .release_port = s3c24xx_serial_release_port,
818 .request_port = s3c24xx_serial_request_port,
819 .config_port = s3c24xx_serial_config_port,
820 .verify_port = s3c24xx_serial_verify_port,
821 };
822
823
824 static struct uart_driver s3c24xx_uart_drv = {
825 .owner = THIS_MODULE,
826 .dev_name = "s3c2410_serial",
827 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
828 .cons = S3C24XX_SERIAL_CONSOLE,
829 .driver_name = S3C24XX_SERIAL_NAME,
830 .major = S3C24XX_SERIAL_MAJOR,
831 .minor = S3C24XX_SERIAL_MINOR,
832 };
833
834 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
835 [0] = {
836 .port = {
837 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
838 .iotype = UPIO_MEM,
839 .irq = IRQ_S3CUART_RX0,
840 .uartclk = 0,
841 .fifosize = 16,
842 .ops = &s3c24xx_serial_ops,
843 .flags = UPF_BOOT_AUTOCONF,
844 .line = 0,
845 }
846 },
847 [1] = {
848 .port = {
849 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
850 .iotype = UPIO_MEM,
851 .irq = IRQ_S3CUART_RX1,
852 .uartclk = 0,
853 .fifosize = 16,
854 .ops = &s3c24xx_serial_ops,
855 .flags = UPF_BOOT_AUTOCONF,
856 .line = 1,
857 }
858 },
859 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
860
861 [2] = {
862 .port = {
863 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
864 .iotype = UPIO_MEM,
865 .irq = IRQ_S3CUART_RX2,
866 .uartclk = 0,
867 .fifosize = 16,
868 .ops = &s3c24xx_serial_ops,
869 .flags = UPF_BOOT_AUTOCONF,
870 .line = 2,
871 }
872 },
873 #endif
874 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
875 [3] = {
876 .port = {
877 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
878 .iotype = UPIO_MEM,
879 .irq = IRQ_S3CUART_RX3,
880 .uartclk = 0,
881 .fifosize = 16,
882 .ops = &s3c24xx_serial_ops,
883 .flags = UPF_BOOT_AUTOCONF,
884 .line = 3,
885 }
886 }
887 #endif
888 };
889
890 /* s3c24xx_serial_resetport
891 *
892 * wrapper to call the specific reset for this port (reset the fifos
893 * and the settings)
894 */
895
896 static inline int s3c24xx_serial_resetport(struct uart_port *port,
897 struct s3c2410_uartcfg *cfg)
898 {
899 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
900
901 return (info->reset_port)(port, cfg);
902 }
903
904
905 #ifdef CONFIG_CPU_FREQ
906
907 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
908 unsigned long val, void *data)
909 {
910 struct s3c24xx_uart_port *port;
911 struct uart_port *uport;
912
913 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
914 uport = &port->port;
915
916 /* check to see if port is enabled */
917
918 if (port->pm_level != 0)
919 return 0;
920
921 /* try and work out if the baudrate is changing, we can detect
922 * a change in rate, but we do not have support for detecting
923 * a disturbance in the clock-rate over the change.
924 */
925
926 if (IS_ERR(port->clk))
927 goto exit;
928
929 if (port->baudclk_rate == clk_get_rate(port->clk))
930 goto exit;
931
932 if (val == CPUFREQ_PRECHANGE) {
933 /* we should really shut the port down whilst the
934 * frequency change is in progress. */
935
936 } else if (val == CPUFREQ_POSTCHANGE) {
937 struct ktermios *termios;
938 struct tty_struct *tty;
939
940 if (uport->info == NULL)
941 goto exit;
942
943 tty = uport->info->port.tty;
944
945 if (tty == NULL)
946 goto exit;
947
948 termios = tty->termios;
949
950 if (termios == NULL) {
951 printk(KERN_WARNING "%s: no termios?\n", __func__);
952 goto exit;
953 }
954
955 s3c24xx_serial_set_termios(uport, termios, NULL);
956 }
957
958 exit:
959 return 0;
960 }
961
962 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
963 {
964 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
965
966 return cpufreq_register_notifier(&port->freq_transition,
967 CPUFREQ_TRANSITION_NOTIFIER);
968 }
969
970 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
971 {
972 cpufreq_unregister_notifier(&port->freq_transition,
973 CPUFREQ_TRANSITION_NOTIFIER);
974 }
975
976 #else
977 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
978 {
979 return 0;
980 }
981
982 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
983 {
984 }
985 #endif
986
987 /* s3c24xx_serial_init_port
988 *
989 * initialise a single serial port from the platform device given
990 */
991
992 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
993 struct s3c24xx_uart_info *info,
994 struct platform_device *platdev)
995 {
996 struct uart_port *port = &ourport->port;
997 struct s3c2410_uartcfg *cfg;
998 struct resource *res;
999 int ret;
1000
1001 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1002
1003 if (platdev == NULL)
1004 return -ENODEV;
1005
1006 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1007
1008 if (port->mapbase != 0)
1009 return 0;
1010
1011 if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
1012 printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
1013 cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
1014 return -ERANGE;
1015 }
1016
1017 /* setup info for port */
1018 port->dev = &platdev->dev;
1019 ourport->info = info;
1020
1021 /* copy the info in from provided structure */
1022 ourport->port.fifosize = info->fifosize;
1023
1024 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1025
1026 port->uartclk = 1;
1027
1028 if (cfg->uart_flags & UPF_CONS_FLOW) {
1029 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1030 port->flags |= UPF_CONS_FLOW;
1031 }
1032
1033 /* sort our the physical and virtual addresses for each UART */
1034
1035 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1036 if (res == NULL) {
1037 printk(KERN_ERR "failed to find memory resource for uart\n");
1038 return -EINVAL;
1039 }
1040
1041 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1042
1043 port->mapbase = res->start;
1044 port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
1045 ret = platform_get_irq(platdev, 0);
1046 if (ret < 0)
1047 port->irq = 0;
1048 else {
1049 port->irq = ret;
1050 ourport->rx_irq = ret;
1051 ourport->tx_irq = ret + 1;
1052 }
1053
1054 ret = platform_get_irq(platdev, 1);
1055 if (ret > 0)
1056 ourport->tx_irq = ret;
1057
1058 ourport->clk = clk_get(&platdev->dev, "uart");
1059
1060 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1061 port->mapbase, port->membase, port->irq,
1062 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1063
1064 /* reset the fifos (and setup the uart) */
1065 s3c24xx_serial_resetport(port, cfg);
1066 return 0;
1067 }
1068
1069 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1070 struct device_attribute *attr,
1071 char *buf)
1072 {
1073 struct uart_port *port = s3c24xx_dev_to_port(dev);
1074 struct s3c24xx_uart_port *ourport = to_ourport(port);
1075
1076 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name);
1077 }
1078
1079 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1080
1081 /* Device driver serial port probe */
1082
1083 static int probe_index;
1084
1085 int s3c24xx_serial_probe(struct platform_device *dev,
1086 struct s3c24xx_uart_info *info)
1087 {
1088 struct s3c24xx_uart_port *ourport;
1089 int ret;
1090
1091 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1092
1093 ourport = &s3c24xx_serial_ports[probe_index];
1094 probe_index++;
1095
1096 dbg("%s: initialising port %p...\n", __func__, ourport);
1097
1098 ret = s3c24xx_serial_init_port(ourport, info, dev);
1099 if (ret < 0)
1100 goto probe_err;
1101
1102 dbg("%s: adding port\n", __func__);
1103 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1104 platform_set_drvdata(dev, &ourport->port);
1105
1106 ret = device_create_file(&dev->dev, &dev_attr_clock_source);
1107 if (ret < 0)
1108 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
1109
1110 ret = s3c24xx_serial_cpufreq_register(ourport);
1111 if (ret < 0)
1112 dev_err(&dev->dev, "failed to add cpufreq notifier\n");
1113
1114 return 0;
1115
1116 probe_err:
1117 return ret;
1118 }
1119
1120 EXPORT_SYMBOL_GPL(s3c24xx_serial_probe);
1121
1122 int s3c24xx_serial_remove(struct platform_device *dev)
1123 {
1124 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1125
1126 if (port) {
1127 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1128 device_remove_file(&dev->dev, &dev_attr_clock_source);
1129 uart_remove_one_port(&s3c24xx_uart_drv, port);
1130 }
1131
1132 return 0;
1133 }
1134
1135 EXPORT_SYMBOL_GPL(s3c24xx_serial_remove);
1136
1137 /* UART power management code */
1138
1139 #ifdef CONFIG_PM
1140
1141 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1142 {
1143 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1144
1145 if (port)
1146 uart_suspend_port(&s3c24xx_uart_drv, port);
1147
1148 return 0;
1149 }
1150
1151 static int s3c24xx_serial_resume(struct platform_device *dev)
1152 {
1153 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1154 struct s3c24xx_uart_port *ourport = to_ourport(port);
1155
1156 if (port) {
1157 clk_enable(ourport->clk);
1158 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1159 clk_disable(ourport->clk);
1160
1161 uart_resume_port(&s3c24xx_uart_drv, port);
1162 }
1163
1164 return 0;
1165 }
1166 #endif
1167
1168 int s3c24xx_serial_init(struct platform_driver *drv,
1169 struct s3c24xx_uart_info *info)
1170 {
1171 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1172
1173 #ifdef CONFIG_PM
1174 drv->suspend = s3c24xx_serial_suspend;
1175 drv->resume = s3c24xx_serial_resume;
1176 #endif
1177
1178 return platform_driver_register(drv);
1179 }
1180
1181 EXPORT_SYMBOL_GPL(s3c24xx_serial_init);
1182
1183 /* module initialisation code */
1184
1185 static int __init s3c24xx_serial_modinit(void)
1186 {
1187 int ret;
1188
1189 ret = uart_register_driver(&s3c24xx_uart_drv);
1190 if (ret < 0) {
1191 printk(KERN_ERR "failed to register UART driver\n");
1192 return -1;
1193 }
1194
1195 return 0;
1196 }
1197
1198 static void __exit s3c24xx_serial_modexit(void)
1199 {
1200 uart_unregister_driver(&s3c24xx_uart_drv);
1201 }
1202
1203 module_init(s3c24xx_serial_modinit);
1204 module_exit(s3c24xx_serial_modexit);
1205
1206 /* Console code */
1207
1208 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1209
1210 static struct uart_port *cons_uart;
1211
1212 static int
1213 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1214 {
1215 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1216 unsigned long ufstat, utrstat;
1217
1218 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1219 /* fifo mode - check ammount of data in fifo registers... */
1220
1221 ufstat = rd_regl(port, S3C2410_UFSTAT);
1222 return (ufstat & info->tx_fifofull) ? 0 : 1;
1223 }
1224
1225 /* in non-fifo mode, we go and use the tx buffer empty */
1226
1227 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1228 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1229 }
1230
1231 static void
1232 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1233 {
1234 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1235 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1236 barrier();
1237 wr_regb(cons_uart, S3C2410_UTXH, ch);
1238 }
1239
1240 static void
1241 s3c24xx_serial_console_write(struct console *co, const char *s,
1242 unsigned int count)
1243 {
1244 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1245 }
1246
1247 static void __init
1248 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1249 int *parity, int *bits)
1250 {
1251 struct s3c24xx_uart_clksrc clksrc;
1252 struct clk *clk;
1253 unsigned int ulcon;
1254 unsigned int ucon;
1255 unsigned int ubrdiv;
1256 unsigned long rate;
1257
1258 ulcon = rd_regl(port, S3C2410_ULCON);
1259 ucon = rd_regl(port, S3C2410_UCON);
1260 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1261
1262 dbg("s3c24xx_serial_get_options: port=%p\n"
1263 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1264 port, ulcon, ucon, ubrdiv);
1265
1266 if ((ucon & 0xf) != 0) {
1267 /* consider the serial port configured if the tx/rx mode set */
1268
1269 switch (ulcon & S3C2410_LCON_CSMASK) {
1270 case S3C2410_LCON_CS5:
1271 *bits = 5;
1272 break;
1273 case S3C2410_LCON_CS6:
1274 *bits = 6;
1275 break;
1276 case S3C2410_LCON_CS7:
1277 *bits = 7;
1278 break;
1279 default:
1280 case S3C2410_LCON_CS8:
1281 *bits = 8;
1282 break;
1283 }
1284
1285 switch (ulcon & S3C2410_LCON_PMASK) {
1286 case S3C2410_LCON_PEVEN:
1287 *parity = 'e';
1288 break;
1289
1290 case S3C2410_LCON_PODD:
1291 *parity = 'o';
1292 break;
1293
1294 case S3C2410_LCON_PNONE:
1295 default:
1296 *parity = 'n';
1297 }
1298
1299 /* now calculate the baud rate */
1300
1301 s3c24xx_serial_getsource(port, &clksrc);
1302
1303 clk = clk_get(port->dev, clksrc.name);
1304 if (!IS_ERR(clk) && clk != NULL)
1305 rate = clk_get_rate(clk) / clksrc.divisor;
1306 else
1307 rate = 1;
1308
1309
1310 *baud = rate / (16 * (ubrdiv + 1));
1311 dbg("calculated baud %d\n", *baud);
1312 }
1313
1314 }
1315
1316 /* s3c24xx_serial_init_ports
1317 *
1318 * initialise the serial ports from the machine provided initialisation
1319 * data.
1320 */
1321
1322 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1323 {
1324 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1325 struct platform_device **platdev_ptr;
1326 int i;
1327
1328 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1329
1330 platdev_ptr = s3c24xx_uart_devs;
1331
1332 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
1333 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1334 }
1335
1336 return 0;
1337 }
1338
1339 static int __init
1340 s3c24xx_serial_console_setup(struct console *co, char *options)
1341 {
1342 struct uart_port *port;
1343 int baud = 9600;
1344 int bits = 8;
1345 int parity = 'n';
1346 int flow = 'n';
1347
1348 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1349 co, co->index, options);
1350
1351 /* is this a valid port */
1352
1353 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1354 co->index = 0;
1355
1356 port = &s3c24xx_serial_ports[co->index].port;
1357
1358 /* is the port configured? */
1359
1360 if (port->mapbase == 0x0) {
1361 co->index = 0;
1362 port = &s3c24xx_serial_ports[co->index].port;
1363 }
1364
1365 cons_uart = port;
1366
1367 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1368
1369 /*
1370 * Check whether an invalid uart number has been specified, and
1371 * if so, search for the first available port that does have
1372 * console support.
1373 */
1374 if (options)
1375 uart_parse_options(options, &baud, &parity, &bits, &flow);
1376 else
1377 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1378
1379 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1380
1381 return uart_set_options(port, co, baud, parity, bits, flow);
1382 }
1383
1384 /* s3c24xx_serial_initconsole
1385 *
1386 * initialise the console from one of the uart drivers
1387 */
1388
1389 static struct console s3c24xx_serial_console = {
1390 .name = S3C24XX_SERIAL_NAME,
1391 .device = uart_console_device,
1392 .flags = CON_PRINTBUFFER,
1393 .index = -1,
1394 .write = s3c24xx_serial_console_write,
1395 .setup = s3c24xx_serial_console_setup
1396 };
1397
1398 int s3c24xx_serial_initconsole(struct platform_driver *drv,
1399 struct s3c24xx_uart_info *info)
1400
1401 {
1402 struct platform_device *dev = s3c24xx_uart_devs[0];
1403
1404 dbg("s3c24xx_serial_initconsole\n");
1405
1406 /* select driver based on the cpu */
1407
1408 if (dev == NULL) {
1409 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1410 return 0;
1411 }
1412
1413 if (strcmp(dev->name, drv->driver.name) != 0)
1414 return 0;
1415
1416 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1417 s3c24xx_serial_init_ports(info);
1418
1419 register_console(&s3c24xx_serial_console);
1420 return 0;
1421 }
1422
1423 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1424
1425 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1426 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1427 MODULE_LICENSE("GPL v2");
Support for the Chinese Samsung S3C2440 based development boards