arch/sh/kernel/cpu/sh4a/setup-sh7723.c

   1 /*
   2  * SH7723 Setup
   3  *
   4  *  Copyright (C) 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/mm.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/uio_driver.h>
  16 #include <linux/sh_timer.h>
  17 #include <asm/clock.h>
  18 #include <asm/mmzone.h>
  19
  20 static struct uio_info vpu_platform_data = {
  21         .name = "VPU5",
  22         .version = "0",
  23         .irq = 60,
  24 };
  25
  26 static struct resource vpu_resources[] = {
  27         [0] = {
  28                 .name   = "VPU",
  29                 .start  = 0xfe900000,
  30                 .end    = 0xfe902807,
  31                 .flags  = IORESOURCE_MEM,
  32         },
  33         [1] = {
  34                 /* place holder for contiguous memory */
  35         },
  36 };
  37
  38 static struct platform_device vpu_device = {
  39         .name           = "uio_pdrv_genirq",
  40         .id             = 0,
  41         .dev = {
  42                 .platform_data  = &vpu_platform_data,
  43         },
  44         .resource       = vpu_resources,
  45         .num_resources  = ARRAY_SIZE(vpu_resources),
  46 };
  47
  48 static struct uio_info veu0_platform_data = {
  49         .name = "VEU2H",
  50         .version = "0",
  51         .irq = 54,
  52 };
  53
  54 static struct resource veu0_resources[] = {
  55         [0] = {
  56                 .name   = "VEU2H0",
  57                 .start  = 0xfe920000,
  58                 .end    = 0xfe92027b,
  59                 .flags  = IORESOURCE_MEM,
  60         },
  61         [1] = {
  62                 /* place holder for contiguous memory */
  63         },
  64 };
  65
  66 static struct platform_device veu0_device = {
  67         .name           = "uio_pdrv_genirq",
  68         .id             = 1,
  69         .dev = {
  70                 .platform_data  = &veu0_platform_data,
  71         },
  72         .resource       = veu0_resources,
  73         .num_resources  = ARRAY_SIZE(veu0_resources),
  74 };
  75
  76 static struct uio_info veu1_platform_data = {
  77         .name = "VEU2H",
  78         .version = "0",
  79         .irq = 27,
  80 };
  81
  82 static struct resource veu1_resources[] = {
  83         [0] = {
  84                 .name   = "VEU2H1",
  85                 .start  = 0xfe924000,
  86                 .end    = 0xfe92427b,
  87                 .flags  = IORESOURCE_MEM,
  88         },
  89         [1] = {
  90                 /* place holder for contiguous memory */
  91         },
  92 };
  93
  94 static struct platform_device veu1_device = {
  95         .name           = "uio_pdrv_genirq",
  96         .id             = 2,
  97         .dev = {
  98                 .platform_data  = &veu1_platform_data,
  99         },
 100         .resource       = veu1_resources,
 101         .num_resources  = ARRAY_SIZE(veu1_resources),
 102 };
 103
 104 static struct sh_timer_config cmt_platform_data = {
 105         .name = "CMT",
 106         .channel_offset = 0x60,
 107         .timer_bit = 5,
 108         .clk = "cmt0",
 109         .clockevent_rating = 125,
 110         .clocksource_rating = 125,
 111 };
 112
 113 static struct resource cmt_resources[] = {
 114         [0] = {
 115                 .name   = "CMT",
 116                 .start  = 0x044a0060,
 117                 .end    = 0x044a006b,
 118                 .flags  = IORESOURCE_MEM,
 119         },
 120         [1] = {
 121                 .start  = 104,
 122                 .flags  = IORESOURCE_IRQ,
 123         },
 124 };
 125
 126 static struct platform_device cmt_device = {
 127         .name           = "sh_cmt",
 128         .id             = 0,
 129         .dev = {
 130                 .platform_data  = &cmt_platform_data,
 131         },
 132         .resource       = cmt_resources,
 133         .num_resources  = ARRAY_SIZE(cmt_resources),
 134 };
 135
 136 static struct sh_timer_config tmu0_platform_data = {
 137         .name = "TMU0",
 138         .channel_offset = 0x04,
 139         .timer_bit = 0,
 140         .clk = "tmu0",
 141         .clockevent_rating = 200,
 142 };
 143
 144 static struct resource tmu0_resources[] = {
 145         [0] = {
 146                 .name   = "TMU0",
 147                 .start  = 0xffd80008,
 148                 .end    = 0xffd80013,
 149                 .flags  = IORESOURCE_MEM,
 150         },
 151         [1] = {
 152                 .start  = 16,
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct platform_device tmu0_device = {
 158         .name           = "sh_tmu",
 159         .id             = 0,
 160         .dev = {
 161                 .platform_data  = &tmu0_platform_data,
 162         },
 163         .resource       = tmu0_resources,
 164         .num_resources  = ARRAY_SIZE(tmu0_resources),
 165 };
 166
 167 static struct sh_timer_config tmu1_platform_data = {
 168         .name = "TMU1",
 169         .channel_offset = 0x10,
 170         .timer_bit = 1,
 171         .clk = "tmu0",
 172         .clocksource_rating = 200,
 173 };
 174
 175 static struct resource tmu1_resources[] = {
 176         [0] = {
 177                 .name   = "TMU1",
 178                 .start  = 0xffd80014,
 179                 .end    = 0xffd8001f,
 180                 .flags  = IORESOURCE_MEM,
 181         },
 182         [1] = {
 183                 .start  = 17,
 184                 .flags  = IORESOURCE_IRQ,
 185         },
 186 };
 187
 188 static struct platform_device tmu1_device = {
 189         .name           = "sh_tmu",
 190         .id             = 1,
 191         .dev = {
 192                 .platform_data  = &tmu1_platform_data,
 193         },
 194         .resource       = tmu1_resources,
 195         .num_resources  = ARRAY_SIZE(tmu1_resources),
 196 };
 197
 198 static struct sh_timer_config tmu2_platform_data = {
 199         .name = "TMU2",
 200         .channel_offset = 0x1c,
 201         .timer_bit = 2,
 202         .clk = "tmu0",
 203 };
 204
 205 static struct resource tmu2_resources[] = {
 206         [0] = {
 207                 .name   = "TMU2",
 208                 .start  = 0xffd80020,
 209                 .end    = 0xffd8002b,
 210                 .flags  = IORESOURCE_MEM,
 211         },
 212         [1] = {
 213                 .start  = 18,
 214                 .flags  = IORESOURCE_IRQ,
 215         },
 216 };
 217
 218 static struct platform_device tmu2_device = {
 219         .name           = "sh_tmu",
 220         .id             = 2,
 221         .dev = {
 222                 .platform_data  = &tmu2_platform_data,
 223         },
 224         .resource       = tmu2_resources,
 225         .num_resources  = ARRAY_SIZE(tmu2_resources),
 226 };
 227
 228 static struct sh_timer_config tmu3_platform_data = {
 229         .name = "TMU3",
 230         .channel_offset = 0x04,
 231         .timer_bit = 0,
 232         .clk = "tmu1",
 233 };
 234
 235 static struct resource tmu3_resources[] = {
 236         [0] = {
 237                 .name   = "TMU3",
 238                 .start  = 0xffd90008,
 239                 .end    = 0xffd90013,
 240                 .flags  = IORESOURCE_MEM,
 241         },
 242         [1] = {
 243                 .start  = 57,
 244                 .flags  = IORESOURCE_IRQ,
 245         },
 246 };
 247
 248 static struct platform_device tmu3_device = {
 249         .name           = "sh_tmu",
 250         .id             = 3,
 251         .dev = {
 252                 .platform_data  = &tmu3_platform_data,
 253         },
 254         .resource       = tmu3_resources,
 255         .num_resources  = ARRAY_SIZE(tmu3_resources),
 256 };
 257
 258 static struct sh_timer_config tmu4_platform_data = {
 259         .name = "TMU4",
 260         .channel_offset = 0x10,
 261         .timer_bit = 1,
 262         .clk = "tmu1",
 263 };
 264
 265 static struct resource tmu4_resources[] = {
 266         [0] = {
 267                 .name   = "TMU4",
 268                 .start  = 0xffd90014,
 269                 .end    = 0xffd9001f,
 270                 .flags  = IORESOURCE_MEM,
 271         },
 272         [1] = {
 273                 .start  = 58,
 274                 .flags  = IORESOURCE_IRQ,
 275         },
 276 };
 277
 278 static struct platform_device tmu4_device = {
 279         .name           = "sh_tmu",
 280         .id             = 4,
 281         .dev = {
 282                 .platform_data  = &tmu4_platform_data,
 283         },
 284         .resource       = tmu4_resources,
 285         .num_resources  = ARRAY_SIZE(tmu4_resources),
 286 };
 287
 288 static struct sh_timer_config tmu5_platform_data = {
 289         .name = "TMU5",
 290         .channel_offset = 0x1c,
 291         .timer_bit = 2,
 292         .clk = "tmu1",
 293 };
 294
 295 static struct resource tmu5_resources[] = {
 296         [0] = {
 297                 .name   = "TMU5",
 298                 .start  = 0xffd90020,
 299                 .end    = 0xffd9002b,
 300                 .flags  = IORESOURCE_MEM,
 301         },
 302         [1] = {
 303                 .start  = 57,
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device tmu5_device = {
 309         .name           = "sh_tmu",
 310         .id             = 5,
 311         .dev = {
 312                 .platform_data  = &tmu5_platform_data,
 313         },
 314         .resource       = tmu5_resources,
 315         .num_resources  = ARRAY_SIZE(tmu5_resources),
 316 };
 317
 318 static struct plat_sci_port sci_platform_data[] = {
 319         {
 320                 .mapbase        = 0xffe00000,
 321                 .flags          = UPF_BOOT_AUTOCONF,
 322                 .type           = PORT_SCIF,
 323                 .irqs           = { 80, 80, 80, 80 },
 324                 .clk            = "scif0",
 325         },{
 326                 .mapbase        = 0xffe10000,
 327                 .flags          = UPF_BOOT_AUTOCONF,
 328                 .type           = PORT_SCIF,
 329                 .irqs           = { 81, 81, 81, 81 },
 330                 .clk            = "scif1",
 331         },{
 332                 .mapbase        = 0xffe20000,
 333                 .flags          = UPF_BOOT_AUTOCONF,
 334                 .type           = PORT_SCIF,
 335                 .irqs           = { 82, 82, 82, 82 },
 336                 .clk            = "scif2",
 337         },{
 338                 .mapbase        = 0xa4e30000,
 339                 .flags          = UPF_BOOT_AUTOCONF,
 340                 .type           = PORT_SCIFA,
 341                 .irqs           = { 56, 56, 56, 56 },
 342                 .clk            = "scif3",
 343         },{
 344                 .mapbase        = 0xa4e40000,
 345                 .flags          = UPF_BOOT_AUTOCONF,
 346                 .type           = PORT_SCIFA,
 347                 .irqs           = { 88, 88, 88, 88 },
 348                 .clk            = "scif4",
 349         },{
 350                 .mapbase        = 0xa4e50000,
 351                 .flags          = UPF_BOOT_AUTOCONF,
 352                 .type           = PORT_SCIFA,
 353                 .irqs           = { 109, 109, 109, 109 },
 354                 .clk            = "scif5",
 355         }, {
 356                 .flags = 0,
 357         }
 358 };
 359
 360 static struct platform_device sci_device = {
 361         .name           = "sh-sci",
 362         .id             = -1,
 363         .dev            = {
 364                 .platform_data  = sci_platform_data,
 365         },
 366 };
 367
 368 static struct resource rtc_resources[] = {
 369         [0] = {
 370                 .start  = 0xa465fec0,
 371                 .end    = 0xa465fec0 + 0x58 - 1,
 372                 .flags  = IORESOURCE_IO,
 373         },
 374         [1] = {
 375                 /* Period IRQ */
 376                 .start  = 69,
 377                 .flags  = IORESOURCE_IRQ,
 378         },
 379         [2] = {
 380                 /* Carry IRQ */
 381                 .start  = 70,
 382                 .flags  = IORESOURCE_IRQ,
 383         },
 384         [3] = {
 385                 /* Alarm IRQ */
 386                 .start  = 68,
 387                 .flags  = IORESOURCE_IRQ,
 388         },
 389 };
 390
 391 static struct platform_device rtc_device = {
 392         .name           = "sh-rtc",
 393         .id             = -1,
 394         .num_resources  = ARRAY_SIZE(rtc_resources),
 395         .resource       = rtc_resources,
 396 };
 397
 398 static struct resource sh7723_usb_host_resources[] = {
 399         [0] = {
 400                 .name   = "r8a66597_hcd",
 401                 .start  = 0xa4d80000,
 402                 .end    = 0xa4d800ff,
 403                 .flags  = IORESOURCE_MEM,
 404         },
 405         [1] = {
 406                 .start  = 65,
 407                 .end    = 65,
 408                 .flags  = IORESOURCE_IRQ,
 409         },
 410 };
 411
 412 static struct platform_device sh7723_usb_host_device = {
 413         .name           = "r8a66597_hcd",
 414         .id             = 0,
 415         .dev = {
 416                 .dma_mask               = NULL,         /*  not use dma */
 417                 .coherent_dma_mask      = 0xffffffff,
 418         },
 419         .num_resources  = ARRAY_SIZE(sh7723_usb_host_resources),
 420         .resource       = sh7723_usb_host_resources,
 421 };
 422
 423 static struct resource iic_resources[] = {
 424         [0] = {
 425                 .name   = "IIC",
 426                 .start  = 0x04470000,
 427                 .end    = 0x04470017,
 428                 .flags  = IORESOURCE_MEM,
 429         },
 430         [1] = {
 431                 .start  = 96,
 432                 .end    = 99,
 433                 .flags  = IORESOURCE_IRQ,
 434        },
 435 };
 436
 437 static struct platform_device iic_device = {
 438         .name           = "i2c-sh_mobile",
 439         .id             = 0, /* "i2c0" clock */
 440         .num_resources  = ARRAY_SIZE(iic_resources),
 441         .resource       = iic_resources,
 442 };
 443
 444 static struct platform_device *sh7723_devices[] __initdata = {
 445         &cmt_device,
 446         &tmu0_device,
 447         &tmu1_device,
 448         &tmu2_device,
 449         &tmu3_device,
 450         &tmu4_device,
 451         &tmu5_device,
 452         &sci_device,
 453         &rtc_device,
 454         &iic_device,
 455         &sh7723_usb_host_device,
 456         &vpu_device,
 457         &veu0_device,
 458         &veu1_device,
 459 };
 460
 461 static int __init sh7723_devices_setup(void)
 462 {
 463         clk_always_enable("meram0"); /* MERAM */
 464         clk_always_enable("veu1"); /* VEU2H1 */
 465         clk_always_enable("veu0"); /* VEU2H0 */
 466         clk_always_enable("vpu0"); /* VPU */
 467
 468         platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
 469         platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
 470         platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
 471
 472         return platform_add_devices(sh7723_devices,
 473                                     ARRAY_SIZE(sh7723_devices));
 474 }
 475 __initcall(sh7723_devices_setup);
 476
 477 static struct platform_device *sh7723_early_devices[] __initdata = {
 478         &cmt_device,
 479         &tmu0_device,
 480         &tmu1_device,
 481         &tmu2_device,
 482         &tmu3_device,
 483         &tmu4_device,
 484         &tmu5_device,
 485 };
 486
 487 void __init plat_early_device_setup(void)
 488 {
 489         early_platform_add_devices(sh7723_early_devices,
 490                                    ARRAY_SIZE(sh7723_early_devices));
 491 }
 492
 493 enum {
 494         UNUSED=0,
 495
 496         /* interrupt sources */
 497         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 498         HUDI,
 499         DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
 500         _2DG_TRI,_2DG_INI,_2DG_CEI,
 501         DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
 502         VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
 503         SCIFA_SCIFA0,
 504         VPU_VPUI,
 505         TPU_TPUI,
 506         ADC_ADI,
 507         USB_USI0,
 508         RTC_ATI,RTC_PRI,RTC_CUI,
 509         DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
 510         DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
 511         KEYSC_KEYI,
 512         SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
 513         MSIOF_MSIOFI0,MSIOF_MSIOFI1,
 514         SCIFA_SCIFA1,
 515         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
 516         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
 517         SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
 518         CMT_CMTI,
 519         TSIF_TSIFI,
 520         SIU_SIUI,
 521         SCIFA_SCIFA2,
 522         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
 523         IRDA_IRDAI,
 524         ATAPI_ATAPII,
 525         SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
 526         VEU2H1_VEU2HI,
 527         LCDC_LCDCI,
 528         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
 529
 530         /* interrupt groups */
 531         DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
 532         SDHI1, RTC, DMAC1B, SDHI0,
 533 };
 534
 535 static struct intc_vect vectors[] __initdata = {
 536         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 537         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 538         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 539         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 540
 541         INTC_VECT(DMAC1A_DEI0,0x700),
 542         INTC_VECT(DMAC1A_DEI1,0x720),
 543         INTC_VECT(DMAC1A_DEI2,0x740),
 544         INTC_VECT(DMAC1A_DEI3,0x760),
 545
 546         INTC_VECT(_2DG_TRI, 0x780),
 547         INTC_VECT(_2DG_INI, 0x7A0),
 548         INTC_VECT(_2DG_CEI, 0x7C0),
 549
 550         INTC_VECT(DMAC0A_DEI0,0x800),
 551         INTC_VECT(DMAC0A_DEI1,0x820),
 552         INTC_VECT(DMAC0A_DEI2,0x840),
 553         INTC_VECT(DMAC0A_DEI3,0x860),
 554
 555         INTC_VECT(VIO_CEUI,0x880),
 556         INTC_VECT(VIO_BEUI,0x8A0),
 557         INTC_VECT(VIO_VEU2HI,0x8C0),
 558         INTC_VECT(VIO_VOUI,0x8E0),
 559
 560         INTC_VECT(SCIFA_SCIFA0,0x900),
 561         INTC_VECT(VPU_VPUI,0x980),
 562         INTC_VECT(TPU_TPUI,0x9A0),
 563         INTC_VECT(ADC_ADI,0x9E0),
 564         INTC_VECT(USB_USI0,0xA20),
 565
 566         INTC_VECT(RTC_ATI,0xA80),
 567         INTC_VECT(RTC_PRI,0xAA0),
 568         INTC_VECT(RTC_CUI,0xAC0),
 569
 570         INTC_VECT(DMAC1B_DEI4,0xB00),
 571         INTC_VECT(DMAC1B_DEI5,0xB20),
 572         INTC_VECT(DMAC1B_DADERR,0xB40),
 573
 574         INTC_VECT(DMAC0B_DEI4,0xB80),
 575         INTC_VECT(DMAC0B_DEI5,0xBA0),
 576         INTC_VECT(DMAC0B_DADERR,0xBC0),
 577
 578         INTC_VECT(KEYSC_KEYI,0xBE0),
 579         INTC_VECT(SCIF_SCIF0,0xC00),
 580         INTC_VECT(SCIF_SCIF1,0xC20),
 581         INTC_VECT(SCIF_SCIF2,0xC40),
 582         INTC_VECT(MSIOF_MSIOFI0,0xC80),
 583         INTC_VECT(MSIOF_MSIOFI1,0xCA0),
 584         INTC_VECT(SCIFA_SCIFA1,0xD00),
 585
 586         INTC_VECT(FLCTL_FLSTEI,0xD80),
 587         INTC_VECT(FLCTL_FLTENDI,0xDA0),
 588         INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
 589         INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
 590
 591         INTC_VECT(I2C_ALI,0xE00),
 592         INTC_VECT(I2C_TACKI,0xE20),
 593         INTC_VECT(I2C_WAITI,0xE40),
 594         INTC_VECT(I2C_DTEI,0xE60),
 595
 596         INTC_VECT(SDHI0_SDHII0,0xE80),
 597         INTC_VECT(SDHI0_SDHII1,0xEA0),
 598         INTC_VECT(SDHI0_SDHII2,0xEC0),
 599
 600         INTC_VECT(CMT_CMTI,0xF00),
 601         INTC_VECT(TSIF_TSIFI,0xF20),
 602         INTC_VECT(SIU_SIUI,0xF80),
 603         INTC_VECT(SCIFA_SCIFA2,0xFA0),
 604
 605         INTC_VECT(TMU0_TUNI0,0x400),
 606         INTC_VECT(TMU0_TUNI1,0x420),
 607         INTC_VECT(TMU0_TUNI2,0x440),
 608
 609         INTC_VECT(IRDA_IRDAI,0x480),
 610         INTC_VECT(ATAPI_ATAPII,0x4A0),
 611
 612         INTC_VECT(SDHI1_SDHII0,0x4E0),
 613         INTC_VECT(SDHI1_SDHII1,0x500),
 614         INTC_VECT(SDHI1_SDHII2,0x520),
 615
 616         INTC_VECT(VEU2H1_VEU2HI,0x560),
 617         INTC_VECT(LCDC_LCDCI,0x580),
 618
 619         INTC_VECT(TMU1_TUNI0,0x920),
 620         INTC_VECT(TMU1_TUNI1,0x940),
 621         INTC_VECT(TMU1_TUNI2,0x960),
 622
 623 };
 624
 625 static struct intc_group groups[] __initdata = {
 626         INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
 627         INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
 628         INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
 629         INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
 630         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
 631         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
 632         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
 633         INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
 634         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
 635         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
 636         INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
 637 };
 638
 639 static struct intc_mask_reg mask_registers[] __initdata = {
 640         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 641           { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
 642         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 643           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
 644         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 645           { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
 646         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 647           { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
 648         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 649           { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
 650         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 651           { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
 652         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 653           { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
 654         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 655           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 656             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
 657         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 658           { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
 659         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 660           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
 661         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 662           { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
 663         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 664           { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
 665         { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
 666           { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
 667         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 668           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 669 };
 670
 671 static struct intc_prio_reg prio_registers[] __initdata = {
 672         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
 673         { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
 674         { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
 675         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 676         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
 677         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
 678         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
 679         { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
 680         { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
 681         { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
 682         { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
 683         { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
 684         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 685           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 686 };
 687
 688 static struct intc_sense_reg sense_registers[] __initdata = {
 689         { 0xa414001c, 16, 2, /* ICR1 */
 690           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 691 };
 692
 693 static struct intc_mask_reg ack_registers[] __initdata = {
 694         { 0xa4140024, 0, 8, /* INTREQ00 */
 695           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 696 };
 697
 698 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
 699                              mask_registers, prio_registers, sense_registers,
 700                              ack_registers);
 701
 702 void __init plat_irq_setup(void)
 703 {
 704         register_intc_controller(&intc_desc);
 705 }