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sata_inic162x: use IDMA for ATA_PROT_DMA
[linux-2.6/mini2440.git] / drivers / ata / sata_inic162x.c
blobdb57f34d22116409ededf25773dc88f8adbf32d1
1 /*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
12 *
13 * - ATA disks work.
14 * - Hotplug works.
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
18 * my guest.
19 * - Both STR and STD work.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
29
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.3"
32
33 enum {
34 MMIO_BAR = 5,
35
36 NR_PORTS = 2,
37
38 IDMA_CPB_TBL_SIZE = 4 * 32,
39
40 INIC_DMA_BOUNDARY = 0xffffff,
41
42 HOST_ACTRL = 0x08,
43 HOST_CTL = 0x7c,
44 HOST_STAT = 0x7e,
45 HOST_IRQ_STAT = 0xbc,
46 HOST_IRQ_MASK = 0xbe,
47
48 PORT_SIZE = 0x40,
49
50 /* registers for ATA TF operation */
51 PORT_TF_DATA = 0x00,
52 PORT_TF_FEATURE = 0x01,
53 PORT_TF_NSECT = 0x02,
54 PORT_TF_LBAL = 0x03,
55 PORT_TF_LBAM = 0x04,
56 PORT_TF_LBAH = 0x05,
57 PORT_TF_DEVICE = 0x06,
58 PORT_TF_COMMAND = 0x07,
59 PORT_TF_ALT_STAT = 0x08,
60 PORT_IRQ_STAT = 0x09,
61 PORT_IRQ_MASK = 0x0a,
62 PORT_PRD_CTL = 0x0b,
63 PORT_PRD_ADDR = 0x0c,
64 PORT_PRD_XFERLEN = 0x10,
65 PORT_CPB_CPBLAR = 0x18,
66 PORT_CPB_PTQFIFO = 0x1c,
67
68 /* IDMA register */
69 PORT_IDMA_CTL = 0x14,
70 PORT_IDMA_STAT = 0x16,
71
72 PORT_RPQ_FIFO = 0x1e,
73 PORT_RPQ_CNT = 0x1f,
74
75 PORT_SCR = 0x20,
76
77 /* HOST_CTL bits */
78 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
79 HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
80 HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
81 HCTL_PWRDWN = (1 << 12), /* power down PHYs */
82 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
83 HCTL_RPGSEL = (1 << 15), /* register page select */
84
85 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
86 HCTL_RPGSEL,
87
88 /* HOST_IRQ_(STAT|MASK) bits */
89 HIRQ_PORT0 = (1 << 0),
90 HIRQ_PORT1 = (1 << 1),
91 HIRQ_SOFT = (1 << 14),
92 HIRQ_GLOBAL = (1 << 15), /* STAT only */
93
94 /* PORT_IRQ_(STAT|MASK) bits */
95 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
96 PIRQ_ONLINE = (1 << 1), /* device plugged */
97 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
98 PIRQ_FATAL = (1 << 3), /* fatal error */
99 PIRQ_ATA = (1 << 4), /* ATA interrupt */
100 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
101 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
102
103 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
104
105 PIRQ_MASK_DMA_READ = PIRQ_REPLY | PIRQ_ATA,
106 PIRQ_MASK_OTHER = PIRQ_REPLY | PIRQ_COMPLETE,
107 PIRQ_MASK_FREEZE = 0xff,
108
109 /* PORT_PRD_CTL bits */
110 PRD_CTL_START = (1 << 0),
111 PRD_CTL_WR = (1 << 3),
112 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
113
114 /* PORT_IDMA_CTL bits */
115 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
116 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
117 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
118 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
119
120 /* PORT_IDMA_STAT bits */
121 IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
122 IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
123 IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
124 IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
125 IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
126 IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
127 IDMA_STAT_DONE = (1 << 7), /* ADMA done */
128
129 IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
130
131 /* CPB Control Flags*/
132 CPB_CTL_VALID = (1 << 0), /* CPB valid */
133 CPB_CTL_QUEUED = (1 << 1), /* queued command */
134 CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
135 CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
136 CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
137
138 /* CPB Response Flags */
139 CPB_RESP_DONE = (1 << 0), /* ATA command complete */
140 CPB_RESP_REL = (1 << 1), /* ATA release */
141 CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
142 CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
143 CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
144 CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
145 CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
146 CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
147
148 /* PRD Control Flags */
149 PRD_DRAIN = (1 << 1), /* ignore data excess */
150 PRD_CDB = (1 << 2), /* atapi packet command pointer */
151 PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
152 PRD_DMA = (1 << 4), /* data transfer method */
153 PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
154 PRD_IOM = (1 << 6), /* io/memory transfer */
155 PRD_END = (1 << 7), /* APRD chain end */
156 };
157
158 /* Comman Parameter Block */
159 struct inic_cpb {
160 u8 resp_flags; /* Response Flags */
161 u8 error; /* ATA Error */
162 u8 status; /* ATA Status */
163 u8 ctl_flags; /* Control Flags */
164 __le32 len; /* Total Transfer Length */
165 __le32 prd; /* First PRD pointer */
166 u8 rsvd[4];
167 /* 16 bytes */
168 u8 feature; /* ATA Feature */
169 u8 hob_feature; /* ATA Ex. Feature */
170 u8 device; /* ATA Device/Head */
171 u8 mirctl; /* Mirror Control */
172 u8 nsect; /* ATA Sector Count */
173 u8 hob_nsect; /* ATA Ex. Sector Count */
174 u8 lbal; /* ATA Sector Number */
175 u8 hob_lbal; /* ATA Ex. Sector Number */
176 u8 lbam; /* ATA Cylinder Low */
177 u8 hob_lbam; /* ATA Ex. Cylinder Low */
178 u8 lbah; /* ATA Cylinder High */
179 u8 hob_lbah; /* ATA Ex. Cylinder High */
180 u8 command; /* ATA Command */
181 u8 ctl; /* ATA Control */
182 u8 slave_error; /* Slave ATA Error */
183 u8 slave_status; /* Slave ATA Status */
184 /* 32 bytes */
185 } __packed;
186
187 /* Physical Region Descriptor */
188 struct inic_prd {
189 __le32 mad; /* Physical Memory Address */
190 __le16 len; /* Transfer Length */
191 u8 rsvd;
192 u8 flags; /* Control Flags */
193 } __packed;
194
195 struct inic_pkt {
196 struct inic_cpb cpb;
197 struct inic_prd prd[LIBATA_MAX_PRD];
198 } __packed;
199
200 struct inic_host_priv {
201 u16 cached_hctl;
202 };
203
204 struct inic_port_priv {
205 struct inic_pkt *pkt;
206 dma_addr_t pkt_dma;
207 u32 *cpb_tbl;
208 dma_addr_t cpb_tbl_dma;
209 u8 dfl_prdctl;
210 u8 cached_prdctl;
211 u8 cached_pirq_mask;
212 };
213
214 static struct scsi_host_template inic_sht = {
215 ATA_BMDMA_SHT(DRV_NAME),
216 .dma_boundary = INIC_DMA_BOUNDARY,
217 };
218
219 static const int scr_map[] = {
220 [SCR_STATUS] = 0,
221 [SCR_ERROR] = 1,
222 [SCR_CONTROL] = 2,
223 };
224
225 static void __iomem *inic_port_base(struct ata_port *ap)
226 {
227 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
228 }
229
230 static void __inic_set_pirq_mask(struct ata_port *ap, u8 mask)
231 {
232 void __iomem *port_base = inic_port_base(ap);
233 struct inic_port_priv *pp = ap->private_data;
234
235 writeb(mask, port_base + PORT_IRQ_MASK);
236 pp->cached_pirq_mask = mask;
237 }
238
239 static void inic_set_pirq_mask(struct ata_port *ap, u8 mask)
240 {
241 struct inic_port_priv *pp = ap->private_data;
242
243 if (pp->cached_pirq_mask != mask)
244 __inic_set_pirq_mask(ap, mask);
245 }
246
247 static void inic_reset_port(void __iomem *port_base)
248 {
249 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
250 u16 ctl;
251
252 ctl = readw(idma_ctl);
253 ctl &= ~(IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN | IDMA_CTL_GO);
254
255 /* mask IRQ and assert reset */
256 writew(ctl | IDMA_CTL_RST_IDMA | IDMA_CTL_ATA_NIEN, idma_ctl);
257 readw(idma_ctl); /* flush */
258
259 /* give it some time */
260 msleep(1);
261
262 /* release reset */
263 writew(ctl | IDMA_CTL_ATA_NIEN, idma_ctl);
264
265 /* clear irq */
266 writeb(0xff, port_base + PORT_IRQ_STAT);
267
268 /* reenable ATA IRQ, turn off IDMA mode */
269 writew(ctl, idma_ctl);
270 }
271
272 static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
273 {
274 void __iomem *scr_addr = ap->ioaddr.scr_addr;
275 void __iomem *addr;
276
277 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
278 return -EINVAL;
279
280 addr = scr_addr + scr_map[sc_reg] * 4;
281 *val = readl(scr_addr + scr_map[sc_reg] * 4);
282
283 /* this controller has stuck DIAG.N, ignore it */
284 if (sc_reg == SCR_ERROR)
285 *val &= ~SERR_PHYRDY_CHG;
286 return 0;
287 }
288
289 static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
290 {
291 void __iomem *scr_addr = ap->ioaddr.scr_addr;
292
293 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
294 return -EINVAL;
295
296 writel(val, scr_addr + scr_map[sc_reg] * 4);
297 return 0;
298 }
299
300 /*
301 * In TF mode, inic162x is very similar to SFF device. TF registers
302 * function the same. DMA engine behaves similary using the same PRD
303 * format as BMDMA but different command register, interrupt and event
304 * notification methods are used. The following inic_bmdma_*()
305 * functions do the impedance matching.
306 */
307 static void inic_bmdma_setup(struct ata_queued_cmd *qc)
308 {
309 struct ata_port *ap = qc->ap;
310 struct inic_port_priv *pp = ap->private_data;
311 void __iomem *port_base = inic_port_base(ap);
312 int rw = qc->tf.flags & ATA_TFLAG_WRITE;
313
314 /* make sure device sees PRD table writes */
315 wmb();
316
317 /* load transfer length */
318 writel(qc->nbytes, port_base + PORT_PRD_XFERLEN);
319
320 /* turn on DMA and specify data direction */
321 pp->cached_prdctl = pp->dfl_prdctl | PRD_CTL_DMAEN;
322 if (!rw)
323 pp->cached_prdctl |= PRD_CTL_WR;
324 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
325
326 /* issue r/w command */
327 ap->ops->sff_exec_command(ap, &qc->tf);
328 }
329
330 static void inic_bmdma_start(struct ata_queued_cmd *qc)
331 {
332 struct ata_port *ap = qc->ap;
333 struct inic_port_priv *pp = ap->private_data;
334 void __iomem *port_base = inic_port_base(ap);
335
336 /* start host DMA transaction */
337 pp->cached_prdctl |= PRD_CTL_START;
338 writeb(pp->cached_prdctl, port_base + PORT_PRD_CTL);
339 }
340
341 static void inic_bmdma_stop(struct ata_queued_cmd *qc)
342 {
343 struct ata_port *ap = qc->ap;
344 struct inic_port_priv *pp = ap->private_data;
345 void __iomem *port_base = inic_port_base(ap);
346
347 /* stop DMA engine */
348 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
349 }
350
351 static u8 inic_bmdma_status(struct ata_port *ap)
352 {
353 /* event is already verified by the interrupt handler */
354 return ATA_DMA_INTR;
355 }
356
357 static void inic_stop_idma(struct ata_port *ap)
358 {
359 void __iomem *port_base = inic_port_base(ap);
360
361 readb(port_base + PORT_RPQ_FIFO);
362 readb(port_base + PORT_RPQ_CNT);
363 writew(0, port_base + PORT_IDMA_CTL);
364 }
365
366 static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
367 {
368 struct ata_eh_info *ehi = &ap->link.eh_info;
369 struct inic_port_priv *pp = ap->private_data;
370 struct inic_cpb *cpb = &pp->pkt->cpb;
371 bool freeze = false;
372
373 ata_ehi_clear_desc(ehi);
374 ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
375 irq_stat, idma_stat);
376
377 inic_stop_idma(ap);
378
379 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
380 ata_ehi_push_desc(ehi, "hotplug");
381 ata_ehi_hotplugged(ehi);
382 freeze = true;
383 }
384
385 if (idma_stat & IDMA_STAT_PERR) {
386 ata_ehi_push_desc(ehi, "PCI error");
387 freeze = true;
388 }
389
390 if (idma_stat & IDMA_STAT_CPBERR) {
391 ata_ehi_push_desc(ehi, "CPB error");
392
393 if (cpb->resp_flags & CPB_RESP_IGNORED) {
394 __ata_ehi_push_desc(ehi, " ignored");
395 ehi->err_mask |= AC_ERR_INVALID;
396 freeze = true;
397 }
398
399 if (cpb->resp_flags & CPB_RESP_ATA_ERR)
400 ehi->err_mask |= AC_ERR_DEV;
401
402 if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
403 __ata_ehi_push_desc(ehi, " spurious-intr");
404 ehi->err_mask |= AC_ERR_HSM;
405 freeze = true;
406 }
407
408 if (cpb->resp_flags &
409 (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
410 __ata_ehi_push_desc(ehi, " data-over/underflow");
411 ehi->err_mask |= AC_ERR_HSM;
412 freeze = true;
413 }
414 }
415
416 if (freeze)
417 ata_port_freeze(ap);
418 else
419 ata_port_abort(ap);
420 }
421
422 static void inic_host_intr(struct ata_port *ap)
423 {
424 void __iomem *port_base = inic_port_base(ap);
425 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
426 u8 irq_stat;
427 u16 idma_stat;
428
429 /* read and clear IRQ status */
430 irq_stat = readb(port_base + PORT_IRQ_STAT);
431 writeb(irq_stat, port_base + PORT_IRQ_STAT);
432 idma_stat = readw(port_base + PORT_IDMA_STAT);
433
434 if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
435 inic_host_err_intr(ap, irq_stat, idma_stat);
436
437 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
438 ap->ops->sff_check_status(ap); /* clear ATA interrupt */
439 goto spurious;
440 }
441
442 if (qc->tf.protocol == ATA_PROT_DMA) {
443 if (likely(idma_stat & IDMA_STAT_DONE)) {
444 inic_stop_idma(ap);
445
446 /* Depending on circumstances, device error
447 * isn't reported by IDMA, check it explicitly.
448 */
449 if (unlikely(readb(port_base + PORT_TF_COMMAND) &
450 (ATA_DF | ATA_ERR)))
451 qc->err_mask |= AC_ERR_DEV;
452
453 ata_qc_complete(qc);
454 return;
455 }
456 } else {
457 if (likely(ata_sff_host_intr(ap, qc)))
458 return;
459 }
460
461 spurious:
462 ap->ops->sff_check_status(ap); /* clear ATA interrupt */
463 }
464
465 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
466 {
467 struct ata_host *host = dev_instance;
468 void __iomem *mmio_base = host->iomap[MMIO_BAR];
469 u16 host_irq_stat;
470 int i, handled = 0;;
471
472 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
473
474 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
475 goto out;
476
477 spin_lock(&host->lock);
478
479 for (i = 0; i < NR_PORTS; i++) {
480 struct ata_port *ap = host->ports[i];
481
482 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
483 continue;
484
485 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
486 inic_host_intr(ap);
487 handled++;
488 } else {
489 if (ata_ratelimit())
490 dev_printk(KERN_ERR, host->dev, "interrupt "
491 "from disabled port %d (0x%x)\n",
492 i, host_irq_stat);
493 }
494 }
495
496 spin_unlock(&host->lock);
497
498 out:
499 return IRQ_RETVAL(handled);
500 }
501
502 static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
503 {
504 struct scatterlist *sg;
505 unsigned int si;
506 u8 flags = PRD_DMA;
507
508 if (qc->tf.flags & ATA_TFLAG_WRITE)
509 flags |= PRD_WRITE;
510
511 for_each_sg(qc->sg, sg, qc->n_elem, si) {
512 prd->mad = cpu_to_le32(sg_dma_address(sg));
513 prd->len = cpu_to_le16(sg_dma_len(sg));
514 prd->flags = flags;
515 prd++;
516 }
517
518 WARN_ON(!si);
519 prd[-1].flags |= PRD_END;
520 }
521
522 static void inic_qc_prep(struct ata_queued_cmd *qc)
523 {
524 struct inic_port_priv *pp = qc->ap->private_data;
525 struct inic_pkt *pkt = pp->pkt;
526 struct inic_cpb *cpb = &pkt->cpb;
527 struct inic_prd *prd = pkt->prd;
528
529 VPRINTK("ENTER\n");
530
531 if (qc->tf.protocol != ATA_PROT_DMA)
532 return;
533
534 /* prepare packet, based on initio driver */
535 memset(pkt, 0, sizeof(struct inic_pkt));
536
537 cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN | CPB_CTL_DATA;
538
539 cpb->len = cpu_to_le32(qc->nbytes);
540 cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
541
542 cpb->device = qc->tf.device;
543 cpb->feature = qc->tf.feature;
544 cpb->nsect = qc->tf.nsect;
545 cpb->lbal = qc->tf.lbal;
546 cpb->lbam = qc->tf.lbam;
547 cpb->lbah = qc->tf.lbah;
548
549 if (qc->tf.flags & ATA_TFLAG_LBA48) {
550 cpb->hob_feature = qc->tf.hob_feature;
551 cpb->hob_nsect = qc->tf.hob_nsect;
552 cpb->hob_lbal = qc->tf.hob_lbal;
553 cpb->hob_lbam = qc->tf.hob_lbam;
554 cpb->hob_lbah = qc->tf.hob_lbah;
555 }
556
557 cpb->command = qc->tf.command;
558 /* don't load ctl - dunno why. it's like that in the initio driver */
559
560 /* setup sg table */
561 inic_fill_sg(prd, qc);
562
563 pp->cpb_tbl[0] = pp->pkt_dma;
564 }
565
566 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
567 {
568 struct ata_port *ap = qc->ap;
569 void __iomem *port_base = inic_port_base(ap);
570
571 if (qc->tf.protocol == ATA_PROT_DMA) {
572 /* fire up the ADMA engine */
573 writew(HCTL_FTHD0, port_base + HOST_CTL);
574 writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
575 writeb(0, port_base + PORT_CPB_PTQFIFO);
576
577 return 0;
578 }
579
580 /* Issuing a command to yet uninitialized port locks up the
581 * controller. Most of the time, this happens for the first
582 * command after reset which are ATA and ATAPI IDENTIFYs.
583 * Fast fail if stat is 0x7f or 0xff for those commands.
584 */
585 if (unlikely(qc->tf.command == ATA_CMD_ID_ATA ||
586 qc->tf.command == ATA_CMD_ID_ATAPI)) {
587 u8 stat = ap->ops->sff_check_status(ap);
588 if (stat == 0x7f || stat == 0xff)
589 return AC_ERR_HSM;
590 }
591
592 return ata_sff_qc_issue(qc);
593 }
594
595 static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
596 {
597 void __iomem *port_base = inic_port_base(ap);
598
599 tf->feature = readb(port_base + PORT_TF_FEATURE);
600 tf->nsect = readb(port_base + PORT_TF_NSECT);
601 tf->lbal = readb(port_base + PORT_TF_LBAL);
602 tf->lbam = readb(port_base + PORT_TF_LBAM);
603 tf->lbah = readb(port_base + PORT_TF_LBAH);
604 tf->device = readb(port_base + PORT_TF_DEVICE);
605 tf->command = readb(port_base + PORT_TF_COMMAND);
606 }
607
608 static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
609 {
610 struct ata_taskfile *rtf = &qc->result_tf;
611 struct ata_taskfile tf;
612
613 /* FIXME: Except for status and error, result TF access
614 * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
615 * None works regardless of which command interface is used.
616 * For now return true iff status indicates device error.
617 * This means that we're reporting bogus sector for RW
618 * failures. Eeekk....
619 */
620 inic_tf_read(qc->ap, &tf);
621
622 if (!(tf.command & ATA_ERR))
623 return false;
624
625 rtf->command = tf.command;
626 rtf->feature = tf.feature;
627 return true;
628 }
629
630 static void inic_freeze(struct ata_port *ap)
631 {
632 void __iomem *port_base = inic_port_base(ap);
633
634 __inic_set_pirq_mask(ap, PIRQ_MASK_FREEZE);
635
636 ap->ops->sff_check_status(ap);
637 writeb(0xff, port_base + PORT_IRQ_STAT);
638 }
639
640 static void inic_thaw(struct ata_port *ap)
641 {
642 void __iomem *port_base = inic_port_base(ap);
643
644 ap->ops->sff_check_status(ap);
645 writeb(0xff, port_base + PORT_IRQ_STAT);
646
647 __inic_set_pirq_mask(ap, PIRQ_MASK_OTHER);
648 }
649
650 static int inic_check_ready(struct ata_link *link)
651 {
652 void __iomem *port_base = inic_port_base(link->ap);
653
654 return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
655 }
656
657 /*
658 * SRST and SControl hardreset don't give valid signature on this
659 * controller. Only controller specific hardreset mechanism works.
660 */
661 static int inic_hardreset(struct ata_link *link, unsigned int *class,
662 unsigned long deadline)
663 {
664 struct ata_port *ap = link->ap;
665 void __iomem *port_base = inic_port_base(ap);
666 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
667 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
668 u16 val;
669 int rc;
670
671 /* hammer it into sane state */
672 inic_reset_port(port_base);
673
674 val = readw(idma_ctl);
675 writew(val | IDMA_CTL_RST_ATA, idma_ctl);
676 readw(idma_ctl); /* flush */
677 msleep(1);
678 writew(val & ~IDMA_CTL_RST_ATA, idma_ctl);
679
680 rc = sata_link_resume(link, timing, deadline);
681 if (rc) {
682 ata_link_printk(link, KERN_WARNING, "failed to resume "
683 "link after reset (errno=%d)\n", rc);
684 return rc;
685 }
686
687 *class = ATA_DEV_NONE;
688 if (ata_link_online(link)) {
689 struct ata_taskfile tf;
690
691 /* wait for link to become ready */
692 rc = ata_wait_after_reset(link, deadline, inic_check_ready);
693 /* link occupied, -ENODEV too is an error */
694 if (rc) {
695 ata_link_printk(link, KERN_WARNING, "device not ready "
696 "after hardreset (errno=%d)\n", rc);
697 return rc;
698 }
699
700 inic_tf_read(ap, &tf);
701 *class = ata_dev_classify(&tf);
702 }
703
704 return 0;
705 }
706
707 static void inic_error_handler(struct ata_port *ap)
708 {
709 void __iomem *port_base = inic_port_base(ap);
710 struct inic_port_priv *pp = ap->private_data;
711 unsigned long flags;
712
713 /* reset PIO HSM and stop DMA engine */
714 inic_reset_port(port_base);
715
716 spin_lock_irqsave(ap->lock, flags);
717 ap->hsm_task_state = HSM_ST_IDLE;
718 writeb(pp->dfl_prdctl, port_base + PORT_PRD_CTL);
719 spin_unlock_irqrestore(ap->lock, flags);
720
721 /* PIO and DMA engines have been stopped, perform recovery */
722 ata_std_error_handler(ap);
723 }
724
725 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
726 {
727 /* make DMA engine forget about the failed command */
728 if (qc->flags & ATA_QCFLAG_FAILED)
729 inic_reset_port(inic_port_base(qc->ap));
730 }
731
732 static void inic_dev_config(struct ata_device *dev)
733 {
734 /* inic can only handle upto LBA28 max sectors */
735 if (dev->max_sectors > ATA_MAX_SECTORS)
736 dev->max_sectors = ATA_MAX_SECTORS;
737
738 if (dev->n_sectors >= 1 << 28) {
739 ata_dev_printk(dev, KERN_ERR,
740 "ERROR: This driver doesn't support LBA48 yet and may cause\n"
741 " data corruption on such devices. Disabling.\n");
742 ata_dev_disable(dev);
743 }
744 }
745
746 static void init_port(struct ata_port *ap)
747 {
748 void __iomem *port_base = inic_port_base(ap);
749 struct inic_port_priv *pp = ap->private_data;
750
751 /* clear packet and CPB table */
752 memset(pp->pkt, 0, sizeof(struct inic_pkt));
753 memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
754
755 /* setup PRD and CPB lookup table addresses */
756 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
757 writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
758 }
759
760 static int inic_port_resume(struct ata_port *ap)
761 {
762 init_port(ap);
763 return 0;
764 }
765
766 static int inic_port_start(struct ata_port *ap)
767 {
768 void __iomem *port_base = inic_port_base(ap);
769 struct device *dev = ap->host->dev;
770 struct inic_port_priv *pp;
771 u8 tmp;
772 int rc;
773
774 /* alloc and initialize private data */
775 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
776 if (!pp)
777 return -ENOMEM;
778 ap->private_data = pp;
779
780 /* default PRD_CTL value, DMAEN, WR and START off */
781 tmp = readb(port_base + PORT_PRD_CTL);
782 tmp &= ~(PRD_CTL_DMAEN | PRD_CTL_WR | PRD_CTL_START);
783 pp->dfl_prdctl = tmp;
784
785 /* Alloc resources */
786 rc = ata_port_start(ap);
787 if (rc)
788 return rc;
789
790 pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
791 &pp->pkt_dma, GFP_KERNEL);
792 if (!pp->pkt)
793 return -ENOMEM;
794
795 pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
796 &pp->cpb_tbl_dma, GFP_KERNEL);
797 if (!pp->cpb_tbl)
798 return -ENOMEM;
799
800 init_port(ap);
801
802 return 0;
803 }
804
805 static struct ata_port_operations inic_port_ops = {
806 .inherits = &ata_sff_port_ops,
807
808 .bmdma_setup = inic_bmdma_setup,
809 .bmdma_start = inic_bmdma_start,
810 .bmdma_stop = inic_bmdma_stop,
811 .bmdma_status = inic_bmdma_status,
812 .qc_prep = inic_qc_prep,
813 .qc_issue = inic_qc_issue,
814 .qc_fill_rtf = inic_qc_fill_rtf,
815
816 .freeze = inic_freeze,
817 .thaw = inic_thaw,
818 .softreset = ATA_OP_NULL, /* softreset is broken */
819 .hardreset = inic_hardreset,
820 .error_handler = inic_error_handler,
821 .post_internal_cmd = inic_post_internal_cmd,
822 .dev_config = inic_dev_config,
823
824 .scr_read = inic_scr_read,
825 .scr_write = inic_scr_write,
826
827 .port_resume = inic_port_resume,
828 .port_start = inic_port_start,
829 };
830
831 static struct ata_port_info inic_port_info = {
832 /* For some reason, ATAPI_PROT_PIO is broken on this
833 * controller, and no, PIO_POLLING does't fix it. It somehow
834 * manages to report the wrong ireason and ignoring ireason
835 * results in machine lock up. Tell libata to always prefer
836 * DMA.
837 */
838 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
839 .pio_mask = 0x1f, /* pio0-4 */
840 .mwdma_mask = 0x07, /* mwdma0-2 */
841 .udma_mask = ATA_UDMA6,
842 .port_ops = &inic_port_ops
843 };
844
845 static int init_controller(void __iomem *mmio_base, u16 hctl)
846 {
847 int i;
848 u16 val;
849
850 hctl &= ~HCTL_KNOWN_BITS;
851
852 /* Soft reset whole controller. Spec says reset duration is 3
853 * PCI clocks, be generous and give it 10ms.
854 */
855 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
856 readw(mmio_base + HOST_CTL); /* flush */
857
858 for (i = 0; i < 10; i++) {
859 msleep(1);
860 val = readw(mmio_base + HOST_CTL);
861 if (!(val & HCTL_SOFTRST))
862 break;
863 }
864
865 if (val & HCTL_SOFTRST)
866 return -EIO;
867
868 /* mask all interrupts and reset ports */
869 for (i = 0; i < NR_PORTS; i++) {
870 void __iomem *port_base = mmio_base + i * PORT_SIZE;
871
872 writeb(0xff, port_base + PORT_IRQ_MASK);
873 inic_reset_port(port_base);
874 }
875
876 /* port IRQ is masked now, unmask global IRQ */
877 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
878 val = readw(mmio_base + HOST_IRQ_MASK);
879 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
880 writew(val, mmio_base + HOST_IRQ_MASK);
881
882 return 0;
883 }
884
885 #ifdef CONFIG_PM
886 static int inic_pci_device_resume(struct pci_dev *pdev)
887 {
888 struct ata_host *host = dev_get_drvdata(&pdev->dev);
889 struct inic_host_priv *hpriv = host->private_data;
890 void __iomem *mmio_base = host->iomap[MMIO_BAR];
891 int rc;
892
893 rc = ata_pci_device_do_resume(pdev);
894 if (rc)
895 return rc;
896
897 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
898 rc = init_controller(mmio_base, hpriv->cached_hctl);
899 if (rc)
900 return rc;
901 }
902
903 ata_host_resume(host);
904
905 return 0;
906 }
907 #endif
908
909 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
910 {
911 static int printed_version;
912 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
913 struct ata_host *host;
914 struct inic_host_priv *hpriv;
915 void __iomem * const *iomap;
916 int i, rc;
917
918 if (!printed_version++)
919 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
920
921 /* alloc host */
922 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
923 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
924 if (!host || !hpriv)
925 return -ENOMEM;
926
927 host->private_data = hpriv;
928
929 /* acquire resources and fill host */
930 rc = pcim_enable_device(pdev);
931 if (rc)
932 return rc;
933
934 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
935 if (rc)
936 return rc;
937 host->iomap = iomap = pcim_iomap_table(pdev);
938
939 for (i = 0; i < NR_PORTS; i++) {
940 struct ata_port *ap = host->ports[i];
941 struct ata_ioports *port = &ap->ioaddr;
942 unsigned int offset = i * PORT_SIZE;
943
944 port->cmd_addr = iomap[2 * i];
945 port->altstatus_addr =
946 port->ctl_addr = (void __iomem *)
947 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS);
948 port->scr_addr = iomap[MMIO_BAR] + offset + PORT_SCR;
949
950 ata_sff_std_ports(port);
951
952 ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio");
953 ata_port_pbar_desc(ap, MMIO_BAR, offset, "port");
954 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
955 (unsigned long long)pci_resource_start(pdev, 2 * i),
956 (unsigned long long)pci_resource_start(pdev, (2 * i + 1)) |
957 ATA_PCI_CTL_OFS);
958 }
959
960 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
961
962 /* Set dma_mask. This devices doesn't support 64bit addressing. */
963 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
964 if (rc) {
965 dev_printk(KERN_ERR, &pdev->dev,
966 "32-bit DMA enable failed\n");
967 return rc;
968 }
969
970 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
971 if (rc) {
972 dev_printk(KERN_ERR, &pdev->dev,
973 "32-bit consistent DMA enable failed\n");
974 return rc;
975 }
976
977 /*
978 * This controller is braindamaged. dma_boundary is 0xffff
979 * like others but it will lock up the whole machine HARD if
980 * 65536 byte PRD entry is fed. Reduce maximum segment size.
981 */
982 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
983 if (rc) {
984 dev_printk(KERN_ERR, &pdev->dev,
985 "failed to set the maximum segment size.\n");
986 return rc;
987 }
988
989 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
990 if (rc) {
991 dev_printk(KERN_ERR, &pdev->dev,
992 "failed to initialize controller\n");
993 return rc;
994 }
995
996 pci_set_master(pdev);
997 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
998 &inic_sht);
999 }
1000
1001 static const struct pci_device_id inic_pci_tbl[] = {
1002 { PCI_VDEVICE(INIT, 0x1622), },
1003 { },
1004 };
1005
1006 static struct pci_driver inic_pci_driver = {
1007 .name = DRV_NAME,
1008 .id_table = inic_pci_tbl,
1009 #ifdef CONFIG_PM
1010 .suspend = ata_pci_device_suspend,
1011 .resume = inic_pci_device_resume,
1012 #endif
1013 .probe = inic_init_one,
1014 .remove = ata_pci_remove_one,
1015 };
1016
1017 static int __init inic_init(void)
1018 {
1019 return pci_register_driver(&inic_pci_driver);
1020 }
1021
1022 static void __exit inic_exit(void)
1023 {
1024 pci_unregister_driver(&inic_pci_driver);
1025 }
1026
1027 MODULE_AUTHOR("Tejun Heo");
1028 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
1029 MODULE_LICENSE("GPL v2");
1030 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
1031 MODULE_VERSION(DRV_VERSION);
1032
1033 module_init(inic_init);
1034 module_exit(inic_exit);
Support for the Chinese Samsung S3C2440 based development boards