arch/ppc/platforms/4xx/ibm405ep.c

   1 /*
   2  * arch/ppc/platforms/ibm405ep.c
   3  *
   4  * Support for IBM PPC 405EP processors.
   5  *
   6  * Author: SAW (IBM), derived from ibmnp405l.c.
   7  *         Maintained by MontaVista Software <source@mvista.com>
   8  *
   9  * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
  10  * terms of the GNU General Public License version 2. This program is
  11  * licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/init.h>
  17 #include <linux/smp.h>
  18 #include <linux/threads.h>
  19 #include <linux/param.h>
  20 #include <linux/string.h>
  21
  22 #include <asm/ibm4xx.h>
  23 #include <asm/ocp.h>
  24 #include <asm/ppc4xx_pic.h>
  25
  26 #include <platforms/4xx/ibm405ep.h>
  27
  28 static struct ocp_func_mal_data ibm405ep_mal0_def = {
  29         .num_tx_chans   = 4,            /* Number of TX channels */
  30         .num_rx_chans   = 2,            /* Number of RX channels */
  31         .txeob_irq      = 11,           /* TX End Of Buffer IRQ  */
  32         .rxeob_irq      = 12,           /* RX End Of Buffer IRQ  */
  33         .txde_irq       = 13,           /* TX Descriptor Error IRQ */
  34         .rxde_irq       = 14,           /* RX Descriptor Error IRQ */
  35         .serr_irq       = 10,           /* MAL System Error IRQ    */
  36         .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  37 };
  38 OCP_SYSFS_MAL_DATA()
  39
  40 static struct ocp_func_emac_data ibm405ep_emac0_def = {
  41         .rgmii_idx      = -1,           /* No RGMII */
  42         .rgmii_mux      = -1,           /* No RGMII */
  43         .zmii_idx       = -1,           /* ZMII device index */
  44         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  45         .mal_idx        = 0,            /* MAL device index */
  46         .mal_rx_chan    = 0,            /* MAL rx channel number */
  47         .mal_tx_chan    = 0,            /* MAL tx channel number */
  48         .wol_irq        = 9,            /* WOL interrupt number */
  49         .mdio_idx       = 0,            /* MDIO via EMAC0 */
  50         .tah_idx        = -1,           /* No TAH */
  51 };
  52
  53 static struct ocp_func_emac_data ibm405ep_emac1_def = {
  54         .rgmii_idx      = -1,           /* No RGMII */
  55         .rgmii_mux      = -1,           /* No RGMII */
  56         .zmii_idx       = -1,           /* ZMII device index */
  57         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  58         .mal_idx        = 0,            /* MAL device index */
  59         .mal_rx_chan    = 1,            /* MAL rx channel number */
  60         .mal_tx_chan    = 2,            /* MAL tx channel number */
  61         .wol_irq        = 9,            /* WOL interrupt number */
  62         .mdio_idx       = 0,            /* MDIO via EMAC0 */
  63         .tah_idx        = -1,           /* No TAH */
  64 };
  65 OCP_SYSFS_EMAC_DATA()
  66
  67 static struct ocp_func_iic_data ibm405ep_iic0_def = {
  68         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  69 };
  70 OCP_SYSFS_IIC_DATA()
  71
  72 struct ocp_def core_ocp[] = {
  73         { .vendor       = OCP_VENDOR_IBM,
  74           .function     = OCP_FUNC_OPB,
  75           .index        = 0,
  76           .paddr        = 0xEF600000,
  77           .irq          = OCP_IRQ_NA,
  78           .pm           = OCP_CPM_NA,
  79         },
  80         { .vendor       = OCP_VENDOR_IBM,
  81           .function     = OCP_FUNC_16550,
  82           .index        = 0,
  83           .paddr        = UART0_IO_BASE,
  84           .irq          = UART0_INT,
  85           .pm           = IBM_CPM_UART0
  86         },
  87         { .vendor       = OCP_VENDOR_IBM,
  88           .function     = OCP_FUNC_16550,
  89           .index        = 1,
  90           .paddr        = UART1_IO_BASE,
  91           .irq          = UART1_INT,
  92           .pm           = IBM_CPM_UART1
  93         },
  94         { .vendor       = OCP_VENDOR_IBM,
  95           .function     = OCP_FUNC_IIC,
  96           .paddr        = 0xEF600500,
  97           .irq          = 2,
  98           .pm           = IBM_CPM_IIC0,
  99           .additions    = &ibm405ep_iic0_def,
 100           .show         = &ocp_show_iic_data
 101         },
 102         { .vendor       = OCP_VENDOR_IBM,
 103           .function     = OCP_FUNC_GPIO,
 104           .paddr        = 0xEF600700,
 105           .irq          = OCP_IRQ_NA,
 106           .pm           = IBM_CPM_GPIO0
 107         },
 108         { .vendor       = OCP_VENDOR_IBM,
 109           .function     = OCP_FUNC_MAL,
 110           .paddr        = OCP_PADDR_NA,
 111           .irq          = OCP_IRQ_NA,
 112           .pm           = OCP_CPM_NA,
 113           .additions    = &ibm405ep_mal0_def,
 114           .show         = &ocp_show_mal_data
 115         },
 116         { .vendor       = OCP_VENDOR_IBM,
 117           .function     = OCP_FUNC_EMAC,
 118           .index        = 0,
 119           .paddr        = EMAC0_BASE,
 120           .irq          = 15,
 121           .pm           = OCP_CPM_NA,
 122           .additions    = &ibm405ep_emac0_def,
 123           .show         = &ocp_show_emac_data
 124         },
 125         { .vendor       = OCP_VENDOR_IBM,
 126           .function     = OCP_FUNC_EMAC,
 127           .index        = 1,
 128           .paddr        = 0xEF600900,
 129           .irq          = 17,
 130           .pm           = OCP_CPM_NA,
 131           .additions    = &ibm405ep_emac1_def,
 132           .show         = &ocp_show_emac_data
 133         },
 134         { .vendor       = OCP_VENDOR_INVALID
 135         }
 136 };
 137
 138 /* Polarity and triggering settings for internal interrupt sources */
 139 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
 140         { .polarity     = 0xffff7f80,
 141           .triggering   = 0x00000000,
 142           .ext_irq_mask = 0x0000007f,   /* IRQ0 - IRQ6 */
 143         }
 144 };