2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
6 * Copyright(C) 2009 Jaswinder Singh Rajput
7 * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter
9 * For licencing details see kernel-base/COPYING
12 #include <linux/perf_counter.h>
13 #include <linux/capability.h>
14 #include <linux/notifier.h>
15 #include <linux/hardirq.h>
16 #include <linux/kprobes.h>
17 #include <linux/module.h>
18 #include <linux/kdebug.h>
19 #include <linux/sched.h>
20 #include <linux/uaccess.h>
23 #include <asm/stacktrace.h>
26 static bool perf_counters_initialized __read_mostly
;
29 * Number of (generic) HW counters:
31 static int nr_counters_generic __read_mostly
;
32 static u64 perf_counter_mask __read_mostly
;
33 static u64 counter_value_mask __read_mostly
;
34 static int counter_value_bits __read_mostly
;
36 static int nr_counters_fixed __read_mostly
;
38 struct cpu_hw_counters
{
39 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
40 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
41 unsigned long interrupts
;
43 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
48 * struct x86_pmu - generic x86 pmu
51 int (*handle_irq
)(struct pt_regs
*, int);
52 u64 (*save_disable_all
)(void);
53 void (*restore_all
)(u64
);
54 u64 (*get_status
)(u64
);
55 void (*ack_status
)(u64
);
56 void (*enable
)(int, u64
);
57 void (*disable
)(int, u64
);
60 u64 (*event_map
)(int);
61 u64 (*raw_event
)(u64
);
65 static struct x86_pmu
*x86_pmu __read_mostly
;
67 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
71 static __read_mostly
int intel_perfmon_version
;
74 * Intel PerfMon v3. Used on Core2 and later.
76 static const u64 intel_perfmon_event_map
[] =
78 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
79 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
80 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
81 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
82 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
83 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
84 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
87 static u64
intel_pmu_event_map(int event
)
89 return intel_perfmon_event_map
[event
];
92 static u64
intel_pmu_raw_event(u64 event
)
94 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
95 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
96 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
98 #define CORE_EVNTSEL_MASK \
99 (CORE_EVNTSEL_EVENT_MASK | \
100 CORE_EVNTSEL_UNIT_MASK | \
101 CORE_EVNTSEL_COUNTER_MASK)
103 return event
& CORE_EVNTSEL_MASK
;
107 * AMD Performance Monitor K7 and later.
109 static const u64 amd_perfmon_event_map
[] =
111 [PERF_COUNT_CPU_CYCLES
] = 0x0076,
112 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
113 [PERF_COUNT_CACHE_REFERENCES
] = 0x0080,
114 [PERF_COUNT_CACHE_MISSES
] = 0x0081,
115 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
116 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
119 static u64
amd_pmu_event_map(int event
)
121 return amd_perfmon_event_map
[event
];
124 static u64
amd_pmu_raw_event(u64 event
)
126 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
127 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
128 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
130 #define K7_EVNTSEL_MASK \
131 (K7_EVNTSEL_EVENT_MASK | \
132 K7_EVNTSEL_UNIT_MASK | \
133 K7_EVNTSEL_COUNTER_MASK)
135 return event
& K7_EVNTSEL_MASK
;
139 * Propagate counter elapsed time into the generic counter.
140 * Can only be executed on the CPU where the counter is active.
141 * Returns the delta events processed.
144 x86_perf_counter_update(struct perf_counter
*counter
,
145 struct hw_perf_counter
*hwc
, int idx
)
147 u64 prev_raw_count
, new_raw_count
, delta
;
150 * Careful: an NMI might modify the previous counter value.
152 * Our tactic to handle this is to first atomically read and
153 * exchange a new raw count - then add that new-prev delta
154 * count to the generic counter atomically:
157 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
158 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
160 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
161 new_raw_count
) != prev_raw_count
)
165 * Now we have the new raw value and have updated the prev
166 * timestamp already. We can now calculate the elapsed delta
167 * (counter-)time and add that to the generic counter.
169 * Careful, not all hw sign-extends above the physical width
170 * of the count, so we do that by clipping the delta to 32 bits:
172 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
174 atomic64_add(delta
, &counter
->count
);
175 atomic64_sub(delta
, &hwc
->period_left
);
178 static atomic_t num_counters
;
179 static DEFINE_MUTEX(pmc_reserve_mutex
);
181 static bool reserve_pmc_hardware(void)
185 if (nmi_watchdog
== NMI_LOCAL_APIC
)
186 disable_lapic_nmi_watchdog();
188 for (i
= 0; i
< nr_counters_generic
; i
++) {
189 if (!reserve_perfctr_nmi(x86_pmu
->perfctr
+ i
))
193 for (i
= 0; i
< nr_counters_generic
; i
++) {
194 if (!reserve_evntsel_nmi(x86_pmu
->eventsel
+ i
))
201 for (i
--; i
>= 0; i
--)
202 release_evntsel_nmi(x86_pmu
->eventsel
+ i
);
204 i
= nr_counters_generic
;
207 for (i
--; i
>= 0; i
--)
208 release_perfctr_nmi(x86_pmu
->perfctr
+ i
);
210 if (nmi_watchdog
== NMI_LOCAL_APIC
)
211 enable_lapic_nmi_watchdog();
216 static void release_pmc_hardware(void)
220 for (i
= 0; i
< nr_counters_generic
; i
++) {
221 release_perfctr_nmi(x86_pmu
->perfctr
+ i
);
222 release_evntsel_nmi(x86_pmu
->eventsel
+ i
);
225 if (nmi_watchdog
== NMI_LOCAL_APIC
)
226 enable_lapic_nmi_watchdog();
229 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
231 if (atomic_dec_and_mutex_lock(&num_counters
, &pmc_reserve_mutex
)) {
232 release_pmc_hardware();
233 mutex_unlock(&pmc_reserve_mutex
);
238 * Setup the hardware configuration for a given hw_event_type
240 static int __hw_perf_counter_init(struct perf_counter
*counter
)
242 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
243 struct hw_perf_counter
*hwc
= &counter
->hw
;
246 /* disable temporarily */
247 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
250 if (unlikely(!perf_counters_initialized
))
254 if (atomic_inc_not_zero(&num_counters
)) {
255 mutex_lock(&pmc_reserve_mutex
);
256 if (atomic_read(&num_counters
) == 0 && !reserve_pmc_hardware())
259 atomic_inc(&num_counters
);
260 mutex_unlock(&pmc_reserve_mutex
);
267 * (keep 'enabled' bit clear for now)
269 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
272 * Count user and OS events unless requested not to.
274 if (!hw_event
->exclude_user
)
275 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
276 if (!hw_event
->exclude_kernel
)
277 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
280 * If privileged enough, allow NMI events:
283 if (capable(CAP_SYS_ADMIN
) && hw_event
->nmi
)
286 hwc
->irq_period
= hw_event
->irq_period
;
288 * Intel PMCs cannot be accessed sanely above 32 bit width,
289 * so we install an artificial 1<<31 period regardless of
290 * the generic counter period:
292 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
293 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
294 hwc
->irq_period
= 0x7FFFFFFF;
296 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
299 * Raw event type provide the config in the event structure
301 if (perf_event_raw(hw_event
)) {
302 hwc
->config
|= x86_pmu
->raw_event(perf_event_config(hw_event
));
304 if (perf_event_id(hw_event
) >= x86_pmu
->max_events
)
309 hwc
->config
|= x86_pmu
->event_map(perf_event_id(hw_event
));
312 counter
->destroy
= hw_perf_counter_destroy
;
317 static u64
intel_pmu_save_disable_all(void)
321 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
322 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
327 static u64
amd_pmu_save_disable_all(void)
329 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
332 enabled
= cpuc
->enabled
;
335 * ensure we write the disable before we start disabling the
336 * counters proper, so that amd_pmu_enable_counter() does the
341 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
344 if (!test_bit(idx
, cpuc
->active_mask
))
346 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
347 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
349 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
350 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
356 u64
hw_perf_save_disable(void)
358 if (unlikely(!perf_counters_initialized
))
361 return x86_pmu
->save_disable_all();
364 * Exported because of ACPI idle
366 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
368 static void intel_pmu_restore_all(u64 ctrl
)
370 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
373 static void amd_pmu_restore_all(u64 ctrl
)
375 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
378 cpuc
->enabled
= ctrl
;
383 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
386 if (!test_bit(idx
, cpuc
->active_mask
))
388 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
389 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
391 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
392 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
396 void hw_perf_restore(u64 ctrl
)
398 if (unlikely(!perf_counters_initialized
))
401 x86_pmu
->restore_all(ctrl
);
404 * Exported because of ACPI idle
406 EXPORT_SYMBOL_GPL(hw_perf_restore
);
408 static u64
intel_pmu_get_status(u64 mask
)
412 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
417 static u64
amd_pmu_get_status(u64 mask
)
422 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
425 if (!(mask
& (1 << idx
)))
428 rdmsrl(MSR_K7_PERFCTR0
+ idx
, val
);
429 val
<<= (64 - counter_value_bits
);
431 status
|= (1 << idx
);
437 static u64
hw_perf_get_status(u64 mask
)
439 if (unlikely(!perf_counters_initialized
))
442 return x86_pmu
->get_status(mask
);
445 static void intel_pmu_ack_status(u64 ack
)
447 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
450 static void amd_pmu_ack_status(u64 ack
)
454 static void hw_perf_ack_status(u64 ack
)
456 if (unlikely(!perf_counters_initialized
))
459 x86_pmu
->ack_status(ack
);
462 static void intel_pmu_enable_counter(int idx
, u64 config
)
464 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
,
465 config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
468 static void amd_pmu_enable_counter(int idx
, u64 config
)
470 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
472 set_bit(idx
, cpuc
->active_mask
);
474 config
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
476 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
479 static void hw_perf_enable(int idx
, u64 config
)
481 if (unlikely(!perf_counters_initialized
))
484 x86_pmu
->enable(idx
, config
);
487 static void intel_pmu_disable_counter(int idx
, u64 config
)
489 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, config
);
492 static void amd_pmu_disable_counter(int idx
, u64 config
)
494 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
496 clear_bit(idx
, cpuc
->active_mask
);
497 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
501 static void hw_perf_disable(int idx
, u64 config
)
503 if (unlikely(!perf_counters_initialized
))
506 x86_pmu
->disable(idx
, config
);
510 __pmc_fixed_disable(struct perf_counter
*counter
,
511 struct hw_perf_counter
*hwc
, unsigned int __idx
)
513 int idx
= __idx
- X86_PMC_IDX_FIXED
;
517 mask
= 0xfULL
<< (idx
* 4);
519 rdmsrl(hwc
->config_base
, ctrl_val
);
521 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
525 __x86_pmu_disable(struct perf_counter
*counter
,
526 struct hw_perf_counter
*hwc
, unsigned int idx
)
528 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
529 __pmc_fixed_disable(counter
, hwc
, idx
);
531 hw_perf_disable(idx
, hwc
->config
);
534 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
537 * Set the next IRQ period, based on the hwc->period_left value.
538 * To be called with the counter disabled in hw:
541 __hw_perf_counter_set_period(struct perf_counter
*counter
,
542 struct hw_perf_counter
*hwc
, int idx
)
544 s64 left
= atomic64_read(&hwc
->period_left
);
545 s64 period
= hwc
->irq_period
;
549 * If we are way outside a reasoable range then just skip forward:
551 if (unlikely(left
<= -period
)) {
553 atomic64_set(&hwc
->period_left
, left
);
556 if (unlikely(left
<= 0)) {
558 atomic64_set(&hwc
->period_left
, left
);
561 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
564 * The hw counter starts counting from this counter offset,
565 * mark it to be able to extra future deltas:
567 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
569 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
570 (u64
)(-left
) & counter_value_mask
);
574 __pmc_fixed_enable(struct perf_counter
*counter
,
575 struct hw_perf_counter
*hwc
, unsigned int __idx
)
577 int idx
= __idx
- X86_PMC_IDX_FIXED
;
578 u64 ctrl_val
, bits
, mask
;
582 * Enable IRQ generation (0x8),
583 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
587 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
589 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
592 mask
= 0xfULL
<< (idx
* 4);
594 rdmsrl(hwc
->config_base
, ctrl_val
);
597 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
601 __x86_pmu_enable(struct perf_counter
*counter
,
602 struct hw_perf_counter
*hwc
, int idx
)
604 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
605 __pmc_fixed_enable(counter
, hwc
, idx
);
607 hw_perf_enable(idx
, hwc
->config
);
611 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
615 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
618 if (unlikely(hwc
->nmi
))
621 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
623 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_INSTRUCTIONS
)))
624 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
625 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_CPU_CYCLES
)))
626 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
627 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_BUS_CYCLES
)))
628 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
634 * Find a PMC slot for the freshly enabled / scheduled in counter:
636 static int x86_pmu_enable(struct perf_counter
*counter
)
638 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
639 struct hw_perf_counter
*hwc
= &counter
->hw
;
642 idx
= fixed_mode_idx(counter
, hwc
);
645 * Try to get the fixed counter, if that is already taken
646 * then try to get a generic counter:
648 if (test_and_set_bit(idx
, cpuc
->used
))
651 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
653 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
654 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
657 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
661 /* Try to get the previous generic counter again */
662 if (test_and_set_bit(idx
, cpuc
->used
)) {
664 idx
= find_first_zero_bit(cpuc
->used
, nr_counters_generic
);
665 if (idx
== nr_counters_generic
)
668 set_bit(idx
, cpuc
->used
);
671 hwc
->config_base
= x86_pmu
->eventsel
;
672 hwc
->counter_base
= x86_pmu
->perfctr
;
675 perf_counters_lapic_init(hwc
->nmi
);
677 __x86_pmu_disable(counter
, hwc
, idx
);
679 cpuc
->counters
[idx
] = counter
;
681 * Make it visible before enabling the hw:
685 __hw_perf_counter_set_period(counter
, hwc
, idx
);
686 __x86_pmu_enable(counter
, hwc
, idx
);
691 void perf_counter_print_debug(void)
693 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
694 struct cpu_hw_counters
*cpuc
;
697 if (!nr_counters_generic
)
702 cpu
= smp_processor_id();
703 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
705 if (intel_perfmon_version
>= 2) {
706 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
707 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
708 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
709 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
712 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
713 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
714 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
715 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
717 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
719 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
720 rdmsrl(x86_pmu
->eventsel
+ idx
, pmc_ctrl
);
721 rdmsrl(x86_pmu
->perfctr
+ idx
, pmc_count
);
723 prev_left
= per_cpu(prev_left
[idx
], cpu
);
725 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
727 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
728 cpu
, idx
, pmc_count
);
729 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
730 cpu
, idx
, prev_left
);
732 for (idx
= 0; idx
< nr_counters_fixed
; idx
++) {
733 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
735 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
736 cpu
, idx
, pmc_count
);
741 static void x86_pmu_disable(struct perf_counter
*counter
)
743 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
744 struct hw_perf_counter
*hwc
= &counter
->hw
;
745 unsigned int idx
= hwc
->idx
;
747 __x86_pmu_disable(counter
, hwc
, idx
);
749 clear_bit(idx
, cpuc
->used
);
750 cpuc
->counters
[idx
] = NULL
;
752 * Make sure the cleared pointer becomes visible before we
753 * (potentially) free the counter:
758 * Drain the remaining delta count out of a counter
759 * that we are disabling:
761 x86_perf_counter_update(counter
, hwc
, idx
);
765 * Save and restart an expired counter. Called by NMI contexts,
766 * so it has to be careful about preempting normal counter ops:
768 static void perf_save_and_restart(struct perf_counter
*counter
)
770 struct hw_perf_counter
*hwc
= &counter
->hw
;
773 x86_perf_counter_update(counter
, hwc
, idx
);
774 __hw_perf_counter_set_period(counter
, hwc
, idx
);
776 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
777 __x86_pmu_enable(counter
, hwc
, idx
);
781 * Maximum interrupt frequency of 100KHz per CPU
783 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
786 * This handler is triggered by the local APIC, so the APIC IRQ handling
789 static int intel_pmu_handle_irq(struct pt_regs
*regs
, int nmi
)
791 int bit
, cpu
= smp_processor_id();
793 struct cpu_hw_counters
*cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
796 cpuc
->throttle_ctrl
= hw_perf_save_disable();
798 status
= hw_perf_get_status(cpuc
->throttle_ctrl
);
804 inc_irq_stat(apic_perf_irqs
);
806 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
807 struct perf_counter
*counter
= cpuc
->counters
[bit
];
809 clear_bit(bit
, (unsigned long *) &status
);
813 perf_save_and_restart(counter
);
814 if (perf_counter_overflow(counter
, nmi
, regs
, 0))
815 __x86_pmu_disable(counter
, &counter
->hw
, bit
);
818 hw_perf_ack_status(ack
);
821 * Repeat if there is more work to be done:
823 status
= hw_perf_get_status(cpuc
->throttle_ctrl
);
828 * Restore - do not reenable when global enable is off or throttled:
830 if (++cpuc
->interrupts
< PERFMON_MAX_INTERRUPTS
)
831 hw_perf_restore(cpuc
->throttle_ctrl
);
836 static int amd_pmu_handle_irq(struct pt_regs
*regs
, int nmi
) { return 0; }
838 void perf_counter_unthrottle(void)
840 struct cpu_hw_counters
*cpuc
;
842 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
845 if (unlikely(!perf_counters_initialized
))
848 cpuc
= &__get_cpu_var(cpu_hw_counters
);
849 if (cpuc
->interrupts
>= PERFMON_MAX_INTERRUPTS
) {
850 if (printk_ratelimit())
851 printk(KERN_WARNING
"PERFMON: max interrupts exceeded!\n");
852 hw_perf_restore(cpuc
->throttle_ctrl
);
854 cpuc
->interrupts
= 0;
857 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
860 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
862 x86_pmu
->handle_irq(regs
, 0);
866 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
870 inc_irq_stat(apic_pending_irqs
);
871 perf_counter_do_pending();
875 void set_perf_counter_pending(void)
877 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
880 void perf_counters_lapic_init(int nmi
)
884 if (!perf_counters_initialized
)
887 * Enable the performance counter vector in the APIC LVT:
889 apic_val
= apic_read(APIC_LVTERR
);
891 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
893 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
895 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
896 apic_write(APIC_LVTERR
, apic_val
);
900 perf_counter_nmi_handler(struct notifier_block
*self
,
901 unsigned long cmd
, void *__args
)
903 struct die_args
*args
= __args
;
904 struct pt_regs
*regs
;
918 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
919 ret
= x86_pmu
->handle_irq(regs
, 1);
921 return ret
? NOTIFY_STOP
: NOTIFY_OK
;
924 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
925 .notifier_call
= perf_counter_nmi_handler
,
930 static struct x86_pmu intel_pmu
= {
931 .handle_irq
= intel_pmu_handle_irq
,
932 .save_disable_all
= intel_pmu_save_disable_all
,
933 .restore_all
= intel_pmu_restore_all
,
934 .get_status
= intel_pmu_get_status
,
935 .ack_status
= intel_pmu_ack_status
,
936 .enable
= intel_pmu_enable_counter
,
937 .disable
= intel_pmu_disable_counter
,
938 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
939 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
940 .event_map
= intel_pmu_event_map
,
941 .raw_event
= intel_pmu_raw_event
,
942 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
945 static struct x86_pmu amd_pmu
= {
946 .handle_irq
= amd_pmu_handle_irq
,
947 .save_disable_all
= amd_pmu_save_disable_all
,
948 .restore_all
= amd_pmu_restore_all
,
949 .get_status
= amd_pmu_get_status
,
950 .ack_status
= amd_pmu_ack_status
,
951 .enable
= amd_pmu_enable_counter
,
952 .disable
= amd_pmu_disable_counter
,
953 .eventsel
= MSR_K7_EVNTSEL0
,
954 .perfctr
= MSR_K7_PERFCTR0
,
955 .event_map
= amd_pmu_event_map
,
956 .raw_event
= amd_pmu_raw_event
,
957 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
960 static struct x86_pmu
*intel_pmu_init(void)
962 union cpuid10_edx edx
;
963 union cpuid10_eax eax
;
967 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
971 * Check whether the Architectural PerfMon supports
972 * Branch Misses Retired Event or not.
974 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
975 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
978 intel_perfmon_version
= eax
.split
.version_id
;
979 if (intel_perfmon_version
< 2)
982 pr_info("Intel Performance Monitoring support detected.\n");
983 pr_info("... version: %d\n", intel_perfmon_version
);
984 pr_info("... bit width: %d\n", eax
.split
.bit_width
);
985 pr_info("... mask length: %d\n", eax
.split
.mask_length
);
987 nr_counters_generic
= eax
.split
.num_counters
;
988 nr_counters_fixed
= edx
.split
.num_counters_fixed
;
989 counter_value_mask
= (1ULL << eax
.split
.bit_width
) - 1;
994 static struct x86_pmu
*amd_pmu_init(void)
996 nr_counters_generic
= 4;
997 nr_counters_fixed
= 0;
998 counter_value_mask
= 0x0000FFFFFFFFFFFFULL
;
999 counter_value_bits
= 48;
1001 pr_info("AMD Performance Monitoring support detected.\n");
1006 void __init
init_hw_perf_counters(void)
1008 switch (boot_cpu_data
.x86_vendor
) {
1009 case X86_VENDOR_INTEL
:
1010 x86_pmu
= intel_pmu_init();
1012 case X86_VENDOR_AMD
:
1013 x86_pmu
= amd_pmu_init();
1021 pr_info("... num counters: %d\n", nr_counters_generic
);
1022 if (nr_counters_generic
> X86_PMC_MAX_GENERIC
) {
1023 nr_counters_generic
= X86_PMC_MAX_GENERIC
;
1024 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
1025 nr_counters_generic
, X86_PMC_MAX_GENERIC
);
1027 perf_counter_mask
= (1 << nr_counters_generic
) - 1;
1028 perf_max_counters
= nr_counters_generic
;
1030 pr_info("... value mask: %016Lx\n", counter_value_mask
);
1032 if (nr_counters_fixed
> X86_PMC_MAX_FIXED
) {
1033 nr_counters_fixed
= X86_PMC_MAX_FIXED
;
1034 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1035 nr_counters_fixed
, X86_PMC_MAX_FIXED
);
1037 pr_info("... fixed counters: %d\n", nr_counters_fixed
);
1039 perf_counter_mask
|= ((1LL << nr_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1041 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1042 perf_counters_initialized
= true;
1044 perf_counters_lapic_init(0);
1045 register_die_notifier(&perf_counter_nmi_notifier
);
1048 static void x86_pmu_read(struct perf_counter
*counter
)
1050 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1053 static const struct pmu pmu
= {
1054 .enable
= x86_pmu_enable
,
1055 .disable
= x86_pmu_disable
,
1056 .read
= x86_pmu_read
,
1059 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1063 err
= __hw_perf_counter_init(counter
);
1065 return ERR_PTR(err
);
1075 void callchain_store(struct perf_callchain_entry
*entry
, unsigned long ip
)
1077 if (entry
->nr
< MAX_STACK_DEPTH
)
1078 entry
->ip
[entry
->nr
++] = ip
;
1081 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1082 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1086 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1088 /* Ignore warnings */
1091 static void backtrace_warning(void *data
, char *msg
)
1093 /* Ignore warnings */
1096 static int backtrace_stack(void *data
, char *name
)
1098 /* Don't bother with IRQ stacks for now */
1102 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1104 struct perf_callchain_entry
*entry
= data
;
1107 callchain_store(entry
, addr
);
1110 static const struct stacktrace_ops backtrace_ops
= {
1111 .warning
= backtrace_warning
,
1112 .warning_symbol
= backtrace_warning_symbol
,
1113 .stack
= backtrace_stack
,
1114 .address
= backtrace_address
,
1118 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1124 callchain_store(entry
, instruction_pointer(regs
));
1126 stack
= ((char *)regs
+ sizeof(struct pt_regs
));
1127 #ifdef CONFIG_FRAME_POINTER
1128 bp
= frame_pointer(regs
);
1133 dump_trace(NULL
, regs
, (void *)stack
, bp
, &backtrace_ops
, entry
);
1135 entry
->kernel
= entry
->nr
- nr
;
1139 struct stack_frame
{
1140 const void __user
*next_fp
;
1141 unsigned long return_address
;
1144 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1148 if (!access_ok(VERIFY_READ
, fp
, sizeof(*frame
)))
1152 pagefault_disable();
1153 if (__copy_from_user_inatomic(frame
, fp
, sizeof(*frame
)))
1161 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1163 struct stack_frame frame
;
1164 const void __user
*fp
;
1167 regs
= (struct pt_regs
*)current
->thread
.sp0
- 1;
1168 fp
= (void __user
*)regs
->bp
;
1170 callchain_store(entry
, regs
->ip
);
1172 while (entry
->nr
< MAX_STACK_DEPTH
) {
1173 frame
.next_fp
= NULL
;
1174 frame
.return_address
= 0;
1176 if (!copy_stack_frame(fp
, &frame
))
1179 if ((unsigned long)fp
< user_stack_pointer(regs
))
1182 callchain_store(entry
, frame
.return_address
);
1186 entry
->user
= entry
->nr
- nr
;
1190 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1197 is_user
= user_mode(regs
);
1199 if (!current
|| current
->pid
== 0)
1202 if (is_user
&& current
->state
!= TASK_RUNNING
)
1206 perf_callchain_kernel(regs
, entry
);
1209 perf_callchain_user(regs
, entry
);
1212 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1214 struct perf_callchain_entry
*entry
;
1217 entry
= &__get_cpu_var(nmi_entry
);
1219 entry
= &__get_cpu_var(irq_entry
);
1226 perf_do_callchain(regs
, entry
);