drivers/net/wireless/ath9k/phy.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18
  19 void
  20 ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex,
  21                     int regWrites)
  22 {
  23         struct ath_hal_5416 *ahp = AH5416(ah);
  24
  25         REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
  26 }
  27
  28 bool
  29 ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
  30 {
  31         u32 channelSel = 0;
  32         u32 bModeSynth = 0;
  33         u32 aModeRefSel = 0;
  34         u32 reg32 = 0;
  35         u16 freq;
  36         struct chan_centers centers;
  37
  38         ath9k_hw_get_channel_centers(ah, chan, &centers);
  39         freq = centers.synth_center;
  40
  41         if (freq < 4800) {
  42                 u32 txctl;
  43
  44                 if (((freq - 2192) % 5) == 0) {
  45                         channelSel = ((freq - 672) * 2 - 3040) / 10;
  46                         bModeSynth = 0;
  47                 } else if (((freq - 2224) % 5) == 0) {
  48                         channelSel = ((freq - 704) * 2 - 3040) / 10;
  49                         bModeSynth = 1;
  50                 } else {
  51                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
  52                                 "Invalid channel %u MHz\n", freq);
  53                         return false;
  54                 }
  55
  56                 channelSel = (channelSel << 2) & 0xff;
  57                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
  58
  59                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
  60                 if (freq == 2484) {
  61
  62                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  63                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
  64                 } else {
  65                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
  66                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
  67                 }
  68
  69         } else if ((freq % 20) == 0 && freq >= 5120) {
  70                 channelSel =
  71                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
  72                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  73         } else if ((freq % 10) == 0) {
  74                 channelSel =
  75                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
  76                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
  77                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
  78                 else
  79                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  80         } else if ((freq % 5) == 0) {
  81                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
  82                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
  83         } else {
  84                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
  85                         "Invalid channel %u MHz\n", freq);
  86                 return false;
  87         }
  88
  89         reg32 =
  90             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
  91             (1 << 5) | 0x1;
  92
  93         REG_WRITE(ah, AR_PHY(0x37), reg32);
  94
  95         ah->ah_curchan = chan;
  96
  97         AH5416(ah)->ah_curchanRadIndex = -1;
  98
  99         return true;
 100 }
 101
 102 bool
 103 ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
 104                             struct ath9k_channel *chan)
 105 {
 106         u16 bMode, fracMode, aModeRefSel = 0;
 107         u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
 108         struct chan_centers centers;
 109         u32 refDivA = 24;
 110
 111         ath9k_hw_get_channel_centers(ah, chan, &centers);
 112         freq = centers.synth_center;
 113
 114         reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
 115         reg32 &= 0xc0000000;
 116
 117         if (freq < 4800) {
 118                 u32 txctl;
 119
 120                 bMode = 1;
 121                 fracMode = 1;
 122                 aModeRefSel = 0;
 123                 channelSel = (freq * 0x10000) / 15;
 124
 125                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 126                 if (freq == 2484) {
 127
 128                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 129                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 130                 } else {
 131                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 132                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 133                 }
 134         } else {
 135                 bMode = 0;
 136                 fracMode = 0;
 137
 138                 if ((freq % 20) == 0) {
 139                         aModeRefSel = 3;
 140                 } else if ((freq % 10) == 0) {
 141                         aModeRefSel = 2;
 142                 } else {
 143                         aModeRefSel = 0;
 144
 145                         fracMode = 1;
 146                         refDivA = 1;
 147                         channelSel = (freq * 0x8000) / 15;
 148
 149                         REG_RMW_FIELD(ah, AR_AN_SYNTH9,
 150                                       AR_AN_SYNTH9_REFDIVA, refDivA);
 151                 }
 152                 if (!fracMode) {
 153                         ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
 154                         channelSel = ndiv & 0x1ff;
 155                         channelFrac = (ndiv & 0xfffffe00) * 2;
 156                         channelSel = (channelSel << 17) | channelFrac;
 157                 }
 158         }
 159
 160         reg32 = reg32 |
 161             (bMode << 29) |
 162             (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
 163
 164         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 165
 166         ah->ah_curchan = chan;
 167
 168         AH5416(ah)->ah_curchanRadIndex = -1;
 169
 170         return true;
 171 }
 172
 173 static void
 174 ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
 175                            u32 numBits, u32 firstBit,
 176                            u32 column)
 177 {
 178         u32 tmp32, mask, arrayEntry, lastBit;
 179         int32_t bitPosition, bitsLeft;
 180
 181         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
 182         arrayEntry = (firstBit - 1) / 8;
 183         bitPosition = (firstBit - 1) % 8;
 184         bitsLeft = numBits;
 185         while (bitsLeft > 0) {
 186                 lastBit = (bitPosition + bitsLeft > 8) ?
 187                     8 : bitPosition + bitsLeft;
 188                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
 189                     (column * 8);
 190                 rfBuf[arrayEntry] &= ~mask;
 191                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
 192                                       (column * 8)) & mask;
 193                 bitsLeft -= 8 - bitPosition;
 194                 tmp32 = tmp32 >> (8 - bitPosition);
 195                 bitPosition = 0;
 196                 arrayEntry++;
 197         }
 198 }
 199
 200 bool
 201 ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
 202                      u16 modesIndex)
 203 {
 204         struct ath_hal_5416 *ahp = AH5416(ah);
 205
 206         u32 eepMinorRev;
 207         u32 ob5GHz = 0, db5GHz = 0;
 208         u32 ob2GHz = 0, db2GHz = 0;
 209         int regWrites = 0;
 210
 211         if (AR_SREV_9280_10_OR_LATER(ah))
 212                 return true;
 213
 214         eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
 215
 216         RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1);
 217
 218         RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1);
 219
 220         RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1);
 221
 222         RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3,
 223                       modesIndex);
 224         {
 225                 int i;
 226                 for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) {
 227                         ahp->ah_analogBank6Data[i] =
 228                             INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex);
 229                 }
 230         }
 231
 232         if (eepMinorRev >= 2) {
 233                 if (IS_CHAN_2GHZ(chan)) {
 234                         ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
 235                         db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
 236                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 237                                                    ob2GHz, 3, 197, 0);
 238                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 239                                                    db2GHz, 3, 194, 0);
 240                 } else {
 241                         ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
 242                         db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
 243                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 244                                                    ob5GHz, 3, 203, 0);
 245                         ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data,
 246                                                    db5GHz, 3, 200, 0);
 247                 }
 248         }
 249
 250         RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1);
 251
 252         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data,
 253                            regWrites);
 254         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data,
 255                            regWrites);
 256         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data,
 257                            regWrites);
 258         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data,
 259                            regWrites);
 260         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data,
 261                            regWrites);
 262         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data,
 263                            regWrites);
 264
 265         return true;
 266 }
 267
 268 void
 269 ath9k_hw_rfdetach(struct ath_hal *ah)
 270 {
 271         struct ath_hal_5416 *ahp = AH5416(ah);
 272
 273         if (ahp->ah_analogBank0Data != NULL) {
 274                 kfree(ahp->ah_analogBank0Data);
 275                 ahp->ah_analogBank0Data = NULL;
 276         }
 277         if (ahp->ah_analogBank1Data != NULL) {
 278                 kfree(ahp->ah_analogBank1Data);
 279                 ahp->ah_analogBank1Data = NULL;
 280         }
 281         if (ahp->ah_analogBank2Data != NULL) {
 282                 kfree(ahp->ah_analogBank2Data);
 283                 ahp->ah_analogBank2Data = NULL;
 284         }
 285         if (ahp->ah_analogBank3Data != NULL) {
 286                 kfree(ahp->ah_analogBank3Data);
 287                 ahp->ah_analogBank3Data = NULL;
 288         }
 289         if (ahp->ah_analogBank6Data != NULL) {
 290                 kfree(ahp->ah_analogBank6Data);
 291                 ahp->ah_analogBank6Data = NULL;
 292         }
 293         if (ahp->ah_analogBank6TPCData != NULL) {
 294                 kfree(ahp->ah_analogBank6TPCData);
 295                 ahp->ah_analogBank6TPCData = NULL;
 296         }
 297         if (ahp->ah_analogBank7Data != NULL) {
 298                 kfree(ahp->ah_analogBank7Data);
 299                 ahp->ah_analogBank7Data = NULL;
 300         }
 301         if (ahp->ah_addac5416_21 != NULL) {
 302                 kfree(ahp->ah_addac5416_21);
 303                 ahp->ah_addac5416_21 = NULL;
 304         }
 305         if (ahp->ah_bank6Temp != NULL) {
 306                 kfree(ahp->ah_bank6Temp);
 307                 ahp->ah_bank6Temp = NULL;
 308         }
 309 }
 310
 311 bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
 312 {
 313         struct ath_hal_5416 *ahp = AH5416(ah);
 314
 315         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 316
 317                 ahp->ah_analogBank0Data =
 318                     kzalloc((sizeof(u32) *
 319                              ahp->ah_iniBank0.ia_rows), GFP_KERNEL);
 320                 ahp->ah_analogBank1Data =
 321                     kzalloc((sizeof(u32) *
 322                              ahp->ah_iniBank1.ia_rows), GFP_KERNEL);
 323                 ahp->ah_analogBank2Data =
 324                     kzalloc((sizeof(u32) *
 325                              ahp->ah_iniBank2.ia_rows), GFP_KERNEL);
 326                 ahp->ah_analogBank3Data =
 327                     kzalloc((sizeof(u32) *
 328                              ahp->ah_iniBank3.ia_rows), GFP_KERNEL);
 329                 ahp->ah_analogBank6Data =
 330                     kzalloc((sizeof(u32) *
 331                              ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 332                 ahp->ah_analogBank6TPCData =
 333                     kzalloc((sizeof(u32) *
 334                              ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
 335                 ahp->ah_analogBank7Data =
 336                     kzalloc((sizeof(u32) *
 337                              ahp->ah_iniBank7.ia_rows), GFP_KERNEL);
 338
 339                 if (ahp->ah_analogBank0Data == NULL
 340                     || ahp->ah_analogBank1Data == NULL
 341                     || ahp->ah_analogBank2Data == NULL
 342                     || ahp->ah_analogBank3Data == NULL
 343                     || ahp->ah_analogBank6Data == NULL
 344                     || ahp->ah_analogBank6TPCData == NULL
 345                     || ahp->ah_analogBank7Data == NULL) {
 346                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 347                                 "Cannot allocate RF banks\n");
 348                         *status = -ENOMEM;
 349                         return false;
 350                 }
 351
 352                 ahp->ah_addac5416_21 =
 353                     kzalloc((sizeof(u32) *
 354                              ahp->ah_iniAddac.ia_rows *
 355                              ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
 356                 if (ahp->ah_addac5416_21 == NULL) {
 357                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 358                                 "Cannot allocate ah_addac5416_21\n");
 359                         *status = -ENOMEM;
 360                         return false;
 361                 }
 362
 363                 ahp->ah_bank6Temp =
 364                     kzalloc((sizeof(u32) *
 365                              ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
 366                 if (ahp->ah_bank6Temp == NULL) {
 367                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 368                                 "Cannot allocate ah_bank6Temp\n");
 369                         *status = -ENOMEM;
 370                         return false;
 371                 }
 372         }
 373
 374         return true;
 375 }
 376
 377 void
 378 ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
 379 {
 380         int i, regWrites = 0;
 381         struct ath_hal_5416 *ahp = AH5416(ah);
 382         u32 bank6SelMask;
 383         u32 *bank6Temp = ahp->ah_bank6Temp;
 384
 385         switch (ahp->ah_diversityControl) {
 386         case ATH9K_ANT_FIXED_A:
 387                 bank6SelMask =
 388                     (ahp->
 389                      ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
 390                     REDUCE_CHAIN_1;
 391                 break;
 392         case ATH9K_ANT_FIXED_B:
 393                 bank6SelMask =
 394                     (ahp->
 395                      ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
 396                     REDUCE_CHAIN_0;
 397                 break;
 398         case ATH9K_ANT_VARIABLE:
 399                 return;
 400                 break;
 401         default:
 402                 return;
 403                 break;
 404         }
 405
 406         for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++)
 407                 bank6Temp[i] = ahp->ah_analogBank6Data[i];
 408
 409         REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
 410
 411         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 189, 0);
 412         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 190, 0);
 413         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 191, 0);
 414         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 192, 0);
 415         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 193, 0);
 416         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 222, 0);
 417         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 245, 0);
 418         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
 419         ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
 420
 421         REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites);
 422
 423         REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
 424 #ifdef ALTER_SWITCH
 425         REG_WRITE(ah, PHY_SWITCH_CHAIN_0,
 426                   (REG_READ(ah, PHY_SWITCH_CHAIN_0) & ~0x38)
 427                   | ((REG_READ(ah, PHY_SWITCH_CHAIN_0) >> 3) & 0x38));
 428 #endif
 429 }