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drm/i915: handle FIFO oversubsription correctly
[linux-2.6/mini2440.git] / drivers / gpu / drm / i915 / intel_display.c
blob890f7108e723c1b5878ff9ca1f701d467a3e5ee4
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/i2c.h>
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "intel_drv.h"
31 #include "i915_drm.h"
32 #include "i915_drv.h"
33 #include "intel_dp.h"
34
35 #include "drm_crtc_helper.h"
36
37 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
38 static void intel_update_watermarks(struct drm_device *dev);
39
40 typedef struct {
41 /* given values */
42 int n;
43 int m1, m2;
44 int p1, p2;
45 /* derived values */
46 int dot;
47 int vco;
48 int m;
49 int p;
50 } intel_clock_t;
51
52 typedef struct {
53 int min, max;
54 } intel_range_t;
55
56 typedef struct {
57 int dot_limit;
58 int p2_slow, p2_fast;
59 } intel_p2_t;
60
61 #define INTEL_P2_NUM 2
62 typedef struct intel_limit intel_limit_t;
63 struct intel_limit {
64 intel_range_t dot, vco, n, m, m1, m2, p, p1;
65 intel_p2_t p2;
66 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
67 int, int, intel_clock_t *);
68 };
69
70 #define I8XX_DOT_MIN 25000
71 #define I8XX_DOT_MAX 350000
72 #define I8XX_VCO_MIN 930000
73 #define I8XX_VCO_MAX 1400000
74 #define I8XX_N_MIN 3
75 #define I8XX_N_MAX 16
76 #define I8XX_M_MIN 96
77 #define I8XX_M_MAX 140
78 #define I8XX_M1_MIN 18
79 #define I8XX_M1_MAX 26
80 #define I8XX_M2_MIN 6
81 #define I8XX_M2_MAX 16
82 #define I8XX_P_MIN 4
83 #define I8XX_P_MAX 128
84 #define I8XX_P1_MIN 2
85 #define I8XX_P1_MAX 33
86 #define I8XX_P1_LVDS_MIN 1
87 #define I8XX_P1_LVDS_MAX 6
88 #define I8XX_P2_SLOW 4
89 #define I8XX_P2_FAST 2
90 #define I8XX_P2_LVDS_SLOW 14
91 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
92 #define I8XX_P2_SLOW_LIMIT 165000
93
94 #define I9XX_DOT_MIN 20000
95 #define I9XX_DOT_MAX 400000
96 #define I9XX_VCO_MIN 1400000
97 #define I9XX_VCO_MAX 2800000
98 #define IGD_VCO_MIN 1700000
99 #define IGD_VCO_MAX 3500000
100 #define I9XX_N_MIN 1
101 #define I9XX_N_MAX 6
102 /* IGD's Ncounter is a ring counter */
103 #define IGD_N_MIN 3
104 #define IGD_N_MAX 6
105 #define I9XX_M_MIN 70
106 #define I9XX_M_MAX 120
107 #define IGD_M_MIN 2
108 #define IGD_M_MAX 256
109 #define I9XX_M1_MIN 10
110 #define I9XX_M1_MAX 22
111 #define I9XX_M2_MIN 5
112 #define I9XX_M2_MAX 9
113 /* IGD M1 is reserved, and must be 0 */
114 #define IGD_M1_MIN 0
115 #define IGD_M1_MAX 0
116 #define IGD_M2_MIN 0
117 #define IGD_M2_MAX 254
118 #define I9XX_P_SDVO_DAC_MIN 5
119 #define I9XX_P_SDVO_DAC_MAX 80
120 #define I9XX_P_LVDS_MIN 7
121 #define I9XX_P_LVDS_MAX 98
122 #define IGD_P_LVDS_MIN 7
123 #define IGD_P_LVDS_MAX 112
124 #define I9XX_P1_MIN 1
125 #define I9XX_P1_MAX 8
126 #define I9XX_P2_SDVO_DAC_SLOW 10
127 #define I9XX_P2_SDVO_DAC_FAST 5
128 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
129 #define I9XX_P2_LVDS_SLOW 14
130 #define I9XX_P2_LVDS_FAST 7
131 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
132
133 /*The parameter is for SDVO on G4x platform*/
134 #define G4X_DOT_SDVO_MIN 25000
135 #define G4X_DOT_SDVO_MAX 270000
136 #define G4X_VCO_MIN 1750000
137 #define G4X_VCO_MAX 3500000
138 #define G4X_N_SDVO_MIN 1
139 #define G4X_N_SDVO_MAX 4
140 #define G4X_M_SDVO_MIN 104
141 #define G4X_M_SDVO_MAX 138
142 #define G4X_M1_SDVO_MIN 17
143 #define G4X_M1_SDVO_MAX 23
144 #define G4X_M2_SDVO_MIN 5
145 #define G4X_M2_SDVO_MAX 11
146 #define G4X_P_SDVO_MIN 10
147 #define G4X_P_SDVO_MAX 30
148 #define G4X_P1_SDVO_MIN 1
149 #define G4X_P1_SDVO_MAX 3
150 #define G4X_P2_SDVO_SLOW 10
151 #define G4X_P2_SDVO_FAST 10
152 #define G4X_P2_SDVO_LIMIT 270000
153
154 /*The parameter is for HDMI_DAC on G4x platform*/
155 #define G4X_DOT_HDMI_DAC_MIN 22000
156 #define G4X_DOT_HDMI_DAC_MAX 400000
157 #define G4X_N_HDMI_DAC_MIN 1
158 #define G4X_N_HDMI_DAC_MAX 4
159 #define G4X_M_HDMI_DAC_MIN 104
160 #define G4X_M_HDMI_DAC_MAX 138
161 #define G4X_M1_HDMI_DAC_MIN 16
162 #define G4X_M1_HDMI_DAC_MAX 23
163 #define G4X_M2_HDMI_DAC_MIN 5
164 #define G4X_M2_HDMI_DAC_MAX 11
165 #define G4X_P_HDMI_DAC_MIN 5
166 #define G4X_P_HDMI_DAC_MAX 80
167 #define G4X_P1_HDMI_DAC_MIN 1
168 #define G4X_P1_HDMI_DAC_MAX 8
169 #define G4X_P2_HDMI_DAC_SLOW 10
170 #define G4X_P2_HDMI_DAC_FAST 5
171 #define G4X_P2_HDMI_DAC_LIMIT 165000
172
173 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
174 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
175 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
176 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
177 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
178 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
179 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
180 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
181 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
182 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
183 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
184 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
185 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
186 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
187 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
188 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
189 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
190 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
191
192 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
193 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
194 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
195 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
196 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
197 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
198 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
199 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
200 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
201 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
202 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
203 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
204 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
205 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
206 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
207 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
208 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
209 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
210
211 /*The parameter is for DISPLAY PORT on G4x platform*/
212 #define G4X_DOT_DISPLAY_PORT_MIN 161670
213 #define G4X_DOT_DISPLAY_PORT_MAX 227000
214 #define G4X_N_DISPLAY_PORT_MIN 1
215 #define G4X_N_DISPLAY_PORT_MAX 2
216 #define G4X_M_DISPLAY_PORT_MIN 97
217 #define G4X_M_DISPLAY_PORT_MAX 108
218 #define G4X_M1_DISPLAY_PORT_MIN 0x10
219 #define G4X_M1_DISPLAY_PORT_MAX 0x12
220 #define G4X_M2_DISPLAY_PORT_MIN 0x05
221 #define G4X_M2_DISPLAY_PORT_MAX 0x06
222 #define G4X_P_DISPLAY_PORT_MIN 10
223 #define G4X_P_DISPLAY_PORT_MAX 20
224 #define G4X_P1_DISPLAY_PORT_MIN 1
225 #define G4X_P1_DISPLAY_PORT_MAX 2
226 #define G4X_P2_DISPLAY_PORT_SLOW 10
227 #define G4X_P2_DISPLAY_PORT_FAST 10
228 #define G4X_P2_DISPLAY_PORT_LIMIT 0
229
230 /* IGDNG */
231 /* as we calculate clock using (register_value + 2) for
232 N/M1/M2, so here the range value for them is (actual_value-2).
233 */
234 #define IGDNG_DOT_MIN 25000
235 #define IGDNG_DOT_MAX 350000
236 #define IGDNG_VCO_MIN 1760000
237 #define IGDNG_VCO_MAX 3510000
238 #define IGDNG_N_MIN 1
239 #define IGDNG_N_MAX 5
240 #define IGDNG_M_MIN 79
241 #define IGDNG_M_MAX 118
242 #define IGDNG_M1_MIN 12
243 #define IGDNG_M1_MAX 23
244 #define IGDNG_M2_MIN 5
245 #define IGDNG_M2_MAX 9
246 #define IGDNG_P_SDVO_DAC_MIN 5
247 #define IGDNG_P_SDVO_DAC_MAX 80
248 #define IGDNG_P_LVDS_MIN 28
249 #define IGDNG_P_LVDS_MAX 112
250 #define IGDNG_P1_MIN 1
251 #define IGDNG_P1_MAX 8
252 #define IGDNG_P2_SDVO_DAC_SLOW 10
253 #define IGDNG_P2_SDVO_DAC_FAST 5
254 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
255 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
256 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
257
258 static bool
259 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
260 int target, int refclk, intel_clock_t *best_clock);
261 static bool
262 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
263 int target, int refclk, intel_clock_t *best_clock);
264 static bool
265 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
266 int target, int refclk, intel_clock_t *best_clock);
267
268 static bool
269 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
270 int target, int refclk, intel_clock_t *best_clock);
271
272 static const intel_limit_t intel_limits_i8xx_dvo = {
273 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
274 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
275 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
276 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
277 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
278 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
279 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
280 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
281 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
282 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
283 .find_pll = intel_find_best_PLL,
284 };
285
286 static const intel_limit_t intel_limits_i8xx_lvds = {
287 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
288 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
289 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
290 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
291 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
292 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
293 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
294 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
295 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
296 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
297 .find_pll = intel_find_best_PLL,
298 };
299
300 static const intel_limit_t intel_limits_i9xx_sdvo = {
301 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
302 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
303 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
304 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
305 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
306 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
307 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
308 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
309 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
310 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
311 .find_pll = intel_find_best_PLL,
312 };
313
314 static const intel_limit_t intel_limits_i9xx_lvds = {
315 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
316 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
317 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
318 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
319 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
320 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
321 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
322 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
323 /* The single-channel range is 25-112Mhz, and dual-channel
324 * is 80-224Mhz. Prefer single channel as much as possible.
325 */
326 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
327 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
328 .find_pll = intel_find_best_PLL,
329 };
330
331 /* below parameter and function is for G4X Chipset Family*/
332 static const intel_limit_t intel_limits_g4x_sdvo = {
333 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
334 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
335 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
336 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
337 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
338 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
339 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
340 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
341 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
342 .p2_slow = G4X_P2_SDVO_SLOW,
343 .p2_fast = G4X_P2_SDVO_FAST
344 },
345 .find_pll = intel_g4x_find_best_PLL,
346 };
347
348 static const intel_limit_t intel_limits_g4x_hdmi = {
349 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
350 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
351 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
352 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
353 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
354 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
355 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
356 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
357 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
358 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
359 .p2_fast = G4X_P2_HDMI_DAC_FAST
360 },
361 .find_pll = intel_g4x_find_best_PLL,
362 };
363
364 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
365 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
366 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
367 .vco = { .min = G4X_VCO_MIN,
368 .max = G4X_VCO_MAX },
369 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
370 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
371 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
372 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
373 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
374 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
375 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
376 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
377 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
378 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
379 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
380 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
381 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
382 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
383 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
384 },
385 .find_pll = intel_g4x_find_best_PLL,
386 };
387
388 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
389 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
390 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
391 .vco = { .min = G4X_VCO_MIN,
392 .max = G4X_VCO_MAX },
393 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
394 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
395 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
396 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
397 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
398 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
399 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
400 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
401 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
402 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
403 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
404 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
405 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
406 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
407 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
408 },
409 .find_pll = intel_g4x_find_best_PLL,
410 };
411
412 static const intel_limit_t intel_limits_g4x_display_port = {
413 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
414 .max = G4X_DOT_DISPLAY_PORT_MAX },
415 .vco = { .min = G4X_VCO_MIN,
416 .max = G4X_VCO_MAX},
417 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
418 .max = G4X_N_DISPLAY_PORT_MAX },
419 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
420 .max = G4X_M_DISPLAY_PORT_MAX },
421 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
422 .max = G4X_M1_DISPLAY_PORT_MAX },
423 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
424 .max = G4X_M2_DISPLAY_PORT_MAX },
425 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
426 .max = G4X_P_DISPLAY_PORT_MAX },
427 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
428 .max = G4X_P1_DISPLAY_PORT_MAX},
429 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
430 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
431 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
432 .find_pll = intel_find_pll_g4x_dp,
433 };
434
435 static const intel_limit_t intel_limits_igd_sdvo = {
436 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
437 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
438 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
439 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
440 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
441 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
442 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
443 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
444 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
445 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
446 .find_pll = intel_find_best_PLL,
447 };
448
449 static const intel_limit_t intel_limits_igd_lvds = {
450 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
451 .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX },
452 .n = { .min = IGD_N_MIN, .max = IGD_N_MAX },
453 .m = { .min = IGD_M_MIN, .max = IGD_M_MAX },
454 .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX },
455 .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX },
456 .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX },
457 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
458 /* IGD only supports single-channel mode. */
459 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
460 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
461 .find_pll = intel_find_best_PLL,
462 };
463
464 static const intel_limit_t intel_limits_igdng_sdvo = {
465 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
466 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
467 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
468 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
469 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
470 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
471 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
472 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
473 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
474 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
475 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
476 .find_pll = intel_igdng_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_igdng_lvds = {
480 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
481 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
482 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
483 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
484 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
485 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
486 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
487 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
488 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
489 .p2_slow = IGDNG_P2_LVDS_SLOW,
490 .p2_fast = IGDNG_P2_LVDS_FAST },
491 .find_pll = intel_igdng_find_best_PLL,
492 };
493
494 static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
495 {
496 const intel_limit_t *limit;
497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
498 limit = &intel_limits_igdng_lvds;
499 else
500 limit = &intel_limits_igdng_sdvo;
501
502 return limit;
503 }
504
505 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
506 {
507 struct drm_device *dev = crtc->dev;
508 struct drm_i915_private *dev_priv = dev->dev_private;
509 const intel_limit_t *limit;
510
511 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
512 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
513 LVDS_CLKB_POWER_UP)
514 /* LVDS with dual channel */
515 limit = &intel_limits_g4x_dual_channel_lvds;
516 else
517 /* LVDS with dual channel */
518 limit = &intel_limits_g4x_single_channel_lvds;
519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
521 limit = &intel_limits_g4x_hdmi;
522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
523 limit = &intel_limits_g4x_sdvo;
524 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
525 limit = &intel_limits_g4x_display_port;
526 } else /* The option is for other outputs */
527 limit = &intel_limits_i9xx_sdvo;
528
529 return limit;
530 }
531
532 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
533 {
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
537 if (IS_IGDNG(dev))
538 limit = intel_igdng_limit(crtc);
539 else if (IS_G4X(dev)) {
540 limit = intel_g4x_limit(crtc);
541 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_i9xx_lvds;
544 else
545 limit = &intel_limits_i9xx_sdvo;
546 } else if (IS_IGD(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
548 limit = &intel_limits_igd_lvds;
549 else
550 limit = &intel_limits_igd_sdvo;
551 } else {
552 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
553 limit = &intel_limits_i8xx_lvds;
554 else
555 limit = &intel_limits_i8xx_dvo;
556 }
557 return limit;
558 }
559
560 /* m1 is reserved as 0 in IGD, n is a ring counter */
561 static void igd_clock(int refclk, intel_clock_t *clock)
562 {
563 clock->m = clock->m2 + 2;
564 clock->p = clock->p1 * clock->p2;
565 clock->vco = refclk * clock->m / clock->n;
566 clock->dot = clock->vco / clock->p;
567 }
568
569 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
570 {
571 if (IS_IGD(dev)) {
572 igd_clock(refclk, clock);
573 return;
574 }
575 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
576 clock->p = clock->p1 * clock->p2;
577 clock->vco = refclk * clock->m / (clock->n + 2);
578 clock->dot = clock->vco / clock->p;
579 }
580
581 /**
582 * Returns whether any output on the specified pipe is of the specified type
583 */
584 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
585 {
586 struct drm_device *dev = crtc->dev;
587 struct drm_mode_config *mode_config = &dev->mode_config;
588 struct drm_connector *l_entry;
589
590 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
591 if (l_entry->encoder &&
592 l_entry->encoder->crtc == crtc) {
593 struct intel_output *intel_output = to_intel_output(l_entry);
594 if (intel_output->type == type)
595 return true;
596 }
597 }
598 return false;
599 }
600
601 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
602 /**
603 * Returns whether the given set of divisors are valid for a given refclk with
604 * the given connectors.
605 */
606
607 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
608 {
609 const intel_limit_t *limit = intel_limit (crtc);
610 struct drm_device *dev = crtc->dev;
611
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid ("p1 out of range\n");
614 if (clock->p < limit->p.min || limit->p.max < clock->p)
615 INTELPllInvalid ("p out of range\n");
616 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
617 INTELPllInvalid ("m2 out of range\n");
618 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
619 INTELPllInvalid ("m1 out of range\n");
620 if (clock->m1 <= clock->m2 && !IS_IGD(dev))
621 INTELPllInvalid ("m1 <= m2\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid ("m out of range\n");
624 if (clock->n < limit->n.min || limit->n.max < clock->n)
625 INTELPllInvalid ("n out of range\n");
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid ("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid ("dot out of range\n");
633
634 return true;
635 }
636
637 static bool
638 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
639 int target, int refclk, intel_clock_t *best_clock)
640
641 {
642 struct drm_device *dev = crtc->dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 intel_clock_t clock;
645 int err = target;
646
647 if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
648 (I915_READ(LVDS)) != 0) {
649 /*
650 * For LVDS, if the panel is on, just rely on its current
651 * settings for dual-channel. We haven't figured out how to
652 * reliably set up different single/dual channel state, if we
653 * even can.
654 */
655 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
656 LVDS_CLKB_POWER_UP)
657 clock.p2 = limit->p2.p2_fast;
658 else
659 clock.p2 = limit->p2.p2_slow;
660 } else {
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
663 else
664 clock.p2 = limit->p2.p2_fast;
665 }
666
667 memset (best_clock, 0, sizeof (*best_clock));
668
669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
670 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) {
671 /* m1 is always 0 in IGD */
672 if (clock.m2 >= clock.m1 && !IS_IGD(dev))
673 break;
674 for (clock.n = limit->n.min; clock.n <= limit->n.max;
675 clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
678 int this_err;
679
680 intel_clock(dev, refclk, &clock);
681
682 if (!intel_PLL_is_valid(crtc, &clock))
683 continue;
684
685 this_err = abs(clock.dot - target);
686 if (this_err < err) {
687 *best_clock = clock;
688 err = this_err;
689 }
690 }
691 }
692 }
693 }
694
695 return (err != target);
696 }
697
698 static bool
699 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
700 int target, int refclk, intel_clock_t *best_clock)
701 {
702 struct drm_device *dev = crtc->dev;
703 struct drm_i915_private *dev_priv = dev->dev_private;
704 intel_clock_t clock;
705 int max_n;
706 bool found;
707 /* approximately equals target * 0.00488 */
708 int err_most = (target >> 8) + (target >> 10);
709 found = false;
710
711 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
712 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
713 LVDS_CLKB_POWER_UP)
714 clock.p2 = limit->p2.p2_fast;
715 else
716 clock.p2 = limit->p2.p2_slow;
717 } else {
718 if (target < limit->p2.dot_limit)
719 clock.p2 = limit->p2.p2_slow;
720 else
721 clock.p2 = limit->p2.p2_fast;
722 }
723
724 memset(best_clock, 0, sizeof(*best_clock));
725 max_n = limit->n.max;
726 /* based on hardware requriment prefer smaller n to precision */
727 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
728 /* based on hardware requirment prefere larger m1,m2, p1 */
729 for (clock.m1 = limit->m1.max;
730 clock.m1 >= limit->m1.min; clock.m1--) {
731 for (clock.m2 = limit->m2.max;
732 clock.m2 >= limit->m2.min; clock.m2--) {
733 for (clock.p1 = limit->p1.max;
734 clock.p1 >= limit->p1.min; clock.p1--) {
735 int this_err;
736
737 intel_clock(dev, refclk, &clock);
738 if (!intel_PLL_is_valid(crtc, &clock))
739 continue;
740 this_err = abs(clock.dot - target) ;
741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
751 return found;
752 }
753
754 static bool
755 intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
756 int target, int refclk, intel_clock_t *best_clock)
757 {
758 struct drm_device *dev = crtc->dev;
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 intel_clock_t clock;
761 int max_n;
762 bool found;
763 int err_most = 47;
764 found = false;
765
766 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
767 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
768 LVDS_CLKB_POWER_UP)
769 clock.p2 = limit->p2.p2_fast;
770 else
771 clock.p2 = limit->p2.p2_slow;
772 } else {
773 if (target < limit->p2.dot_limit)
774 clock.p2 = limit->p2.p2_slow;
775 else
776 clock.p2 = limit->p2.p2_fast;
777 }
778
779 memset(best_clock, 0, sizeof(*best_clock));
780 max_n = limit->n.max;
781 /* based on hardware requriment prefer smaller n to precision */
782 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
783 /* based on hardware requirment prefere larger m1,m2, p1 */
784 for (clock.m1 = limit->m1.max;
785 clock.m1 >= limit->m1.min; clock.m1--) {
786 for (clock.m2 = limit->m2.max;
787 clock.m2 >= limit->m2.min; clock.m2--) {
788 for (clock.p1 = limit->p1.max;
789 clock.p1 >= limit->p1.min; clock.p1--) {
790 int this_err;
791
792 intel_clock(dev, refclk, &clock);
793 if (!intel_PLL_is_valid(crtc, &clock))
794 continue;
795 this_err = abs((10000 - (target*10000/clock.dot)));
796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 /* found on first matching */
802 goto out;
803 }
804 }
805 }
806 }
807 }
808 out:
809 return found;
810 }
811
812 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
813 static bool
814 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
815 int target, int refclk, intel_clock_t *best_clock)
816 {
817 intel_clock_t clock;
818 if (target < 200000) {
819 clock.p1 = 2;
820 clock.p2 = 10;
821 clock.n = 2;
822 clock.m1 = 23;
823 clock.m2 = 8;
824 } else {
825 clock.p1 = 1;
826 clock.p2 = 10;
827 clock.n = 1;
828 clock.m1 = 14;
829 clock.m2 = 2;
830 }
831 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
832 clock.p = (clock.p1 * clock.p2);
833 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
834 memcpy(best_clock, &clock, sizeof(intel_clock_t));
835 return true;
836 }
837
838 void
839 intel_wait_for_vblank(struct drm_device *dev)
840 {
841 /* Wait for 20ms, i.e. one cycle at 50hz. */
842 mdelay(20);
843 }
844
845 static int
846 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
847 struct drm_framebuffer *old_fb)
848 {
849 struct drm_device *dev = crtc->dev;
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 struct drm_i915_master_private *master_priv;
852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
853 struct intel_framebuffer *intel_fb;
854 struct drm_i915_gem_object *obj_priv;
855 struct drm_gem_object *obj;
856 int pipe = intel_crtc->pipe;
857 unsigned long Start, Offset;
858 int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
859 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
860 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
861 int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
862 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
863 u32 dspcntr, alignment;
864 int ret;
865
866 /* no fb bound */
867 if (!crtc->fb) {
868 DRM_DEBUG("No FB bound\n");
869 return 0;
870 }
871
872 switch (pipe) {
873 case 0:
874 case 1:
875 break;
876 default:
877 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
878 return -EINVAL;
879 }
880
881 intel_fb = to_intel_framebuffer(crtc->fb);
882 obj = intel_fb->obj;
883 obj_priv = obj->driver_private;
884
885 switch (obj_priv->tiling_mode) {
886 case I915_TILING_NONE:
887 alignment = 64 * 1024;
888 break;
889 case I915_TILING_X:
890 /* pin() will align the object as required by fence */
891 alignment = 0;
892 break;
893 case I915_TILING_Y:
894 /* FIXME: Is this true? */
895 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
896 return -EINVAL;
897 default:
898 BUG();
899 }
900
901 mutex_lock(&dev->struct_mutex);
902 ret = i915_gem_object_pin(obj, alignment);
903 if (ret != 0) {
904 mutex_unlock(&dev->struct_mutex);
905 return ret;
906 }
907
908 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
909 if (ret != 0) {
910 i915_gem_object_unpin(obj);
911 mutex_unlock(&dev->struct_mutex);
912 return ret;
913 }
914
915 /* Pre-i965 needs to install a fence for tiled scan-out */
916 if (!IS_I965G(dev) &&
917 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
918 obj_priv->tiling_mode != I915_TILING_NONE) {
919 ret = i915_gem_object_get_fence_reg(obj);
920 if (ret != 0) {
921 i915_gem_object_unpin(obj);
922 mutex_unlock(&dev->struct_mutex);
923 return ret;
924 }
925 }
926
927 dspcntr = I915_READ(dspcntr_reg);
928 /* Mask out pixel format bits in case we change it */
929 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
930 switch (crtc->fb->bits_per_pixel) {
931 case 8:
932 dspcntr |= DISPPLANE_8BPP;
933 break;
934 case 16:
935 if (crtc->fb->depth == 15)
936 dspcntr |= DISPPLANE_15_16BPP;
937 else
938 dspcntr |= DISPPLANE_16BPP;
939 break;
940 case 24:
941 case 32:
942 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
943 break;
944 default:
945 DRM_ERROR("Unknown color depth\n");
946 i915_gem_object_unpin(obj);
947 mutex_unlock(&dev->struct_mutex);
948 return -EINVAL;
949 }
950 if (IS_I965G(dev)) {
951 if (obj_priv->tiling_mode != I915_TILING_NONE)
952 dspcntr |= DISPPLANE_TILED;
953 else
954 dspcntr &= ~DISPPLANE_TILED;
955 }
956
957 I915_WRITE(dspcntr_reg, dspcntr);
958
959 Start = obj_priv->gtt_offset;
960 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
961
962 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
963 I915_WRITE(dspstride, crtc->fb->pitch);
964 if (IS_I965G(dev)) {
965 I915_WRITE(dspbase, Offset);
966 I915_READ(dspbase);
967 I915_WRITE(dspsurf, Start);
968 I915_READ(dspsurf);
969 I915_WRITE(dsptileoff, (y << 16) | x);
970 } else {
971 I915_WRITE(dspbase, Start + Offset);
972 I915_READ(dspbase);
973 }
974
975 intel_wait_for_vblank(dev);
976
977 if (old_fb) {
978 intel_fb = to_intel_framebuffer(old_fb);
979 i915_gem_object_unpin(intel_fb->obj);
980 }
981 mutex_unlock(&dev->struct_mutex);
982
983 if (!dev->primary->master)
984 return 0;
985
986 master_priv = dev->primary->master->driver_priv;
987 if (!master_priv->sarea_priv)
988 return 0;
989
990 if (pipe) {
991 master_priv->sarea_priv->pipeB_x = x;
992 master_priv->sarea_priv->pipeB_y = y;
993 } else {
994 master_priv->sarea_priv->pipeA_x = x;
995 master_priv->sarea_priv->pipeA_y = y;
996 }
997
998 return 0;
999 }
1000
1001 static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1002 {
1003 struct drm_device *dev = crtc->dev;
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1006 int pipe = intel_crtc->pipe;
1007 int plane = intel_crtc->plane;
1008 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1009 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1010 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1011 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1012 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1013 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1014 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1015 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1016 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1017 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1018 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1019 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1020 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1021 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1022 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1023 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1024 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1025 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1026 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1027 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1028 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1029 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1030 u32 temp;
1031 int tries = 5, j;
1032
1033 /* XXX: When our outputs are all unaware of DPMS modes other than off
1034 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1035 */
1036 switch (mode) {
1037 case DRM_MODE_DPMS_ON:
1038 case DRM_MODE_DPMS_STANDBY:
1039 case DRM_MODE_DPMS_SUSPEND:
1040 DRM_DEBUG("crtc %d dpms on\n", pipe);
1041 /* enable PCH DPLL */
1042 temp = I915_READ(pch_dpll_reg);
1043 if ((temp & DPLL_VCO_ENABLE) == 0) {
1044 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1045 I915_READ(pch_dpll_reg);
1046 }
1047
1048 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1049 temp = I915_READ(fdi_rx_reg);
1050 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1051 FDI_SEL_PCDCLK |
1052 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1053 I915_READ(fdi_rx_reg);
1054 udelay(200);
1055
1056 /* Enable CPU FDI TX PLL, always on for IGDNG */
1057 temp = I915_READ(fdi_tx_reg);
1058 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1059 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1060 I915_READ(fdi_tx_reg);
1061 udelay(100);
1062 }
1063
1064 /* Enable CPU pipe */
1065 temp = I915_READ(pipeconf_reg);
1066 if ((temp & PIPEACONF_ENABLE) == 0) {
1067 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1068 I915_READ(pipeconf_reg);
1069 udelay(100);
1070 }
1071
1072 /* configure and enable CPU plane */
1073 temp = I915_READ(dspcntr_reg);
1074 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1075 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1076 /* Flush the plane changes */
1077 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1078 }
1079
1080 /* enable CPU FDI TX and PCH FDI RX */
1081 temp = I915_READ(fdi_tx_reg);
1082 temp |= FDI_TX_ENABLE;
1083 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1084 temp &= ~FDI_LINK_TRAIN_NONE;
1085 temp |= FDI_LINK_TRAIN_PATTERN_1;
1086 I915_WRITE(fdi_tx_reg, temp);
1087 I915_READ(fdi_tx_reg);
1088
1089 temp = I915_READ(fdi_rx_reg);
1090 temp &= ~FDI_LINK_TRAIN_NONE;
1091 temp |= FDI_LINK_TRAIN_PATTERN_1;
1092 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1093 I915_READ(fdi_rx_reg);
1094
1095 udelay(150);
1096
1097 /* Train FDI. */
1098 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1099 for train result */
1100 temp = I915_READ(fdi_rx_imr_reg);
1101 temp &= ~FDI_RX_SYMBOL_LOCK;
1102 temp &= ~FDI_RX_BIT_LOCK;
1103 I915_WRITE(fdi_rx_imr_reg, temp);
1104 I915_READ(fdi_rx_imr_reg);
1105 udelay(150);
1106
1107 temp = I915_READ(fdi_rx_iir_reg);
1108 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1109
1110 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1111 for (j = 0; j < tries; j++) {
1112 temp = I915_READ(fdi_rx_iir_reg);
1113 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1114 if (temp & FDI_RX_BIT_LOCK)
1115 break;
1116 udelay(200);
1117 }
1118 if (j != tries)
1119 I915_WRITE(fdi_rx_iir_reg,
1120 temp | FDI_RX_BIT_LOCK);
1121 else
1122 DRM_DEBUG("train 1 fail\n");
1123 } else {
1124 I915_WRITE(fdi_rx_iir_reg,
1125 temp | FDI_RX_BIT_LOCK);
1126 DRM_DEBUG("train 1 ok 2!\n");
1127 }
1128 temp = I915_READ(fdi_tx_reg);
1129 temp &= ~FDI_LINK_TRAIN_NONE;
1130 temp |= FDI_LINK_TRAIN_PATTERN_2;
1131 I915_WRITE(fdi_tx_reg, temp);
1132
1133 temp = I915_READ(fdi_rx_reg);
1134 temp &= ~FDI_LINK_TRAIN_NONE;
1135 temp |= FDI_LINK_TRAIN_PATTERN_2;
1136 I915_WRITE(fdi_rx_reg, temp);
1137
1138 udelay(150);
1139
1140 temp = I915_READ(fdi_rx_iir_reg);
1141 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1142
1143 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1144 for (j = 0; j < tries; j++) {
1145 temp = I915_READ(fdi_rx_iir_reg);
1146 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1147 if (temp & FDI_RX_SYMBOL_LOCK)
1148 break;
1149 udelay(200);
1150 }
1151 if (j != tries) {
1152 I915_WRITE(fdi_rx_iir_reg,
1153 temp | FDI_RX_SYMBOL_LOCK);
1154 DRM_DEBUG("train 2 ok 1!\n");
1155 } else
1156 DRM_DEBUG("train 2 fail\n");
1157 } else {
1158 I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1159 DRM_DEBUG("train 2 ok 2!\n");
1160 }
1161 DRM_DEBUG("train done\n");
1162
1163 /* set transcoder timing */
1164 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1165 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1166 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1167
1168 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1169 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1170 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1171
1172 /* enable PCH transcoder */
1173 temp = I915_READ(transconf_reg);
1174 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1175 I915_READ(transconf_reg);
1176
1177 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1178 ;
1179
1180 /* enable normal */
1181
1182 temp = I915_READ(fdi_tx_reg);
1183 temp &= ~FDI_LINK_TRAIN_NONE;
1184 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1185 FDI_TX_ENHANCE_FRAME_ENABLE);
1186 I915_READ(fdi_tx_reg);
1187
1188 temp = I915_READ(fdi_rx_reg);
1189 temp &= ~FDI_LINK_TRAIN_NONE;
1190 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1191 FDI_RX_ENHANCE_FRAME_ENABLE);
1192 I915_READ(fdi_rx_reg);
1193
1194 /* wait one idle pattern time */
1195 udelay(100);
1196
1197 intel_crtc_load_lut(crtc);
1198
1199 break;
1200 case DRM_MODE_DPMS_OFF:
1201 DRM_DEBUG("crtc %d dpms off\n", pipe);
1202
1203 /* Disable the VGA plane that we never use */
1204 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1205
1206 /* Disable display plane */
1207 temp = I915_READ(dspcntr_reg);
1208 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1209 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1210 /* Flush the plane changes */
1211 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1212 I915_READ(dspbase_reg);
1213 }
1214
1215 /* disable cpu pipe, disable after all planes disabled */
1216 temp = I915_READ(pipeconf_reg);
1217 if ((temp & PIPEACONF_ENABLE) != 0) {
1218 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1219 I915_READ(pipeconf_reg);
1220 /* wait for cpu pipe off, pipe state */
1221 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1222 ;
1223 } else
1224 DRM_DEBUG("crtc %d is disabled\n", pipe);
1225
1226 /* IGDNG-A : disable cpu panel fitter ? */
1227 temp = I915_READ(pf_ctl_reg);
1228 if ((temp & PF_ENABLE) != 0) {
1229 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1230 I915_READ(pf_ctl_reg);
1231 }
1232
1233 /* disable CPU FDI tx and PCH FDI rx */
1234 temp = I915_READ(fdi_tx_reg);
1235 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1236 I915_READ(fdi_tx_reg);
1237
1238 temp = I915_READ(fdi_rx_reg);
1239 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1240 I915_READ(fdi_rx_reg);
1241
1242 /* still set train pattern 1 */
1243 temp = I915_READ(fdi_tx_reg);
1244 temp &= ~FDI_LINK_TRAIN_NONE;
1245 temp |= FDI_LINK_TRAIN_PATTERN_1;
1246 I915_WRITE(fdi_tx_reg, temp);
1247
1248 temp = I915_READ(fdi_rx_reg);
1249 temp &= ~FDI_LINK_TRAIN_NONE;
1250 temp |= FDI_LINK_TRAIN_PATTERN_1;
1251 I915_WRITE(fdi_rx_reg, temp);
1252
1253 /* disable PCH transcoder */
1254 temp = I915_READ(transconf_reg);
1255 if ((temp & TRANS_ENABLE) != 0) {
1256 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1257 I915_READ(transconf_reg);
1258 /* wait for PCH transcoder off, transcoder state */
1259 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1260 ;
1261 }
1262
1263 /* disable PCH DPLL */
1264 temp = I915_READ(pch_dpll_reg);
1265 if ((temp & DPLL_VCO_ENABLE) != 0) {
1266 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1267 I915_READ(pch_dpll_reg);
1268 }
1269
1270 temp = I915_READ(fdi_rx_reg);
1271 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1272 temp &= ~FDI_SEL_PCDCLK;
1273 temp &= ~FDI_RX_PLL_ENABLE;
1274 I915_WRITE(fdi_rx_reg, temp);
1275 I915_READ(fdi_rx_reg);
1276 }
1277
1278 /* Wait for the clocks to turn off. */
1279 udelay(150);
1280 break;
1281 }
1282 }
1283
1284 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1285 {
1286 struct drm_device *dev = crtc->dev;
1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1289 int pipe = intel_crtc->pipe;
1290 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1291 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
1292 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
1293 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1294 u32 temp;
1295
1296 /* XXX: When our outputs are all unaware of DPMS modes other than off
1297 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1298 */
1299 switch (mode) {
1300 case DRM_MODE_DPMS_ON:
1301 case DRM_MODE_DPMS_STANDBY:
1302 case DRM_MODE_DPMS_SUSPEND:
1303 /* Enable the DPLL */
1304 temp = I915_READ(dpll_reg);
1305 if ((temp & DPLL_VCO_ENABLE) == 0) {
1306 I915_WRITE(dpll_reg, temp);
1307 I915_READ(dpll_reg);
1308 /* Wait for the clocks to stabilize. */
1309 udelay(150);
1310 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1311 I915_READ(dpll_reg);
1312 /* Wait for the clocks to stabilize. */
1313 udelay(150);
1314 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1315 I915_READ(dpll_reg);
1316 /* Wait for the clocks to stabilize. */
1317 udelay(150);
1318 }
1319
1320 /* Enable the pipe */
1321 temp = I915_READ(pipeconf_reg);
1322 if ((temp & PIPEACONF_ENABLE) == 0)
1323 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1324
1325 /* Enable the plane */
1326 temp = I915_READ(dspcntr_reg);
1327 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1328 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1329 /* Flush the plane changes */
1330 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1331 }
1332
1333 intel_crtc_load_lut(crtc);
1334
1335 /* Give the overlay scaler a chance to enable if it's on this pipe */
1336 //intel_crtc_dpms_video(crtc, true); TODO
1337 intel_update_watermarks(dev);
1338 break;
1339 case DRM_MODE_DPMS_OFF:
1340 intel_update_watermarks(dev);
1341 /* Give the overlay scaler a chance to disable if it's on this pipe */
1342 //intel_crtc_dpms_video(crtc, FALSE); TODO
1343
1344 /* Disable the VGA plane that we never use */
1345 I915_WRITE(VGACNTRL, VGA_DISP_DISABLE);
1346
1347 /* Disable display plane */
1348 temp = I915_READ(dspcntr_reg);
1349 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1350 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1351 /* Flush the plane changes */
1352 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1353 I915_READ(dspbase_reg);
1354 }
1355
1356 if (!IS_I9XX(dev)) {
1357 /* Wait for vblank for the disable to take effect */
1358 intel_wait_for_vblank(dev);
1359 }
1360
1361 /* Next, disable display pipes */
1362 temp = I915_READ(pipeconf_reg);
1363 if ((temp & PIPEACONF_ENABLE) != 0) {
1364 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1365 I915_READ(pipeconf_reg);
1366 }
1367
1368 /* Wait for vblank for the disable to take effect. */
1369 intel_wait_for_vblank(dev);
1370
1371 temp = I915_READ(dpll_reg);
1372 if ((temp & DPLL_VCO_ENABLE) != 0) {
1373 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1374 I915_READ(dpll_reg);
1375 }
1376
1377 /* Wait for the clocks to turn off. */
1378 udelay(150);
1379 break;
1380 }
1381 }
1382
1383 /**
1384 * Sets the power management mode of the pipe and plane.
1385 *
1386 * This code should probably grow support for turning the cursor off and back
1387 * on appropriately at the same time as we're turning the pipe off/on.
1388 */
1389 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1390 {
1391 struct drm_device *dev = crtc->dev;
1392 struct drm_i915_master_private *master_priv;
1393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1394 int pipe = intel_crtc->pipe;
1395 bool enabled;
1396
1397 if (IS_IGDNG(dev))
1398 igdng_crtc_dpms(crtc, mode);
1399 else
1400 i9xx_crtc_dpms(crtc, mode);
1401
1402 if (!dev->primary->master)
1403 return;
1404
1405 master_priv = dev->primary->master->driver_priv;
1406 if (!master_priv->sarea_priv)
1407 return;
1408
1409 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1410
1411 switch (pipe) {
1412 case 0:
1413 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1414 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1415 break;
1416 case 1:
1417 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1418 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1419 break;
1420 default:
1421 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1422 break;
1423 }
1424
1425 intel_crtc->dpms_mode = mode;
1426 }
1427
1428 static void intel_crtc_prepare (struct drm_crtc *crtc)
1429 {
1430 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1431 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1432 }
1433
1434 static void intel_crtc_commit (struct drm_crtc *crtc)
1435 {
1436 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1437 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1438 }
1439
1440 void intel_encoder_prepare (struct drm_encoder *encoder)
1441 {
1442 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1443 /* lvds has its own version of prepare see intel_lvds_prepare */
1444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1445 }
1446
1447 void intel_encoder_commit (struct drm_encoder *encoder)
1448 {
1449 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1450 /* lvds has its own version of commit see intel_lvds_commit */
1451 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1452 }
1453
1454 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1455 struct drm_display_mode *mode,
1456 struct drm_display_mode *adjusted_mode)
1457 {
1458 struct drm_device *dev = crtc->dev;
1459 if (IS_IGDNG(dev)) {
1460 /* FDI link clock is fixed at 2.7G */
1461 if (mode->clock * 3 > 27000 * 4)
1462 return MODE_CLOCK_HIGH;
1463 }
1464 return true;
1465 }
1466
1467
1468 /** Returns the core display clock speed for i830 - i945 */
1469 static int intel_get_core_clock_speed(struct drm_device *dev)
1470 {
1471
1472 /* Core clock values taken from the published datasheets.
1473 * The 830 may go up to 166 Mhz, which we should check.
1474 */
1475 if (IS_I945G(dev))
1476 return 400000;
1477 else if (IS_I915G(dev))
1478 return 333000;
1479 else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev))
1480 return 200000;
1481 else if (IS_I915GM(dev)) {
1482 u16 gcfgc = 0;
1483
1484 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
1485
1486 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
1487 return 133000;
1488 else {
1489 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
1490 case GC_DISPLAY_CLOCK_333_MHZ:
1491 return 333000;
1492 default:
1493 case GC_DISPLAY_CLOCK_190_200_MHZ:
1494 return 190000;
1495 }
1496 }
1497 } else if (IS_I865G(dev))
1498 return 266000;
1499 else if (IS_I855(dev)) {
1500 u16 hpllcc = 0;
1501 /* Assume that the hardware is in the high speed state. This
1502 * should be the default.
1503 */
1504 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
1505 case GC_CLOCK_133_200:
1506 case GC_CLOCK_100_200:
1507 return 200000;
1508 case GC_CLOCK_166_250:
1509 return 250000;
1510 case GC_CLOCK_100_133:
1511 return 133000;
1512 }
1513 } else /* 852, 830 */
1514 return 133000;
1515
1516 return 0; /* Silence gcc warning */
1517 }
1518
1519 /**
1520 * Return the pipe currently connected to the panel fitter,
1521 * or -1 if the panel fitter is not present or not in use
1522 */
1523 static int intel_panel_fitter_pipe (struct drm_device *dev)
1524 {
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526 u32 pfit_control;
1527
1528 /* i830 doesn't have a panel fitter */
1529 if (IS_I830(dev))
1530 return -1;
1531
1532 pfit_control = I915_READ(PFIT_CONTROL);
1533
1534 /* See if the panel fitter is in use */
1535 if ((pfit_control & PFIT_ENABLE) == 0)
1536 return -1;
1537
1538 /* 965 can place panel fitter on either pipe */
1539 if (IS_I965G(dev))
1540 return (pfit_control >> 29) & 0x3;
1541
1542 /* older chips can only use pipe 1 */
1543 return 1;
1544 }
1545
1546 struct fdi_m_n {
1547 u32 tu;
1548 u32 gmch_m;
1549 u32 gmch_n;
1550 u32 link_m;
1551 u32 link_n;
1552 };
1553
1554 static void
1555 fdi_reduce_ratio(u32 *num, u32 *den)
1556 {
1557 while (*num > 0xffffff || *den > 0xffffff) {
1558 *num >>= 1;
1559 *den >>= 1;
1560 }
1561 }
1562
1563 #define DATA_N 0x800000
1564 #define LINK_N 0x80000
1565
1566 static void
1567 igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1568 int pixel_clock, int link_clock,
1569 struct fdi_m_n *m_n)
1570 {
1571 u64 temp;
1572
1573 m_n->tu = 64; /* default size */
1574
1575 temp = (u64) DATA_N * pixel_clock;
1576 temp = div_u64(temp, link_clock);
1577 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes);
1578 m_n->gmch_n = DATA_N;
1579 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1580
1581 temp = (u64) LINK_N * pixel_clock;
1582 m_n->link_m = div_u64(temp, link_clock);
1583 m_n->link_n = LINK_N;
1584 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1585 }
1586
1587
1588 struct intel_watermark_params {
1589 unsigned long fifo_size;
1590 unsigned long max_wm;
1591 unsigned long default_wm;
1592 unsigned long guard_size;
1593 unsigned long cacheline_size;
1594 };
1595
1596 /* IGD has different values for various configs */
1597 static struct intel_watermark_params igd_display_wm = {
1598 IGD_DISPLAY_FIFO,
1599 IGD_MAX_WM,
1600 IGD_DFT_WM,
1601 IGD_GUARD_WM,
1602 IGD_FIFO_LINE_SIZE
1603 };
1604 static struct intel_watermark_params igd_display_hplloff_wm = {
1605 IGD_DISPLAY_FIFO,
1606 IGD_MAX_WM,
1607 IGD_DFT_HPLLOFF_WM,
1608 IGD_GUARD_WM,
1609 IGD_FIFO_LINE_SIZE
1610 };
1611 static struct intel_watermark_params igd_cursor_wm = {
1612 IGD_CURSOR_FIFO,
1613 IGD_CURSOR_MAX_WM,
1614 IGD_CURSOR_DFT_WM,
1615 IGD_CURSOR_GUARD_WM,
1616 IGD_FIFO_LINE_SIZE,
1617 };
1618 static struct intel_watermark_params igd_cursor_hplloff_wm = {
1619 IGD_CURSOR_FIFO,
1620 IGD_CURSOR_MAX_WM,
1621 IGD_CURSOR_DFT_WM,
1622 IGD_CURSOR_GUARD_WM,
1623 IGD_FIFO_LINE_SIZE
1624 };
1625 static struct intel_watermark_params i945_wm_info = {
1626 I945_FIFO_SIZE,
1627 I915_MAX_WM,
1628 1,
1629 2,
1630 I915_FIFO_LINE_SIZE
1631 };
1632 static struct intel_watermark_params i915_wm_info = {
1633 I915_FIFO_SIZE,
1634 I915_MAX_WM,
1635 1,
1636 2,
1637 I915_FIFO_LINE_SIZE
1638 };
1639 static struct intel_watermark_params i855_wm_info = {
1640 I855GM_FIFO_SIZE,
1641 I915_MAX_WM,
1642 1,
1643 2,
1644 I830_FIFO_LINE_SIZE
1645 };
1646 static struct intel_watermark_params i830_wm_info = {
1647 I830_FIFO_SIZE,
1648 I915_MAX_WM,
1649 1,
1650 2,
1651 I830_FIFO_LINE_SIZE
1652 };
1653
1654 /**
1655 * intel_calculate_wm - calculate watermark level
1656 * @clock_in_khz: pixel clock
1657 * @wm: chip FIFO params
1658 * @pixel_size: display pixel size
1659 * @latency_ns: memory latency for the platform
1660 *
1661 * Calculate the watermark level (the level at which the display plane will
1662 * start fetching from memory again). Each chip has a different display
1663 * FIFO size and allocation, so the caller needs to figure that out and pass
1664 * in the correct intel_watermark_params structure.
1665 *
1666 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1667 * on the pixel size. When it reaches the watermark level, it'll start
1668 * fetching FIFO line sized based chunks from memory until the FIFO fills
1669 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1670 * will occur, and a display engine hang could result.
1671 */
1672 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1673 struct intel_watermark_params *wm,
1674 int pixel_size,
1675 unsigned long latency_ns)
1676 {
1677 long entries_required, wm_size;
1678
1679 entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
1680 entries_required /= wm->cacheline_size;
1681
1682 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);
1683
1684 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
1685
1686 DRM_DEBUG("FIFO watermark level: %d\n", wm_size);
1687
1688 /* Don't promote wm_size to unsigned... */
1689 if (wm_size > (long)wm->max_wm)
1690 wm_size = wm->max_wm;
1691 if (wm_size <= 0)
1692 wm_size = wm->default_wm;
1693 return wm_size;
1694 }
1695
1696 struct cxsr_latency {
1697 int is_desktop;
1698 unsigned long fsb_freq;
1699 unsigned long mem_freq;
1700 unsigned long display_sr;
1701 unsigned long display_hpll_disable;
1702 unsigned long cursor_sr;
1703 unsigned long cursor_hpll_disable;
1704 };
1705
1706 static struct cxsr_latency cxsr_latency_table[] = {
1707 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1708 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1709 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1710
1711 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1712 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1713 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1714
1715 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1716 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1717 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1718
1719 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1720 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1721 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1722
1723 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1724 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1725 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1726
1727 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1728 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1729 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1730 };
1731
1732 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
1733 int mem)
1734 {
1735 int i;
1736 struct cxsr_latency *latency;
1737
1738 if (fsb == 0 || mem == 0)
1739 return NULL;
1740
1741 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
1742 latency = &cxsr_latency_table[i];
1743 if (is_desktop == latency->is_desktop &&
1744 fsb == latency->fsb_freq && mem == latency->mem_freq)
1745 break;
1746 }
1747 if (i >= ARRAY_SIZE(cxsr_latency_table)) {
1748 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1749 return NULL;
1750 }
1751 return latency;
1752 }
1753
1754 static void igd_disable_cxsr(struct drm_device *dev)
1755 {
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 u32 reg;
1758
1759 /* deactivate cxsr */
1760 reg = I915_READ(DSPFW3);
1761 reg &= ~(IGD_SELF_REFRESH_EN);
1762 I915_WRITE(DSPFW3, reg);
1763 DRM_INFO("Big FIFO is disabled\n");
1764 }
1765
1766 static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock,
1767 int pixel_size)
1768 {
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 u32 reg;
1771 unsigned long wm;
1772 struct cxsr_latency *latency;
1773
1774 latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq,
1775 dev_priv->mem_freq);
1776 if (!latency) {
1777 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1778 igd_disable_cxsr(dev);
1779 return;
1780 }
1781
1782 /* Display SR */
1783 wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size,
1784 latency->display_sr);
1785 reg = I915_READ(DSPFW1);
1786 reg &= 0x7fffff;
1787 reg |= wm << 23;
1788 I915_WRITE(DSPFW1, reg);
1789 DRM_DEBUG("DSPFW1 register is %x\n", reg);
1790
1791 /* cursor SR */
1792 wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size,
1793 latency->cursor_sr);
1794 reg = I915_READ(DSPFW3);
1795 reg &= ~(0x3f << 24);
1796 reg |= (wm & 0x3f) << 24;
1797 I915_WRITE(DSPFW3, reg);
1798
1799 /* Display HPLL off SR */
1800 wm = intel_calculate_wm(clock, &igd_display_hplloff_wm,
1801 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
1802 reg = I915_READ(DSPFW3);
1803 reg &= 0xfffffe00;
1804 reg |= wm & 0x1ff;
1805 I915_WRITE(DSPFW3, reg);
1806
1807 /* cursor HPLL off SR */
1808 wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size,
1809 latency->cursor_hpll_disable);
1810 reg = I915_READ(DSPFW3);
1811 reg &= ~(0x3f << 16);
1812 reg |= (wm & 0x3f) << 16;
1813 I915_WRITE(DSPFW3, reg);
1814 DRM_DEBUG("DSPFW3 register is %x\n", reg);
1815
1816 /* activate cxsr */
1817 reg = I915_READ(DSPFW3);
1818 reg |= IGD_SELF_REFRESH_EN;
1819 I915_WRITE(DSPFW3, reg);
1820
1821 DRM_INFO("Big FIFO is enabled\n");
1822
1823 return;
1824 }
1825
1826 const static int latency_ns = 3000; /* default for non-igd platforms */
1827
1828 static int intel_get_fifo_size(struct drm_device *dev, int plane)
1829 {
1830 struct drm_i915_private *dev_priv = dev->dev_private;
1831 uint32_t dsparb = I915_READ(DSPARB);
1832 int size;
1833
1834 if (IS_I9XX(dev)) {
1835 if (plane == 0)
1836 size = dsparb & 0x7f;
1837 else
1838 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
1839 (dsparb & 0x7f);
1840 } else if (IS_I85X(dev)) {
1841 if (plane == 0)
1842 size = dsparb & 0x1ff;
1843 else
1844 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
1845 (dsparb & 0x1ff);
1846 size >>= 1; /* Convert to cachelines */
1847 } else {
1848 size = dsparb & 0x7f;
1849 size >>= 1; /* Convert to cachelines */
1850 }
1851
1852 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A",
1853 size);
1854
1855 return size;
1856 }
1857
1858 static void i965_update_wm(struct drm_device *dev)
1859 {
1860 struct drm_i915_private *dev_priv = dev->dev_private;
1861
1862 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
1863
1864 /* 965 has limitations... */
1865 I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
1866 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1867 }
1868
1869 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1870 int planeb_clock, int sr_hdisplay, int pixel_size)
1871 {
1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 uint32_t fwater_lo;
1874 uint32_t fwater_hi;
1875 int total_size, cacheline_size, cwm, srwm = 1;
1876 int planea_wm, planeb_wm;
1877 struct intel_watermark_params planea_params, planeb_params;
1878 unsigned long line_time_us;
1879 int sr_clock, sr_entries = 0;
1880
1881 /* Create copies of the base settings for each pipe */
1882 if (IS_I965GM(dev) || IS_I945GM(dev))
1883 planea_params = planeb_params = i945_wm_info;
1884 else if (IS_I9XX(dev))
1885 planea_params = planeb_params = i915_wm_info;
1886 else
1887 planea_params = planeb_params = i855_wm_info;
1888
1889 /* Grab a couple of global values before we overwrite them */
1890 total_size = planea_params.fifo_size;
1891 cacheline_size = planea_params.cacheline_size;
1892
1893 /* Update per-plane FIFO sizes */
1894 planea_params.fifo_size = intel_get_fifo_size(dev, 0);
1895 planeb_params.fifo_size = intel_get_fifo_size(dev, 1);
1896
1897 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
1898 pixel_size, latency_ns);
1899 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
1900 pixel_size, latency_ns);
1901 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1902
1903 /*
1904 * Overlay gets an aggressive default since video jitter is bad.
1905 */
1906 cwm = 2;
1907
1908 /* Calc sr entries for one plane configs */
1909 if (!planea_clock || !planeb_clock) {
1910 /* self-refresh has much higher latency */
1911 const static int sr_latency_ns = 6000;
1912
1913 sr_clock = planea_clock ? planea_clock : planeb_clock;
1914 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
1915
1916 /* Use ns/us then divide to preserve precision */
1917 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
1918 pixel_size * sr_hdisplay) / 1000;
1919 sr_entries = roundup(sr_entries / cacheline_size, 1);
1920 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
1921 srwm = total_size - sr_entries;
1922 if (srwm < 0)
1923 srwm = 1;
1924 }
1925
1926 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1927 planea_wm, planeb_wm, cwm, srwm);
1928
1929 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1930 fwater_hi = (cwm & 0x1f);
1931
1932 /* Set request length to 8 cachelines per fetch */
1933 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1934 fwater_hi = fwater_hi | (1 << 8);
1935
1936 I915_WRITE(FW_BLC, fwater_lo);
1937 I915_WRITE(FW_BLC2, fwater_hi);
1938 if (IS_I9XX(dev))
1939 I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
1940 }
1941
1942 static void i830_update_wm(struct drm_device *dev, int planea_clock,
1943 int pixel_size)
1944 {
1945 struct drm_i915_private *dev_priv = dev->dev_private;
1946 uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
1947 int planea_wm;
1948
1949 i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
1950
1951 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
1952 pixel_size, latency_ns);
1953 fwater_lo = fwater_lo | planea_wm;
1954
1955 I915_WRITE(FW_BLC, fwater_lo);
1956 }
1957
1958 /**
1959 * intel_update_watermarks - update FIFO watermark values based on current modes
1960 *
1961 * Calculate watermark values for the various WM regs based on current mode
1962 * and plane configuration.
1963 *
1964 * There are several cases to deal with here:
1965 * - normal (i.e. non-self-refresh)
1966 * - self-refresh (SR) mode
1967 * - lines are large relative to FIFO size (buffer can hold up to 2)
1968 * - lines are small relative to FIFO size (buffer can hold more than 2
1969 * lines), so need to account for TLB latency
1970 *
1971 * The normal calculation is:
1972 * watermark = dotclock * bytes per pixel * latency
1973 * where latency is platform & configuration dependent (we assume pessimal
1974 * values here).
1975 *
1976 * The SR calculation is:
1977 * watermark = (trunc(latency/line time)+1) * surface width *
1978 * bytes per pixel
1979 * where
1980 * line time = htotal / dotclock
1981 * and latency is assumed to be high, as above.
1982 *
1983 * The final value programmed to the register should always be rounded up,
1984 * and include an extra 2 entries to account for clock crossings.
1985 *
1986 * We don't use the sprite, so we can ignore that. And on Crestline we have
1987 * to set the non-SR watermarks to 8.
1988 */
1989 static void intel_update_watermarks(struct drm_device *dev)
1990 {
1991 struct drm_crtc *crtc;
1992 struct intel_crtc *intel_crtc;
1993 int sr_hdisplay = 0;
1994 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
1995 int enabled = 0, pixel_size = 0;
1996
1997 if (DSPARB_HWCONTROL(dev))
1998 return;
1999
2000 /* Get the clock config from both planes */
2001 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2002 intel_crtc = to_intel_crtc(crtc);
2003 if (crtc->enabled) {
2004 enabled++;
2005 if (intel_crtc->plane == 0) {
2006 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2007 intel_crtc->pipe, crtc->mode.clock);
2008 planea_clock = crtc->mode.clock;
2009 } else {
2010 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2011 intel_crtc->pipe, crtc->mode.clock);
2012 planeb_clock = crtc->mode.clock;
2013 }
2014 sr_hdisplay = crtc->mode.hdisplay;
2015 sr_clock = crtc->mode.clock;
2016 if (crtc->fb)
2017 pixel_size = crtc->fb->bits_per_pixel / 8;
2018 else
2019 pixel_size = 4; /* by default */
2020 }
2021 }
2022
2023 if (enabled <= 0)
2024 return;
2025
2026 /* Single plane configs can enable self refresh */
2027 if (enabled == 1 && IS_IGD(dev))
2028 igd_enable_cxsr(dev, sr_clock, pixel_size);
2029 else if (IS_IGD(dev))
2030 igd_disable_cxsr(dev);
2031
2032 if (IS_I965G(dev))
2033 i965_update_wm(dev);
2034 else if (IS_I9XX(dev) || IS_MOBILE(dev))
2035 i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay,
2036 pixel_size);
2037 else
2038 i830_update_wm(dev, planea_clock, pixel_size);
2039 }
2040
2041 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2042 struct drm_display_mode *mode,
2043 struct drm_display_mode *adjusted_mode,
2044 int x, int y,
2045 struct drm_framebuffer *old_fb)
2046 {
2047 struct drm_device *dev = crtc->dev;
2048 struct drm_i915_private *dev_priv = dev->dev_private;
2049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2050 int pipe = intel_crtc->pipe;
2051 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2052 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2053 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2054 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
2055 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2056 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2057 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2058 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2059 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2060 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2061 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2062 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
2063 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
2064 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2065 int refclk, num_outputs = 0;
2066 intel_clock_t clock;
2067 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
2068 bool ok, is_sdvo = false, is_dvo = false;
2069 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2070 struct drm_mode_config *mode_config = &dev->mode_config;
2071 struct drm_connector *connector;
2072 const intel_limit_t *limit;
2073 int ret;
2074 struct fdi_m_n m_n = {0};
2075 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2076 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2077 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2078 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2079 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2080 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2081 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2082 int lvds_reg = LVDS;
2083 u32 temp;
2084 int sdvo_pixel_multiply;
2085
2086 drm_vblank_pre_modeset(dev, pipe);
2087
2088 list_for_each_entry(connector, &mode_config->connector_list, head) {
2089 struct intel_output *intel_output = to_intel_output(connector);
2090
2091 if (!connector->encoder || connector->encoder->crtc != crtc)
2092 continue;
2093
2094 switch (intel_output->type) {
2095 case INTEL_OUTPUT_LVDS:
2096 is_lvds = true;
2097 break;
2098 case INTEL_OUTPUT_SDVO:
2099 case INTEL_OUTPUT_HDMI:
2100 is_sdvo = true;
2101 if (intel_output->needs_tv_clock)
2102 is_tv = true;
2103 break;
2104 case INTEL_OUTPUT_DVO:
2105 is_dvo = true;
2106 break;
2107 case INTEL_OUTPUT_TVOUT:
2108 is_tv = true;
2109 break;
2110 case INTEL_OUTPUT_ANALOG:
2111 is_crt = true;
2112 break;
2113 case INTEL_OUTPUT_DISPLAYPORT:
2114 is_dp = true;
2115 break;
2116 }
2117
2118 num_outputs++;
2119 }
2120
2121 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2122 refclk = dev_priv->lvds_ssc_freq * 1000;
2123 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
2124 } else if (IS_I9XX(dev)) {
2125 refclk = 96000;
2126 if (IS_IGDNG(dev))
2127 refclk = 120000; /* 120Mhz refclk */
2128 } else {
2129 refclk = 48000;
2130 }
2131
2132
2133 /*
2134 * Returns a set of divisors for the desired target clock with the given
2135 * refclk, or FALSE. The returned values represent the clock equation:
2136 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2137 */
2138 limit = intel_limit(crtc);
2139 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2140 if (!ok) {
2141 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2142 drm_vblank_post_modeset(dev, pipe);
2143 return -EINVAL;
2144 }
2145
2146 /* SDVO TV has fixed PLL values depend on its clock range,
2147 this mirrors vbios setting. */
2148 if (is_sdvo && is_tv) {
2149 if (adjusted_mode->clock >= 100000
2150 && adjusted_mode->clock < 140500) {
2151 clock.p1 = 2;
2152 clock.p2 = 10;
2153 clock.n = 3;
2154 clock.m1 = 16;
2155 clock.m2 = 8;
2156 } else if (adjusted_mode->clock >= 140500
2157 && adjusted_mode->clock <= 200000) {
2158 clock.p1 = 1;
2159 clock.p2 = 10;
2160 clock.n = 6;
2161 clock.m1 = 12;
2162 clock.m2 = 8;
2163 }
2164 }
2165
2166 /* FDI link */
2167 if (IS_IGDNG(dev))
2168 igdng_compute_m_n(3, 4, /* lane num 4 */
2169 adjusted_mode->clock,
2170 270000, /* lane clock */
2171 &m_n);
2172
2173 if (IS_IGD(dev))
2174 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2175 else
2176 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
2177
2178 if (!IS_IGDNG(dev))
2179 dpll = DPLL_VGA_MODE_DIS;
2180
2181 if (IS_I9XX(dev)) {
2182 if (is_lvds)
2183 dpll |= DPLLB_MODE_LVDS;
2184 else
2185 dpll |= DPLLB_MODE_DAC_SERIAL;
2186 if (is_sdvo) {
2187 dpll |= DPLL_DVO_HIGH_SPEED;
2188 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2189 if (IS_I945G(dev) || IS_I945GM(dev))
2190 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
2191 else if (IS_IGDNG(dev))
2192 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
2193 }
2194 if (is_dp)
2195 dpll |= DPLL_DVO_HIGH_SPEED;
2196
2197 /* compute bitmask from p1 value */
2198 if (IS_IGD(dev))
2199 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
2200 else {
2201 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2202 /* also FPA1 */
2203 if (IS_IGDNG(dev))
2204 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2205 }
2206 switch (clock.p2) {
2207 case 5:
2208 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
2209 break;
2210 case 7:
2211 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
2212 break;
2213 case 10:
2214 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
2215 break;
2216 case 14:
2217 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
2218 break;
2219 }
2220 if (IS_I965G(dev) && !IS_IGDNG(dev))
2221 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
2222 } else {
2223 if (is_lvds) {
2224 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2225 } else {
2226 if (clock.p1 == 2)
2227 dpll |= PLL_P1_DIVIDE_BY_TWO;
2228 else
2229 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
2230 if (clock.p2 == 4)
2231 dpll |= PLL_P2_DIVIDE_BY_4;
2232 }
2233 }
2234
2235 if (is_sdvo && is_tv)
2236 dpll |= PLL_REF_INPUT_TVCLKINBC;
2237 else if (is_tv)
2238 /* XXX: just matching BIOS for now */
2239 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2240 dpll |= 3;
2241 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
2242 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
2243 else
2244 dpll |= PLL_REF_INPUT_DREFCLK;
2245
2246 /* setup pipeconf */
2247 pipeconf = I915_READ(pipeconf_reg);
2248
2249 /* Set up the display plane register */
2250 dspcntr = DISPPLANE_GAMMA_ENABLE;
2251
2252 /* IGDNG's plane is forced to pipe, bit 24 is to
2253 enable color space conversion */
2254 if (!IS_IGDNG(dev)) {
2255 if (pipe == 0)
2256 dspcntr |= DISPPLANE_SEL_PIPE_A;
2257 else
2258 dspcntr |= DISPPLANE_SEL_PIPE_B;
2259 }
2260
2261 if (pipe == 0 && !IS_I965G(dev)) {
2262 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2263 * core speed.
2264 *
2265 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2266 * pipe == 0 check?
2267 */
2268 if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10)
2269 pipeconf |= PIPEACONF_DOUBLE_WIDE;
2270 else
2271 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
2272 }
2273
2274 dspcntr |= DISPLAY_PLANE_ENABLE;
2275 pipeconf |= PIPEACONF_ENABLE;
2276 dpll |= DPLL_VCO_ENABLE;
2277
2278
2279 /* Disable the panel fitter if it was on our pipe */
2280 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
2281 I915_WRITE(PFIT_CONTROL, 0);
2282
2283 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
2284 drm_mode_debug_printmodeline(mode);
2285
2286 /* assign to IGDNG registers */
2287 if (IS_IGDNG(dev)) {
2288 fp_reg = pch_fp_reg;
2289 dpll_reg = pch_dpll_reg;
2290 }
2291
2292 if (dpll & DPLL_VCO_ENABLE) {
2293 I915_WRITE(fp_reg, fp);
2294 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
2295 I915_READ(dpll_reg);
2296 udelay(150);
2297 }
2298
2299 if (IS_IGDNG(dev)) {
2300 /* enable PCH clock reference source */
2301 /* XXX need to change the setting for other outputs */
2302 u32 temp;
2303 temp = I915_READ(PCH_DREF_CONTROL);
2304 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2305 temp |= DREF_NONSPREAD_CK505_ENABLE;
2306 temp &= ~DREF_SSC_SOURCE_MASK;
2307 temp |= DREF_SSC_SOURCE_ENABLE;
2308 temp &= ~DREF_SSC1_ENABLE;
2309 /* if no eDP, disable source output to CPU */
2310 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2311 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
2312 I915_WRITE(PCH_DREF_CONTROL, temp);
2313 }
2314
2315 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2316 * This is an exception to the general rule that mode_set doesn't turn
2317 * things on.
2318 */
2319 if (is_lvds) {
2320 u32 lvds;
2321
2322 if (IS_IGDNG(dev))
2323 lvds_reg = PCH_LVDS;
2324
2325 lvds = I915_READ(lvds_reg);
2326 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
2327 /* Set the B0-B3 data pairs corresponding to whether we're going to
2328 * set the DPLLs for dual-channel mode or not.
2329 */
2330 if (clock.p2 == 7)
2331 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
2332 else
2333 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
2334
2335 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2336 * appropriately here, but we need to look more thoroughly into how
2337 * panels behave in the two modes.
2338 */
2339
2340 I915_WRITE(lvds_reg, lvds);
2341 I915_READ(lvds_reg);
2342 }
2343 if (is_dp)
2344 intel_dp_set_m_n(crtc, mode, adjusted_mode);
2345
2346 I915_WRITE(fp_reg, fp);
2347 I915_WRITE(dpll_reg, dpll);
2348 I915_READ(dpll_reg);
2349 /* Wait for the clocks to stabilize. */
2350 udelay(150);
2351
2352 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
2353 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
2354 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
2355 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
2356 } else {
2357 /* write it again -- the BIOS does, after all */
2358 I915_WRITE(dpll_reg, dpll);
2359 }
2360 I915_READ(dpll_reg);
2361 /* Wait for the clocks to stabilize. */
2362 udelay(150);
2363
2364 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
2365 ((adjusted_mode->crtc_htotal - 1) << 16));
2366 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
2367 ((adjusted_mode->crtc_hblank_end - 1) << 16));
2368 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
2369 ((adjusted_mode->crtc_hsync_end - 1) << 16));
2370 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
2371 ((adjusted_mode->crtc_vtotal - 1) << 16));
2372 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
2373 ((adjusted_mode->crtc_vblank_end - 1) << 16));
2374 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
2375 ((adjusted_mode->crtc_vsync_end - 1) << 16));
2376 /* pipesrc and dspsize control the size that is scaled from, which should
2377 * always be the user's requested size.
2378 */
2379 if (!IS_IGDNG(dev)) {
2380 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
2381 (mode->hdisplay - 1));
2382 I915_WRITE(dsppos_reg, 0);
2383 }
2384 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2385
2386 if (IS_IGDNG(dev)) {
2387 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
2388 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
2389 I915_WRITE(link_m1_reg, m_n.link_m);
2390 I915_WRITE(link_n1_reg, m_n.link_n);
2391
2392 /* enable FDI RX PLL too */
2393 temp = I915_READ(fdi_rx_reg);
2394 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
2395 udelay(200);
2396 }
2397
2398 I915_WRITE(pipeconf_reg, pipeconf);
2399 I915_READ(pipeconf_reg);
2400
2401 intel_wait_for_vblank(dev);
2402
2403 I915_WRITE(dspcntr_reg, dspcntr);
2404
2405 /* Flush the plane changes */
2406 ret = intel_pipe_set_base(crtc, x, y, old_fb);
2407
2408 intel_update_watermarks(dev);
2409
2410 drm_vblank_post_modeset(dev, pipe);
2411
2412 return ret;
2413 }
2414
2415 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2416 void intel_crtc_load_lut(struct drm_crtc *crtc)
2417 {
2418 struct drm_device *dev = crtc->dev;
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2421 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
2422 int i;
2423
2424 /* The clocks have to be on to load the palette. */
2425 if (!crtc->enabled)
2426 return;
2427
2428 /* use legacy palette for IGDNG */
2429 if (IS_IGDNG(dev))
2430 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
2431 LGC_PALETTE_B;
2432
2433 for (i = 0; i < 256; i++) {
2434 I915_WRITE(palreg + 4 * i,
2435 (intel_crtc->lut_r[i] << 16) |
2436 (intel_crtc->lut_g[i] << 8) |
2437 intel_crtc->lut_b[i]);
2438 }
2439 }
2440
2441 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
2442 struct drm_file *file_priv,
2443 uint32_t handle,
2444 uint32_t width, uint32_t height)
2445 {
2446 struct drm_device *dev = crtc->dev;
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2449 struct drm_gem_object *bo;
2450 struct drm_i915_gem_object *obj_priv;
2451 int pipe = intel_crtc->pipe;
2452 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
2453 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
2454 uint32_t temp = I915_READ(control);
2455 size_t addr;
2456 int ret;
2457
2458 DRM_DEBUG("\n");
2459
2460 /* if we want to turn off the cursor ignore width and height */
2461 if (!handle) {
2462 DRM_DEBUG("cursor off\n");
2463 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2464 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
2465 temp |= CURSOR_MODE_DISABLE;
2466 } else {
2467 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
2468 }
2469 addr = 0;
2470 bo = NULL;
2471 mutex_lock(&dev->struct_mutex);
2472 goto finish;
2473 }
2474
2475 /* Currently we only support 64x64 cursors */
2476 if (width != 64 || height != 64) {
2477 DRM_ERROR("we currently only support 64x64 cursors\n");
2478 return -EINVAL;
2479 }
2480
2481 bo = drm_gem_object_lookup(dev, file_priv, handle);
2482 if (!bo)
2483 return -ENOENT;
2484
2485 obj_priv = bo->driver_private;
2486
2487 if (bo->size < width * height * 4) {
2488 DRM_ERROR("buffer is to small\n");
2489 ret = -ENOMEM;
2490 goto fail;
2491 }
2492
2493 /* we only need to pin inside GTT if cursor is non-phy */
2494 mutex_lock(&dev->struct_mutex);
2495 if (!dev_priv->cursor_needs_physical) {
2496 ret = i915_gem_object_pin(bo, PAGE_SIZE);
2497 if (ret) {
2498 DRM_ERROR("failed to pin cursor bo\n");
2499 goto fail_locked;
2500 }
2501 addr = obj_priv->gtt_offset;
2502 } else {
2503 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
2504 if (ret) {
2505 DRM_ERROR("failed to attach phys object\n");
2506 goto fail_locked;
2507 }
2508 addr = obj_priv->phys_obj->handle->busaddr;
2509 }
2510
2511 if (!IS_I9XX(dev))
2512 I915_WRITE(CURSIZE, (height << 12) | width);
2513
2514 /* Hooray for CUR*CNTR differences */
2515 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
2516 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
2517 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
2518 temp |= (pipe << 28); /* Connect to correct pipe */
2519 } else {
2520 temp &= ~(CURSOR_FORMAT_MASK);
2521 temp |= CURSOR_ENABLE;
2522 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
2523 }
2524
2525 finish:
2526 I915_WRITE(control, temp);
2527 I915_WRITE(base, addr);
2528
2529 if (intel_crtc->cursor_bo) {
2530 if (dev_priv->cursor_needs_physical) {
2531 if (intel_crtc->cursor_bo != bo)
2532 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
2533 } else
2534 i915_gem_object_unpin(intel_crtc->cursor_bo);
2535 drm_gem_object_unreference(intel_crtc->cursor_bo);
2536 }
2537 mutex_unlock(&dev->struct_mutex);
2538
2539 intel_crtc->cursor_addr = addr;
2540 intel_crtc->cursor_bo = bo;
2541
2542 return 0;
2543 fail:
2544 mutex_lock(&dev->struct_mutex);
2545 fail_locked:
2546 drm_gem_object_unreference(bo);
2547 mutex_unlock(&dev->struct_mutex);
2548 return ret;
2549 }
2550
2551 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
2552 {
2553 struct drm_device *dev = crtc->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556 int pipe = intel_crtc->pipe;
2557 uint32_t temp = 0;
2558 uint32_t adder;
2559
2560 if (x < 0) {
2561 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
2562 x = -x;
2563 }
2564 if (y < 0) {
2565 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
2566 y = -y;
2567 }
2568
2569 temp |= x << CURSOR_X_SHIFT;
2570 temp |= y << CURSOR_Y_SHIFT;
2571
2572 adder = intel_crtc->cursor_addr;
2573 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
2574 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
2575
2576 return 0;
2577 }
2578
2579 /** Sets the color ramps on behalf of RandR */
2580 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
2581 u16 blue, int regno)
2582 {
2583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2584
2585 intel_crtc->lut_r[regno] = red >> 8;
2586 intel_crtc->lut_g[regno] = green >> 8;
2587 intel_crtc->lut_b[regno] = blue >> 8;
2588 }
2589
2590 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2591 u16 *blue, uint32_t size)
2592 {
2593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2594 int i;
2595
2596 if (size != 256)
2597 return;
2598
2599 for (i = 0; i < 256; i++) {
2600 intel_crtc->lut_r[i] = red[i] >> 8;
2601 intel_crtc->lut_g[i] = green[i] >> 8;
2602 intel_crtc->lut_b[i] = blue[i] >> 8;
2603 }
2604
2605 intel_crtc_load_lut(crtc);
2606 }
2607
2608 /**
2609 * Get a pipe with a simple mode set on it for doing load-based monitor
2610 * detection.
2611 *
2612 * It will be up to the load-detect code to adjust the pipe as appropriate for
2613 * its requirements. The pipe will be connected to no other outputs.
2614 *
2615 * Currently this code will only succeed if there is a pipe with no outputs
2616 * configured for it. In the future, it could choose to temporarily disable
2617 * some outputs to free up a pipe for its use.
2618 *
2619 * \return crtc, or NULL if no pipes are available.
2620 */
2621
2622 /* VESA 640x480x72Hz mode to set on the pipe */
2623 static struct drm_display_mode load_detect_mode = {
2624 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
2625 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
2626 };
2627
2628 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
2629 struct drm_display_mode *mode,
2630 int *dpms_mode)
2631 {
2632 struct intel_crtc *intel_crtc;
2633 struct drm_crtc *possible_crtc;
2634 struct drm_crtc *supported_crtc =NULL;
2635 struct drm_encoder *encoder = &intel_output->enc;
2636 struct drm_crtc *crtc = NULL;
2637 struct drm_device *dev = encoder->dev;
2638 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2639 struct drm_crtc_helper_funcs *crtc_funcs;
2640 int i = -1;
2641
2642 /*
2643 * Algorithm gets a little messy:
2644 * - if the connector already has an assigned crtc, use it (but make
2645 * sure it's on first)
2646 * - try to find the first unused crtc that can drive this connector,
2647 * and use that if we find one
2648 * - if there are no unused crtcs available, try to use the first
2649 * one we found that supports the connector
2650 */
2651
2652 /* See if we already have a CRTC for this connector */
2653 if (encoder->crtc) {
2654 crtc = encoder->crtc;
2655 /* Make sure the crtc and connector are running */
2656 intel_crtc = to_intel_crtc(crtc);
2657 *dpms_mode = intel_crtc->dpms_mode;
2658 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2659 crtc_funcs = crtc->helper_private;
2660 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2661 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2662 }
2663 return crtc;
2664 }
2665
2666 /* Find an unused one (if possible) */
2667 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
2668 i++;
2669 if (!(encoder->possible_crtcs & (1 << i)))
2670 continue;
2671 if (!possible_crtc->enabled) {
2672 crtc = possible_crtc;
2673 break;
2674 }
2675 if (!supported_crtc)
2676 supported_crtc = possible_crtc;
2677 }
2678
2679 /*
2680 * If we didn't find an unused CRTC, don't use any.
2681 */
2682 if (!crtc) {
2683 return NULL;
2684 }
2685
2686 encoder->crtc = crtc;
2687 intel_output->base.encoder = encoder;
2688 intel_output->load_detect_temp = true;
2689
2690 intel_crtc = to_intel_crtc(crtc);
2691 *dpms_mode = intel_crtc->dpms_mode;
2692
2693 if (!crtc->enabled) {
2694 if (!mode)
2695 mode = &load_detect_mode;
2696 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
2697 } else {
2698 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
2699 crtc_funcs = crtc->helper_private;
2700 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2701 }
2702
2703 /* Add this connector to the crtc */
2704 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
2705 encoder_funcs->commit(encoder);
2706 }
2707 /* let the connector get through one full cycle before testing */
2708 intel_wait_for_vblank(dev);
2709
2710 return crtc;
2711 }
2712
2713 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
2714 {
2715 struct drm_encoder *encoder = &intel_output->enc;
2716 struct drm_device *dev = encoder->dev;
2717 struct drm_crtc *crtc = encoder->crtc;
2718 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2719 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2720
2721 if (intel_output->load_detect_temp) {
2722 encoder->crtc = NULL;
2723 intel_output->base.encoder = NULL;
2724 intel_output->load_detect_temp = false;
2725 crtc->enabled = drm_helper_crtc_in_use(crtc);
2726 drm_helper_disable_unused_functions(dev);
2727 }
2728
2729 /* Switch crtc and output back off if necessary */
2730 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
2731 if (encoder->crtc == crtc)
2732 encoder_funcs->dpms(encoder, dpms_mode);
2733 crtc_funcs->dpms(crtc, dpms_mode);
2734 }
2735 }
2736
2737 /* Returns the clock of the currently programmed mode of the given pipe. */
2738 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
2739 {
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742 int pipe = intel_crtc->pipe;
2743 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
2744 u32 fp;
2745 intel_clock_t clock;
2746
2747 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
2748 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
2749 else
2750 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
2751
2752 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
2753 if (IS_IGD(dev)) {
2754 clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
2755 clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT;
2756 } else {
2757 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
2758 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
2759 }
2760
2761 if (IS_I9XX(dev)) {
2762 if (IS_IGD(dev))
2763 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >>
2764 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD);
2765 else
2766 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
2767 DPLL_FPA01_P1_POST_DIV_SHIFT);
2768
2769 switch (dpll & DPLL_MODE_MASK) {
2770 case DPLLB_MODE_DAC_SERIAL:
2771 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
2772 5 : 10;
2773 break;
2774 case DPLLB_MODE_LVDS:
2775 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
2776 7 : 14;
2777 break;
2778 default:
2779 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
2780 "mode\n", (int)(dpll & DPLL_MODE_MASK));
2781 return 0;
2782 }
2783
2784 /* XXX: Handle the 100Mhz refclk */
2785 intel_clock(dev, 96000, &clock);
2786 } else {
2787 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
2788
2789 if (is_lvds) {
2790 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
2791 DPLL_FPA01_P1_POST_DIV_SHIFT);
2792 clock.p2 = 14;
2793
2794 if ((dpll & PLL_REF_INPUT_MASK) ==
2795 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
2796 /* XXX: might not be 66MHz */
2797 intel_clock(dev, 66000, &clock);
2798 } else
2799 intel_clock(dev, 48000, &clock);
2800 } else {
2801 if (dpll & PLL_P1_DIVIDE_BY_TWO)
2802 clock.p1 = 2;
2803 else {
2804 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
2805 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
2806 }
2807 if (dpll & PLL_P2_DIVIDE_BY_4)
2808 clock.p2 = 4;
2809 else
2810 clock.p2 = 2;
2811
2812 intel_clock(dev, 48000, &clock);
2813 }
2814 }
2815
2816 /* XXX: It would be nice to validate the clocks, but we can't reuse
2817 * i830PllIsValid() because it relies on the xf86_config connector
2818 * configuration being accurate, which it isn't necessarily.
2819 */
2820
2821 return clock.dot;
2822 }
2823
2824 /** Returns the currently programmed mode of the given pipe. */
2825 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
2826 struct drm_crtc *crtc)
2827 {
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830 int pipe = intel_crtc->pipe;
2831 struct drm_display_mode *mode;
2832 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
2833 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
2834 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
2835 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
2836
2837 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
2838 if (!mode)
2839 return NULL;
2840
2841 mode->clock = intel_crtc_clock_get(dev, crtc);
2842 mode->hdisplay = (htot & 0xffff) + 1;
2843 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
2844 mode->hsync_start = (hsync & 0xffff) + 1;
2845 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
2846 mode->vdisplay = (vtot & 0xffff) + 1;
2847 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
2848 mode->vsync_start = (vsync & 0xffff) + 1;
2849 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
2850
2851 drm_mode_set_name(mode);
2852 drm_mode_set_crtcinfo(mode, 0);
2853
2854 return mode;
2855 }
2856
2857 static void intel_crtc_destroy(struct drm_crtc *crtc)
2858 {
2859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2860
2861 if (intel_crtc->mode_set.mode)
2862 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
2863 drm_crtc_cleanup(crtc);
2864 kfree(intel_crtc);
2865 }
2866
2867 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
2868 .dpms = intel_crtc_dpms,
2869 .mode_fixup = intel_crtc_mode_fixup,
2870 .mode_set = intel_crtc_mode_set,
2871 .mode_set_base = intel_pipe_set_base,
2872 .prepare = intel_crtc_prepare,
2873 .commit = intel_crtc_commit,
2874 };
2875
2876 static const struct drm_crtc_funcs intel_crtc_funcs = {
2877 .cursor_set = intel_crtc_cursor_set,
2878 .cursor_move = intel_crtc_cursor_move,
2879 .gamma_set = intel_crtc_gamma_set,
2880 .set_config = drm_crtc_helper_set_config,
2881 .destroy = intel_crtc_destroy,
2882 };
2883
2884
2885 static void intel_crtc_init(struct drm_device *dev, int pipe)
2886 {
2887 struct intel_crtc *intel_crtc;
2888 int i;
2889
2890 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2891 if (intel_crtc == NULL)
2892 return;
2893
2894 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
2895
2896 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
2897 intel_crtc->pipe = pipe;
2898 intel_crtc->plane = pipe;
2899 for (i = 0; i < 256; i++) {
2900 intel_crtc->lut_r[i] = i;
2901 intel_crtc->lut_g[i] = i;
2902 intel_crtc->lut_b[i] = i;
2903 }
2904
2905 intel_crtc->cursor_addr = 0;
2906 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
2907 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
2908
2909 intel_crtc->mode_set.crtc = &intel_crtc->base;
2910 intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1);
2911 intel_crtc->mode_set.num_connectors = 0;
2912
2913 if (i915_fbpercrtc) {
2914
2915
2916
2917 }
2918 }
2919
2920 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
2921 struct drm_file *file_priv)
2922 {
2923 drm_i915_private_t *dev_priv = dev->dev_private;
2924 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
2925 struct drm_crtc *crtc = NULL;
2926 int pipe = -1;
2927
2928 if (!dev_priv) {
2929 DRM_ERROR("called with no initialization\n");
2930 return -EINVAL;
2931 }
2932
2933 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 if (crtc->base.id == pipe_from_crtc_id->crtc_id) {
2936 pipe = intel_crtc->pipe;
2937 break;
2938 }
2939 }
2940
2941 if (pipe == -1) {
2942 DRM_ERROR("no such CRTC id\n");
2943 return -EINVAL;
2944 }
2945
2946 pipe_from_crtc_id->pipe = pipe;
2947
2948 return 0;
2949 }
2950
2951 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
2952 {
2953 struct drm_crtc *crtc = NULL;
2954
2955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2957 if (intel_crtc->pipe == pipe)
2958 break;
2959 }
2960 return crtc;
2961 }
2962
2963 static int intel_connector_clones(struct drm_device *dev, int type_mask)
2964 {
2965 int index_mask = 0;
2966 struct drm_connector *connector;
2967 int entry = 0;
2968
2969 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2970 struct intel_output *intel_output = to_intel_output(connector);
2971 if (type_mask & (1 << intel_output->type))
2972 index_mask |= (1 << entry);
2973 entry++;
2974 }
2975 return index_mask;
2976 }
2977
2978
2979 static void intel_setup_outputs(struct drm_device *dev)
2980 {
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct drm_connector *connector;
2983
2984 intel_crt_init(dev);
2985
2986 /* Set up integrated LVDS */
2987 if (IS_MOBILE(dev) && !IS_I830(dev))
2988 intel_lvds_init(dev);
2989
2990 if (IS_IGDNG(dev)) {
2991 int found;
2992
2993 if (I915_READ(HDMIB) & PORT_DETECTED) {
2994 /* check SDVOB */
2995 /* found = intel_sdvo_init(dev, HDMIB); */
2996 found = 0;
2997 if (!found)
2998 intel_hdmi_init(dev, HDMIB);
2999 }
3000
3001 if (I915_READ(HDMIC) & PORT_DETECTED)
3002 intel_hdmi_init(dev, HDMIC);
3003
3004 if (I915_READ(HDMID) & PORT_DETECTED)
3005 intel_hdmi_init(dev, HDMID);
3006
3007 } else if (IS_I9XX(dev)) {
3008 int found;
3009 u32 reg;
3010
3011 if (I915_READ(SDVOB) & SDVO_DETECTED) {
3012 found = intel_sdvo_init(dev, SDVOB);
3013 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3014 intel_hdmi_init(dev, SDVOB);
3015 if (!found && SUPPORTS_INTEGRATED_DP(dev))
3016 intel_dp_init(dev, DP_B);
3017 }
3018
3019 /* Before G4X SDVOC doesn't have its own detect register */
3020 if (IS_G4X(dev))
3021 reg = SDVOC;
3022 else
3023 reg = SDVOB;
3024
3025 if (I915_READ(reg) & SDVO_DETECTED) {
3026 found = intel_sdvo_init(dev, SDVOC);
3027 if (!found && SUPPORTS_INTEGRATED_HDMI(dev))
3028 intel_hdmi_init(dev, SDVOC);
3029 if (!found && SUPPORTS_INTEGRATED_DP(dev))
3030 intel_dp_init(dev, DP_C);
3031 }
3032 if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED))
3033 intel_dp_init(dev, DP_D);
3034 } else
3035 intel_dvo_init(dev);
3036
3037 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
3038 intel_tv_init(dev);
3039
3040 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3041 struct intel_output *intel_output = to_intel_output(connector);
3042 struct drm_encoder *encoder = &intel_output->enc;
3043 int crtc_mask = 0, clone_mask = 0;
3044
3045 /* valid crtcs */
3046 switch(intel_output->type) {
3047 case INTEL_OUTPUT_HDMI:
3048 crtc_mask = ((1 << 0)|
3049 (1 << 1));
3050 clone_mask = ((1 << INTEL_OUTPUT_HDMI));
3051 break;
3052 case INTEL_OUTPUT_DVO:
3053 case INTEL_OUTPUT_SDVO:
3054 crtc_mask = ((1 << 0)|
3055 (1 << 1));
3056 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3057 (1 << INTEL_OUTPUT_DVO) |
3058 (1 << INTEL_OUTPUT_SDVO));
3059 break;
3060 case INTEL_OUTPUT_ANALOG:
3061 crtc_mask = ((1 << 0)|
3062 (1 << 1));
3063 clone_mask = ((1 << INTEL_OUTPUT_ANALOG) |
3064 (1 << INTEL_OUTPUT_DVO) |
3065 (1 << INTEL_OUTPUT_SDVO));
3066 break;
3067 case INTEL_OUTPUT_LVDS:
3068 crtc_mask = (1 << 1);
3069 clone_mask = (1 << INTEL_OUTPUT_LVDS);
3070 break;
3071 case INTEL_OUTPUT_TVOUT:
3072 crtc_mask = ((1 << 0) |
3073 (1 << 1));
3074 clone_mask = (1 << INTEL_OUTPUT_TVOUT);
3075 break;
3076 case INTEL_OUTPUT_DISPLAYPORT:
3077 crtc_mask = ((1 << 0) |
3078 (1 << 1));
3079 clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT);
3080 break;
3081 }
3082 encoder->possible_crtcs = crtc_mask;
3083 encoder->possible_clones = intel_connector_clones(dev, clone_mask);
3084 }
3085 }
3086
3087 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
3088 {
3089 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3090 struct drm_device *dev = fb->dev;
3091
3092 if (fb->fbdev)
3093 intelfb_remove(dev, fb);
3094
3095 drm_framebuffer_cleanup(fb);
3096 mutex_lock(&dev->struct_mutex);
3097 drm_gem_object_unreference(intel_fb->obj);
3098 mutex_unlock(&dev->struct_mutex);
3099
3100 kfree(intel_fb);
3101 }
3102
3103 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
3104 struct drm_file *file_priv,
3105 unsigned int *handle)
3106 {
3107 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
3108 struct drm_gem_object *object = intel_fb->obj;
3109
3110 return drm_gem_handle_create(file_priv, object, handle);
3111 }
3112
3113 static const struct drm_framebuffer_funcs intel_fb_funcs = {
3114 .destroy = intel_user_framebuffer_destroy,
3115 .create_handle = intel_user_framebuffer_create_handle,
3116 };
3117
3118 int intel_framebuffer_create(struct drm_device *dev,
3119 struct drm_mode_fb_cmd *mode_cmd,
3120 struct drm_framebuffer **fb,
3121 struct drm_gem_object *obj)
3122 {
3123 struct intel_framebuffer *intel_fb;
3124 int ret;
3125
3126 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
3127 if (!intel_fb)
3128 return -ENOMEM;
3129
3130 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
3131 if (ret) {
3132 DRM_ERROR("framebuffer init failed %d\n", ret);
3133 return ret;
3134 }
3135
3136 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
3137
3138 intel_fb->obj = obj;
3139
3140 *fb = &intel_fb->base;
3141
3142 return 0;
3143 }
3144
3145
3146 static struct drm_framebuffer *
3147 intel_user_framebuffer_create(struct drm_device *dev,
3148 struct drm_file *filp,
3149 struct drm_mode_fb_cmd *mode_cmd)
3150 {
3151 struct drm_gem_object *obj;
3152 struct drm_framebuffer *fb;
3153 int ret;
3154
3155 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
3156 if (!obj)
3157 return NULL;
3158
3159 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
3160 if (ret) {
3161 mutex_lock(&dev->struct_mutex);
3162 drm_gem_object_unreference(obj);
3163 mutex_unlock(&dev->struct_mutex);
3164 return NULL;
3165 }
3166
3167 return fb;
3168 }
3169
3170 static const struct drm_mode_config_funcs intel_mode_funcs = {
3171 .fb_create = intel_user_framebuffer_create,
3172 .fb_changed = intelfb_probe,
3173 };
3174
3175 void intel_modeset_init(struct drm_device *dev)
3176 {
3177 int num_pipe;
3178 int i;
3179
3180 drm_mode_config_init(dev);
3181
3182 dev->mode_config.min_width = 0;
3183 dev->mode_config.min_height = 0;
3184
3185 dev->mode_config.funcs = (void *)&intel_mode_funcs;
3186
3187 if (IS_I965G(dev)) {
3188 dev->mode_config.max_width = 8192;
3189 dev->mode_config.max_height = 8192;
3190 } else if (IS_I9XX(dev)) {
3191 dev->mode_config.max_width = 4096;
3192 dev->mode_config.max_height = 4096;
3193 } else {
3194 dev->mode_config.max_width = 2048;
3195 dev->mode_config.max_height = 2048;
3196 }
3197
3198 /* set memory base */
3199 if (IS_I9XX(dev))
3200 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
3201 else
3202 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
3203
3204 if (IS_MOBILE(dev) || IS_I9XX(dev))
3205 num_pipe = 2;
3206 else
3207 num_pipe = 1;
3208 DRM_DEBUG("%d display pipe%s available.\n",
3209 num_pipe, num_pipe > 1 ? "s" : "");
3210
3211 for (i = 0; i < num_pipe; i++) {
3212 intel_crtc_init(dev, i);
3213 }
3214
3215 intel_setup_outputs(dev);
3216 }
3217
3218 void intel_modeset_cleanup(struct drm_device *dev)
3219 {
3220 drm_mode_config_cleanup(dev);
3221 }
3222
3223
3224 /* current intel driver doesn't take advantage of encoders
3225 always give back the encoder for the connector
3226 */
3227 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
3228 {
3229 struct intel_output *intel_output = to_intel_output(connector);
3230
3231 return &intel_output->enc;
3232 }
Support for the Chinese Samsung S3C2440 based development boards