drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40
  41 /* timeout waiting for the controller to respond */
  42 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  43
  44 #define OMAP_I2C_REV_REG                0x00
  45 #define OMAP_I2C_IE_REG                 0x04
  46 #define OMAP_I2C_STAT_REG               0x08
  47 #define OMAP_I2C_IV_REG                 0x0c
  48 #define OMAP_I2C_SYSS_REG               0x10
  49 #define OMAP_I2C_BUF_REG                0x14
  50 #define OMAP_I2C_CNT_REG                0x18
  51 #define OMAP_I2C_DATA_REG               0x1c
  52 #define OMAP_I2C_SYSC_REG               0x20
  53 #define OMAP_I2C_CON_REG                0x24
  54 #define OMAP_I2C_OA_REG                 0x28
  55 #define OMAP_I2C_SA_REG                 0x2c
  56 #define OMAP_I2C_PSC_REG                0x30
  57 #define OMAP_I2C_SCLL_REG               0x34
  58 #define OMAP_I2C_SCLH_REG               0x38
  59 #define OMAP_I2C_SYSTEST_REG            0x3c
  60 #define OMAP_I2C_BUFSTAT_REG            0x40
  61
  62 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  63 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  64 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  65 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  66 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  67 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  68 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  69 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  70
  71 /* I2C Status Register (OMAP_I2C_STAT): */
  72 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  73 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  74 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  75 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  76 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  77 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  78 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  79 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  80 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  81 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  82 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  83 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  84
  85 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  86 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  87 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
  88 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  89 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
  90
  91 /* I2C Configuration Register (OMAP_I2C_CON): */
  92 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  93 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  94 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
  95 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
  96 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
  97 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
  98 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
  99 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 100 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 101 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 102
 103 /* I2C SCL time value when Master */
 104 #define OMAP_I2C_SCLL_HSSCLL    8
 105 #define OMAP_I2C_SCLH_HSSCLH    8
 106
 107 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 108 #ifdef DEBUG
 109 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 110 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 111 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 112 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 113 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 114 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 115 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 116 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 117 #endif
 118
 119 /* I2C System Status register (OMAP_I2C_SYSS): */
 120 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 121
 122 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 123 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 124
 125 struct omap_i2c_dev {
 126         struct device           *dev;
 127         void __iomem            *base;          /* virtual */
 128         int                     irq;
 129         struct clk              *iclk;          /* Interface clock */
 130         struct clk              *fclk;          /* Functional clock */
 131         struct completion       cmd_complete;
 132         struct resource         *ioarea;
 133         u32                     speed;          /* Speed of bus in Khz */
 134         u16                     cmd_err;
 135         u8                      *buf;
 136         size_t                  buf_len;
 137         struct i2c_adapter      adapter;
 138         u8                      fifo_size;      /* use as flag and value
 139                                                  * fifo_size==0 implies no fifo
 140                                                  * if set, should be trsh+1
 141                                                  */
 142         unsigned                rev1:1;
 143         unsigned                b_hw:1;         /* bad h/w fixes */
 144         unsigned                idle:1;
 145         u16                     iestate;        /* Saved interrupt register */
 146 };
 147
 148 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 149                                       int reg, u16 val)
 150 {
 151         __raw_writew(val, i2c_dev->base + reg);
 152 }
 153
 154 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 155 {
 156         return __raw_readw(i2c_dev->base + reg);
 157 }
 158
 159 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 160 {
 161         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 162                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 163                 if (IS_ERR(dev->iclk)) {
 164                         dev->iclk = NULL;
 165                         return -ENODEV;
 166                 }
 167         }
 168
 169         dev->fclk = clk_get(dev->dev, "i2c_fck");
 170         if (IS_ERR(dev->fclk)) {
 171                 if (dev->iclk != NULL) {
 172                         clk_put(dev->iclk);
 173                         dev->iclk = NULL;
 174                 }
 175                 dev->fclk = NULL;
 176                 return -ENODEV;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 183 {
 184         clk_put(dev->fclk);
 185         dev->fclk = NULL;
 186         if (dev->iclk != NULL) {
 187                 clk_put(dev->iclk);
 188                 dev->iclk = NULL;
 189         }
 190 }
 191
 192 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 193 {
 194         WARN_ON(!dev->idle);
 195
 196         if (dev->iclk != NULL)
 197                 clk_enable(dev->iclk);
 198         clk_enable(dev->fclk);
 199         dev->idle = 0;
 200         if (dev->iestate)
 201                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 202 }
 203
 204 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 205 {
 206         u16 iv;
 207
 208         WARN_ON(dev->idle);
 209
 210         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 211         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 212         if (dev->rev1) {
 213                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
 214         } else {
 215                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 216
 217                 /* Flush posted write before the dev->idle store occurs */
 218                 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 219         }
 220         dev->idle = 1;
 221         clk_disable(dev->fclk);
 222         if (dev->iclk != NULL)
 223                 clk_disable(dev->iclk);
 224 }
 225
 226 static int omap_i2c_init(struct omap_i2c_dev *dev)
 227 {
 228         u16 psc = 0, scll = 0, sclh = 0;
 229         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 230         unsigned long fclk_rate = 12000000;
 231         unsigned long timeout;
 232         unsigned long internal_clk = 0;
 233
 234         if (!dev->rev1) {
 235                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 236                 /* For some reason we need to set the EN bit before the
 237                  * reset done bit gets set. */
 238                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 239                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 240                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 241                          OMAP_I2C_SYSS_RDONE)) {
 242                         if (time_after(jiffies, timeout)) {
 243                                 dev_warn(dev->dev, "timeout waiting "
 244                                                 "for controller reset\n");
 245                                 return -ETIMEDOUT;
 246                         }
 247                         msleep(1);
 248                 }
 249         }
 250         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 251
 252         if (cpu_class_is_omap1()) {
 253                 struct clk *armxor_ck;
 254
 255                 armxor_ck = clk_get(NULL, "armxor_ck");
 256                 if (IS_ERR(armxor_ck))
 257                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 258                 else {
 259                         fclk_rate = clk_get_rate(armxor_ck);
 260                         clk_put(armxor_ck);
 261                 }
 262                 /* TRM for 5912 says the I2C clock must be prescaled to be
 263                  * between 7 - 12 MHz. The XOR input clock is typically
 264                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 265                  *
 266                  * XOR MHz      Divider         Prescaler
 267                  * 12           1               0
 268                  * 13           2               1
 269                  * 19.2         2               1
 270                  */
 271                 if (fclk_rate > 12000000)
 272                         psc = fclk_rate / 12000000;
 273         }
 274
 275         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 276
 277                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
 278                 internal_clk = 19200;
 279                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 280
 281                 /* Compute prescaler divisor */
 282                 psc = fclk_rate / internal_clk;
 283                 psc = psc - 1;
 284
 285                 /* If configured for High Speed */
 286                 if (dev->speed > 400) {
 287                         /* For first phase of HS mode */
 288                         fsscll = internal_clk / (400 * 2) - 6;
 289                         fssclh = internal_clk / (400 * 2) - 6;
 290
 291                         /* For second phase of HS mode */
 292                         hsscll = fclk_rate / (dev->speed * 2) - 6;
 293                         hssclh = fclk_rate / (dev->speed * 2) - 6;
 294                 } else {
 295                         /* To handle F/S modes */
 296                         fsscll = internal_clk / (dev->speed * 2) - 6;
 297                         fssclh = internal_clk / (dev->speed * 2) - 6;
 298                 }
 299                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 300                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 301         } else {
 302                 /* Program desired operating rate */
 303                 fclk_rate /= (psc + 1) * 1000;
 304                 if (psc > 2)
 305                         psc = 2;
 306                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 307                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 308         }
 309
 310         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 311         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 312
 313         /* SCL low and high time values */
 314         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 315         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 316
 317         if (dev->fifo_size)
 318                 /* Note: setup required fifo size - 1 */
 319                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
 320                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
 321                                         OMAP_I2C_BUF_RXFIF_CLR |
 322                                         (dev->fifo_size - 1) | /* XTRSH */
 323                                         OMAP_I2C_BUF_TXFIF_CLR);
 324
 325         /* Take the I2C module out of reset: */
 326         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 327
 328         /* Enable interrupts */
 329         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 330                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 331                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 332                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 333                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
 334         return 0;
 335 }
 336
 337 /*
 338  * Waiting on Bus Busy
 339  */
 340 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 341 {
 342         unsigned long timeout;
 343
 344         timeout = jiffies + OMAP_I2C_TIMEOUT;
 345         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 346                 if (time_after(jiffies, timeout)) {
 347                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 348                         return -ETIMEDOUT;
 349                 }
 350                 msleep(1);
 351         }
 352
 353         return 0;
 354 }
 355
 356 /*
 357  * Low level master read/write transaction.
 358  */
 359 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 360                              struct i2c_msg *msg, int stop)
 361 {
 362         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 363         int r;
 364         u16 w;
 365
 366         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 367                 msg->addr, msg->len, msg->flags, stop);
 368
 369         if (msg->len == 0)
 370                 return -EINVAL;
 371
 372         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 373
 374         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 375         dev->buf = msg->buf;
 376         dev->buf_len = msg->len;
 377
 378         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 379
 380         /* Clear the FIFO Buffers */
 381         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 382         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 383         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 384
 385         init_completion(&dev->cmd_complete);
 386         dev->cmd_err = 0;
 387
 388         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 389
 390         /* High speed configuration */
 391         if (dev->speed > 400)
 392                 w |= OMAP_I2C_CON_OPMODE_HS;
 393
 394         if (msg->flags & I2C_M_TEN)
 395                 w |= OMAP_I2C_CON_XA;
 396         if (!(msg->flags & I2C_M_RD))
 397                 w |= OMAP_I2C_CON_TRX;
 398
 399         if (!dev->b_hw && stop)
 400                 w |= OMAP_I2C_CON_STP;
 401
 402         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 403
 404         /*
 405          * Don't write stt and stp together on some hardware.
 406          */
 407         if (dev->b_hw && stop) {
 408                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 409                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 410                 while (con & OMAP_I2C_CON_STT) {
 411                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 412
 413                         /* Let the user know if i2c is in a bad state */
 414                         if (time_after(jiffies, delay)) {
 415                                 dev_err(dev->dev, "controller timed out "
 416                                 "waiting for start condition to finish\n");
 417                                 return -ETIMEDOUT;
 418                         }
 419                         cpu_relax();
 420                 }
 421
 422                 w |= OMAP_I2C_CON_STP;
 423                 w &= ~OMAP_I2C_CON_STT;
 424                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 425         }
 426
 427         /*
 428          * REVISIT: We should abort the transfer on signals, but the bus goes
 429          * into arbitration and we're currently unable to recover from it.
 430          */
 431         r = wait_for_completion_timeout(&dev->cmd_complete,
 432                                         OMAP_I2C_TIMEOUT);
 433         dev->buf_len = 0;
 434         if (r < 0)
 435                 return r;
 436         if (r == 0) {
 437                 dev_err(dev->dev, "controller timed out\n");
 438                 omap_i2c_init(dev);
 439                 return -ETIMEDOUT;
 440         }
 441
 442         if (likely(!dev->cmd_err))
 443                 return 0;
 444
 445         /* We have an error */
 446         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 447                             OMAP_I2C_STAT_XUDF)) {
 448                 omap_i2c_init(dev);
 449                 return -EIO;
 450         }
 451
 452         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 453                 if (msg->flags & I2C_M_IGNORE_NAK)
 454                         return 0;
 455                 if (stop) {
 456                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 457                         w |= OMAP_I2C_CON_STP;
 458                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 459                 }
 460                 return -EREMOTEIO;
 461         }
 462         return -EIO;
 463 }
 464
 465
 466 /*
 467  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 468  * to do the work during IRQ processing.
 469  */
 470 static int
 471 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 472 {
 473         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 474         int i;
 475         int r;
 476
 477         omap_i2c_unidle(dev);
 478
 479         r = omap_i2c_wait_for_bb(dev);
 480         if (r < 0)
 481                 goto out;
 482
 483         for (i = 0; i < num; i++) {
 484                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 485                 if (r != 0)
 486                         break;
 487         }
 488
 489         if (r == 0)
 490                 r = num;
 491 out:
 492         omap_i2c_idle(dev);
 493         return r;
 494 }
 495
 496 static u32
 497 omap_i2c_func(struct i2c_adapter *adap)
 498 {
 499         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 500 }
 501
 502 static inline void
 503 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 504 {
 505         dev->cmd_err |= err;
 506         complete(&dev->cmd_complete);
 507 }
 508
 509 static inline void
 510 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 511 {
 512         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 513 }
 514
 515 /* rev1 devices are apparently only on some 15xx */
 516 #ifdef CONFIG_ARCH_OMAP15XX
 517
 518 static irqreturn_t
 519 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 520 {
 521         struct omap_i2c_dev *dev = dev_id;
 522         u16 iv, w;
 523
 524         if (dev->idle)
 525                 return IRQ_NONE;
 526
 527         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 528         switch (iv) {
 529         case 0x00:      /* None */
 530                 break;
 531         case 0x01:      /* Arbitration lost */
 532                 dev_err(dev->dev, "Arbitration lost\n");
 533                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 534                 break;
 535         case 0x02:      /* No acknowledgement */
 536                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 537                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 538                 break;
 539         case 0x03:      /* Register access ready */
 540                 omap_i2c_complete_cmd(dev, 0);
 541                 break;
 542         case 0x04:      /* Receive data ready */
 543                 if (dev->buf_len) {
 544                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 545                         *dev->buf++ = w;
 546                         dev->buf_len--;
 547                         if (dev->buf_len) {
 548                                 *dev->buf++ = w >> 8;
 549                                 dev->buf_len--;
 550                         }
 551                 } else
 552                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 553                 break;
 554         case 0x05:      /* Transmit data ready */
 555                 if (dev->buf_len) {
 556                         w = *dev->buf++;
 557                         dev->buf_len--;
 558                         if (dev->buf_len) {
 559                                 w |= *dev->buf++ << 8;
 560                                 dev->buf_len--;
 561                         }
 562                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 563                 } else
 564                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 565                 break;
 566         default:
 567                 return IRQ_NONE;
 568         }
 569
 570         return IRQ_HANDLED;
 571 }
 572 #else
 573 #define omap_i2c_rev1_isr               NULL
 574 #endif
 575
 576 static irqreturn_t
 577 omap_i2c_isr(int this_irq, void *dev_id)
 578 {
 579         struct omap_i2c_dev *dev = dev_id;
 580         u16 bits;
 581         u16 stat, w;
 582         int err, count = 0;
 583
 584         if (dev->idle)
 585                 return IRQ_NONE;
 586
 587         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 588         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 589                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 590                 if (count++ == 100) {
 591                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 592                         break;
 593                 }
 594
 595                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 596
 597                 err = 0;
 598                 if (stat & OMAP_I2C_STAT_NACK) {
 599                         err |= OMAP_I2C_STAT_NACK;
 600                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 601                                            OMAP_I2C_CON_STP);
 602                 }
 603                 if (stat & OMAP_I2C_STAT_AL) {
 604                         dev_err(dev->dev, "Arbitration lost\n");
 605                         err |= OMAP_I2C_STAT_AL;
 606                 }
 607                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 608                                         OMAP_I2C_STAT_AL))
 609                         omap_i2c_complete_cmd(dev, err);
 610                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 611                         u8 num_bytes = 1;
 612                         if (dev->fifo_size) {
 613                                 if (stat & OMAP_I2C_STAT_RRDY)
 614                                         num_bytes = dev->fifo_size;
 615                                 else
 616                                         num_bytes = omap_i2c_read_reg(dev,
 617                                                         OMAP_I2C_BUFSTAT_REG);
 618                         }
 619                         while (num_bytes) {
 620                                 num_bytes--;
 621                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 622                                 if (dev->buf_len) {
 623                                         *dev->buf++ = w;
 624                                         dev->buf_len--;
 625                                         /* Data reg from 2430 is 8 bit wide */
 626                                         if (!cpu_is_omap2430() &&
 627                                                         !cpu_is_omap34xx()) {
 628                                                 if (dev->buf_len) {
 629                                                         *dev->buf++ = w >> 8;
 630                                                         dev->buf_len--;
 631                                                 }
 632                                         }
 633                                 } else {
 634                                         if (stat & OMAP_I2C_STAT_RRDY)
 635                                                 dev_err(dev->dev,
 636                                                         "RRDY IRQ while no data"
 637                                                                 " requested\n");
 638                                         if (stat & OMAP_I2C_STAT_RDR)
 639                                                 dev_err(dev->dev,
 640                                                         "RDR IRQ while no data"
 641                                                                 " requested\n");
 642                                         break;
 643                                 }
 644                         }
 645                         omap_i2c_ack_stat(dev,
 646                                 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 647                         continue;
 648                 }
 649                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 650                         u8 num_bytes = 1;
 651                         if (dev->fifo_size) {
 652                                 if (stat & OMAP_I2C_STAT_XRDY)
 653                                         num_bytes = dev->fifo_size;
 654                                 else
 655                                         num_bytes = omap_i2c_read_reg(dev,
 656                                                         OMAP_I2C_BUFSTAT_REG);
 657                         }
 658                         while (num_bytes) {
 659                                 num_bytes--;
 660                                 w = 0;
 661                                 if (dev->buf_len) {
 662                                         w = *dev->buf++;
 663                                         dev->buf_len--;
 664                                         /* Data reg from  2430 is 8 bit wide */
 665                                         if (!cpu_is_omap2430() &&
 666                                                         !cpu_is_omap34xx()) {
 667                                                 if (dev->buf_len) {
 668                                                         w |= *dev->buf++ << 8;
 669                                                         dev->buf_len--;
 670                                                 }
 671                                         }
 672                                 } else {
 673                                         if (stat & OMAP_I2C_STAT_XRDY)
 674                                                 dev_err(dev->dev,
 675                                                         "XRDY IRQ while no "
 676                                                         "data to send\n");
 677                                         if (stat & OMAP_I2C_STAT_XDR)
 678                                                 dev_err(dev->dev,
 679                                                         "XDR IRQ while no "
 680                                                         "data to send\n");
 681                                         break;
 682                                 }
 683                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 684                         }
 685                         omap_i2c_ack_stat(dev,
 686                                 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 687                         continue;
 688                 }
 689                 if (stat & OMAP_I2C_STAT_ROVR) {
 690                         dev_err(dev->dev, "Receive overrun\n");
 691                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 692                 }
 693                 if (stat & OMAP_I2C_STAT_XUDF) {
 694                         dev_err(dev->dev, "Transmit underflow\n");
 695                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 696                 }
 697         }
 698
 699         return count ? IRQ_HANDLED : IRQ_NONE;
 700 }
 701
 702 static const struct i2c_algorithm omap_i2c_algo = {
 703         .master_xfer    = omap_i2c_xfer,
 704         .functionality  = omap_i2c_func,
 705 };
 706
 707 static int __init
 708 omap_i2c_probe(struct platform_device *pdev)
 709 {
 710         struct omap_i2c_dev     *dev;
 711         struct i2c_adapter      *adap;
 712         struct resource         *mem, *irq, *ioarea;
 713         int r;
 714         u32 speed = 0;
 715
 716         /* NOTE: driver uses the static register mapping */
 717         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 718         if (!mem) {
 719                 dev_err(&pdev->dev, "no mem resource?\n");
 720                 return -ENODEV;
 721         }
 722         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 723         if (!irq) {
 724                 dev_err(&pdev->dev, "no irq resource?\n");
 725                 return -ENODEV;
 726         }
 727
 728         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 729                         pdev->name);
 730         if (!ioarea) {
 731                 dev_err(&pdev->dev, "I2C region already claimed\n");
 732                 return -EBUSY;
 733         }
 734
 735         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 736         if (!dev) {
 737                 r = -ENOMEM;
 738                 goto err_release_region;
 739         }
 740
 741         if (pdev->dev.platform_data != NULL)
 742                 speed = *(u32 *)pdev->dev.platform_data;
 743         else
 744                 speed = 100;    /* Defualt speed */
 745
 746         dev->speed = speed;
 747         dev->idle = 1;
 748         dev->dev = &pdev->dev;
 749         dev->irq = irq->start;
 750         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
 751         if (!dev->base) {
 752                 r = -ENOMEM;
 753                 goto err_free_mem;
 754         }
 755
 756         platform_set_drvdata(pdev, dev);
 757
 758         if ((r = omap_i2c_get_clocks(dev)) != 0)
 759                 goto err_iounmap;
 760
 761         omap_i2c_unidle(dev);
 762
 763         if (cpu_is_omap15xx())
 764                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 765
 766         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 767                 u16 s;
 768
 769                 /* Set up the fifo size - Get total size */
 770                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
 771                 dev->fifo_size = 0x8 << s;
 772
 773                 /*
 774                  * Set up notification threshold as half the total available
 775                  * size. This is to ensure that we can handle the status on int
 776                  * call back latencies.
 777                  */
 778                 dev->fifo_size = (dev->fifo_size / 2);
 779                 dev->b_hw = 1; /* Enable hardware fixes */
 780         }
 781
 782         /* reset ASAP, clearing any IRQs */
 783         omap_i2c_init(dev);
 784
 785         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 786                         0, pdev->name, dev);
 787
 788         if (r) {
 789                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 790                 goto err_unuse_clocks;
 791         }
 792         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 793         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 794                  pdev->id, r >> 4, r & 0xf, dev->speed);
 795
 796         omap_i2c_idle(dev);
 797
 798         adap = &dev->adapter;
 799         i2c_set_adapdata(adap, dev);
 800         adap->owner = THIS_MODULE;
 801         adap->class = I2C_CLASS_HWMON;
 802         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 803         adap->algo = &omap_i2c_algo;
 804         adap->dev.parent = &pdev->dev;
 805
 806         /* i2c device drivers may be active on return from add_adapter() */
 807         adap->nr = pdev->id;
 808         r = i2c_add_numbered_adapter(adap);
 809         if (r) {
 810                 dev_err(dev->dev, "failure adding adapter\n");
 811                 goto err_free_irq;
 812         }
 813
 814         return 0;
 815
 816 err_free_irq:
 817         free_irq(dev->irq, dev);
 818 err_unuse_clocks:
 819         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 820         omap_i2c_idle(dev);
 821         omap_i2c_put_clocks(dev);
 822 err_iounmap:
 823         iounmap(dev->base);
 824 err_free_mem:
 825         platform_set_drvdata(pdev, NULL);
 826         kfree(dev);
 827 err_release_region:
 828         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 829
 830         return r;
 831 }
 832
 833 static int
 834 omap_i2c_remove(struct platform_device *pdev)
 835 {
 836         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 837         struct resource         *mem;
 838
 839         platform_set_drvdata(pdev, NULL);
 840
 841         free_irq(dev->irq, dev);
 842         i2c_del_adapter(&dev->adapter);
 843         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 844         omap_i2c_put_clocks(dev);
 845         iounmap(dev->base);
 846         kfree(dev);
 847         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 848         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 849         return 0;
 850 }
 851
 852 static struct platform_driver omap_i2c_driver = {
 853         .probe          = omap_i2c_probe,
 854         .remove         = omap_i2c_remove,
 855         .driver         = {
 856                 .name   = "i2c_omap",
 857                 .owner  = THIS_MODULE,
 858         },
 859 };
 860
 861 /* I2C may be needed to bring up other drivers */
 862 static int __init
 863 omap_i2c_init_driver(void)
 864 {
 865         return platform_driver_register(&omap_i2c_driver);
 866 }
 867 subsys_initcall(omap_i2c_init_driver);
 868
 869 static void __exit omap_i2c_exit_driver(void)
 870 {
 871         platform_driver_unregister(&omap_i2c_driver);
 872 }
 873 module_exit(omap_i2c_exit_driver);
 874
 875 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 876 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 877 MODULE_LICENSE("GPL");
 878 MODULE_ALIAS("platform:i2c_omap");