arch/arm/mach-realview/platsmp.c

   1 /*
   2  *  linux/arch/arm/mach-realview/platsmp.c
   3  *
   4  *  Copyright (C) 2002 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/smp.h>
  16
  17 #include <asm/cacheflush.h>
  18 #include <asm/hardware.h>
  19 #include <asm/io.h>
  20 #include <asm/mach-types.h>
  21
  22 #include <asm/arch/board-eb.h>
  23 #include <asm/arch/board-pb11mp.h>
  24 #include <asm/arch/scu.h>
  25
  26 extern void realview_secondary_startup(void);
  27
  28 /*
  29  * control for which core is the next to come out of the secondary
  30  * boot "holding pen"
  31  */
  32 volatile int __cpuinitdata pen_release = -1;
  33
  34 static unsigned int __init get_core_count(void)
  35 {
  36         unsigned int ncores;
  37         void __iomem *scu_base = 0;
  38
  39         if (machine_is_realview_eb() && core_tile_eb11mp())
  40                 scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
  41         else if (machine_is_realview_pb11mp())
  42                 scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
  43
  44         if (scu_base) {
  45                 ncores = __raw_readl(scu_base + SCU_CONFIG);
  46                 ncores = (ncores & 0x03) + 1;
  47         } else
  48                 ncores = 1;
  49
  50         return ncores;
  51 }
  52
  53 /*
  54  * Setup the SCU
  55  */
  56 static void scu_enable(void)
  57 {
  58         u32 scu_ctrl;
  59         void __iomem *scu_base;
  60
  61         if (machine_is_realview_eb() && core_tile_eb11mp())
  62                 scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
  63         else if (machine_is_realview_pb11mp())
  64                 scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
  65         else
  66                 BUG();
  67
  68         scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
  69         scu_ctrl |= 1;
  70         __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
  71 }
  72
  73 static DEFINE_SPINLOCK(boot_lock);
  74
  75 void __cpuinit platform_secondary_init(unsigned int cpu)
  76 {
  77         /*
  78          * the primary core may have used a "cross call" soft interrupt
  79          * to get this processor out of WFI in the BootMonitor - make
  80          * sure that we are no longer being sent this soft interrupt
  81          */
  82         smp_cross_call_done(cpumask_of_cpu(cpu));
  83
  84         /*
  85          * if any interrupts are already enabled for the primary
  86          * core (e.g. timer irq), then they will not have been enabled
  87          * for us: do so
  88          */
  89         if (machine_is_realview_eb() && core_tile_eb11mp())
  90                 gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
  91         else if (machine_is_realview_pb11mp())
  92                 gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
  93
  94         /*
  95          * let the primary processor know we're out of the
  96          * pen, then head off into the C entry point
  97          */
  98         pen_release = -1;
  99         smp_wmb();
 100
 101         /*
 102          * Synchronise with the boot thread.
 103          */
 104         spin_lock(&boot_lock);
 105         spin_unlock(&boot_lock);
 106 }
 107
 108 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 109 {
 110         unsigned long timeout;
 111
 112         /*
 113          * set synchronisation state between this boot processor
 114          * and the secondary one
 115          */
 116         spin_lock(&boot_lock);
 117
 118         /*
 119          * The secondary processor is waiting to be released from
 120          * the holding pen - release it, then wait for it to flag
 121          * that it has been released by resetting pen_release.
 122          *
 123          * Note that "pen_release" is the hardware CPU ID, whereas
 124          * "cpu" is Linux's internal ID.
 125          */
 126         pen_release = cpu;
 127         flush_cache_all();
 128
 129         /*
 130          * XXX
 131          *
 132          * This is a later addition to the booting protocol: the
 133          * bootMonitor now puts secondary cores into WFI, so
 134          * poke_milo() no longer gets the cores moving; we need
 135          * to send a soft interrupt to wake the secondary core.
 136          * Use smp_cross_call() for this, since there's little
 137          * point duplicating the code here
 138          */
 139         smp_cross_call(cpumask_of_cpu(cpu));
 140
 141         timeout = jiffies + (1 * HZ);
 142         while (time_before(jiffies, timeout)) {
 143                 smp_rmb();
 144                 if (pen_release == -1)
 145                         break;
 146
 147                 udelay(10);
 148         }
 149
 150         /*
 151          * now the secondary core is starting up let it run its
 152          * calibrations, then wait for it to finish
 153          */
 154         spin_unlock(&boot_lock);
 155
 156         return pen_release != -1 ? -ENOSYS : 0;
 157 }
 158
 159 static void __init poke_milo(void)
 160 {
 161         extern void secondary_startup(void);
 162
 163         /* nobody is to be released from the pen yet */
 164         pen_release = -1;
 165
 166         /*
 167          * write the address of secondary startup into the system-wide
 168          * flags register, then clear the bottom two bits, which is what
 169          * BootMonitor is waiting for
 170          */
 171 #if 1
 172 #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
 173         __raw_writel(virt_to_phys(realview_secondary_startup),
 174                      __io_address(REALVIEW_SYS_BASE) +
 175                      REALVIEW_SYS_FLAGSS_OFFSET);
 176 #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
 177         __raw_writel(3,
 178                      __io_address(REALVIEW_SYS_BASE) +
 179                      REALVIEW_SYS_FLAGSC_OFFSET);
 180 #endif
 181
 182         mb();
 183 }
 184
 185 /*
 186  * Initialise the CPU possible map early - this describes the CPUs
 187  * which may be present or become present in the system.
 188  */
 189 void __init smp_init_cpus(void)
 190 {
 191         unsigned int i, ncores = get_core_count();
 192
 193         for (i = 0; i < ncores; i++)
 194                 cpu_set(i, cpu_possible_map);
 195 }
 196
 197 void __init smp_prepare_cpus(unsigned int max_cpus)
 198 {
 199         unsigned int ncores = get_core_count();
 200         unsigned int cpu = smp_processor_id();
 201         int i;
 202
 203         /* sanity check */
 204         if (ncores == 0) {
 205                 printk(KERN_ERR
 206                        "Realview: strange CM count of 0? Default to 1\n");
 207
 208                 ncores = 1;
 209         }
 210
 211         if (ncores > NR_CPUS) {
 212                 printk(KERN_WARNING
 213                        "Realview: no. of cores (%d) greater than configured "
 214                        "maximum of %d - clipping\n",
 215                        ncores, NR_CPUS);
 216                 ncores = NR_CPUS;
 217         }
 218
 219         smp_store_cpu_info(cpu);
 220
 221         /*
 222          * are we trying to boot more cores than exist?
 223          */
 224         if (max_cpus > ncores)
 225                 max_cpus = ncores;
 226
 227 #ifdef CONFIG_LOCAL_TIMERS
 228         /*
 229          * Enable the local timer for primary CPU. If the device is
 230          * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
 231          * realview_timer_init
 232          */
 233         if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
 234             machine_is_realview_pb11mp())
 235                 local_timer_setup(cpu);
 236 #endif
 237
 238         /*
 239          * Initialise the present map, which describes the set of CPUs
 240          * actually populated at the present time.
 241          */
 242         for (i = 0; i < max_cpus; i++)
 243                 cpu_set(i, cpu_present_map);
 244
 245         /*
 246          * Initialise the SCU if there are more than one CPU and let
 247          * them know where to start. Note that, on modern versions of
 248          * MILO, the "poke" doesn't actually do anything until each
 249          * individual core is sent a soft interrupt to get it out of
 250          * WFI
 251          */
 252         if (max_cpus > 1) {
 253                 scu_enable();
 254                 poke_milo();
 255         }
 256 }