arch/arm/mach-omap2/clock24xx.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock.c
   3  *
   4  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2008 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  *  Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
  12  *  Gordon McNutt and RidgeRun, Inc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18 #undef DEBUG
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/device.h>
  23 #include <linux/list.h>
  24 #include <linux/errno.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/bitops.h>
  30
  31 #include <mach/clock.h>
  32 #include <mach/sram.h>
  33 #include <asm/div64.h>
  34
  35 #include "memory.h"
  36 #include "clock.h"
  37 #include "clock24xx.h"
  38 #include "prm.h"
  39 #include "prm-regbits-24xx.h"
  40 #include "cm.h"
  41 #include "cm-regbits-24xx.h"
  42
  43 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
  44 #define EN_APLL_STOPPED                 0
  45 #define EN_APLL_LOCKED                  3
  46
  47 /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */
  48 #define APLLS_CLKIN_19_2MHZ             0
  49 #define APLLS_CLKIN_13MHZ               2
  50 #define APLLS_CLKIN_12MHZ               3
  51
  52 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
  53
  54 static struct prcm_config *curr_prcm_set;
  55 static struct clk *vclk;
  56 static struct clk *sclk;
  57
  58 /*-------------------------------------------------------------------------
  59  * Omap24xx specific clock functions
  60  *-------------------------------------------------------------------------*/
  61
  62 /* This actually returns the rate of core_ck, not dpll_ck. */
  63 static u32 omap2_get_dpll_rate_24xx(struct clk *tclk)
  64 {
  65         long long dpll_clk;
  66         u8 amult;
  67
  68         dpll_clk = omap2_get_dpll_rate(tclk);
  69
  70         amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
  71         amult &= OMAP24XX_CORE_CLK_SRC_MASK;
  72         dpll_clk *= amult;
  73
  74         return dpll_clk;
  75 }
  76
  77 static int omap2_enable_osc_ck(struct clk *clk)
  78 {
  79         u32 pcc;
  80
  81         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
  82
  83         __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
  84                       OMAP24XX_PRCM_CLKSRC_CTRL);
  85
  86         return 0;
  87 }
  88
  89 static void omap2_disable_osc_ck(struct clk *clk)
  90 {
  91         u32 pcc;
  92
  93         pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
  94
  95         __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
  96                       OMAP24XX_PRCM_CLKSRC_CTRL);
  97 }
  98
  99 #ifdef OLD_CK
 100 /* Recalculate SYST_CLK */
 101 static void omap2_sys_clk_recalc(struct clk * clk)
 102 {
 103         u32 div = PRCM_CLKSRC_CTRL;
 104         div &= (1 << 7) | (1 << 6);     /* Test if ext clk divided by 1 or 2 */
 105         div >>= clk->rate_offset;
 106         clk->rate = (clk->parent->rate / div);
 107         propagate_rate(clk);
 108 }
 109 #endif  /* OLD_CK */
 110
 111 /* Enable an APLL if off */
 112 static int omap2_clk_fixed_enable(struct clk *clk)
 113 {
 114         u32 cval, apll_mask;
 115
 116         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 117
 118         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 119
 120         if ((cval & apll_mask) == apll_mask)
 121                 return 0;   /* apll already enabled */
 122
 123         cval &= ~apll_mask;
 124         cval |= apll_mask;
 125         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 126
 127         if (clk == &apll96_ck)
 128                 cval = OMAP24XX_ST_96M_APLL;
 129         else if (clk == &apll54_ck)
 130                 cval = OMAP24XX_ST_54M_APLL;
 131
 132         omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
 133                             clk->name);
 134
 135         /*
 136          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
 137          * fails?
 138          */
 139         return 0;
 140 }
 141
 142 /* Stop APLL */
 143 static void omap2_clk_fixed_disable(struct clk *clk)
 144 {
 145         u32 cval;
 146
 147         cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 148         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
 149         cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 150 }
 151
 152 /*
 153  * Uses the current prcm set to tell if a rate is valid.
 154  * You can go slower, but not faster within a given rate set.
 155  */
 156 long omap2_dpllcore_round_rate(unsigned long target_rate)
 157 {
 158         u32 high, low, core_clk_src;
 159
 160         core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 161         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 162
 163         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
 164                 high = curr_prcm_set->dpll_speed * 2;
 165                 low = curr_prcm_set->dpll_speed;
 166         } else {                                /* DPLL clockout x 2 */
 167                 high = curr_prcm_set->dpll_speed;
 168                 low = curr_prcm_set->dpll_speed / 2;
 169         }
 170
 171 #ifdef DOWN_VARIABLE_DPLL
 172         if (target_rate > high)
 173                 return high;
 174         else
 175                 return target_rate;
 176 #else
 177         if (target_rate > low)
 178                 return high;
 179         else
 180                 return low;
 181 #endif
 182
 183 }
 184
 185 static void omap2_dpllcore_recalc(struct clk *clk)
 186 {
 187         clk->rate = omap2_get_dpll_rate_24xx(clk);
 188
 189         propagate_rate(clk);
 190 }
 191
 192 static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
 193 {
 194         u32 cur_rate, low, mult, div, valid_rate, done_rate;
 195         u32 bypass = 0;
 196         struct prcm_config tmpset;
 197         const struct dpll_data *dd;
 198         unsigned long flags;
 199         int ret = -EINVAL;
 200
 201         local_irq_save(flags);
 202         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 203         mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 204         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 205
 206         if ((rate == (cur_rate / 2)) && (mult == 2)) {
 207                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 208         } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
 209                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 210         } else if (rate != cur_rate) {
 211                 valid_rate = omap2_dpllcore_round_rate(rate);
 212                 if (valid_rate != rate)
 213                         goto dpll_exit;
 214
 215                 if (mult == 1)
 216                         low = curr_prcm_set->dpll_speed;
 217                 else
 218                         low = curr_prcm_set->dpll_speed / 2;
 219
 220                 dd = clk->dpll_data;
 221                 if (!dd)
 222                         goto dpll_exit;
 223
 224                 tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
 225                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
 226                                            dd->div1_mask);
 227                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
 228                 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
 229                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
 230                 if (rate > low) {
 231                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
 232                         mult = ((rate / 2) / 1000000);
 233                         done_rate = CORE_CLK_SRC_DPLL_X2;
 234                 } else {
 235                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL;
 236                         mult = (rate / 1000000);
 237                         done_rate = CORE_CLK_SRC_DPLL;
 238                 }
 239                 tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask));
 240                 tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask));
 241
 242                 /* Worst case */
 243                 tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS;
 244
 245                 if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
 246                         bypass = 1;
 247
 248                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
 249
 250                 /* Force dll lock mode */
 251                 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
 252                                bypass);
 253
 254                 /* Errata: ret dll entry state */
 255                 omap2_init_memory_params(omap2_dll_force_needed());
 256                 omap2_reprogram_sdrc(done_rate, 0);
 257         }
 258         omap2_dpllcore_recalc(&dpll_ck);
 259         ret = 0;
 260
 261 dpll_exit:
 262         local_irq_restore(flags);
 263         return(ret);
 264 }
 265
 266 /**
 267  * omap2_table_mpu_recalc - just return the MPU speed
 268  * @clk: virt_prcm_set struct clk
 269  *
 270  * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
 271  */
 272 static void omap2_table_mpu_recalc(struct clk *clk)
 273 {
 274         clk->rate = curr_prcm_set->mpu_speed;
 275 }
 276
 277 /*
 278  * Look for a rate equal or less than the target rate given a configuration set.
 279  *
 280  * What's not entirely clear is "which" field represents the key field.
 281  * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
 282  * just uses the ARM rates.
 283  */
 284 static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 285 {
 286         struct prcm_config *ptr;
 287         long highest_rate;
 288
 289         if (clk != &virt_prcm_set)
 290                 return -EINVAL;
 291
 292         highest_rate = -EINVAL;
 293
 294         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
 295                 if (!(ptr->flags & cpu_mask))
 296                         continue;
 297                 if (ptr->xtal_speed != sys_ck.rate)
 298                         continue;
 299
 300                 highest_rate = ptr->mpu_speed;
 301
 302                 /* Can check only after xtal frequency check */
 303                 if (ptr->mpu_speed <= rate)
 304                         break;
 305         }
 306         return highest_rate;
 307 }
 308
 309 /* Sets basic clocks based on the specified rate */
 310 static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 311 {
 312         u32 cur_rate, done_rate, bypass = 0, tmp;
 313         struct prcm_config *prcm;
 314         unsigned long found_speed = 0;
 315         unsigned long flags;
 316
 317         if (clk != &virt_prcm_set)
 318                 return -EINVAL;
 319
 320         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 321                 if (!(prcm->flags & cpu_mask))
 322                         continue;
 323
 324                 if (prcm->xtal_speed != sys_ck.rate)
 325                         continue;
 326
 327                 if (prcm->mpu_speed <= rate) {
 328                         found_speed = prcm->mpu_speed;
 329                         break;
 330                 }
 331         }
 332
 333         if (!found_speed) {
 334                 printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
 335                        rate / 1000000);
 336                 return -EINVAL;
 337         }
 338
 339         curr_prcm_set = prcm;
 340         cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 341
 342         if (prcm->dpll_speed == cur_rate / 2) {
 343                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
 344         } else if (prcm->dpll_speed == cur_rate * 2) {
 345                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 346         } else if (prcm->dpll_speed != cur_rate) {
 347                 local_irq_save(flags);
 348
 349                 if (prcm->dpll_speed == prcm->xtal_speed)
 350                         bypass = 1;
 351
 352                 if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
 353                     CORE_CLK_SRC_DPLL_X2)
 354                         done_rate = CORE_CLK_SRC_DPLL_X2;
 355                 else
 356                         done_rate = CORE_CLK_SRC_DPLL;
 357
 358                 /* MPU divider */
 359                 cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 360
 361                 /* dsp + iva1 div(2420), iva2.1(2430) */
 362                 cm_write_mod_reg(prcm->cm_clksel_dsp,
 363                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 364
 365                 cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 366
 367                 /* Major subsystem dividers */
 368                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
 369                 cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
 370                 if (cpu_is_omap2430())
 371                         cm_write_mod_reg(prcm->cm_clksel_mdm,
 372                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 373
 374                 /* x2 to enter init_mem */
 375                 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
 376
 377                 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
 378                                bypass);
 379
 380                 omap2_init_memory_params(omap2_dll_force_needed());
 381                 omap2_reprogram_sdrc(done_rate, 0);
 382
 383                 local_irq_restore(flags);
 384         }
 385         omap2_dpllcore_recalc(&dpll_ck);
 386
 387         return 0;
 388 }
 389
 390 static struct clk_functions omap2_clk_functions = {
 391         .clk_enable             = omap2_clk_enable,
 392         .clk_disable            = omap2_clk_disable,
 393         .clk_round_rate         = omap2_clk_round_rate,
 394         .clk_set_rate           = omap2_clk_set_rate,
 395         .clk_set_parent         = omap2_clk_set_parent,
 396         .clk_disable_unused     = omap2_clk_disable_unused,
 397 };
 398
 399 static u32 omap2_get_apll_clkin(void)
 400 {
 401         u32 aplls, sclk = 0;
 402
 403         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
 404         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
 405         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 406
 407         if (aplls == APLLS_CLKIN_19_2MHZ)
 408                 sclk = 19200000;
 409         else if (aplls == APLLS_CLKIN_13MHZ)
 410                 sclk = 13000000;
 411         else if (aplls == APLLS_CLKIN_12MHZ)
 412                 sclk = 12000000;
 413
 414         return sclk;
 415 }
 416
 417 static u32 omap2_get_sysclkdiv(void)
 418 {
 419         u32 div;
 420
 421         div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
 422         div &= OMAP_SYSCLKDIV_MASK;
 423         div >>= OMAP_SYSCLKDIV_SHIFT;
 424
 425         return div;
 426 }
 427
 428 static void omap2_osc_clk_recalc(struct clk *clk)
 429 {
 430         clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv();
 431         propagate_rate(clk);
 432 }
 433
 434 static void omap2_sys_clk_recalc(struct clk *clk)
 435 {
 436         clk->rate = clk->parent->rate / omap2_get_sysclkdiv();
 437         propagate_rate(clk);
 438 }
 439
 440 /*
 441  * Set clocks for bypass mode for reboot to work.
 442  */
 443 void omap2_clk_prepare_for_reboot(void)
 444 {
 445         u32 rate;
 446
 447         if (vclk == NULL || sclk == NULL)
 448                 return;
 449
 450         rate = clk_get_rate(sclk);
 451         clk_set_rate(vclk, rate);
 452 }
 453
 454 /*
 455  * Switch the MPU rate if specified on cmdline.
 456  * We cannot do this early until cmdline is parsed.
 457  */
 458 static int __init omap2_clk_arch_init(void)
 459 {
 460         if (!mpurate)
 461                 return -EINVAL;
 462
 463         if (omap2_select_table_rate(&virt_prcm_set, mpurate))
 464                 printk(KERN_ERR "Could not find matching MPU rate\n");
 465
 466         recalculate_root_clocks();
 467
 468         printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): "
 469                "%ld.%01ld/%ld/%ld MHz\n",
 470                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 471                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 472
 473         return 0;
 474 }
 475 arch_initcall(omap2_clk_arch_init);
 476
 477 int __init omap2_clk_init(void)
 478 {
 479         struct prcm_config *prcm;
 480         struct clk **clkp;
 481         u32 clkrate;
 482
 483         if (cpu_is_omap242x())
 484                 cpu_mask = RATE_IN_242X;
 485         else if (cpu_is_omap2430())
 486                 cpu_mask = RATE_IN_243X;
 487
 488         clk_init(&omap2_clk_functions);
 489
 490         omap2_osc_clk_recalc(&osc_ck);
 491         omap2_sys_clk_recalc(&sys_ck);
 492
 493         for (clkp = onchip_24xx_clks;
 494              clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks);
 495              clkp++) {
 496
 497                 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) {
 498                         clk_register(*clkp);
 499                         continue;
 500                 }
 501
 502                 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) {
 503                         clk_register(*clkp);
 504                         continue;
 505                 }
 506         }
 507
 508         /* Check the MPU rate set by bootloader */
 509         clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
 510         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
 511                 if (!(prcm->flags & cpu_mask))
 512                         continue;
 513                 if (prcm->xtal_speed != sys_ck.rate)
 514                         continue;
 515                 if (prcm->dpll_speed <= clkrate)
 516                          break;
 517         }
 518         curr_prcm_set = prcm;
 519
 520         recalculate_root_clocks();
 521
 522         printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
 523                "%ld.%01ld/%ld/%ld MHz\n",
 524                (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
 525                (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
 526
 527         /*
 528          * Only enable those clocks we will need, let the drivers
 529          * enable other clocks as necessary
 530          */
 531         clk_enable_init_clocks();
 532
 533         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
 534         vclk = clk_get(NULL, "virt_prcm_set");
 535         sclk = clk_get(NULL, "sys_ck");
 536
 537         return 0;
 538 }