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[TG3]: Fix 2nd ifup failure on 5752M.
[linux-2.6/mini2440.git] / drivers / net / tg3.c
blob8f059b7968bd71aba86ce4226cb0ee3e6e5d97de
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
26 #include <linux/in.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
41
42 #include <net/checksum.h>
43
44 #include <asm/system.h>
45 #include <asm/io.h>
46 #include <asm/byteorder.h>
47 #include <asm/uaccess.h>
48
49 #ifdef CONFIG_SPARC64
50 #include <asm/idprom.h>
51 #include <asm/oplib.h>
52 #include <asm/pbm.h>
53 #endif
54
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
57 #else
58 #define TG3_VLAN_TAG_USED 0
59 #endif
60
61 #ifdef NETIF_F_TSO
62 #define TG3_TSO_SUPPORT 1
63 #else
64 #define TG3_TSO_SUPPORT 0
65 #endif
66
67 #include "tg3.h"
68
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.68"
72 #define DRV_MODULE_RELDATE "November 02, 2006"
73
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
78 (NETIF_MSG_DRV | \
79 NETIF_MSG_PROBE | \
80 NETIF_MSG_LINK | \
81 NETIF_MSG_TIMER | \
82 NETIF_MSG_IFDOWN | \
83 NETIF_MSG_IFUP | \
84 NETIF_MSG_RX_ERR | \
85 NETIF_MSG_TX_ERR)
86
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
89 */
90 #define TG3_TX_TIMEOUT (5 * HZ)
91
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
96
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
100 */
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
111 */
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
114
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
117
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RING_SIZE)
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
125 TG3_TX_RING_SIZE)
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
127
128 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
129 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
130
131 /* minimum number of free TX descriptors required to wake up TX process */
132 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
133
134 /* number of ETHTOOL_GSTATS u64's */
135 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
136
137 #define TG3_NUM_TEST 6
138
139 static char version[] __devinitdata =
140 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
141
142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
144 MODULE_LICENSE("GPL");
145 MODULE_VERSION(DRV_MODULE_VERSION);
146
147 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
148 module_param(tg3_debug, int, 0);
149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
150
151 static struct pci_device_id tg3_pci_tbl[] = {
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
204 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
205 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
207 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
208 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
209 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
210 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
211 {}
212 };
213
214 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
215
216 static const struct {
217 const char string[ETH_GSTRING_LEN];
218 } ethtool_stats_keys[TG3_NUM_STATS] = {
219 { "rx_octets" },
220 { "rx_fragments" },
221 { "rx_ucast_packets" },
222 { "rx_mcast_packets" },
223 { "rx_bcast_packets" },
224 { "rx_fcs_errors" },
225 { "rx_align_errors" },
226 { "rx_xon_pause_rcvd" },
227 { "rx_xoff_pause_rcvd" },
228 { "rx_mac_ctrl_rcvd" },
229 { "rx_xoff_entered" },
230 { "rx_frame_too_long_errors" },
231 { "rx_jabbers" },
232 { "rx_undersize_packets" },
233 { "rx_in_length_errors" },
234 { "rx_out_length_errors" },
235 { "rx_64_or_less_octet_packets" },
236 { "rx_65_to_127_octet_packets" },
237 { "rx_128_to_255_octet_packets" },
238 { "rx_256_to_511_octet_packets" },
239 { "rx_512_to_1023_octet_packets" },
240 { "rx_1024_to_1522_octet_packets" },
241 { "rx_1523_to_2047_octet_packets" },
242 { "rx_2048_to_4095_octet_packets" },
243 { "rx_4096_to_8191_octet_packets" },
244 { "rx_8192_to_9022_octet_packets" },
245
246 { "tx_octets" },
247 { "tx_collisions" },
248
249 { "tx_xon_sent" },
250 { "tx_xoff_sent" },
251 { "tx_flow_control" },
252 { "tx_mac_errors" },
253 { "tx_single_collisions" },
254 { "tx_mult_collisions" },
255 { "tx_deferred" },
256 { "tx_excessive_collisions" },
257 { "tx_late_collisions" },
258 { "tx_collide_2times" },
259 { "tx_collide_3times" },
260 { "tx_collide_4times" },
261 { "tx_collide_5times" },
262 { "tx_collide_6times" },
263 { "tx_collide_7times" },
264 { "tx_collide_8times" },
265 { "tx_collide_9times" },
266 { "tx_collide_10times" },
267 { "tx_collide_11times" },
268 { "tx_collide_12times" },
269 { "tx_collide_13times" },
270 { "tx_collide_14times" },
271 { "tx_collide_15times" },
272 { "tx_ucast_packets" },
273 { "tx_mcast_packets" },
274 { "tx_bcast_packets" },
275 { "tx_carrier_sense_errors" },
276 { "tx_discards" },
277 { "tx_errors" },
278
279 { "dma_writeq_full" },
280 { "dma_write_prioq_full" },
281 { "rxbds_empty" },
282 { "rx_discards" },
283 { "rx_errors" },
284 { "rx_threshold_hit" },
285
286 { "dma_readq_full" },
287 { "dma_read_prioq_full" },
288 { "tx_comp_queue_full" },
289
290 { "ring_set_send_prod_index" },
291 { "ring_status_update" },
292 { "nic_irqs" },
293 { "nic_avoided_irqs" },
294 { "nic_tx_threshold_hit" }
295 };
296
297 static const struct {
298 const char string[ETH_GSTRING_LEN];
299 } ethtool_test_keys[TG3_NUM_TEST] = {
300 { "nvram test (online) " },
301 { "link test (online) " },
302 { "register test (offline)" },
303 { "memory test (offline)" },
304 { "loopback test (offline)" },
305 { "interrupt test (offline)" },
306 };
307
308 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
309 {
310 writel(val, tp->regs + off);
311 }
312
313 static u32 tg3_read32(struct tg3 *tp, u32 off)
314 {
315 return (readl(tp->regs + off));
316 }
317
318 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
319 {
320 unsigned long flags;
321
322 spin_lock_irqsave(&tp->indirect_lock, flags);
323 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325 spin_unlock_irqrestore(&tp->indirect_lock, flags);
326 }
327
328 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
329 {
330 writel(val, tp->regs + off);
331 readl(tp->regs + off);
332 }
333
334 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
335 {
336 unsigned long flags;
337 u32 val;
338
339 spin_lock_irqsave(&tp->indirect_lock, flags);
340 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
341 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
342 spin_unlock_irqrestore(&tp->indirect_lock, flags);
343 return val;
344 }
345
346 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
347 {
348 unsigned long flags;
349
350 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
351 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
352 TG3_64BIT_REG_LOW, val);
353 return;
354 }
355 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
356 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
357 TG3_64BIT_REG_LOW, val);
358 return;
359 }
360
361 spin_lock_irqsave(&tp->indirect_lock, flags);
362 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
363 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
364 spin_unlock_irqrestore(&tp->indirect_lock, flags);
365
366 /* In indirect mode when disabling interrupts, we also need
367 * to clear the interrupt bit in the GRC local ctrl register.
368 */
369 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
370 (val == 0x1)) {
371 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
372 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
373 }
374 }
375
376 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
377 {
378 unsigned long flags;
379 u32 val;
380
381 spin_lock_irqsave(&tp->indirect_lock, flags);
382 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
383 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
384 spin_unlock_irqrestore(&tp->indirect_lock, flags);
385 return val;
386 }
387
388 /* usec_wait specifies the wait time in usec when writing to certain registers
389 * where it is unsafe to read back the register without some delay.
390 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
391 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
392 */
393 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
394 {
395 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
396 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
397 /* Non-posted methods */
398 tp->write32(tp, off, val);
399 else {
400 /* Posted method */
401 tg3_write32(tp, off, val);
402 if (usec_wait)
403 udelay(usec_wait);
404 tp->read32(tp, off);
405 }
406 /* Wait again after the read for the posted method to guarantee that
407 * the wait time is met.
408 */
409 if (usec_wait)
410 udelay(usec_wait);
411 }
412
413 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
414 {
415 tp->write32_mbox(tp, off, val);
416 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
417 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
418 tp->read32_mbox(tp, off);
419 }
420
421 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
422 {
423 void __iomem *mbox = tp->regs + off;
424 writel(val, mbox);
425 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
426 writel(val, mbox);
427 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
428 readl(mbox);
429 }
430
431 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
432 {
433 return (readl(tp->regs + off + GRCMBOX_BASE));
434 }
435
436 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
437 {
438 writel(val, tp->regs + off + GRCMBOX_BASE);
439 }
440
441 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
442 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
443 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
444 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
445 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
446
447 #define tw32(reg,val) tp->write32(tp, reg, val)
448 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
449 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
450 #define tr32(reg) tp->read32(tp, reg)
451
452 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
453 {
454 unsigned long flags;
455
456 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
457 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
458 return;
459
460 spin_lock_irqsave(&tp->indirect_lock, flags);
461 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
462 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
464
465 /* Always leave this as zero. */
466 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
467 } else {
468 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
469 tw32_f(TG3PCI_MEM_WIN_DATA, val);
470
471 /* Always leave this as zero. */
472 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
473 }
474 spin_unlock_irqrestore(&tp->indirect_lock, flags);
475 }
476
477 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
478 {
479 unsigned long flags;
480
481 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
482 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
483 *val = 0;
484 return;
485 }
486
487 spin_lock_irqsave(&tp->indirect_lock, flags);
488 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
489 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
490 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
491
492 /* Always leave this as zero. */
493 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
494 } else {
495 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
496 *val = tr32(TG3PCI_MEM_WIN_DATA);
497
498 /* Always leave this as zero. */
499 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
500 }
501 spin_unlock_irqrestore(&tp->indirect_lock, flags);
502 }
503
504 static void tg3_disable_ints(struct tg3 *tp)
505 {
506 tw32(TG3PCI_MISC_HOST_CTRL,
507 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
508 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
509 }
510
511 static inline void tg3_cond_int(struct tg3 *tp)
512 {
513 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
514 (tp->hw_status->status & SD_STATUS_UPDATED))
515 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
516 else
517 tw32(HOSTCC_MODE, tp->coalesce_mode |
518 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
519 }
520
521 static void tg3_enable_ints(struct tg3 *tp)
522 {
523 tp->irq_sync = 0;
524 wmb();
525
526 tw32(TG3PCI_MISC_HOST_CTRL,
527 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
530 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
531 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
532 (tp->last_tag << 24));
533 tg3_cond_int(tp);
534 }
535
536 static inline unsigned int tg3_has_work(struct tg3 *tp)
537 {
538 struct tg3_hw_status *sblk = tp->hw_status;
539 unsigned int work_exists = 0;
540
541 /* check for phy events */
542 if (!(tp->tg3_flags &
543 (TG3_FLAG_USE_LINKCHG_REG |
544 TG3_FLAG_POLL_SERDES))) {
545 if (sblk->status & SD_STATUS_LINK_CHG)
546 work_exists = 1;
547 }
548 /* check for RX/TX work to do */
549 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
550 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
551 work_exists = 1;
552
553 return work_exists;
554 }
555
556 /* tg3_restart_ints
557 * similar to tg3_enable_ints, but it accurately determines whether there
558 * is new work pending and can return without flushing the PIO write
559 * which reenables interrupts
560 */
561 static void tg3_restart_ints(struct tg3 *tp)
562 {
563 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
564 tp->last_tag << 24);
565 mmiowb();
566
567 /* When doing tagged status, this work check is unnecessary.
568 * The last_tag we write above tells the chip which piece of
569 * work we've completed.
570 */
571 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
572 tg3_has_work(tp))
573 tw32(HOSTCC_MODE, tp->coalesce_mode |
574 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
575 }
576
577 static inline void tg3_netif_stop(struct tg3 *tp)
578 {
579 tp->dev->trans_start = jiffies; /* prevent tx timeout */
580 netif_poll_disable(tp->dev);
581 netif_tx_disable(tp->dev);
582 }
583
584 static inline void tg3_netif_start(struct tg3 *tp)
585 {
586 netif_wake_queue(tp->dev);
587 /* NOTE: unconditional netif_wake_queue is only appropriate
588 * so long as all callers are assured to have free tx slots
589 * (such as after tg3_init_hw)
590 */
591 netif_poll_enable(tp->dev);
592 tp->hw_status->status |= SD_STATUS_UPDATED;
593 tg3_enable_ints(tp);
594 }
595
596 static void tg3_switch_clocks(struct tg3 *tp)
597 {
598 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
599 u32 orig_clock_ctrl;
600
601 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
602 return;
603
604 orig_clock_ctrl = clock_ctrl;
605 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
606 CLOCK_CTRL_CLKRUN_OENABLE |
607 0x1f);
608 tp->pci_clock_ctrl = clock_ctrl;
609
610 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
611 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
612 tw32_wait_f(TG3PCI_CLOCK_CTRL,
613 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
614 }
615 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
616 tw32_wait_f(TG3PCI_CLOCK_CTRL,
617 clock_ctrl |
618 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
619 40);
620 tw32_wait_f(TG3PCI_CLOCK_CTRL,
621 clock_ctrl | (CLOCK_CTRL_ALTCLK),
622 40);
623 }
624 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
625 }
626
627 #define PHY_BUSY_LOOPS 5000
628
629 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
630 {
631 u32 frame_val;
632 unsigned int loops;
633 int ret;
634
635 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
636 tw32_f(MAC_MI_MODE,
637 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
638 udelay(80);
639 }
640
641 *val = 0x0;
642
643 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
644 MI_COM_PHY_ADDR_MASK);
645 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
646 MI_COM_REG_ADDR_MASK);
647 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
648
649 tw32_f(MAC_MI_COM, frame_val);
650
651 loops = PHY_BUSY_LOOPS;
652 while (loops != 0) {
653 udelay(10);
654 frame_val = tr32(MAC_MI_COM);
655
656 if ((frame_val & MI_COM_BUSY) == 0) {
657 udelay(5);
658 frame_val = tr32(MAC_MI_COM);
659 break;
660 }
661 loops -= 1;
662 }
663
664 ret = -EBUSY;
665 if (loops != 0) {
666 *val = frame_val & MI_COM_DATA_MASK;
667 ret = 0;
668 }
669
670 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
671 tw32_f(MAC_MI_MODE, tp->mi_mode);
672 udelay(80);
673 }
674
675 return ret;
676 }
677
678 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
679 {
680 u32 frame_val;
681 unsigned int loops;
682 int ret;
683
684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
685 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
686 return 0;
687
688 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
689 tw32_f(MAC_MI_MODE,
690 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
691 udelay(80);
692 }
693
694 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
695 MI_COM_PHY_ADDR_MASK);
696 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
697 MI_COM_REG_ADDR_MASK);
698 frame_val |= (val & MI_COM_DATA_MASK);
699 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
700
701 tw32_f(MAC_MI_COM, frame_val);
702
703 loops = PHY_BUSY_LOOPS;
704 while (loops != 0) {
705 udelay(10);
706 frame_val = tr32(MAC_MI_COM);
707 if ((frame_val & MI_COM_BUSY) == 0) {
708 udelay(5);
709 frame_val = tr32(MAC_MI_COM);
710 break;
711 }
712 loops -= 1;
713 }
714
715 ret = -EBUSY;
716 if (loops != 0)
717 ret = 0;
718
719 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
720 tw32_f(MAC_MI_MODE, tp->mi_mode);
721 udelay(80);
722 }
723
724 return ret;
725 }
726
727 static void tg3_phy_set_wirespeed(struct tg3 *tp)
728 {
729 u32 val;
730
731 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
732 return;
733
734 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
735 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
736 tg3_writephy(tp, MII_TG3_AUX_CTRL,
737 (val | (1 << 15) | (1 << 4)));
738 }
739
740 static int tg3_bmcr_reset(struct tg3 *tp)
741 {
742 u32 phy_control;
743 int limit, err;
744
745 /* OK, reset it, and poll the BMCR_RESET bit until it
746 * clears or we time out.
747 */
748 phy_control = BMCR_RESET;
749 err = tg3_writephy(tp, MII_BMCR, phy_control);
750 if (err != 0)
751 return -EBUSY;
752
753 limit = 5000;
754 while (limit--) {
755 err = tg3_readphy(tp, MII_BMCR, &phy_control);
756 if (err != 0)
757 return -EBUSY;
758
759 if ((phy_control & BMCR_RESET) == 0) {
760 udelay(40);
761 break;
762 }
763 udelay(10);
764 }
765 if (limit <= 0)
766 return -EBUSY;
767
768 return 0;
769 }
770
771 static int tg3_wait_macro_done(struct tg3 *tp)
772 {
773 int limit = 100;
774
775 while (limit--) {
776 u32 tmp32;
777
778 if (!tg3_readphy(tp, 0x16, &tmp32)) {
779 if ((tmp32 & 0x1000) == 0)
780 break;
781 }
782 }
783 if (limit <= 0)
784 return -EBUSY;
785
786 return 0;
787 }
788
789 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
790 {
791 static const u32 test_pat[4][6] = {
792 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
793 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
794 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
795 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
796 };
797 int chan;
798
799 for (chan = 0; chan < 4; chan++) {
800 int i;
801
802 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
803 (chan * 0x2000) | 0x0200);
804 tg3_writephy(tp, 0x16, 0x0002);
805
806 for (i = 0; i < 6; i++)
807 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
808 test_pat[chan][i]);
809
810 tg3_writephy(tp, 0x16, 0x0202);
811 if (tg3_wait_macro_done(tp)) {
812 *resetp = 1;
813 return -EBUSY;
814 }
815
816 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
817 (chan * 0x2000) | 0x0200);
818 tg3_writephy(tp, 0x16, 0x0082);
819 if (tg3_wait_macro_done(tp)) {
820 *resetp = 1;
821 return -EBUSY;
822 }
823
824 tg3_writephy(tp, 0x16, 0x0802);
825 if (tg3_wait_macro_done(tp)) {
826 *resetp = 1;
827 return -EBUSY;
828 }
829
830 for (i = 0; i < 6; i += 2) {
831 u32 low, high;
832
833 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
834 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
835 tg3_wait_macro_done(tp)) {
836 *resetp = 1;
837 return -EBUSY;
838 }
839 low &= 0x7fff;
840 high &= 0x000f;
841 if (low != test_pat[chan][i] ||
842 high != test_pat[chan][i+1]) {
843 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
844 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
845 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
846
847 return -EBUSY;
848 }
849 }
850 }
851
852 return 0;
853 }
854
855 static int tg3_phy_reset_chanpat(struct tg3 *tp)
856 {
857 int chan;
858
859 for (chan = 0; chan < 4; chan++) {
860 int i;
861
862 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
863 (chan * 0x2000) | 0x0200);
864 tg3_writephy(tp, 0x16, 0x0002);
865 for (i = 0; i < 6; i++)
866 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
867 tg3_writephy(tp, 0x16, 0x0202);
868 if (tg3_wait_macro_done(tp))
869 return -EBUSY;
870 }
871
872 return 0;
873 }
874
875 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
876 {
877 u32 reg32, phy9_orig;
878 int retries, do_phy_reset, err;
879
880 retries = 10;
881 do_phy_reset = 1;
882 do {
883 if (do_phy_reset) {
884 err = tg3_bmcr_reset(tp);
885 if (err)
886 return err;
887 do_phy_reset = 0;
888 }
889
890 /* Disable transmitter and interrupt. */
891 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
892 continue;
893
894 reg32 |= 0x3000;
895 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
896
897 /* Set full-duplex, 1000 mbps. */
898 tg3_writephy(tp, MII_BMCR,
899 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
900
901 /* Set to master mode. */
902 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
903 continue;
904
905 tg3_writephy(tp, MII_TG3_CTRL,
906 (MII_TG3_CTRL_AS_MASTER |
907 MII_TG3_CTRL_ENABLE_AS_MASTER));
908
909 /* Enable SM_DSP_CLOCK and 6dB. */
910 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
911
912 /* Block the PHY control access. */
913 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
914 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
915
916 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
917 if (!err)
918 break;
919 } while (--retries);
920
921 err = tg3_phy_reset_chanpat(tp);
922 if (err)
923 return err;
924
925 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
926 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
927
928 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
929 tg3_writephy(tp, 0x16, 0x0000);
930
931 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
932 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
933 /* Set Extended packet length bit for jumbo frames */
934 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
935 }
936 else {
937 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
938 }
939
940 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
941
942 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
943 reg32 &= ~0x3000;
944 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
945 } else if (!err)
946 err = -EBUSY;
947
948 return err;
949 }
950
951 static void tg3_link_report(struct tg3 *);
952
953 /* This will reset the tigon3 PHY if there is no valid
954 * link unless the FORCE argument is non-zero.
955 */
956 static int tg3_phy_reset(struct tg3 *tp)
957 {
958 u32 phy_status;
959 int err;
960
961 err = tg3_readphy(tp, MII_BMSR, &phy_status);
962 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
963 if (err != 0)
964 return -EBUSY;
965
966 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
967 netif_carrier_off(tp->dev);
968 tg3_link_report(tp);
969 }
970
971 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
972 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
973 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
974 err = tg3_phy_reset_5703_4_5(tp);
975 if (err)
976 return err;
977 goto out;
978 }
979
980 err = tg3_bmcr_reset(tp);
981 if (err)
982 return err;
983
984 out:
985 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
986 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
987 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
988 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
989 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
990 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
991 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
992 }
993 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
994 tg3_writephy(tp, 0x1c, 0x8d68);
995 tg3_writephy(tp, 0x1c, 0x8d68);
996 }
997 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
998 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
999 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1000 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1001 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1002 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1003 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1004 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1005 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1006 }
1007 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1008 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1009 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1010 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1011 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1012 }
1013 /* Set Extended packet length bit (bit 14) on all chips that */
1014 /* support jumbo frames */
1015 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1016 /* Cannot do read-modify-write on 5401 */
1017 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1018 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1019 u32 phy_reg;
1020
1021 /* Set bit 14 with read-modify-write to preserve other bits */
1022 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1023 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1025 }
1026
1027 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1028 * jumbo frames transmission.
1029 */
1030 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1031 u32 phy_reg;
1032
1033 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1034 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1035 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1036 }
1037
1038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1039 u32 phy_reg;
1040
1041 /* adjust output voltage */
1042 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1043
1044 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1045 u32 phy_reg2;
1046
1047 tg3_writephy(tp, MII_TG3_EPHY_TEST,
1048 phy_reg | MII_TG3_EPHY_SHADOW_EN);
1049 /* Enable auto-MDIX */
1050 if (!tg3_readphy(tp, 0x10, &phy_reg2))
1051 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1052 tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1053 }
1054 }
1055
1056 tg3_phy_set_wirespeed(tp);
1057 return 0;
1058 }
1059
1060 static void tg3_frob_aux_power(struct tg3 *tp)
1061 {
1062 struct tg3 *tp_peer = tp;
1063
1064 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1065 return;
1066
1067 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1068 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1069 struct net_device *dev_peer;
1070
1071 dev_peer = pci_get_drvdata(tp->pdev_peer);
1072 /* remove_one() may have been run on the peer. */
1073 if (!dev_peer)
1074 tp_peer = tp;
1075 else
1076 tp_peer = netdev_priv(dev_peer);
1077 }
1078
1079 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1080 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1081 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1082 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1085 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1086 (GRC_LCLCTRL_GPIO_OE0 |
1087 GRC_LCLCTRL_GPIO_OE1 |
1088 GRC_LCLCTRL_GPIO_OE2 |
1089 GRC_LCLCTRL_GPIO_OUTPUT0 |
1090 GRC_LCLCTRL_GPIO_OUTPUT1),
1091 100);
1092 } else {
1093 u32 no_gpio2;
1094 u32 grc_local_ctrl = 0;
1095
1096 if (tp_peer != tp &&
1097 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1098 return;
1099
1100 /* Workaround to prevent overdrawing Amps. */
1101 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1102 ASIC_REV_5714) {
1103 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1104 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1105 grc_local_ctrl, 100);
1106 }
1107
1108 /* On 5753 and variants, GPIO2 cannot be used. */
1109 no_gpio2 = tp->nic_sram_data_cfg &
1110 NIC_SRAM_DATA_CFG_NO_GPIO2;
1111
1112 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1113 GRC_LCLCTRL_GPIO_OE1 |
1114 GRC_LCLCTRL_GPIO_OE2 |
1115 GRC_LCLCTRL_GPIO_OUTPUT1 |
1116 GRC_LCLCTRL_GPIO_OUTPUT2;
1117 if (no_gpio2) {
1118 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1119 GRC_LCLCTRL_GPIO_OUTPUT2);
1120 }
1121 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1122 grc_local_ctrl, 100);
1123
1124 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1125
1126 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1127 grc_local_ctrl, 100);
1128
1129 if (!no_gpio2) {
1130 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1131 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1132 grc_local_ctrl, 100);
1133 }
1134 }
1135 } else {
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1137 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1138 if (tp_peer != tp &&
1139 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1140 return;
1141
1142 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1143 (GRC_LCLCTRL_GPIO_OE1 |
1144 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1145
1146 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1147 GRC_LCLCTRL_GPIO_OE1, 100);
1148
1149 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1150 (GRC_LCLCTRL_GPIO_OE1 |
1151 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1152 }
1153 }
1154 }
1155
1156 static int tg3_setup_phy(struct tg3 *, int);
1157
1158 #define RESET_KIND_SHUTDOWN 0
1159 #define RESET_KIND_INIT 1
1160 #define RESET_KIND_SUSPEND 2
1161
1162 static void tg3_write_sig_post_reset(struct tg3 *, int);
1163 static int tg3_halt_cpu(struct tg3 *, u32);
1164 static int tg3_nvram_lock(struct tg3 *);
1165 static void tg3_nvram_unlock(struct tg3 *);
1166
1167 static void tg3_power_down_phy(struct tg3 *tp)
1168 {
1169 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1170 return;
1171
1172 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1173 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1174 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1175 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1176 }
1177
1178 /* The PHY should not be powered down on some chips because
1179 * of bugs.
1180 */
1181 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1182 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1183 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1184 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1185 return;
1186 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1187 }
1188
1189 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1190 {
1191 u32 misc_host_ctrl;
1192 u16 power_control, power_caps;
1193 int pm = tp->pm_cap;
1194
1195 /* Make sure register accesses (indirect or otherwise)
1196 * will function correctly.
1197 */
1198 pci_write_config_dword(tp->pdev,
1199 TG3PCI_MISC_HOST_CTRL,
1200 tp->misc_host_ctrl);
1201
1202 pci_read_config_word(tp->pdev,
1203 pm + PCI_PM_CTRL,
1204 &power_control);
1205 power_control |= PCI_PM_CTRL_PME_STATUS;
1206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1207 switch (state) {
1208 case PCI_D0:
1209 power_control |= 0;
1210 pci_write_config_word(tp->pdev,
1211 pm + PCI_PM_CTRL,
1212 power_control);
1213 udelay(100); /* Delay after power state change */
1214
1215 /* Switch out of Vaux if it is not a LOM */
1216 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1217 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1218
1219 return 0;
1220
1221 case PCI_D1:
1222 power_control |= 1;
1223 break;
1224
1225 case PCI_D2:
1226 power_control |= 2;
1227 break;
1228
1229 case PCI_D3hot:
1230 power_control |= 3;
1231 break;
1232
1233 default:
1234 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1235 "requested.\n",
1236 tp->dev->name, state);
1237 return -EINVAL;
1238 };
1239
1240 power_control |= PCI_PM_CTRL_PME_ENABLE;
1241
1242 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1243 tw32(TG3PCI_MISC_HOST_CTRL,
1244 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1245
1246 if (tp->link_config.phy_is_low_power == 0) {
1247 tp->link_config.phy_is_low_power = 1;
1248 tp->link_config.orig_speed = tp->link_config.speed;
1249 tp->link_config.orig_duplex = tp->link_config.duplex;
1250 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1251 }
1252
1253 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1254 tp->link_config.speed = SPEED_10;
1255 tp->link_config.duplex = DUPLEX_HALF;
1256 tp->link_config.autoneg = AUTONEG_ENABLE;
1257 tg3_setup_phy(tp, 0);
1258 }
1259
1260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1261 u32 val;
1262
1263 val = tr32(GRC_VCPU_EXT_CTRL);
1264 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1265 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1266 int i;
1267 u32 val;
1268
1269 for (i = 0; i < 200; i++) {
1270 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1271 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1272 break;
1273 msleep(1);
1274 }
1275 }
1276 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1277 WOL_DRV_STATE_SHUTDOWN |
1278 WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1279
1280 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1281
1282 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1283 u32 mac_mode;
1284
1285 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1286 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1287 udelay(40);
1288
1289 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1290 mac_mode = MAC_MODE_PORT_MODE_GMII;
1291 else
1292 mac_mode = MAC_MODE_PORT_MODE_MII;
1293
1294 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1295 !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1296 mac_mode |= MAC_MODE_LINK_POLARITY;
1297 } else {
1298 mac_mode = MAC_MODE_PORT_MODE_TBI;
1299 }
1300
1301 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1302 tw32(MAC_LED_CTRL, tp->led_ctrl);
1303
1304 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1305 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1306 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1307
1308 tw32_f(MAC_MODE, mac_mode);
1309 udelay(100);
1310
1311 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1312 udelay(10);
1313 }
1314
1315 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1316 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1317 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1318 u32 base_val;
1319
1320 base_val = tp->pci_clock_ctrl;
1321 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1322 CLOCK_CTRL_TXCLK_DISABLE);
1323
1324 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1325 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1326 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1327 /* do nothing */
1328 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1329 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1330 u32 newbits1, newbits2;
1331
1332 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1333 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1334 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1335 CLOCK_CTRL_TXCLK_DISABLE |
1336 CLOCK_CTRL_ALTCLK);
1337 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1338 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1339 newbits1 = CLOCK_CTRL_625_CORE;
1340 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1341 } else {
1342 newbits1 = CLOCK_CTRL_ALTCLK;
1343 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1344 }
1345
1346 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1347 40);
1348
1349 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1350 40);
1351
1352 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1353 u32 newbits3;
1354
1355 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1356 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1357 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1358 CLOCK_CTRL_TXCLK_DISABLE |
1359 CLOCK_CTRL_44MHZ_CORE);
1360 } else {
1361 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1362 }
1363
1364 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1365 tp->pci_clock_ctrl | newbits3, 40);
1366 }
1367 }
1368
1369 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1370 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1371 tg3_power_down_phy(tp);
1372
1373 tg3_frob_aux_power(tp);
1374
1375 /* Workaround for unstable PLL clock */
1376 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1377 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1378 u32 val = tr32(0x7d00);
1379
1380 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1381 tw32(0x7d00, val);
1382 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1383 int err;
1384
1385 err = tg3_nvram_lock(tp);
1386 tg3_halt_cpu(tp, RX_CPU_BASE);
1387 if (!err)
1388 tg3_nvram_unlock(tp);
1389 }
1390 }
1391
1392 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1393
1394 /* Finally, set the new power state. */
1395 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1396 udelay(100); /* Delay after power state change */
1397
1398 return 0;
1399 }
1400
1401 static void tg3_link_report(struct tg3 *tp)
1402 {
1403 if (!netif_carrier_ok(tp->dev)) {
1404 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1405 } else {
1406 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1407 tp->dev->name,
1408 (tp->link_config.active_speed == SPEED_1000 ?
1409 1000 :
1410 (tp->link_config.active_speed == SPEED_100 ?
1411 100 : 10)),
1412 (tp->link_config.active_duplex == DUPLEX_FULL ?
1413 "full" : "half"));
1414
1415 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1416 "%s for RX.\n",
1417 tp->dev->name,
1418 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1419 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1420 }
1421 }
1422
1423 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1424 {
1425 u32 new_tg3_flags = 0;
1426 u32 old_rx_mode = tp->rx_mode;
1427 u32 old_tx_mode = tp->tx_mode;
1428
1429 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1430
1431 /* Convert 1000BaseX flow control bits to 1000BaseT
1432 * bits before resolving flow control.
1433 */
1434 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1435 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1436 ADVERTISE_PAUSE_ASYM);
1437 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1438
1439 if (local_adv & ADVERTISE_1000XPAUSE)
1440 local_adv |= ADVERTISE_PAUSE_CAP;
1441 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1442 local_adv |= ADVERTISE_PAUSE_ASYM;
1443 if (remote_adv & LPA_1000XPAUSE)
1444 remote_adv |= LPA_PAUSE_CAP;
1445 if (remote_adv & LPA_1000XPAUSE_ASYM)
1446 remote_adv |= LPA_PAUSE_ASYM;
1447 }
1448
1449 if (local_adv & ADVERTISE_PAUSE_CAP) {
1450 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1451 if (remote_adv & LPA_PAUSE_CAP)
1452 new_tg3_flags |=
1453 (TG3_FLAG_RX_PAUSE |
1454 TG3_FLAG_TX_PAUSE);
1455 else if (remote_adv & LPA_PAUSE_ASYM)
1456 new_tg3_flags |=
1457 (TG3_FLAG_RX_PAUSE);
1458 } else {
1459 if (remote_adv & LPA_PAUSE_CAP)
1460 new_tg3_flags |=
1461 (TG3_FLAG_RX_PAUSE |
1462 TG3_FLAG_TX_PAUSE);
1463 }
1464 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1465 if ((remote_adv & LPA_PAUSE_CAP) &&
1466 (remote_adv & LPA_PAUSE_ASYM))
1467 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1468 }
1469
1470 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1471 tp->tg3_flags |= new_tg3_flags;
1472 } else {
1473 new_tg3_flags = tp->tg3_flags;
1474 }
1475
1476 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1477 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1478 else
1479 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1480
1481 if (old_rx_mode != tp->rx_mode) {
1482 tw32_f(MAC_RX_MODE, tp->rx_mode);
1483 }
1484
1485 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1486 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1487 else
1488 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1489
1490 if (old_tx_mode != tp->tx_mode) {
1491 tw32_f(MAC_TX_MODE, tp->tx_mode);
1492 }
1493 }
1494
1495 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1496 {
1497 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1498 case MII_TG3_AUX_STAT_10HALF:
1499 *speed = SPEED_10;
1500 *duplex = DUPLEX_HALF;
1501 break;
1502
1503 case MII_TG3_AUX_STAT_10FULL:
1504 *speed = SPEED_10;
1505 *duplex = DUPLEX_FULL;
1506 break;
1507
1508 case MII_TG3_AUX_STAT_100HALF:
1509 *speed = SPEED_100;
1510 *duplex = DUPLEX_HALF;
1511 break;
1512
1513 case MII_TG3_AUX_STAT_100FULL:
1514 *speed = SPEED_100;
1515 *duplex = DUPLEX_FULL;
1516 break;
1517
1518 case MII_TG3_AUX_STAT_1000HALF:
1519 *speed = SPEED_1000;
1520 *duplex = DUPLEX_HALF;
1521 break;
1522
1523 case MII_TG3_AUX_STAT_1000FULL:
1524 *speed = SPEED_1000;
1525 *duplex = DUPLEX_FULL;
1526 break;
1527
1528 default:
1529 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1530 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1531 SPEED_10;
1532 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1533 DUPLEX_HALF;
1534 break;
1535 }
1536 *speed = SPEED_INVALID;
1537 *duplex = DUPLEX_INVALID;
1538 break;
1539 };
1540 }
1541
1542 static void tg3_phy_copper_begin(struct tg3 *tp)
1543 {
1544 u32 new_adv;
1545 int i;
1546
1547 if (tp->link_config.phy_is_low_power) {
1548 /* Entering low power mode. Disable gigabit and
1549 * 100baseT advertisements.
1550 */
1551 tg3_writephy(tp, MII_TG3_CTRL, 0);
1552
1553 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1554 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1555 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1556 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1557
1558 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1559 } else if (tp->link_config.speed == SPEED_INVALID) {
1560 tp->link_config.advertising =
1561 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1562 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1563 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1564 ADVERTISED_Autoneg | ADVERTISED_MII);
1565
1566 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1567 tp->link_config.advertising &=
1568 ~(ADVERTISED_1000baseT_Half |
1569 ADVERTISED_1000baseT_Full);
1570
1571 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1572 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1573 new_adv |= ADVERTISE_10HALF;
1574 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1575 new_adv |= ADVERTISE_10FULL;
1576 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1577 new_adv |= ADVERTISE_100HALF;
1578 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1579 new_adv |= ADVERTISE_100FULL;
1580 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1581
1582 if (tp->link_config.advertising &
1583 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1584 new_adv = 0;
1585 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1586 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1587 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1588 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1589 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1590 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1591 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1592 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1593 MII_TG3_CTRL_ENABLE_AS_MASTER);
1594 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1595 } else {
1596 tg3_writephy(tp, MII_TG3_CTRL, 0);
1597 }
1598 } else {
1599 /* Asking for a specific link mode. */
1600 if (tp->link_config.speed == SPEED_1000) {
1601 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1602 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1603
1604 if (tp->link_config.duplex == DUPLEX_FULL)
1605 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1606 else
1607 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1608 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1609 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1610 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1611 MII_TG3_CTRL_ENABLE_AS_MASTER);
1612 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1613 } else {
1614 tg3_writephy(tp, MII_TG3_CTRL, 0);
1615
1616 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1617 if (tp->link_config.speed == SPEED_100) {
1618 if (tp->link_config.duplex == DUPLEX_FULL)
1619 new_adv |= ADVERTISE_100FULL;
1620 else
1621 new_adv |= ADVERTISE_100HALF;
1622 } else {
1623 if (tp->link_config.duplex == DUPLEX_FULL)
1624 new_adv |= ADVERTISE_10FULL;
1625 else
1626 new_adv |= ADVERTISE_10HALF;
1627 }
1628 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1629 }
1630 }
1631
1632 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1633 tp->link_config.speed != SPEED_INVALID) {
1634 u32 bmcr, orig_bmcr;
1635
1636 tp->link_config.active_speed = tp->link_config.speed;
1637 tp->link_config.active_duplex = tp->link_config.duplex;
1638
1639 bmcr = 0;
1640 switch (tp->link_config.speed) {
1641 default:
1642 case SPEED_10:
1643 break;
1644
1645 case SPEED_100:
1646 bmcr |= BMCR_SPEED100;
1647 break;
1648
1649 case SPEED_1000:
1650 bmcr |= TG3_BMCR_SPEED1000;
1651 break;
1652 };
1653
1654 if (tp->link_config.duplex == DUPLEX_FULL)
1655 bmcr |= BMCR_FULLDPLX;
1656
1657 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1658 (bmcr != orig_bmcr)) {
1659 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1660 for (i = 0; i < 1500; i++) {
1661 u32 tmp;
1662
1663 udelay(10);
1664 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1665 tg3_readphy(tp, MII_BMSR, &tmp))
1666 continue;
1667 if (!(tmp & BMSR_LSTATUS)) {
1668 udelay(40);
1669 break;
1670 }
1671 }
1672 tg3_writephy(tp, MII_BMCR, bmcr);
1673 udelay(40);
1674 }
1675 } else {
1676 tg3_writephy(tp, MII_BMCR,
1677 BMCR_ANENABLE | BMCR_ANRESTART);
1678 }
1679 }
1680
1681 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1682 {
1683 int err;
1684
1685 /* Turn off tap power management. */
1686 /* Set Extended packet length bit */
1687 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1688
1689 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1690 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1691
1692 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1693 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1694
1695 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1696 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1697
1698 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1699 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1700
1701 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1702 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1703
1704 udelay(40);
1705
1706 return err;
1707 }
1708
1709 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1710 {
1711 u32 adv_reg, all_mask;
1712
1713 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1714 return 0;
1715
1716 all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1717 ADVERTISE_100HALF | ADVERTISE_100FULL);
1718 if ((adv_reg & all_mask) != all_mask)
1719 return 0;
1720 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1721 u32 tg3_ctrl;
1722
1723 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1724 return 0;
1725
1726 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1727 MII_TG3_CTRL_ADV_1000_FULL);
1728 if ((tg3_ctrl & all_mask) != all_mask)
1729 return 0;
1730 }
1731 return 1;
1732 }
1733
1734 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1735 {
1736 int current_link_up;
1737 u32 bmsr, dummy;
1738 u16 current_speed;
1739 u8 current_duplex;
1740 int i, err;
1741
1742 tw32(MAC_EVENT, 0);
1743
1744 tw32_f(MAC_STATUS,
1745 (MAC_STATUS_SYNC_CHANGED |
1746 MAC_STATUS_CFG_CHANGED |
1747 MAC_STATUS_MI_COMPLETION |
1748 MAC_STATUS_LNKSTATE_CHANGED));
1749 udelay(40);
1750
1751 tp->mi_mode = MAC_MI_MODE_BASE;
1752 tw32_f(MAC_MI_MODE, tp->mi_mode);
1753 udelay(80);
1754
1755 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1756
1757 /* Some third-party PHYs need to be reset on link going
1758 * down.
1759 */
1760 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1761 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1762 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1763 netif_carrier_ok(tp->dev)) {
1764 tg3_readphy(tp, MII_BMSR, &bmsr);
1765 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1766 !(bmsr & BMSR_LSTATUS))
1767 force_reset = 1;
1768 }
1769 if (force_reset)
1770 tg3_phy_reset(tp);
1771
1772 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1773 tg3_readphy(tp, MII_BMSR, &bmsr);
1774 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1775 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1776 bmsr = 0;
1777
1778 if (!(bmsr & BMSR_LSTATUS)) {
1779 err = tg3_init_5401phy_dsp(tp);
1780 if (err)
1781 return err;
1782
1783 tg3_readphy(tp, MII_BMSR, &bmsr);
1784 for (i = 0; i < 1000; i++) {
1785 udelay(10);
1786 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1787 (bmsr & BMSR_LSTATUS)) {
1788 udelay(40);
1789 break;
1790 }
1791 }
1792
1793 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1794 !(bmsr & BMSR_LSTATUS) &&
1795 tp->link_config.active_speed == SPEED_1000) {
1796 err = tg3_phy_reset(tp);
1797 if (!err)
1798 err = tg3_init_5401phy_dsp(tp);
1799 if (err)
1800 return err;
1801 }
1802 }
1803 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1804 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1805 /* 5701 {A0,B0} CRC bug workaround */
1806 tg3_writephy(tp, 0x15, 0x0a75);
1807 tg3_writephy(tp, 0x1c, 0x8c68);
1808 tg3_writephy(tp, 0x1c, 0x8d68);
1809 tg3_writephy(tp, 0x1c, 0x8c68);
1810 }
1811
1812 /* Clear pending interrupts... */
1813 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1814 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1815
1816 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1817 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1818 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1819 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1820
1821 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1822 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1823 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1824 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1825 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1826 else
1827 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1828 }
1829
1830 current_link_up = 0;
1831 current_speed = SPEED_INVALID;
1832 current_duplex = DUPLEX_INVALID;
1833
1834 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1835 u32 val;
1836
1837 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1838 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1839 if (!(val & (1 << 10))) {
1840 val |= (1 << 10);
1841 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1842 goto relink;
1843 }
1844 }
1845
1846 bmsr = 0;
1847 for (i = 0; i < 100; i++) {
1848 tg3_readphy(tp, MII_BMSR, &bmsr);
1849 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850 (bmsr & BMSR_LSTATUS))
1851 break;
1852 udelay(40);
1853 }
1854
1855 if (bmsr & BMSR_LSTATUS) {
1856 u32 aux_stat, bmcr;
1857
1858 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1859 for (i = 0; i < 2000; i++) {
1860 udelay(10);
1861 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1862 aux_stat)
1863 break;
1864 }
1865
1866 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1867 &current_speed,
1868 &current_duplex);
1869
1870 bmcr = 0;
1871 for (i = 0; i < 200; i++) {
1872 tg3_readphy(tp, MII_BMCR, &bmcr);
1873 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1874 continue;
1875 if (bmcr && bmcr != 0x7fff)
1876 break;
1877 udelay(10);
1878 }
1879
1880 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1881 if (bmcr & BMCR_ANENABLE) {
1882 current_link_up = 1;
1883
1884 /* Force autoneg restart if we are exiting
1885 * low power mode.
1886 */
1887 if (!tg3_copper_is_advertising_all(tp))
1888 current_link_up = 0;
1889 } else {
1890 current_link_up = 0;
1891 }
1892 } else {
1893 if (!(bmcr & BMCR_ANENABLE) &&
1894 tp->link_config.speed == current_speed &&
1895 tp->link_config.duplex == current_duplex) {
1896 current_link_up = 1;
1897 } else {
1898 current_link_up = 0;
1899 }
1900 }
1901
1902 tp->link_config.active_speed = current_speed;
1903 tp->link_config.active_duplex = current_duplex;
1904 }
1905
1906 if (current_link_up == 1 &&
1907 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1908 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1909 u32 local_adv, remote_adv;
1910
1911 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1912 local_adv = 0;
1913 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1914
1915 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1916 remote_adv = 0;
1917
1918 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1919
1920 /* If we are not advertising full pause capability,
1921 * something is wrong. Bring the link down and reconfigure.
1922 */
1923 if (local_adv != ADVERTISE_PAUSE_CAP) {
1924 current_link_up = 0;
1925 } else {
1926 tg3_setup_flow_control(tp, local_adv, remote_adv);
1927 }
1928 }
1929 relink:
1930 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1931 u32 tmp;
1932
1933 tg3_phy_copper_begin(tp);
1934
1935 tg3_readphy(tp, MII_BMSR, &tmp);
1936 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1937 (tmp & BMSR_LSTATUS))
1938 current_link_up = 1;
1939 }
1940
1941 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1942 if (current_link_up == 1) {
1943 if (tp->link_config.active_speed == SPEED_100 ||
1944 tp->link_config.active_speed == SPEED_10)
1945 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1946 else
1947 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1948 } else
1949 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1950
1951 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1952 if (tp->link_config.active_duplex == DUPLEX_HALF)
1953 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1954
1955 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1957 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1958 (current_link_up == 1 &&
1959 tp->link_config.active_speed == SPEED_10))
1960 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1961 } else {
1962 if (current_link_up == 1)
1963 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1964 }
1965
1966 /* ??? Without this setting Netgear GA302T PHY does not
1967 * ??? send/receive packets...
1968 */
1969 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1970 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1971 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1972 tw32_f(MAC_MI_MODE, tp->mi_mode);
1973 udelay(80);
1974 }
1975
1976 tw32_f(MAC_MODE, tp->mac_mode);
1977 udelay(40);
1978
1979 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1980 /* Polled via timer. */
1981 tw32_f(MAC_EVENT, 0);
1982 } else {
1983 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1984 }
1985 udelay(40);
1986
1987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1988 current_link_up == 1 &&
1989 tp->link_config.active_speed == SPEED_1000 &&
1990 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1991 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1992 udelay(120);
1993 tw32_f(MAC_STATUS,
1994 (MAC_STATUS_SYNC_CHANGED |
1995 MAC_STATUS_CFG_CHANGED));
1996 udelay(40);
1997 tg3_write_mem(tp,
1998 NIC_SRAM_FIRMWARE_MBOX,
1999 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2000 }
2001
2002 if (current_link_up != netif_carrier_ok(tp->dev)) {
2003 if (current_link_up)
2004 netif_carrier_on(tp->dev);
2005 else
2006 netif_carrier_off(tp->dev);
2007 tg3_link_report(tp);
2008 }
2009
2010 return 0;
2011 }
2012
2013 struct tg3_fiber_aneginfo {
2014 int state;
2015 #define ANEG_STATE_UNKNOWN 0
2016 #define ANEG_STATE_AN_ENABLE 1
2017 #define ANEG_STATE_RESTART_INIT 2
2018 #define ANEG_STATE_RESTART 3
2019 #define ANEG_STATE_DISABLE_LINK_OK 4
2020 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2021 #define ANEG_STATE_ABILITY_DETECT 6
2022 #define ANEG_STATE_ACK_DETECT_INIT 7
2023 #define ANEG_STATE_ACK_DETECT 8
2024 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2025 #define ANEG_STATE_COMPLETE_ACK 10
2026 #define ANEG_STATE_IDLE_DETECT_INIT 11
2027 #define ANEG_STATE_IDLE_DETECT 12
2028 #define ANEG_STATE_LINK_OK 13
2029 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2030 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2031
2032 u32 flags;
2033 #define MR_AN_ENABLE 0x00000001
2034 #define MR_RESTART_AN 0x00000002
2035 #define MR_AN_COMPLETE 0x00000004
2036 #define MR_PAGE_RX 0x00000008
2037 #define MR_NP_LOADED 0x00000010
2038 #define MR_TOGGLE_TX 0x00000020
2039 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2040 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2041 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2042 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2043 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2044 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2045 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2046 #define MR_TOGGLE_RX 0x00002000
2047 #define MR_NP_RX 0x00004000
2048
2049 #define MR_LINK_OK 0x80000000
2050
2051 unsigned long link_time, cur_time;
2052
2053 u32 ability_match_cfg;
2054 int ability_match_count;
2055
2056 char ability_match, idle_match, ack_match;
2057
2058 u32 txconfig, rxconfig;
2059 #define ANEG_CFG_NP 0x00000080
2060 #define ANEG_CFG_ACK 0x00000040
2061 #define ANEG_CFG_RF2 0x00000020
2062 #define ANEG_CFG_RF1 0x00000010
2063 #define ANEG_CFG_PS2 0x00000001
2064 #define ANEG_CFG_PS1 0x00008000
2065 #define ANEG_CFG_HD 0x00004000
2066 #define ANEG_CFG_FD 0x00002000
2067 #define ANEG_CFG_INVAL 0x00001f06
2068
2069 };
2070 #define ANEG_OK 0
2071 #define ANEG_DONE 1
2072 #define ANEG_TIMER_ENAB 2
2073 #define ANEG_FAILED -1
2074
2075 #define ANEG_STATE_SETTLE_TIME 10000
2076
2077 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2078 struct tg3_fiber_aneginfo *ap)
2079 {
2080 unsigned long delta;
2081 u32 rx_cfg_reg;
2082 int ret;
2083
2084 if (ap->state == ANEG_STATE_UNKNOWN) {
2085 ap->rxconfig = 0;
2086 ap->link_time = 0;
2087 ap->cur_time = 0;
2088 ap->ability_match_cfg = 0;
2089 ap->ability_match_count = 0;
2090 ap->ability_match = 0;
2091 ap->idle_match = 0;
2092 ap->ack_match = 0;
2093 }
2094 ap->cur_time++;
2095
2096 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2097 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2098
2099 if (rx_cfg_reg != ap->ability_match_cfg) {
2100 ap->ability_match_cfg = rx_cfg_reg;
2101 ap->ability_match = 0;
2102 ap->ability_match_count = 0;
2103 } else {
2104 if (++ap->ability_match_count > 1) {
2105 ap->ability_match = 1;
2106 ap->ability_match_cfg = rx_cfg_reg;
2107 }
2108 }
2109 if (rx_cfg_reg & ANEG_CFG_ACK)
2110 ap->ack_match = 1;
2111 else
2112 ap->ack_match = 0;
2113
2114 ap->idle_match = 0;
2115 } else {
2116 ap->idle_match = 1;
2117 ap->ability_match_cfg = 0;
2118 ap->ability_match_count = 0;
2119 ap->ability_match = 0;
2120 ap->ack_match = 0;
2121
2122 rx_cfg_reg = 0;
2123 }
2124
2125 ap->rxconfig = rx_cfg_reg;
2126 ret = ANEG_OK;
2127
2128 switch(ap->state) {
2129 case ANEG_STATE_UNKNOWN:
2130 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2131 ap->state = ANEG_STATE_AN_ENABLE;
2132
2133 /* fallthru */
2134 case ANEG_STATE_AN_ENABLE:
2135 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2136 if (ap->flags & MR_AN_ENABLE) {
2137 ap->link_time = 0;
2138 ap->cur_time = 0;
2139 ap->ability_match_cfg = 0;
2140 ap->ability_match_count = 0;
2141 ap->ability_match = 0;
2142 ap->idle_match = 0;
2143 ap->ack_match = 0;
2144
2145 ap->state = ANEG_STATE_RESTART_INIT;
2146 } else {
2147 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2148 }
2149 break;
2150
2151 case ANEG_STATE_RESTART_INIT:
2152 ap->link_time = ap->cur_time;
2153 ap->flags &= ~(MR_NP_LOADED);
2154 ap->txconfig = 0;
2155 tw32(MAC_TX_AUTO_NEG, 0);
2156 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2157 tw32_f(MAC_MODE, tp->mac_mode);
2158 udelay(40);
2159
2160 ret = ANEG_TIMER_ENAB;
2161 ap->state = ANEG_STATE_RESTART;
2162
2163 /* fallthru */
2164 case ANEG_STATE_RESTART:
2165 delta = ap->cur_time - ap->link_time;
2166 if (delta > ANEG_STATE_SETTLE_TIME) {
2167 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2168 } else {
2169 ret = ANEG_TIMER_ENAB;
2170 }
2171 break;
2172
2173 case ANEG_STATE_DISABLE_LINK_OK:
2174 ret = ANEG_DONE;
2175 break;
2176
2177 case ANEG_STATE_ABILITY_DETECT_INIT:
2178 ap->flags &= ~(MR_TOGGLE_TX);
2179 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2180 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2181 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2182 tw32_f(MAC_MODE, tp->mac_mode);
2183 udelay(40);
2184
2185 ap->state = ANEG_STATE_ABILITY_DETECT;
2186 break;
2187
2188 case ANEG_STATE_ABILITY_DETECT:
2189 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2190 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2191 }
2192 break;
2193
2194 case ANEG_STATE_ACK_DETECT_INIT:
2195 ap->txconfig |= ANEG_CFG_ACK;
2196 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2197 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2198 tw32_f(MAC_MODE, tp->mac_mode);
2199 udelay(40);
2200
2201 ap->state = ANEG_STATE_ACK_DETECT;
2202
2203 /* fallthru */
2204 case ANEG_STATE_ACK_DETECT:
2205 if (ap->ack_match != 0) {
2206 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2207 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2208 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2209 } else {
2210 ap->state = ANEG_STATE_AN_ENABLE;
2211 }
2212 } else if (ap->ability_match != 0 &&
2213 ap->rxconfig == 0) {
2214 ap->state = ANEG_STATE_AN_ENABLE;
2215 }
2216 break;
2217
2218 case ANEG_STATE_COMPLETE_ACK_INIT:
2219 if (ap->rxconfig & ANEG_CFG_INVAL) {
2220 ret = ANEG_FAILED;
2221 break;
2222 }
2223 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2224 MR_LP_ADV_HALF_DUPLEX |
2225 MR_LP_ADV_SYM_PAUSE |
2226 MR_LP_ADV_ASYM_PAUSE |
2227 MR_LP_ADV_REMOTE_FAULT1 |
2228 MR_LP_ADV_REMOTE_FAULT2 |
2229 MR_LP_ADV_NEXT_PAGE |
2230 MR_TOGGLE_RX |
2231 MR_NP_RX);
2232 if (ap->rxconfig & ANEG_CFG_FD)
2233 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2234 if (ap->rxconfig & ANEG_CFG_HD)
2235 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2236 if (ap->rxconfig & ANEG_CFG_PS1)
2237 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2238 if (ap->rxconfig & ANEG_CFG_PS2)
2239 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2240 if (ap->rxconfig & ANEG_CFG_RF1)
2241 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2242 if (ap->rxconfig & ANEG_CFG_RF2)
2243 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2244 if (ap->rxconfig & ANEG_CFG_NP)
2245 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2246
2247 ap->link_time = ap->cur_time;
2248
2249 ap->flags ^= (MR_TOGGLE_TX);
2250 if (ap->rxconfig & 0x0008)
2251 ap->flags |= MR_TOGGLE_RX;
2252 if (ap->rxconfig & ANEG_CFG_NP)
2253 ap->flags |= MR_NP_RX;
2254 ap->flags |= MR_PAGE_RX;
2255
2256 ap->state = ANEG_STATE_COMPLETE_ACK;
2257 ret = ANEG_TIMER_ENAB;
2258 break;
2259
2260 case ANEG_STATE_COMPLETE_ACK:
2261 if (ap->ability_match != 0 &&
2262 ap->rxconfig == 0) {
2263 ap->state = ANEG_STATE_AN_ENABLE;
2264 break;
2265 }
2266 delta = ap->cur_time - ap->link_time;
2267 if (delta > ANEG_STATE_SETTLE_TIME) {
2268 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2269 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2270 } else {
2271 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2272 !(ap->flags & MR_NP_RX)) {
2273 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2274 } else {
2275 ret = ANEG_FAILED;
2276 }
2277 }
2278 }
2279 break;
2280
2281 case ANEG_STATE_IDLE_DETECT_INIT:
2282 ap->link_time = ap->cur_time;
2283 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2284 tw32_f(MAC_MODE, tp->mac_mode);
2285 udelay(40);
2286
2287 ap->state = ANEG_STATE_IDLE_DETECT;
2288 ret = ANEG_TIMER_ENAB;
2289 break;
2290
2291 case ANEG_STATE_IDLE_DETECT:
2292 if (ap->ability_match != 0 &&
2293 ap->rxconfig == 0) {
2294 ap->state = ANEG_STATE_AN_ENABLE;
2295 break;
2296 }
2297 delta = ap->cur_time - ap->link_time;
2298 if (delta > ANEG_STATE_SETTLE_TIME) {
2299 /* XXX another gem from the Broadcom driver :( */
2300 ap->state = ANEG_STATE_LINK_OK;
2301 }
2302 break;
2303
2304 case ANEG_STATE_LINK_OK:
2305 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2306 ret = ANEG_DONE;
2307 break;
2308
2309 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2310 /* ??? unimplemented */
2311 break;
2312
2313 case ANEG_STATE_NEXT_PAGE_WAIT:
2314 /* ??? unimplemented */
2315 break;
2316
2317 default:
2318 ret = ANEG_FAILED;
2319 break;
2320 };
2321
2322 return ret;
2323 }
2324
2325 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2326 {
2327 int res = 0;
2328 struct tg3_fiber_aneginfo aninfo;
2329 int status = ANEG_FAILED;
2330 unsigned int tick;
2331 u32 tmp;
2332
2333 tw32_f(MAC_TX_AUTO_NEG, 0);
2334
2335 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2336 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2337 udelay(40);
2338
2339 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2340 udelay(40);
2341
2342 memset(&aninfo, 0, sizeof(aninfo));
2343 aninfo.flags |= MR_AN_ENABLE;
2344 aninfo.state = ANEG_STATE_UNKNOWN;
2345 aninfo.cur_time = 0;
2346 tick = 0;
2347 while (++tick < 195000) {
2348 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2349 if (status == ANEG_DONE || status == ANEG_FAILED)
2350 break;
2351
2352 udelay(1);
2353 }
2354
2355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2356 tw32_f(MAC_MODE, tp->mac_mode);
2357 udelay(40);
2358
2359 *flags = aninfo.flags;
2360
2361 if (status == ANEG_DONE &&
2362 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2363 MR_LP_ADV_FULL_DUPLEX)))
2364 res = 1;
2365
2366 return res;
2367 }
2368
2369 static void tg3_init_bcm8002(struct tg3 *tp)
2370 {
2371 u32 mac_status = tr32(MAC_STATUS);
2372 int i;
2373
2374 /* Reset when initting first time or we have a link. */
2375 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2376 !(mac_status & MAC_STATUS_PCS_SYNCED))
2377 return;
2378
2379 /* Set PLL lock range. */
2380 tg3_writephy(tp, 0x16, 0x8007);
2381
2382 /* SW reset */
2383 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2384
2385 /* Wait for reset to complete. */
2386 /* XXX schedule_timeout() ... */
2387 for (i = 0; i < 500; i++)
2388 udelay(10);
2389
2390 /* Config mode; select PMA/Ch 1 regs. */
2391 tg3_writephy(tp, 0x10, 0x8411);
2392
2393 /* Enable auto-lock and comdet, select txclk for tx. */
2394 tg3_writephy(tp, 0x11, 0x0a10);
2395
2396 tg3_writephy(tp, 0x18, 0x00a0);
2397 tg3_writephy(tp, 0x16, 0x41ff);
2398
2399 /* Assert and deassert POR. */
2400 tg3_writephy(tp, 0x13, 0x0400);
2401 udelay(40);
2402 tg3_writephy(tp, 0x13, 0x0000);
2403
2404 tg3_writephy(tp, 0x11, 0x0a50);
2405 udelay(40);
2406 tg3_writephy(tp, 0x11, 0x0a10);
2407
2408 /* Wait for signal to stabilize */
2409 /* XXX schedule_timeout() ... */
2410 for (i = 0; i < 15000; i++)
2411 udelay(10);
2412
2413 /* Deselect the channel register so we can read the PHYID
2414 * later.
2415 */
2416 tg3_writephy(tp, 0x10, 0x8011);
2417 }
2418
2419 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2420 {
2421 u32 sg_dig_ctrl, sg_dig_status;
2422 u32 serdes_cfg, expected_sg_dig_ctrl;
2423 int workaround, port_a;
2424 int current_link_up;
2425
2426 serdes_cfg = 0;
2427 expected_sg_dig_ctrl = 0;
2428 workaround = 0;
2429 port_a = 1;
2430 current_link_up = 0;
2431
2432 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2433 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2434 workaround = 1;
2435 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2436 port_a = 0;
2437
2438 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2439 /* preserve bits 20-23 for voltage regulator */
2440 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2441 }
2442
2443 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2444
2445 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2446 if (sg_dig_ctrl & (1 << 31)) {
2447 if (workaround) {
2448 u32 val = serdes_cfg;
2449
2450 if (port_a)
2451 val |= 0xc010000;
2452 else
2453 val |= 0x4010000;
2454 tw32_f(MAC_SERDES_CFG, val);
2455 }
2456 tw32_f(SG_DIG_CTRL, 0x01388400);
2457 }
2458 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2459 tg3_setup_flow_control(tp, 0, 0);
2460 current_link_up = 1;
2461 }
2462 goto out;
2463 }
2464
2465 /* Want auto-negotiation. */
2466 expected_sg_dig_ctrl = 0x81388400;
2467
2468 /* Pause capability */
2469 expected_sg_dig_ctrl |= (1 << 11);
2470
2471 /* Asymettric pause */
2472 expected_sg_dig_ctrl |= (1 << 12);
2473
2474 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2475 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2476 tp->serdes_counter &&
2477 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2478 MAC_STATUS_RCVD_CFG)) ==
2479 MAC_STATUS_PCS_SYNCED)) {
2480 tp->serdes_counter--;
2481 current_link_up = 1;
2482 goto out;
2483 }
2484 restart_autoneg:
2485 if (workaround)
2486 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2487 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2488 udelay(5);
2489 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2490
2491 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2492 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2493 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2494 MAC_STATUS_SIGNAL_DET)) {
2495 sg_dig_status = tr32(SG_DIG_STATUS);
2496 mac_status = tr32(MAC_STATUS);
2497
2498 if ((sg_dig_status & (1 << 1)) &&
2499 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2500 u32 local_adv, remote_adv;
2501
2502 local_adv = ADVERTISE_PAUSE_CAP;
2503 remote_adv = 0;
2504 if (sg_dig_status & (1 << 19))
2505 remote_adv |= LPA_PAUSE_CAP;
2506 if (sg_dig_status & (1 << 20))
2507 remote_adv |= LPA_PAUSE_ASYM;
2508
2509 tg3_setup_flow_control(tp, local_adv, remote_adv);
2510 current_link_up = 1;
2511 tp->serdes_counter = 0;
2512 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2513 } else if (!(sg_dig_status & (1 << 1))) {
2514 if (tp->serdes_counter)
2515 tp->serdes_counter--;
2516 else {
2517 if (workaround) {
2518 u32 val = serdes_cfg;
2519
2520 if (port_a)
2521 val |= 0xc010000;
2522 else
2523 val |= 0x4010000;
2524
2525 tw32_f(MAC_SERDES_CFG, val);
2526 }
2527
2528 tw32_f(SG_DIG_CTRL, 0x01388400);
2529 udelay(40);
2530
2531 /* Link parallel detection - link is up */
2532 /* only if we have PCS_SYNC and not */
2533 /* receiving config code words */
2534 mac_status = tr32(MAC_STATUS);
2535 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2536 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2537 tg3_setup_flow_control(tp, 0, 0);
2538 current_link_up = 1;
2539 tp->tg3_flags2 |=
2540 TG3_FLG2_PARALLEL_DETECT;
2541 tp->serdes_counter =
2542 SERDES_PARALLEL_DET_TIMEOUT;
2543 } else
2544 goto restart_autoneg;
2545 }
2546 }
2547 } else {
2548 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2549 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2550 }
2551
2552 out:
2553 return current_link_up;
2554 }
2555
2556 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2557 {
2558 int current_link_up = 0;
2559
2560 if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2561 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2562 goto out;
2563 }
2564
2565 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2566 u32 flags;
2567 int i;
2568
2569 if (fiber_autoneg(tp, &flags)) {
2570 u32 local_adv, remote_adv;
2571
2572 local_adv = ADVERTISE_PAUSE_CAP;
2573 remote_adv = 0;
2574 if (flags & MR_LP_ADV_SYM_PAUSE)
2575 remote_adv |= LPA_PAUSE_CAP;
2576 if (flags & MR_LP_ADV_ASYM_PAUSE)
2577 remote_adv |= LPA_PAUSE_ASYM;
2578
2579 tg3_setup_flow_control(tp, local_adv, remote_adv);
2580
2581 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2582 current_link_up = 1;
2583 }
2584 for (i = 0; i < 30; i++) {
2585 udelay(20);
2586 tw32_f(MAC_STATUS,
2587 (MAC_STATUS_SYNC_CHANGED |
2588 MAC_STATUS_CFG_CHANGED));
2589 udelay(40);
2590 if ((tr32(MAC_STATUS) &
2591 (MAC_STATUS_SYNC_CHANGED |
2592 MAC_STATUS_CFG_CHANGED)) == 0)
2593 break;
2594 }
2595
2596 mac_status = tr32(MAC_STATUS);
2597 if (current_link_up == 0 &&
2598 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2599 !(mac_status & MAC_STATUS_RCVD_CFG))
2600 current_link_up = 1;
2601 } else {
2602 /* Forcing 1000FD link up. */
2603 current_link_up = 1;
2604 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2605
2606 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2607 udelay(40);
2608 }
2609
2610 out:
2611 return current_link_up;
2612 }
2613
2614 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2615 {
2616 u32 orig_pause_cfg;
2617 u16 orig_active_speed;
2618 u8 orig_active_duplex;
2619 u32 mac_status;
2620 int current_link_up;
2621 int i;
2622
2623 orig_pause_cfg =
2624 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2625 TG3_FLAG_TX_PAUSE));
2626 orig_active_speed = tp->link_config.active_speed;
2627 orig_active_duplex = tp->link_config.active_duplex;
2628
2629 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2630 netif_carrier_ok(tp->dev) &&
2631 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2632 mac_status = tr32(MAC_STATUS);
2633 mac_status &= (MAC_STATUS_PCS_SYNCED |
2634 MAC_STATUS_SIGNAL_DET |
2635 MAC_STATUS_CFG_CHANGED |
2636 MAC_STATUS_RCVD_CFG);
2637 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2638 MAC_STATUS_SIGNAL_DET)) {
2639 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2640 MAC_STATUS_CFG_CHANGED));
2641 return 0;
2642 }
2643 }
2644
2645 tw32_f(MAC_TX_AUTO_NEG, 0);
2646
2647 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2648 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2649 tw32_f(MAC_MODE, tp->mac_mode);
2650 udelay(40);
2651
2652 if (tp->phy_id == PHY_ID_BCM8002)
2653 tg3_init_bcm8002(tp);
2654
2655 /* Enable link change event even when serdes polling. */
2656 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2657 udelay(40);
2658
2659 current_link_up = 0;
2660 mac_status = tr32(MAC_STATUS);
2661
2662 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2663 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2664 else
2665 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2666
2667 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668 tw32_f(MAC_MODE, tp->mac_mode);
2669 udelay(40);
2670
2671 tp->hw_status->status =
2672 (SD_STATUS_UPDATED |
2673 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2674
2675 for (i = 0; i < 100; i++) {
2676 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2677 MAC_STATUS_CFG_CHANGED));
2678 udelay(5);
2679 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2680 MAC_STATUS_CFG_CHANGED |
2681 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2682 break;
2683 }
2684
2685 mac_status = tr32(MAC_STATUS);
2686 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2687 current_link_up = 0;
2688 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2689 tp->serdes_counter == 0) {
2690 tw32_f(MAC_MODE, (tp->mac_mode |
2691 MAC_MODE_SEND_CONFIGS));
2692 udelay(1);
2693 tw32_f(MAC_MODE, tp->mac_mode);
2694 }
2695 }
2696
2697 if (current_link_up == 1) {
2698 tp->link_config.active_speed = SPEED_1000;
2699 tp->link_config.active_duplex = DUPLEX_FULL;
2700 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2701 LED_CTRL_LNKLED_OVERRIDE |
2702 LED_CTRL_1000MBPS_ON));
2703 } else {
2704 tp->link_config.active_speed = SPEED_INVALID;
2705 tp->link_config.active_duplex = DUPLEX_INVALID;
2706 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2707 LED_CTRL_LNKLED_OVERRIDE |
2708 LED_CTRL_TRAFFIC_OVERRIDE));
2709 }
2710
2711 if (current_link_up != netif_carrier_ok(tp->dev)) {
2712 if (current_link_up)
2713 netif_carrier_on(tp->dev);
2714 else
2715 netif_carrier_off(tp->dev);
2716 tg3_link_report(tp);
2717 } else {
2718 u32 now_pause_cfg =
2719 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2720 TG3_FLAG_TX_PAUSE);
2721 if (orig_pause_cfg != now_pause_cfg ||
2722 orig_active_speed != tp->link_config.active_speed ||
2723 orig_active_duplex != tp->link_config.active_duplex)
2724 tg3_link_report(tp);
2725 }
2726
2727 return 0;
2728 }
2729
2730 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2731 {
2732 int current_link_up, err = 0;
2733 u32 bmsr, bmcr;
2734 u16 current_speed;
2735 u8 current_duplex;
2736
2737 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2738 tw32_f(MAC_MODE, tp->mac_mode);
2739 udelay(40);
2740
2741 tw32(MAC_EVENT, 0);
2742
2743 tw32_f(MAC_STATUS,
2744 (MAC_STATUS_SYNC_CHANGED |
2745 MAC_STATUS_CFG_CHANGED |
2746 MAC_STATUS_MI_COMPLETION |
2747 MAC_STATUS_LNKSTATE_CHANGED));
2748 udelay(40);
2749
2750 if (force_reset)
2751 tg3_phy_reset(tp);
2752
2753 current_link_up = 0;
2754 current_speed = SPEED_INVALID;
2755 current_duplex = DUPLEX_INVALID;
2756
2757 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2758 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2759 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2760 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2761 bmsr |= BMSR_LSTATUS;
2762 else
2763 bmsr &= ~BMSR_LSTATUS;
2764 }
2765
2766 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2767
2768 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2769 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2770 /* do nothing, just check for link up at the end */
2771 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2772 u32 adv, new_adv;
2773
2774 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2775 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2776 ADVERTISE_1000XPAUSE |
2777 ADVERTISE_1000XPSE_ASYM |
2778 ADVERTISE_SLCT);
2779
2780 /* Always advertise symmetric PAUSE just like copper */
2781 new_adv |= ADVERTISE_1000XPAUSE;
2782
2783 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2784 new_adv |= ADVERTISE_1000XHALF;
2785 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2786 new_adv |= ADVERTISE_1000XFULL;
2787
2788 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2789 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2790 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2791 tg3_writephy(tp, MII_BMCR, bmcr);
2792
2793 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2794 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2795 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2796
2797 return err;
2798 }
2799 } else {
2800 u32 new_bmcr;
2801
2802 bmcr &= ~BMCR_SPEED1000;
2803 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2804
2805 if (tp->link_config.duplex == DUPLEX_FULL)
2806 new_bmcr |= BMCR_FULLDPLX;
2807
2808 if (new_bmcr != bmcr) {
2809 /* BMCR_SPEED1000 is a reserved bit that needs
2810 * to be set on write.
2811 */
2812 new_bmcr |= BMCR_SPEED1000;
2813
2814 /* Force a linkdown */
2815 if (netif_carrier_ok(tp->dev)) {
2816 u32 adv;
2817
2818 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2819 adv &= ~(ADVERTISE_1000XFULL |
2820 ADVERTISE_1000XHALF |
2821 ADVERTISE_SLCT);
2822 tg3_writephy(tp, MII_ADVERTISE, adv);
2823 tg3_writephy(tp, MII_BMCR, bmcr |
2824 BMCR_ANRESTART |
2825 BMCR_ANENABLE);
2826 udelay(10);
2827 netif_carrier_off(tp->dev);
2828 }
2829 tg3_writephy(tp, MII_BMCR, new_bmcr);
2830 bmcr = new_bmcr;
2831 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2832 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2833 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2834 ASIC_REV_5714) {
2835 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2836 bmsr |= BMSR_LSTATUS;
2837 else
2838 bmsr &= ~BMSR_LSTATUS;
2839 }
2840 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2841 }
2842 }
2843
2844 if (bmsr & BMSR_LSTATUS) {
2845 current_speed = SPEED_1000;
2846 current_link_up = 1;
2847 if (bmcr & BMCR_FULLDPLX)
2848 current_duplex = DUPLEX_FULL;
2849 else
2850 current_duplex = DUPLEX_HALF;
2851
2852 if (bmcr & BMCR_ANENABLE) {
2853 u32 local_adv, remote_adv, common;
2854
2855 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2856 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2857 common = local_adv & remote_adv;
2858 if (common & (ADVERTISE_1000XHALF |
2859 ADVERTISE_1000XFULL)) {
2860 if (common & ADVERTISE_1000XFULL)
2861 current_duplex = DUPLEX_FULL;
2862 else
2863 current_duplex = DUPLEX_HALF;
2864
2865 tg3_setup_flow_control(tp, local_adv,
2866 remote_adv);
2867 }
2868 else
2869 current_link_up = 0;
2870 }
2871 }
2872
2873 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2874 if (tp->link_config.active_duplex == DUPLEX_HALF)
2875 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2876
2877 tw32_f(MAC_MODE, tp->mac_mode);
2878 udelay(40);
2879
2880 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2881
2882 tp->link_config.active_speed = current_speed;
2883 tp->link_config.active_duplex = current_duplex;
2884
2885 if (current_link_up != netif_carrier_ok(tp->dev)) {
2886 if (current_link_up)
2887 netif_carrier_on(tp->dev);
2888 else {
2889 netif_carrier_off(tp->dev);
2890 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2891 }
2892 tg3_link_report(tp);
2893 }
2894 return err;
2895 }
2896
2897 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2898 {
2899 if (tp->serdes_counter) {
2900 /* Give autoneg time to complete. */
2901 tp->serdes_counter--;
2902 return;
2903 }
2904 if (!netif_carrier_ok(tp->dev) &&
2905 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2906 u32 bmcr;
2907
2908 tg3_readphy(tp, MII_BMCR, &bmcr);
2909 if (bmcr & BMCR_ANENABLE) {
2910 u32 phy1, phy2;
2911
2912 /* Select shadow register 0x1f */
2913 tg3_writephy(tp, 0x1c, 0x7c00);
2914 tg3_readphy(tp, 0x1c, &phy1);
2915
2916 /* Select expansion interrupt status register */
2917 tg3_writephy(tp, 0x17, 0x0f01);
2918 tg3_readphy(tp, 0x15, &phy2);
2919 tg3_readphy(tp, 0x15, &phy2);
2920
2921 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2922 /* We have signal detect and not receiving
2923 * config code words, link is up by parallel
2924 * detection.
2925 */
2926
2927 bmcr &= ~BMCR_ANENABLE;
2928 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2929 tg3_writephy(tp, MII_BMCR, bmcr);
2930 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2931 }
2932 }
2933 }
2934 else if (netif_carrier_ok(tp->dev) &&
2935 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2936 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2937 u32 phy2;
2938
2939 /* Select expansion interrupt status register */
2940 tg3_writephy(tp, 0x17, 0x0f01);
2941 tg3_readphy(tp, 0x15, &phy2);
2942 if (phy2 & 0x20) {
2943 u32 bmcr;
2944
2945 /* Config code words received, turn on autoneg. */
2946 tg3_readphy(tp, MII_BMCR, &bmcr);
2947 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2948
2949 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2950
2951 }
2952 }
2953 }
2954
2955 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2956 {
2957 int err;
2958
2959 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2960 err = tg3_setup_fiber_phy(tp, force_reset);
2961 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2962 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2963 } else {
2964 err = tg3_setup_copper_phy(tp, force_reset);
2965 }
2966
2967 if (tp->link_config.active_speed == SPEED_1000 &&
2968 tp->link_config.active_duplex == DUPLEX_HALF)
2969 tw32(MAC_TX_LENGTHS,
2970 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2971 (6 << TX_LENGTHS_IPG_SHIFT) |
2972 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2973 else
2974 tw32(MAC_TX_LENGTHS,
2975 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2976 (6 << TX_LENGTHS_IPG_SHIFT) |
2977 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2978
2979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2980 if (netif_carrier_ok(tp->dev)) {
2981 tw32(HOSTCC_STAT_COAL_TICKS,
2982 tp->coal.stats_block_coalesce_usecs);
2983 } else {
2984 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2985 }
2986 }
2987
2988 return err;
2989 }
2990
2991 /* This is called whenever we suspect that the system chipset is re-
2992 * ordering the sequence of MMIO to the tx send mailbox. The symptom
2993 * is bogus tx completions. We try to recover by setting the
2994 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
2995 * in the workqueue.
2996 */
2997 static void tg3_tx_recover(struct tg3 *tp)
2998 {
2999 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3000 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3001
3002 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3003 "mapped I/O cycles to the network device, attempting to "
3004 "recover. Please report the problem to the driver maintainer "
3005 "and include system chipset information.\n", tp->dev->name);
3006
3007 spin_lock(&tp->lock);
3008 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3009 spin_unlock(&tp->lock);
3010 }
3011
3012 static inline u32 tg3_tx_avail(struct tg3 *tp)
3013 {
3014 smp_mb();
3015 return (tp->tx_pending -
3016 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3017 }
3018
3019 /* Tigon3 never reports partial packet sends. So we do not
3020 * need special logic to handle SKBs that have not had all
3021 * of their frags sent yet, like SunGEM does.
3022 */
3023 static void tg3_tx(struct tg3 *tp)
3024 {
3025 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3026 u32 sw_idx = tp->tx_cons;
3027
3028 while (sw_idx != hw_idx) {
3029 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3030 struct sk_buff *skb = ri->skb;
3031 int i, tx_bug = 0;
3032
3033 if (unlikely(skb == NULL)) {
3034 tg3_tx_recover(tp);
3035 return;
3036 }
3037
3038 pci_unmap_single(tp->pdev,
3039 pci_unmap_addr(ri, mapping),
3040 skb_headlen(skb),
3041 PCI_DMA_TODEVICE);
3042
3043 ri->skb = NULL;
3044
3045 sw_idx = NEXT_TX(sw_idx);
3046
3047 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3048 ri = &tp->tx_buffers[sw_idx];
3049 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3050 tx_bug = 1;
3051
3052 pci_unmap_page(tp->pdev,
3053 pci_unmap_addr(ri, mapping),
3054 skb_shinfo(skb)->frags[i].size,
3055 PCI_DMA_TODEVICE);
3056
3057 sw_idx = NEXT_TX(sw_idx);
3058 }
3059
3060 dev_kfree_skb(skb);
3061
3062 if (unlikely(tx_bug)) {
3063 tg3_tx_recover(tp);
3064 return;
3065 }
3066 }
3067
3068 tp->tx_cons = sw_idx;
3069
3070 /* Need to make the tx_cons update visible to tg3_start_xmit()
3071 * before checking for netif_queue_stopped(). Without the
3072 * memory barrier, there is a small possibility that tg3_start_xmit()
3073 * will miss it and cause the queue to be stopped forever.
3074 */
3075 smp_mb();
3076
3077 if (unlikely(netif_queue_stopped(tp->dev) &&
3078 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3079 netif_tx_lock(tp->dev);
3080 if (netif_queue_stopped(tp->dev) &&
3081 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3082 netif_wake_queue(tp->dev);
3083 netif_tx_unlock(tp->dev);
3084 }
3085 }
3086
3087 /* Returns size of skb allocated or < 0 on error.
3088 *
3089 * We only need to fill in the address because the other members
3090 * of the RX descriptor are invariant, see tg3_init_rings.
3091 *
3092 * Note the purposeful assymetry of cpu vs. chip accesses. For
3093 * posting buffers we only dirty the first cache line of the RX
3094 * descriptor (containing the address). Whereas for the RX status
3095 * buffers the cpu only reads the last cacheline of the RX descriptor
3096 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3097 */
3098 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3099 int src_idx, u32 dest_idx_unmasked)
3100 {
3101 struct tg3_rx_buffer_desc *desc;
3102 struct ring_info *map, *src_map;
3103 struct sk_buff *skb;
3104 dma_addr_t mapping;
3105 int skb_size, dest_idx;
3106
3107 src_map = NULL;
3108 switch (opaque_key) {
3109 case RXD_OPAQUE_RING_STD:
3110 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3111 desc = &tp->rx_std[dest_idx];
3112 map = &tp->rx_std_buffers[dest_idx];
3113 if (src_idx >= 0)
3114 src_map = &tp->rx_std_buffers[src_idx];
3115 skb_size = tp->rx_pkt_buf_sz;
3116 break;
3117
3118 case RXD_OPAQUE_RING_JUMBO:
3119 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3120 desc = &tp->rx_jumbo[dest_idx];
3121 map = &tp->rx_jumbo_buffers[dest_idx];
3122 if (src_idx >= 0)
3123 src_map = &tp->rx_jumbo_buffers[src_idx];
3124 skb_size = RX_JUMBO_PKT_BUF_SZ;
3125 break;
3126
3127 default:
3128 return -EINVAL;
3129 };
3130
3131 /* Do not overwrite any of the map or rp information
3132 * until we are sure we can commit to a new buffer.
3133 *
3134 * Callers depend upon this behavior and assume that
3135 * we leave everything unchanged if we fail.
3136 */
3137 skb = netdev_alloc_skb(tp->dev, skb_size);
3138 if (skb == NULL)
3139 return -ENOMEM;
3140
3141 skb_reserve(skb, tp->rx_offset);
3142
3143 mapping = pci_map_single(tp->pdev, skb->data,
3144 skb_size - tp->rx_offset,
3145 PCI_DMA_FROMDEVICE);
3146
3147 map->skb = skb;
3148 pci_unmap_addr_set(map, mapping, mapping);
3149
3150 if (src_map != NULL)
3151 src_map->skb = NULL;
3152
3153 desc->addr_hi = ((u64)mapping >> 32);
3154 desc->addr_lo = ((u64)mapping & 0xffffffff);
3155
3156 return skb_size;
3157 }
3158
3159 /* We only need to move over in the address because the other
3160 * members of the RX descriptor are invariant. See notes above
3161 * tg3_alloc_rx_skb for full details.
3162 */
3163 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3164 int src_idx, u32 dest_idx_unmasked)
3165 {
3166 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3167 struct ring_info *src_map, *dest_map;
3168 int dest_idx;
3169
3170 switch (opaque_key) {
3171 case RXD_OPAQUE_RING_STD:
3172 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3173 dest_desc = &tp->rx_std[dest_idx];
3174 dest_map = &tp->rx_std_buffers[dest_idx];
3175 src_desc = &tp->rx_std[src_idx];
3176 src_map = &tp->rx_std_buffers[src_idx];
3177 break;
3178
3179 case RXD_OPAQUE_RING_JUMBO:
3180 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3181 dest_desc = &tp->rx_jumbo[dest_idx];
3182 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3183 src_desc = &tp->rx_jumbo[src_idx];
3184 src_map = &tp->rx_jumbo_buffers[src_idx];
3185 break;
3186
3187 default:
3188 return;
3189 };
3190
3191 dest_map->skb = src_map->skb;
3192 pci_unmap_addr_set(dest_map, mapping,
3193 pci_unmap_addr(src_map, mapping));
3194 dest_desc->addr_hi = src_desc->addr_hi;
3195 dest_desc->addr_lo = src_desc->addr_lo;
3196
3197 src_map->skb = NULL;
3198 }
3199
3200 #if TG3_VLAN_TAG_USED
3201 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3202 {
3203 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3204 }
3205 #endif
3206
3207 /* The RX ring scheme is composed of multiple rings which post fresh
3208 * buffers to the chip, and one special ring the chip uses to report
3209 * status back to the host.
3210 *
3211 * The special ring reports the status of received packets to the
3212 * host. The chip does not write into the original descriptor the
3213 * RX buffer was obtained from. The chip simply takes the original
3214 * descriptor as provided by the host, updates the status and length
3215 * field, then writes this into the next status ring entry.
3216 *
3217 * Each ring the host uses to post buffers to the chip is described
3218 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3219 * it is first placed into the on-chip ram. When the packet's length
3220 * is known, it walks down the TG3_BDINFO entries to select the ring.
3221 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3222 * which is within the range of the new packet's length is chosen.
3223 *
3224 * The "separate ring for rx status" scheme may sound queer, but it makes
3225 * sense from a cache coherency perspective. If only the host writes
3226 * to the buffer post rings, and only the chip writes to the rx status
3227 * rings, then cache lines never move beyond shared-modified state.
3228 * If both the host and chip were to write into the same ring, cache line
3229 * eviction could occur since both entities want it in an exclusive state.
3230 */
3231 static int tg3_rx(struct tg3 *tp, int budget)
3232 {
3233 u32 work_mask, rx_std_posted = 0;
3234 u32 sw_idx = tp->rx_rcb_ptr;
3235 u16 hw_idx;
3236 int received;
3237
3238 hw_idx = tp->hw_status->idx[0].rx_producer;
3239 /*
3240 * We need to order the read of hw_idx and the read of
3241 * the opaque cookie.
3242 */
3243 rmb();
3244 work_mask = 0;
3245 received = 0;
3246 while (sw_idx != hw_idx && budget > 0) {
3247 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3248 unsigned int len;
3249 struct sk_buff *skb;
3250 dma_addr_t dma_addr;
3251 u32 opaque_key, desc_idx, *post_ptr;
3252
3253 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3254 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3255 if (opaque_key == RXD_OPAQUE_RING_STD) {
3256 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3257 mapping);
3258 skb = tp->rx_std_buffers[desc_idx].skb;
3259 post_ptr = &tp->rx_std_ptr;
3260 rx_std_posted++;
3261 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3262 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3263 mapping);
3264 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3265 post_ptr = &tp->rx_jumbo_ptr;
3266 }
3267 else {
3268 goto next_pkt_nopost;
3269 }
3270
3271 work_mask |= opaque_key;
3272
3273 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3274 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3275 drop_it:
3276 tg3_recycle_rx(tp, opaque_key,
3277 desc_idx, *post_ptr);
3278 drop_it_no_recycle:
3279 /* Other statistics kept track of by card. */
3280 tp->net_stats.rx_dropped++;
3281 goto next_pkt;
3282 }
3283
3284 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3285
3286 if (len > RX_COPY_THRESHOLD
3287 && tp->rx_offset == 2
3288 /* rx_offset != 2 iff this is a 5701 card running
3289 * in PCI-X mode [see tg3_get_invariants()] */
3290 ) {
3291 int skb_size;
3292
3293 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3294 desc_idx, *post_ptr);
3295 if (skb_size < 0)
3296 goto drop_it;
3297
3298 pci_unmap_single(tp->pdev, dma_addr,
3299 skb_size - tp->rx_offset,
3300 PCI_DMA_FROMDEVICE);
3301
3302 skb_put(skb, len);
3303 } else {
3304 struct sk_buff *copy_skb;
3305
3306 tg3_recycle_rx(tp, opaque_key,
3307 desc_idx, *post_ptr);
3308
3309 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3310 if (copy_skb == NULL)
3311 goto drop_it_no_recycle;
3312
3313 skb_reserve(copy_skb, 2);
3314 skb_put(copy_skb, len);
3315 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3316 memcpy(copy_skb->data, skb->data, len);
3317 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3318
3319 /* We'll reuse the original ring buffer. */
3320 skb = copy_skb;
3321 }
3322
3323 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3324 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3325 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3326 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3327 skb->ip_summed = CHECKSUM_UNNECESSARY;
3328 else
3329 skb->ip_summed = CHECKSUM_NONE;
3330
3331 skb->protocol = eth_type_trans(skb, tp->dev);
3332 #if TG3_VLAN_TAG_USED
3333 if (tp->vlgrp != NULL &&
3334 desc->type_flags & RXD_FLAG_VLAN) {
3335 tg3_vlan_rx(tp, skb,
3336 desc->err_vlan & RXD_VLAN_MASK);
3337 } else
3338 #endif
3339 netif_receive_skb(skb);
3340
3341 tp->dev->last_rx = jiffies;
3342 received++;
3343 budget--;
3344
3345 next_pkt:
3346 (*post_ptr)++;
3347
3348 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3349 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3350
3351 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3352 TG3_64BIT_REG_LOW, idx);
3353 work_mask &= ~RXD_OPAQUE_RING_STD;
3354 rx_std_posted = 0;
3355 }
3356 next_pkt_nopost:
3357 sw_idx++;
3358 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3359
3360 /* Refresh hw_idx to see if there is new work */
3361 if (sw_idx == hw_idx) {
3362 hw_idx = tp->hw_status->idx[0].rx_producer;
3363 rmb();
3364 }
3365 }
3366
3367 /* ACK the status ring. */
3368 tp->rx_rcb_ptr = sw_idx;
3369 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3370
3371 /* Refill RX ring(s). */
3372 if (work_mask & RXD_OPAQUE_RING_STD) {
3373 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3374 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3375 sw_idx);
3376 }
3377 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3378 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3379 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3380 sw_idx);
3381 }
3382 mmiowb();
3383
3384 return received;
3385 }
3386
3387 static int tg3_poll(struct net_device *netdev, int *budget)
3388 {
3389 struct tg3 *tp = netdev_priv(netdev);
3390 struct tg3_hw_status *sblk = tp->hw_status;
3391 int done;
3392
3393 /* handle link change and other phy events */
3394 if (!(tp->tg3_flags &
3395 (TG3_FLAG_USE_LINKCHG_REG |
3396 TG3_FLAG_POLL_SERDES))) {
3397 if (sblk->status & SD_STATUS_LINK_CHG) {
3398 sblk->status = SD_STATUS_UPDATED |
3399 (sblk->status & ~SD_STATUS_LINK_CHG);
3400 spin_lock(&tp->lock);
3401 tg3_setup_phy(tp, 0);
3402 spin_unlock(&tp->lock);
3403 }
3404 }
3405
3406 /* run TX completion thread */
3407 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3408 tg3_tx(tp);
3409 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3410 netif_rx_complete(netdev);
3411 schedule_work(&tp->reset_task);
3412 return 0;
3413 }
3414 }
3415
3416 /* run RX thread, within the bounds set by NAPI.
3417 * All RX "locking" is done by ensuring outside
3418 * code synchronizes with dev->poll()
3419 */
3420 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3421 int orig_budget = *budget;
3422 int work_done;
3423
3424 if (orig_budget > netdev->quota)
3425 orig_budget = netdev->quota;
3426
3427 work_done = tg3_rx(tp, orig_budget);
3428
3429 *budget -= work_done;
3430 netdev->quota -= work_done;
3431 }
3432
3433 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3434 tp->last_tag = sblk->status_tag;
3435 rmb();
3436 } else
3437 sblk->status &= ~SD_STATUS_UPDATED;
3438
3439 /* if no more work, tell net stack and NIC we're done */
3440 done = !tg3_has_work(tp);
3441 if (done) {
3442 netif_rx_complete(netdev);
3443 tg3_restart_ints(tp);
3444 }
3445
3446 return (done ? 0 : 1);
3447 }
3448
3449 static void tg3_irq_quiesce(struct tg3 *tp)
3450 {
3451 BUG_ON(tp->irq_sync);
3452
3453 tp->irq_sync = 1;
3454 smp_mb();
3455
3456 synchronize_irq(tp->pdev->irq);
3457 }
3458
3459 static inline int tg3_irq_sync(struct tg3 *tp)
3460 {
3461 return tp->irq_sync;
3462 }
3463
3464 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3465 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3466 * with as well. Most of the time, this is not necessary except when
3467 * shutting down the device.
3468 */
3469 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3470 {
3471 if (irq_sync)
3472 tg3_irq_quiesce(tp);
3473 spin_lock_bh(&tp->lock);
3474 }
3475
3476 static inline void tg3_full_unlock(struct tg3 *tp)
3477 {
3478 spin_unlock_bh(&tp->lock);
3479 }
3480
3481 /* One-shot MSI handler - Chip automatically disables interrupt
3482 * after sending MSI so driver doesn't have to do it.
3483 */
3484 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3485 {
3486 struct net_device *dev = dev_id;
3487 struct tg3 *tp = netdev_priv(dev);
3488
3489 prefetch(tp->hw_status);
3490 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3491
3492 if (likely(!tg3_irq_sync(tp)))
3493 netif_rx_schedule(dev); /* schedule NAPI poll */
3494
3495 return IRQ_HANDLED;
3496 }
3497
3498 /* MSI ISR - No need to check for interrupt sharing and no need to
3499 * flush status block and interrupt mailbox. PCI ordering rules
3500 * guarantee that MSI will arrive after the status block.
3501 */
3502 static irqreturn_t tg3_msi(int irq, void *dev_id)
3503 {
3504 struct net_device *dev = dev_id;
3505 struct tg3 *tp = netdev_priv(dev);
3506
3507 prefetch(tp->hw_status);
3508 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3509 /*
3510 * Writing any value to intr-mbox-0 clears PCI INTA# and
3511 * chip-internal interrupt pending events.
3512 * Writing non-zero to intr-mbox-0 additional tells the
3513 * NIC to stop sending us irqs, engaging "in-intr-handler"
3514 * event coalescing.
3515 */
3516 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3517 if (likely(!tg3_irq_sync(tp)))
3518 netif_rx_schedule(dev); /* schedule NAPI poll */
3519
3520 return IRQ_RETVAL(1);
3521 }
3522
3523 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3524 {
3525 struct net_device *dev = dev_id;
3526 struct tg3 *tp = netdev_priv(dev);
3527 struct tg3_hw_status *sblk = tp->hw_status;
3528 unsigned int handled = 1;
3529
3530 /* In INTx mode, it is possible for the interrupt to arrive at
3531 * the CPU before the status block posted prior to the interrupt.
3532 * Reading the PCI State register will confirm whether the
3533 * interrupt is ours and will flush the status block.
3534 */
3535 if ((sblk->status & SD_STATUS_UPDATED) ||
3536 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3537 /*
3538 * Writing any value to intr-mbox-0 clears PCI INTA# and
3539 * chip-internal interrupt pending events.
3540 * Writing non-zero to intr-mbox-0 additional tells the
3541 * NIC to stop sending us irqs, engaging "in-intr-handler"
3542 * event coalescing.
3543 */
3544 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3545 0x00000001);
3546 if (tg3_irq_sync(tp))
3547 goto out;
3548 sblk->status &= ~SD_STATUS_UPDATED;
3549 if (likely(tg3_has_work(tp))) {
3550 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3551 netif_rx_schedule(dev); /* schedule NAPI poll */
3552 } else {
3553 /* No work, shared interrupt perhaps? re-enable
3554 * interrupts, and flush that PCI write
3555 */
3556 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3557 0x00000000);
3558 }
3559 } else { /* shared interrupt */
3560 handled = 0;
3561 }
3562 out:
3563 return IRQ_RETVAL(handled);
3564 }
3565
3566 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3567 {
3568 struct net_device *dev = dev_id;
3569 struct tg3 *tp = netdev_priv(dev);
3570 struct tg3_hw_status *sblk = tp->hw_status;
3571 unsigned int handled = 1;
3572
3573 /* In INTx mode, it is possible for the interrupt to arrive at
3574 * the CPU before the status block posted prior to the interrupt.
3575 * Reading the PCI State register will confirm whether the
3576 * interrupt is ours and will flush the status block.
3577 */
3578 if ((sblk->status_tag != tp->last_tag) ||
3579 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3580 /*
3581 * writing any value to intr-mbox-0 clears PCI INTA# and
3582 * chip-internal interrupt pending events.
3583 * writing non-zero to intr-mbox-0 additional tells the
3584 * NIC to stop sending us irqs, engaging "in-intr-handler"
3585 * event coalescing.
3586 */
3587 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3588 0x00000001);
3589 if (tg3_irq_sync(tp))
3590 goto out;
3591 if (netif_rx_schedule_prep(dev)) {
3592 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3593 /* Update last_tag to mark that this status has been
3594 * seen. Because interrupt may be shared, we may be
3595 * racing with tg3_poll(), so only update last_tag
3596 * if tg3_poll() is not scheduled.
3597 */
3598 tp->last_tag = sblk->status_tag;
3599 __netif_rx_schedule(dev);
3600 }
3601 } else { /* shared interrupt */
3602 handled = 0;
3603 }
3604 out:
3605 return IRQ_RETVAL(handled);
3606 }
3607
3608 /* ISR for interrupt test */
3609 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3610 {
3611 struct net_device *dev = dev_id;
3612 struct tg3 *tp = netdev_priv(dev);
3613 struct tg3_hw_status *sblk = tp->hw_status;
3614
3615 if ((sblk->status & SD_STATUS_UPDATED) ||
3616 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3617 tg3_disable_ints(tp);
3618 return IRQ_RETVAL(1);
3619 }
3620 return IRQ_RETVAL(0);
3621 }
3622
3623 static int tg3_init_hw(struct tg3 *, int);
3624 static int tg3_halt(struct tg3 *, int, int);
3625
3626 /* Restart hardware after configuration changes, self-test, etc.
3627 * Invoked with tp->lock held.
3628 */
3629 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3630 {
3631 int err;
3632
3633 err = tg3_init_hw(tp, reset_phy);
3634 if (err) {
3635 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3636 "aborting.\n", tp->dev->name);
3637 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3638 tg3_full_unlock(tp);
3639 del_timer_sync(&tp->timer);
3640 tp->irq_sync = 0;
3641 netif_poll_enable(tp->dev);
3642 dev_close(tp->dev);
3643 tg3_full_lock(tp, 0);
3644 }
3645 return err;
3646 }
3647
3648 #ifdef CONFIG_NET_POLL_CONTROLLER
3649 static void tg3_poll_controller(struct net_device *dev)
3650 {
3651 struct tg3 *tp = netdev_priv(dev);
3652
3653 tg3_interrupt(tp->pdev->irq, dev);
3654 }
3655 #endif
3656
3657 static void tg3_reset_task(void *_data)
3658 {
3659 struct tg3 *tp = _data;
3660 unsigned int restart_timer;
3661
3662 tg3_full_lock(tp, 0);
3663 tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3664
3665 if (!netif_running(tp->dev)) {
3666 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3667 tg3_full_unlock(tp);
3668 return;
3669 }
3670
3671 tg3_full_unlock(tp);
3672
3673 tg3_netif_stop(tp);
3674
3675 tg3_full_lock(tp, 1);
3676
3677 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3678 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3679
3680 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3681 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3682 tp->write32_rx_mbox = tg3_write_flush_reg32;
3683 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3684 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3685 }
3686
3687 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3688 if (tg3_init_hw(tp, 1))
3689 goto out;
3690
3691 tg3_netif_start(tp);
3692
3693 if (restart_timer)
3694 mod_timer(&tp->timer, jiffies + 1);
3695
3696 out:
3697 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3698
3699 tg3_full_unlock(tp);
3700 }
3701
3702 static void tg3_tx_timeout(struct net_device *dev)
3703 {
3704 struct tg3 *tp = netdev_priv(dev);
3705
3706 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3707 dev->name);
3708
3709 schedule_work(&tp->reset_task);
3710 }
3711
3712 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3713 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3714 {
3715 u32 base = (u32) mapping & 0xffffffff;
3716
3717 return ((base > 0xffffdcc0) &&
3718 (base + len + 8 < base));
3719 }
3720
3721 /* Test for DMA addresses > 40-bit */
3722 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3723 int len)
3724 {
3725 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3726 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3727 return (((u64) mapping + len) > DMA_40BIT_MASK);
3728 return 0;
3729 #else
3730 return 0;
3731 #endif
3732 }
3733
3734 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3735
3736 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3737 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3738 u32 last_plus_one, u32 *start,
3739 u32 base_flags, u32 mss)
3740 {
3741 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3742 dma_addr_t new_addr = 0;
3743 u32 entry = *start;
3744 int i, ret = 0;
3745
3746 if (!new_skb) {
3747 ret = -1;
3748 } else {
3749 /* New SKB is guaranteed to be linear. */
3750 entry = *start;
3751 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3752 PCI_DMA_TODEVICE);
3753 /* Make sure new skb does not cross any 4G boundaries.
3754 * Drop the packet if it does.
3755 */
3756 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3757 ret = -1;
3758 dev_kfree_skb(new_skb);
3759 new_skb = NULL;
3760 } else {
3761 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3762 base_flags, 1 | (mss << 1));
3763 *start = NEXT_TX(entry);
3764 }
3765 }
3766
3767 /* Now clean up the sw ring entries. */
3768 i = 0;
3769 while (entry != last_plus_one) {
3770 int len;
3771
3772 if (i == 0)
3773 len = skb_headlen(skb);
3774 else
3775 len = skb_shinfo(skb)->frags[i-1].size;
3776 pci_unmap_single(tp->pdev,
3777 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3778 len, PCI_DMA_TODEVICE);
3779 if (i == 0) {
3780 tp->tx_buffers[entry].skb = new_skb;
3781 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3782 } else {
3783 tp->tx_buffers[entry].skb = NULL;
3784 }
3785 entry = NEXT_TX(entry);
3786 i++;
3787 }
3788
3789 dev_kfree_skb(skb);
3790
3791 return ret;
3792 }
3793
3794 static void tg3_set_txd(struct tg3 *tp, int entry,
3795 dma_addr_t mapping, int len, u32 flags,
3796 u32 mss_and_is_end)
3797 {
3798 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3799 int is_end = (mss_and_is_end & 0x1);
3800 u32 mss = (mss_and_is_end >> 1);
3801 u32 vlan_tag = 0;
3802
3803 if (is_end)
3804 flags |= TXD_FLAG_END;
3805 if (flags & TXD_FLAG_VLAN) {
3806 vlan_tag = flags >> 16;
3807 flags &= 0xffff;
3808 }
3809 vlan_tag |= (mss << TXD_MSS_SHIFT);
3810
3811 txd->addr_hi = ((u64) mapping >> 32);
3812 txd->addr_lo = ((u64) mapping & 0xffffffff);
3813 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3814 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3815 }
3816
3817 /* hard_start_xmit for devices that don't have any bugs and
3818 * support TG3_FLG2_HW_TSO_2 only.
3819 */
3820 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3821 {
3822 struct tg3 *tp = netdev_priv(dev);
3823 dma_addr_t mapping;
3824 u32 len, entry, base_flags, mss;
3825
3826 len = skb_headlen(skb);
3827
3828 /* We are running in BH disabled context with netif_tx_lock
3829 * and TX reclaim runs via tp->poll inside of a software
3830 * interrupt. Furthermore, IRQ processing runs lockless so we have
3831 * no IRQ context deadlocks to worry about either. Rejoice!
3832 */
3833 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3834 if (!netif_queue_stopped(dev)) {
3835 netif_stop_queue(dev);
3836
3837 /* This is a hard error, log it. */
3838 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3839 "queue awake!\n", dev->name);
3840 }
3841 return NETDEV_TX_BUSY;
3842 }
3843
3844 entry = tp->tx_prod;
3845 base_flags = 0;
3846 #if TG3_TSO_SUPPORT != 0
3847 mss = 0;
3848 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3849 (mss = skb_shinfo(skb)->gso_size) != 0) {
3850 int tcp_opt_len, ip_tcp_len;
3851
3852 if (skb_header_cloned(skb) &&
3853 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3854 dev_kfree_skb(skb);
3855 goto out_unlock;
3856 }
3857
3858 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3859 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3860 else {
3861 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3862 ip_tcp_len = (skb->nh.iph->ihl * 4) +
3863 sizeof(struct tcphdr);
3864
3865 skb->nh.iph->check = 0;
3866 skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3867 tcp_opt_len);
3868 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3869 }
3870
3871 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3872 TXD_FLAG_CPU_POST_DMA);
3873
3874 skb->h.th->check = 0;
3875
3876 }
3877 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3878 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3879 #else
3880 mss = 0;
3881 if (skb->ip_summed == CHECKSUM_PARTIAL)
3882 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3883 #endif
3884 #if TG3_VLAN_TAG_USED
3885 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3886 base_flags |= (TXD_FLAG_VLAN |
3887 (vlan_tx_tag_get(skb) << 16));
3888 #endif
3889
3890 /* Queue skb data, a.k.a. the main skb fragment. */
3891 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3892
3893 tp->tx_buffers[entry].skb = skb;
3894 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3895
3896 tg3_set_txd(tp, entry, mapping, len, base_flags,
3897 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3898
3899 entry = NEXT_TX(entry);
3900
3901 /* Now loop through additional data fragments, and queue them. */
3902 if (skb_shinfo(skb)->nr_frags > 0) {
3903 unsigned int i, last;
3904
3905 last = skb_shinfo(skb)->nr_frags - 1;
3906 for (i = 0; i <= last; i++) {
3907 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3908
3909 len = frag->size;
3910 mapping = pci_map_page(tp->pdev,
3911 frag->page,
3912 frag->page_offset,
3913 len, PCI_DMA_TODEVICE);
3914
3915 tp->tx_buffers[entry].skb = NULL;
3916 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3917
3918 tg3_set_txd(tp, entry, mapping, len,
3919 base_flags, (i == last) | (mss << 1));
3920
3921 entry = NEXT_TX(entry);
3922 }
3923 }
3924
3925 /* Packets are ready, update Tx producer idx local and on card. */
3926 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3927
3928 tp->tx_prod = entry;
3929 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3930 netif_stop_queue(dev);
3931 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3932 netif_wake_queue(tp->dev);
3933 }
3934
3935 out_unlock:
3936 mmiowb();
3937
3938 dev->trans_start = jiffies;
3939
3940 return NETDEV_TX_OK;
3941 }
3942
3943 #if TG3_TSO_SUPPORT != 0
3944 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3945
3946 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3947 * TSO header is greater than 80 bytes.
3948 */
3949 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3950 {
3951 struct sk_buff *segs, *nskb;
3952
3953 /* Estimate the number of fragments in the worst case */
3954 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3955 netif_stop_queue(tp->dev);
3956 return NETDEV_TX_BUSY;
3957 }
3958
3959 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3960 if (unlikely(IS_ERR(segs)))
3961 goto tg3_tso_bug_end;
3962
3963 do {
3964 nskb = segs;
3965 segs = segs->next;
3966 nskb->next = NULL;
3967 tg3_start_xmit_dma_bug(nskb, tp->dev);
3968 } while (segs);
3969
3970 tg3_tso_bug_end:
3971 dev_kfree_skb(skb);
3972
3973 return NETDEV_TX_OK;
3974 }
3975 #endif
3976
3977 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3978 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3979 */
3980 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3981 {
3982 struct tg3 *tp = netdev_priv(dev);
3983 dma_addr_t mapping;
3984 u32 len, entry, base_flags, mss;
3985 int would_hit_hwbug;
3986
3987 len = skb_headlen(skb);
3988
3989 /* We are running in BH disabled context with netif_tx_lock
3990 * and TX reclaim runs via tp->poll inside of a software
3991 * interrupt. Furthermore, IRQ processing runs lockless so we have
3992 * no IRQ context deadlocks to worry about either. Rejoice!
3993 */
3994 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3995 if (!netif_queue_stopped(dev)) {
3996 netif_stop_queue(dev);
3997
3998 /* This is a hard error, log it. */
3999 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4000 "queue awake!\n", dev->name);
4001 }
4002 return NETDEV_TX_BUSY;
4003 }
4004
4005 entry = tp->tx_prod;
4006 base_flags = 0;
4007 if (skb->ip_summed == CHECKSUM_PARTIAL)
4008 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4009 #if TG3_TSO_SUPPORT != 0
4010 mss = 0;
4011 if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4012 (mss = skb_shinfo(skb)->gso_size) != 0) {
4013 int tcp_opt_len, ip_tcp_len, hdr_len;
4014
4015 if (skb_header_cloned(skb) &&
4016 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4017 dev_kfree_skb(skb);
4018 goto out_unlock;
4019 }
4020
4021 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4022 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4023
4024 hdr_len = ip_tcp_len + tcp_opt_len;
4025 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4026 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4027 return (tg3_tso_bug(tp, skb));
4028
4029 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4030 TXD_FLAG_CPU_POST_DMA);
4031
4032 skb->nh.iph->check = 0;
4033 skb->nh.iph->tot_len = htons(mss + hdr_len);
4034 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4035 skb->h.th->check = 0;
4036 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4037 }
4038 else {
4039 skb->h.th->check =
4040 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4041 skb->nh.iph->daddr,
4042 0, IPPROTO_TCP, 0);
4043 }
4044
4045 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4046 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4047 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4048 int tsflags;
4049
4050 tsflags = ((skb->nh.iph->ihl - 5) +
4051 (tcp_opt_len >> 2));
4052 mss |= (tsflags << 11);
4053 }
4054 } else {
4055 if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4056 int tsflags;
4057
4058 tsflags = ((skb->nh.iph->ihl - 5) +
4059 (tcp_opt_len >> 2));
4060 base_flags |= tsflags << 12;
4061 }
4062 }
4063 }
4064 #else
4065 mss = 0;
4066 #endif
4067 #if TG3_VLAN_TAG_USED
4068 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4069 base_flags |= (TXD_FLAG_VLAN |
4070 (vlan_tx_tag_get(skb) << 16));
4071 #endif
4072
4073 /* Queue skb data, a.k.a. the main skb fragment. */
4074 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4075
4076 tp->tx_buffers[entry].skb = skb;
4077 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4078
4079 would_hit_hwbug = 0;
4080
4081 if (tg3_4g_overflow_test(mapping, len))
4082 would_hit_hwbug = 1;
4083
4084 tg3_set_txd(tp, entry, mapping, len, base_flags,
4085 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4086
4087 entry = NEXT_TX(entry);
4088
4089 /* Now loop through additional data fragments, and queue them. */
4090 if (skb_shinfo(skb)->nr_frags > 0) {
4091 unsigned int i, last;
4092
4093 last = skb_shinfo(skb)->nr_frags - 1;
4094 for (i = 0; i <= last; i++) {
4095 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4096
4097 len = frag->size;
4098 mapping = pci_map_page(tp->pdev,
4099 frag->page,
4100 frag->page_offset,
4101 len, PCI_DMA_TODEVICE);
4102
4103 tp->tx_buffers[entry].skb = NULL;
4104 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4105
4106 if (tg3_4g_overflow_test(mapping, len))
4107 would_hit_hwbug = 1;
4108
4109 if (tg3_40bit_overflow_test(tp, mapping, len))
4110 would_hit_hwbug = 1;
4111
4112 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4113 tg3_set_txd(tp, entry, mapping, len,
4114 base_flags, (i == last)|(mss << 1));
4115 else
4116 tg3_set_txd(tp, entry, mapping, len,
4117 base_flags, (i == last));
4118
4119 entry = NEXT_TX(entry);
4120 }
4121 }
4122
4123 if (would_hit_hwbug) {
4124 u32 last_plus_one = entry;
4125 u32 start;
4126
4127 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4128 start &= (TG3_TX_RING_SIZE - 1);
4129
4130 /* If the workaround fails due to memory/mapping
4131 * failure, silently drop this packet.
4132 */
4133 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4134 &start, base_flags, mss))
4135 goto out_unlock;
4136
4137 entry = start;
4138 }
4139
4140 /* Packets are ready, update Tx producer idx local and on card. */
4141 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4142
4143 tp->tx_prod = entry;
4144 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4145 netif_stop_queue(dev);
4146 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4147 netif_wake_queue(tp->dev);
4148 }
4149
4150 out_unlock:
4151 mmiowb();
4152
4153 dev->trans_start = jiffies;
4154
4155 return NETDEV_TX_OK;
4156 }
4157
4158 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4159 int new_mtu)
4160 {
4161 dev->mtu = new_mtu;
4162
4163 if (new_mtu > ETH_DATA_LEN) {
4164 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4165 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4166 ethtool_op_set_tso(dev, 0);
4167 }
4168 else
4169 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4170 } else {
4171 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4172 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4173 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4174 }
4175 }
4176
4177 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4178 {
4179 struct tg3 *tp = netdev_priv(dev);
4180 int err;
4181
4182 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4183 return -EINVAL;
4184
4185 if (!netif_running(dev)) {
4186 /* We'll just catch it later when the
4187 * device is up'd.
4188 */
4189 tg3_set_mtu(dev, tp, new_mtu);
4190 return 0;
4191 }
4192
4193 tg3_netif_stop(tp);
4194
4195 tg3_full_lock(tp, 1);
4196
4197 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4198
4199 tg3_set_mtu(dev, tp, new_mtu);
4200
4201 err = tg3_restart_hw(tp, 0);
4202
4203 if (!err)
4204 tg3_netif_start(tp);
4205
4206 tg3_full_unlock(tp);
4207
4208 return err;
4209 }
4210
4211 /* Free up pending packets in all rx/tx rings.
4212 *
4213 * The chip has been shut down and the driver detached from
4214 * the networking, so no interrupts or new tx packets will
4215 * end up in the driver. tp->{tx,}lock is not held and we are not
4216 * in an interrupt context and thus may sleep.
4217 */
4218 static void tg3_free_rings(struct tg3 *tp)
4219 {
4220 struct ring_info *rxp;
4221 int i;
4222
4223 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4224 rxp = &tp->rx_std_buffers[i];
4225
4226 if (rxp->skb == NULL)
4227 continue;
4228 pci_unmap_single(tp->pdev,
4229 pci_unmap_addr(rxp, mapping),
4230 tp->rx_pkt_buf_sz - tp->rx_offset,
4231 PCI_DMA_FROMDEVICE);
4232 dev_kfree_skb_any(rxp->skb);
4233 rxp->skb = NULL;
4234 }
4235
4236 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4237 rxp = &tp->rx_jumbo_buffers[i];
4238
4239 if (rxp->skb == NULL)
4240 continue;
4241 pci_unmap_single(tp->pdev,
4242 pci_unmap_addr(rxp, mapping),
4243 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4244 PCI_DMA_FROMDEVICE);
4245 dev_kfree_skb_any(rxp->skb);
4246 rxp->skb = NULL;
4247 }
4248
4249 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4250 struct tx_ring_info *txp;
4251 struct sk_buff *skb;
4252 int j;
4253
4254 txp = &tp->tx_buffers[i];
4255 skb = txp->skb;
4256
4257 if (skb == NULL) {
4258 i++;
4259 continue;
4260 }
4261
4262 pci_unmap_single(tp->pdev,
4263 pci_unmap_addr(txp, mapping),
4264 skb_headlen(skb),
4265 PCI_DMA_TODEVICE);
4266 txp->skb = NULL;
4267
4268 i++;
4269
4270 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4271 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4272 pci_unmap_page(tp->pdev,
4273 pci_unmap_addr(txp, mapping),
4274 skb_shinfo(skb)->frags[j].size,
4275 PCI_DMA_TODEVICE);
4276 i++;
4277 }
4278
4279 dev_kfree_skb_any(skb);
4280 }
4281 }
4282
4283 /* Initialize tx/rx rings for packet processing.
4284 *
4285 * The chip has been shut down and the driver detached from
4286 * the networking, so no interrupts or new tx packets will
4287 * end up in the driver. tp->{tx,}lock are held and thus
4288 * we may not sleep.
4289 */
4290 static int tg3_init_rings(struct tg3 *tp)
4291 {
4292 u32 i;
4293
4294 /* Free up all the SKBs. */
4295 tg3_free_rings(tp);
4296
4297 /* Zero out all descriptors. */
4298 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4299 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4300 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4301 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4302
4303 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4304 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4305 (tp->dev->mtu > ETH_DATA_LEN))
4306 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4307
4308 /* Initialize invariants of the rings, we only set this
4309 * stuff once. This works because the card does not
4310 * write into the rx buffer posting rings.
4311 */
4312 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4313 struct tg3_rx_buffer_desc *rxd;
4314
4315 rxd = &tp->rx_std[i];
4316 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4317 << RXD_LEN_SHIFT;
4318 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4319 rxd->opaque = (RXD_OPAQUE_RING_STD |
4320 (i << RXD_OPAQUE_INDEX_SHIFT));
4321 }
4322
4323 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4324 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4325 struct tg3_rx_buffer_desc *rxd;
4326
4327 rxd = &tp->rx_jumbo[i];
4328 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4329 << RXD_LEN_SHIFT;
4330 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4331 RXD_FLAG_JUMBO;
4332 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4333 (i << RXD_OPAQUE_INDEX_SHIFT));
4334 }
4335 }
4336
4337 /* Now allocate fresh SKBs for each rx ring. */
4338 for (i = 0; i < tp->rx_pending; i++) {
4339 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4340 printk(KERN_WARNING PFX
4341 "%s: Using a smaller RX standard ring, "
4342 "only %d out of %d buffers were allocated "
4343 "successfully.\n",
4344 tp->dev->name, i, tp->rx_pending);
4345 if (i == 0)
4346 return -ENOMEM;
4347 tp->rx_pending = i;
4348 break;
4349 }
4350 }
4351
4352 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4353 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4354 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4355 -1, i) < 0) {
4356 printk(KERN_WARNING PFX
4357 "%s: Using a smaller RX jumbo ring, "
4358 "only %d out of %d buffers were "
4359 "allocated successfully.\n",
4360 tp->dev->name, i, tp->rx_jumbo_pending);
4361 if (i == 0) {
4362 tg3_free_rings(tp);
4363 return -ENOMEM;
4364 }
4365 tp->rx_jumbo_pending = i;
4366 break;
4367 }
4368 }
4369 }
4370 return 0;
4371 }
4372
4373 /*
4374 * Must not be invoked with interrupt sources disabled and
4375 * the hardware shutdown down.
4376 */
4377 static void tg3_free_consistent(struct tg3 *tp)
4378 {
4379 kfree(tp->rx_std_buffers);
4380 tp->rx_std_buffers = NULL;
4381 if (tp->rx_std) {
4382 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4383 tp->rx_std, tp->rx_std_mapping);
4384 tp->rx_std = NULL;
4385 }
4386 if (tp->rx_jumbo) {
4387 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4388 tp->rx_jumbo, tp->rx_jumbo_mapping);
4389 tp->rx_jumbo = NULL;
4390 }
4391 if (tp->rx_rcb) {
4392 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4393 tp->rx_rcb, tp->rx_rcb_mapping);
4394 tp->rx_rcb = NULL;
4395 }
4396 if (tp->tx_ring) {
4397 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4398 tp->tx_ring, tp->tx_desc_mapping);
4399 tp->tx_ring = NULL;
4400 }
4401 if (tp->hw_status) {
4402 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4403 tp->hw_status, tp->status_mapping);
4404 tp->hw_status = NULL;
4405 }
4406 if (tp->hw_stats) {
4407 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4408 tp->hw_stats, tp->stats_mapping);
4409 tp->hw_stats = NULL;
4410 }
4411 }
4412
4413 /*
4414 * Must not be invoked with interrupt sources disabled and
4415 * the hardware shutdown down. Can sleep.
4416 */
4417 static int tg3_alloc_consistent(struct tg3 *tp)
4418 {
4419 tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4420 (TG3_RX_RING_SIZE +
4421 TG3_RX_JUMBO_RING_SIZE)) +
4422 (sizeof(struct tx_ring_info) *
4423 TG3_TX_RING_SIZE),
4424 GFP_KERNEL);
4425 if (!tp->rx_std_buffers)
4426 return -ENOMEM;
4427
4428 memset(tp->rx_std_buffers, 0,
4429 (sizeof(struct ring_info) *
4430 (TG3_RX_RING_SIZE +
4431 TG3_RX_JUMBO_RING_SIZE)) +
4432 (sizeof(struct tx_ring_info) *
4433 TG3_TX_RING_SIZE));
4434
4435 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4436 tp->tx_buffers = (struct tx_ring_info *)
4437 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4438
4439 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4440 &tp->rx_std_mapping);
4441 if (!tp->rx_std)
4442 goto err_out;
4443
4444 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4445 &tp->rx_jumbo_mapping);
4446
4447 if (!tp->rx_jumbo)
4448 goto err_out;
4449
4450 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4451 &tp->rx_rcb_mapping);
4452 if (!tp->rx_rcb)
4453 goto err_out;
4454
4455 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4456 &tp->tx_desc_mapping);
4457 if (!tp->tx_ring)
4458 goto err_out;
4459
4460 tp->hw_status = pci_alloc_consistent(tp->pdev,
4461 TG3_HW_STATUS_SIZE,
4462 &tp->status_mapping);
4463 if (!tp->hw_status)
4464 goto err_out;
4465
4466 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4467 sizeof(struct tg3_hw_stats),
4468 &tp->stats_mapping);
4469 if (!tp->hw_stats)
4470 goto err_out;
4471
4472 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4473 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4474
4475 return 0;
4476
4477 err_out:
4478 tg3_free_consistent(tp);
4479 return -ENOMEM;
4480 }
4481
4482 #define MAX_WAIT_CNT 1000
4483
4484 /* To stop a block, clear the enable bit and poll till it
4485 * clears. tp->lock is held.
4486 */
4487 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4488 {
4489 unsigned int i;
4490 u32 val;
4491
4492 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4493 switch (ofs) {
4494 case RCVLSC_MODE:
4495 case DMAC_MODE:
4496 case MBFREE_MODE:
4497 case BUFMGR_MODE:
4498 case MEMARB_MODE:
4499 /* We can't enable/disable these bits of the
4500 * 5705/5750, just say success.
4501 */
4502 return 0;
4503
4504 default:
4505 break;
4506 };
4507 }
4508
4509 val = tr32(ofs);
4510 val &= ~enable_bit;
4511 tw32_f(ofs, val);
4512
4513 for (i = 0; i < MAX_WAIT_CNT; i++) {
4514 udelay(100);
4515 val = tr32(ofs);
4516 if ((val & enable_bit) == 0)
4517 break;
4518 }
4519
4520 if (i == MAX_WAIT_CNT && !silent) {
4521 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4522 "ofs=%lx enable_bit=%x\n",
4523 ofs, enable_bit);
4524 return -ENODEV;
4525 }
4526
4527 return 0;
4528 }
4529
4530 /* tp->lock is held. */
4531 static int tg3_abort_hw(struct tg3 *tp, int silent)
4532 {
4533 int i, err;
4534
4535 tg3_disable_ints(tp);
4536
4537 tp->rx_mode &= ~RX_MODE_ENABLE;
4538 tw32_f(MAC_RX_MODE, tp->rx_mode);
4539 udelay(10);
4540
4541 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4542 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4543 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4544 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4545 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4546 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4547
4548 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4549 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4550 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4551 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4552 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4553 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4554 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4555
4556 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4557 tw32_f(MAC_MODE, tp->mac_mode);
4558 udelay(40);
4559
4560 tp->tx_mode &= ~TX_MODE_ENABLE;
4561 tw32_f(MAC_TX_MODE, tp->tx_mode);
4562
4563 for (i = 0; i < MAX_WAIT_CNT; i++) {
4564 udelay(100);
4565 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4566 break;
4567 }
4568 if (i >= MAX_WAIT_CNT) {
4569 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4570 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4571 tp->dev->name, tr32(MAC_TX_MODE));
4572 err |= -ENODEV;
4573 }
4574
4575 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4576 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4577 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4578
4579 tw32(FTQ_RESET, 0xffffffff);
4580 tw32(FTQ_RESET, 0x00000000);
4581
4582 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4583 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4584
4585 if (tp->hw_status)
4586 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4587 if (tp->hw_stats)
4588 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4589
4590 return err;
4591 }
4592
4593 /* tp->lock is held. */
4594 static int tg3_nvram_lock(struct tg3 *tp)
4595 {
4596 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4597 int i;
4598
4599 if (tp->nvram_lock_cnt == 0) {
4600 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4601 for (i = 0; i < 8000; i++) {
4602 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4603 break;
4604 udelay(20);
4605 }
4606 if (i == 8000) {
4607 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4608 return -ENODEV;
4609 }
4610 }
4611 tp->nvram_lock_cnt++;
4612 }
4613 return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static void tg3_nvram_unlock(struct tg3 *tp)
4618 {
4619 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4620 if (tp->nvram_lock_cnt > 0)
4621 tp->nvram_lock_cnt--;
4622 if (tp->nvram_lock_cnt == 0)
4623 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4624 }
4625 }
4626
4627 /* tp->lock is held. */
4628 static void tg3_enable_nvram_access(struct tg3 *tp)
4629 {
4630 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4631 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4632 u32 nvaccess = tr32(NVRAM_ACCESS);
4633
4634 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4635 }
4636 }
4637
4638 /* tp->lock is held. */
4639 static void tg3_disable_nvram_access(struct tg3 *tp)
4640 {
4641 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4642 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4643 u32 nvaccess = tr32(NVRAM_ACCESS);
4644
4645 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4646 }
4647 }
4648
4649 /* tp->lock is held. */
4650 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4651 {
4652 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4653 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4654
4655 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4656 switch (kind) {
4657 case RESET_KIND_INIT:
4658 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4659 DRV_STATE_START);
4660 break;
4661
4662 case RESET_KIND_SHUTDOWN:
4663 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4664 DRV_STATE_UNLOAD);
4665 break;
4666
4667 case RESET_KIND_SUSPEND:
4668 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4669 DRV_STATE_SUSPEND);
4670 break;
4671
4672 default:
4673 break;
4674 };
4675 }
4676 }
4677
4678 /* tp->lock is held. */
4679 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4680 {
4681 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4682 switch (kind) {
4683 case RESET_KIND_INIT:
4684 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4685 DRV_STATE_START_DONE);
4686 break;
4687
4688 case RESET_KIND_SHUTDOWN:
4689 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4690 DRV_STATE_UNLOAD_DONE);
4691 break;
4692
4693 default:
4694 break;
4695 };
4696 }
4697 }
4698
4699 /* tp->lock is held. */
4700 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4701 {
4702 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4703 switch (kind) {
4704 case RESET_KIND_INIT:
4705 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4706 DRV_STATE_START);
4707 break;
4708
4709 case RESET_KIND_SHUTDOWN:
4710 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4711 DRV_STATE_UNLOAD);
4712 break;
4713
4714 case RESET_KIND_SUSPEND:
4715 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716 DRV_STATE_SUSPEND);
4717 break;
4718
4719 default:
4720 break;
4721 };
4722 }
4723 }
4724
4725 static int tg3_poll_fw(struct tg3 *tp)
4726 {
4727 int i;
4728 u32 val;
4729
4730 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4731 for (i = 0; i < 400; i++) {
4732 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4733 return 0;
4734 udelay(10);
4735 }
4736 return -ENODEV;
4737 }
4738
4739 /* Wait for firmware initialization to complete. */
4740 for (i = 0; i < 100000; i++) {
4741 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4742 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4743 break;
4744 udelay(10);
4745 }
4746
4747 /* Chip might not be fitted with firmware. Some Sun onboard
4748 * parts are configured like that. So don't signal the timeout
4749 * of the above loop as an error, but do report the lack of
4750 * running firmware once.
4751 */
4752 if (i >= 100000 &&
4753 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4754 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4755
4756 printk(KERN_INFO PFX "%s: No firmware running.\n",
4757 tp->dev->name);
4758 }
4759
4760 return 0;
4761 }
4762
4763 static void tg3_stop_fw(struct tg3 *);
4764
4765 /* tp->lock is held. */
4766 static int tg3_chip_reset(struct tg3 *tp)
4767 {
4768 u32 val;
4769 void (*write_op)(struct tg3 *, u32, u32);
4770 int err;
4771
4772 tg3_nvram_lock(tp);
4773
4774 /* No matching tg3_nvram_unlock() after this because
4775 * chip reset below will undo the nvram lock.
4776 */
4777 tp->nvram_lock_cnt = 0;
4778
4779 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4780 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4781 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4782 tw32(GRC_FASTBOOT_PC, 0);
4783
4784 /*
4785 * We must avoid the readl() that normally takes place.
4786 * It locks machines, causes machine checks, and other
4787 * fun things. So, temporarily disable the 5701
4788 * hardware workaround, while we do the reset.
4789 */
4790 write_op = tp->write32;
4791 if (write_op == tg3_write_flush_reg32)
4792 tp->write32 = tg3_write32;
4793
4794 /* do the reset */
4795 val = GRC_MISC_CFG_CORECLK_RESET;
4796
4797 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4798 if (tr32(0x7e2c) == 0x60) {
4799 tw32(0x7e2c, 0x20);
4800 }
4801 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4802 tw32(GRC_MISC_CFG, (1 << 29));
4803 val |= (1 << 29);
4804 }
4805 }
4806
4807 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4808 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4809 tw32(GRC_VCPU_EXT_CTRL,
4810 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4811 }
4812
4813 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4814 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4815 tw32(GRC_MISC_CFG, val);
4816
4817 /* restore 5701 hardware bug workaround write method */
4818 tp->write32 = write_op;
4819
4820 /* Unfortunately, we have to delay before the PCI read back.
4821 * Some 575X chips even will not respond to a PCI cfg access
4822 * when the reset command is given to the chip.
4823 *
4824 * How do these hardware designers expect things to work
4825 * properly if the PCI write is posted for a long period
4826 * of time? It is always necessary to have some method by
4827 * which a register read back can occur to push the write
4828 * out which does the reset.
4829 *
4830 * For most tg3 variants the trick below was working.
4831 * Ho hum...
4832 */
4833 udelay(120);
4834
4835 /* Flush PCI posted writes. The normal MMIO registers
4836 * are inaccessible at this time so this is the only
4837 * way to make this reliably (actually, this is no longer
4838 * the case, see above). I tried to use indirect
4839 * register read/write but this upset some 5701 variants.
4840 */
4841 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4842
4843 udelay(120);
4844
4845 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4846 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4847 int i;
4848 u32 cfg_val;
4849
4850 /* Wait for link training to complete. */
4851 for (i = 0; i < 5000; i++)
4852 udelay(100);
4853
4854 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4855 pci_write_config_dword(tp->pdev, 0xc4,
4856 cfg_val | (1 << 15));
4857 }
4858 /* Set PCIE max payload size and clear error status. */
4859 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4860 }
4861
4862 /* Re-enable indirect register accesses. */
4863 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4864 tp->misc_host_ctrl);
4865
4866 /* Set MAX PCI retry to zero. */
4867 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4868 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4869 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4870 val |= PCISTATE_RETRY_SAME_DMA;
4871 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4872
4873 pci_restore_state(tp->pdev);
4874
4875 /* Make sure PCI-X relaxed ordering bit is clear. */
4876 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4877 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4878 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4879
4880 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4881 u32 val;
4882
4883 /* Chip reset on 5780 will reset MSI enable bit,
4884 * so need to restore it.
4885 */
4886 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4887 u16 ctrl;
4888
4889 pci_read_config_word(tp->pdev,
4890 tp->msi_cap + PCI_MSI_FLAGS,
4891 &ctrl);
4892 pci_write_config_word(tp->pdev,
4893 tp->msi_cap + PCI_MSI_FLAGS,
4894 ctrl | PCI_MSI_FLAGS_ENABLE);
4895 val = tr32(MSGINT_MODE);
4896 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4897 }
4898
4899 val = tr32(MEMARB_MODE);
4900 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4901
4902 } else
4903 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4904
4905 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4906 tg3_stop_fw(tp);
4907 tw32(0x5000, 0x400);
4908 }
4909
4910 tw32(GRC_MODE, tp->grc_mode);
4911
4912 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4913 u32 val = tr32(0xc4);
4914
4915 tw32(0xc4, val | (1 << 15));
4916 }
4917
4918 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4919 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4920 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4921 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4922 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4923 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4924 }
4925
4926 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4927 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4928 tw32_f(MAC_MODE, tp->mac_mode);
4929 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4930 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4931 tw32_f(MAC_MODE, tp->mac_mode);
4932 } else
4933 tw32_f(MAC_MODE, 0);
4934 udelay(40);
4935
4936 err = tg3_poll_fw(tp);
4937 if (err)
4938 return err;
4939
4940 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4941 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4942 u32 val = tr32(0x7c00);
4943
4944 tw32(0x7c00, val | (1 << 25));
4945 }
4946
4947 /* Reprobe ASF enable state. */
4948 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4949 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4950 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4951 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4952 u32 nic_cfg;
4953
4954 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4955 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4956 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4957 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4958 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4959 }
4960 }
4961
4962 return 0;
4963 }
4964
4965 /* tp->lock is held. */
4966 static void tg3_stop_fw(struct tg3 *tp)
4967 {
4968 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4969 u32 val;
4970 int i;
4971
4972 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4973 val = tr32(GRC_RX_CPU_EVENT);
4974 val |= (1 << 14);
4975 tw32(GRC_RX_CPU_EVENT, val);
4976
4977 /* Wait for RX cpu to ACK the event. */
4978 for (i = 0; i < 100; i++) {
4979 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4980 break;
4981 udelay(1);
4982 }
4983 }
4984 }
4985
4986 /* tp->lock is held. */
4987 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4988 {
4989 int err;
4990
4991 tg3_stop_fw(tp);
4992
4993 tg3_write_sig_pre_reset(tp, kind);
4994
4995 tg3_abort_hw(tp, silent);
4996 err = tg3_chip_reset(tp);
4997
4998 tg3_write_sig_legacy(tp, kind);
4999 tg3_write_sig_post_reset(tp, kind);
5000
5001 if (err)
5002 return err;
5003
5004 return 0;
5005 }
5006
5007 #define TG3_FW_RELEASE_MAJOR 0x0
5008 #define TG3_FW_RELASE_MINOR 0x0
5009 #define TG3_FW_RELEASE_FIX 0x0
5010 #define TG3_FW_START_ADDR 0x08000000
5011 #define TG3_FW_TEXT_ADDR 0x08000000
5012 #define TG3_FW_TEXT_LEN 0x9c0
5013 #define TG3_FW_RODATA_ADDR 0x080009c0
5014 #define TG3_FW_RODATA_LEN 0x60
5015 #define TG3_FW_DATA_ADDR 0x08000a40
5016 #define TG3_FW_DATA_LEN 0x20
5017 #define TG3_FW_SBSS_ADDR 0x08000a60
5018 #define TG3_FW_SBSS_LEN 0xc
5019 #define TG3_FW_BSS_ADDR 0x08000a70
5020 #define TG3_FW_BSS_LEN 0x10
5021
5022 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5023 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5024 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5025 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5026 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5027 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5028 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5029 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5030 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5031 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5032 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5033 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5034 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5035 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5036 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5037 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5038 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5039 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5040 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5041 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5042 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5043 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5044 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5045 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5046 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5047 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5048 0, 0, 0, 0, 0, 0,
5049 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5050 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5051 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5052 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5053 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5054 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5055 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5056 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5057 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5058 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5059 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5060 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5061 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5062 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5063 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5064 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5065 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5066 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5067 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5068 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5069 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5070 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5071 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5072 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5073 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5074 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5075 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5076 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5077 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5078 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5079 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5080 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5081 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5082 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5083 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5084 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5085 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5086 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5087 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5088 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5089 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5090 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5091 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5092 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5093 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5094 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5095 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5096 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5097 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5098 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5099 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5100 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5101 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5102 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5103 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5104 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5105 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5106 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5107 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5108 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5109 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5110 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5111 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5112 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5113 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5114 };
5115
5116 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5117 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5118 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5119 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5120 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5121 0x00000000
5122 };
5123
5124 #if 0 /* All zeros, don't eat up space with it. */
5125 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5126 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5127 0x00000000, 0x00000000, 0x00000000, 0x00000000
5128 };
5129 #endif
5130
5131 #define RX_CPU_SCRATCH_BASE 0x30000
5132 #define RX_CPU_SCRATCH_SIZE 0x04000
5133 #define TX_CPU_SCRATCH_BASE 0x34000
5134 #define TX_CPU_SCRATCH_SIZE 0x04000
5135
5136 /* tp->lock is held. */
5137 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5138 {
5139 int i;
5140
5141 BUG_ON(offset == TX_CPU_BASE &&
5142 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5143
5144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5145 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5146
5147 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5148 return 0;
5149 }
5150 if (offset == RX_CPU_BASE) {
5151 for (i = 0; i < 10000; i++) {
5152 tw32(offset + CPU_STATE, 0xffffffff);
5153 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5154 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5155 break;
5156 }
5157
5158 tw32(offset + CPU_STATE, 0xffffffff);
5159 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5160 udelay(10);
5161 } else {
5162 for (i = 0; i < 10000; i++) {
5163 tw32(offset + CPU_STATE, 0xffffffff);
5164 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5165 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5166 break;
5167 }
5168 }
5169
5170 if (i >= 10000) {
5171 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5172 "and %s CPU\n",
5173 tp->dev->name,
5174 (offset == RX_CPU_BASE ? "RX" : "TX"));
5175 return -ENODEV;
5176 }
5177
5178 /* Clear firmware's nvram arbitration. */
5179 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5180 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5181 return 0;
5182 }
5183
5184 struct fw_info {
5185 unsigned int text_base;
5186 unsigned int text_len;
5187 const u32 *text_data;
5188 unsigned int rodata_base;
5189 unsigned int rodata_len;
5190 const u32 *rodata_data;
5191 unsigned int data_base;
5192 unsigned int data_len;
5193 const u32 *data_data;
5194 };
5195
5196 /* tp->lock is held. */
5197 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5198 int cpu_scratch_size, struct fw_info *info)
5199 {
5200 int err, lock_err, i;
5201 void (*write_op)(struct tg3 *, u32, u32);
5202
5203 if (cpu_base == TX_CPU_BASE &&
5204 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5205 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5206 "TX cpu firmware on %s which is 5705.\n",
5207 tp->dev->name);
5208 return -EINVAL;
5209 }
5210
5211 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5212 write_op = tg3_write_mem;
5213 else
5214 write_op = tg3_write_indirect_reg32;
5215
5216 /* It is possible that bootcode is still loading at this point.
5217 * Get the nvram lock first before halting the cpu.
5218 */
5219 lock_err = tg3_nvram_lock(tp);
5220 err = tg3_halt_cpu(tp, cpu_base);
5221 if (!lock_err)
5222 tg3_nvram_unlock(tp);
5223 if (err)
5224 goto out;
5225
5226 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5227 write_op(tp, cpu_scratch_base + i, 0);
5228 tw32(cpu_base + CPU_STATE, 0xffffffff);
5229 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5230 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5231 write_op(tp, (cpu_scratch_base +
5232 (info->text_base & 0xffff) +
5233 (i * sizeof(u32))),
5234 (info->text_data ?
5235 info->text_data[i] : 0));
5236 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5237 write_op(tp, (cpu_scratch_base +
5238 (info->rodata_base & 0xffff) +
5239 (i * sizeof(u32))),
5240 (info->rodata_data ?
5241 info->rodata_data[i] : 0));
5242 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5243 write_op(tp, (cpu_scratch_base +
5244 (info->data_base & 0xffff) +
5245 (i * sizeof(u32))),
5246 (info->data_data ?
5247 info->data_data[i] : 0));
5248
5249 err = 0;
5250
5251 out:
5252 return err;
5253 }
5254
5255 /* tp->lock is held. */
5256 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5257 {
5258 struct fw_info info;
5259 int err, i;
5260
5261 info.text_base = TG3_FW_TEXT_ADDR;
5262 info.text_len = TG3_FW_TEXT_LEN;
5263 info.text_data = &tg3FwText[0];
5264 info.rodata_base = TG3_FW_RODATA_ADDR;
5265 info.rodata_len = TG3_FW_RODATA_LEN;
5266 info.rodata_data = &tg3FwRodata[0];
5267 info.data_base = TG3_FW_DATA_ADDR;
5268 info.data_len = TG3_FW_DATA_LEN;
5269 info.data_data = NULL;
5270
5271 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5272 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5273 &info);
5274 if (err)
5275 return err;
5276
5277 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5278 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5279 &info);
5280 if (err)
5281 return err;
5282
5283 /* Now startup only the RX cpu. */
5284 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5285 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5286
5287 for (i = 0; i < 5; i++) {
5288 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5289 break;
5290 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5291 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5292 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5293 udelay(1000);
5294 }
5295 if (i >= 5) {
5296 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5297 "to set RX CPU PC, is %08x should be %08x\n",
5298 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5299 TG3_FW_TEXT_ADDR);
5300 return -ENODEV;
5301 }
5302 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5303 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5304
5305 return 0;
5306 }
5307
5308 #if TG3_TSO_SUPPORT != 0
5309
5310 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5311 #define TG3_TSO_FW_RELASE_MINOR 0x6
5312 #define TG3_TSO_FW_RELEASE_FIX 0x0
5313 #define TG3_TSO_FW_START_ADDR 0x08000000
5314 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5315 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5316 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5317 #define TG3_TSO_FW_RODATA_LEN 0x60
5318 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5319 #define TG3_TSO_FW_DATA_LEN 0x30
5320 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5321 #define TG3_TSO_FW_SBSS_LEN 0x2c
5322 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5323 #define TG3_TSO_FW_BSS_LEN 0x894
5324
5325 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5326 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5327 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5328 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5329 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5330 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5331 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5332 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5333 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5334 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5335 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5336 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5337 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5338 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5339 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5340 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5341 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5342 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5343 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5344 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5345 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5346 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5347 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5348 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5349 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5350 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5351 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5352 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5353 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5354 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5355 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5356 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5357 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5358 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5359 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5360 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5361 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5362 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5363 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5364 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5365 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5366 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5367 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5368 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5369 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5370 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5371 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5372 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5373 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5374 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5375 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5376 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5377 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5378 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5379 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5380 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5381 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5382 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5383 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5384 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5385 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5386 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5387 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5388 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5389 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5390 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5391 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5392 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5393 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5394 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5395 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5396 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5397 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5398 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5399 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5400 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5401 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5402 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5403 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5404 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5405 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5406 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5407 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5408 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5409 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5410 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5411 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5412 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5413 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5414 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5415 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5416 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5417 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5418 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5419 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5420 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5421 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5422 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5423 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5424 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5425 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5426 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5427 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5428 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5429 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5430 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5431 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5432 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5433 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5434 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5435 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5436 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5437 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5438 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5439 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5440 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5441 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5442 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5443 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5444 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5445 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5446 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5447 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5448 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5449 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5450 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5451 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5452 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5453 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5454 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5455 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5456 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5457 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5458 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5459 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5460 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5461 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5462 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5463 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5464 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5465 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5466 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5467 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5468 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5469 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5470 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5471 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5472 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5473 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5474 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5475 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5476 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5477 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5478 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5479 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5480 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5481 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5482 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5483 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5484 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5485 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5486 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5487 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5488 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5489 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5490 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5491 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5492 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5493 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5494 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5495 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5496 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5497 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5498 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5499 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5500 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5501 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5502 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5503 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5504 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5505 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5506 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5507 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5508 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5509 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5510 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5511 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5512 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5513 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5514 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5515 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5516 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5517 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5518 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5519 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5520 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5521 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5522 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5523 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5524 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5525 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5526 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5527 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5528 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5529 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5530 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5531 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5532 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5533 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5534 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5535 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5536 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5537 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5538 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5539 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5540 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5541 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5542 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5543 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5544 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5545 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5546 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5547 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5548 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5549 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5550 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5551 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5552 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5553 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5554 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5555 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5556 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5557 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5558 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5559 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5560 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5561 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5562 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5563 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5564 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5565 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5566 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5567 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5568 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5569 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5570 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5571 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5572 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5573 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5574 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5575 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5576 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5577 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5578 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5579 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5580 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5581 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5582 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5583 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5584 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5585 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5586 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5587 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5588 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5589 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5590 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5591 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5592 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5593 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5594 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5595 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5596 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5597 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5598 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5599 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5600 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5601 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5602 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5603 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5604 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5605 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5606 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5607 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5608 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5609 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5610 };
5611
5612 static const u32 tg3TsoFwRodata[] = {
5613 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5614 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5615 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5616 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5617 0x00000000,
5618 };
5619
5620 static const u32 tg3TsoFwData[] = {
5621 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5622 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5623 0x00000000,
5624 };
5625
5626 /* 5705 needs a special version of the TSO firmware. */
5627 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5628 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5629 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5630 #define TG3_TSO5_FW_START_ADDR 0x00010000
5631 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5632 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5633 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5634 #define TG3_TSO5_FW_RODATA_LEN 0x50
5635 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5636 #define TG3_TSO5_FW_DATA_LEN 0x20
5637 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5638 #define TG3_TSO5_FW_SBSS_LEN 0x28
5639 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5640 #define TG3_TSO5_FW_BSS_LEN 0x88
5641
5642 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5643 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5644 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5645 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5646 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5647 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5648 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5649 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5650 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5651 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5652 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5653 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5654 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5655 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5656 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5657 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5658 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5659 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5660 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5661 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5662 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5663 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5664 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5665 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5666 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5667 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5668 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5669 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5670 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5671 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5672 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5673 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5674 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5675 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5676 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5677 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5678 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5679 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5680 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5681 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5682 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5683 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5684 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5685 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5686 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5687 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5688 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5689 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5690 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5691 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5692 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5693 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5694 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5695 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5696 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5697 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5698 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5699 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5700 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5701 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5702 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5703 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5704 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5705 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5706 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5707 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5708 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5709 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5710 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5711 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5712 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5713 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5714 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5715 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5716 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5717 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5718 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5719 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5720 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5721 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5722 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5723 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5724 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5725 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5726 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5727 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5728 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5729 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5730 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5731 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5732 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5733 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5734 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5735 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5736 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5737 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5738 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5739 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5740 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5741 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5742 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5743 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5744 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5745 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5746 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5747 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5748 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5749 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5750 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5751 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5752 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5753 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5754 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5755 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5756 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5757 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5758 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5759 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5760 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5761 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5762 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5763 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5764 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5765 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5766 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5767 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5768 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5769 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5770 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5771 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5772 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5773 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5774 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5775 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5776 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5777 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5778 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5779 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5780 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5781 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5782 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5783 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5784 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5785 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5786 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5787 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5788 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5789 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5790 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5791 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5792 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5793 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5794 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5795 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5796 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5797 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5798 0x00000000, 0x00000000, 0x00000000,
5799 };
5800
5801 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5802 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5803 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5804 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5805 0x00000000, 0x00000000, 0x00000000,
5806 };
5807
5808 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5809 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5810 0x00000000, 0x00000000, 0x00000000,
5811 };
5812
5813 /* tp->lock is held. */
5814 static int tg3_load_tso_firmware(struct tg3 *tp)
5815 {
5816 struct fw_info info;
5817 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5818 int err, i;
5819
5820 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5821 return 0;
5822
5823 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5824 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5825 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5826 info.text_data = &tg3Tso5FwText[0];
5827 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5828 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5829 info.rodata_data = &tg3Tso5FwRodata[0];
5830 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5831 info.data_len = TG3_TSO5_FW_DATA_LEN;
5832 info.data_data = &tg3Tso5FwData[0];
5833 cpu_base = RX_CPU_BASE;
5834 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5835 cpu_scratch_size = (info.text_len +
5836 info.rodata_len +
5837 info.data_len +
5838 TG3_TSO5_FW_SBSS_LEN +
5839 TG3_TSO5_FW_BSS_LEN);
5840 } else {
5841 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5842 info.text_len = TG3_TSO_FW_TEXT_LEN;
5843 info.text_data = &tg3TsoFwText[0];
5844 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5845 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5846 info.rodata_data = &tg3TsoFwRodata[0];
5847 info.data_base = TG3_TSO_FW_DATA_ADDR;
5848 info.data_len = TG3_TSO_FW_DATA_LEN;
5849 info.data_data = &tg3TsoFwData[0];
5850 cpu_base = TX_CPU_BASE;
5851 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5852 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5853 }
5854
5855 err = tg3_load_firmware_cpu(tp, cpu_base,
5856 cpu_scratch_base, cpu_scratch_size,
5857 &info);
5858 if (err)
5859 return err;
5860
5861 /* Now startup the cpu. */
5862 tw32(cpu_base + CPU_STATE, 0xffffffff);
5863 tw32_f(cpu_base + CPU_PC, info.text_base);
5864
5865 for (i = 0; i < 5; i++) {
5866 if (tr32(cpu_base + CPU_PC) == info.text_base)
5867 break;
5868 tw32(cpu_base + CPU_STATE, 0xffffffff);
5869 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5870 tw32_f(cpu_base + CPU_PC, info.text_base);
5871 udelay(1000);
5872 }
5873 if (i >= 5) {
5874 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5875 "to set CPU PC, is %08x should be %08x\n",
5876 tp->dev->name, tr32(cpu_base + CPU_PC),
5877 info.text_base);
5878 return -ENODEV;
5879 }
5880 tw32(cpu_base + CPU_STATE, 0xffffffff);
5881 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5882 return 0;
5883 }
5884
5885 #endif /* TG3_TSO_SUPPORT != 0 */
5886
5887 /* tp->lock is held. */
5888 static void __tg3_set_mac_addr(struct tg3 *tp)
5889 {
5890 u32 addr_high, addr_low;
5891 int i;
5892
5893 addr_high = ((tp->dev->dev_addr[0] << 8) |
5894 tp->dev->dev_addr[1]);
5895 addr_low = ((tp->dev->dev_addr[2] << 24) |
5896 (tp->dev->dev_addr[3] << 16) |
5897 (tp->dev->dev_addr[4] << 8) |
5898 (tp->dev->dev_addr[5] << 0));
5899 for (i = 0; i < 4; i++) {
5900 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5901 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5902 }
5903
5904 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5905 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5906 for (i = 0; i < 12; i++) {
5907 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5908 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5909 }
5910 }
5911
5912 addr_high = (tp->dev->dev_addr[0] +
5913 tp->dev->dev_addr[1] +
5914 tp->dev->dev_addr[2] +
5915 tp->dev->dev_addr[3] +
5916 tp->dev->dev_addr[4] +
5917 tp->dev->dev_addr[5]) &
5918 TX_BACKOFF_SEED_MASK;
5919 tw32(MAC_TX_BACKOFF_SEED, addr_high);
5920 }
5921
5922 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5923 {
5924 struct tg3 *tp = netdev_priv(dev);
5925 struct sockaddr *addr = p;
5926 int err = 0;
5927
5928 if (!is_valid_ether_addr(addr->sa_data))
5929 return -EINVAL;
5930
5931 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5932
5933 if (!netif_running(dev))
5934 return 0;
5935
5936 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5937 /* Reset chip so that ASF can re-init any MAC addresses it
5938 * needs.
5939 */
5940 tg3_netif_stop(tp);
5941 tg3_full_lock(tp, 1);
5942
5943 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5944 err = tg3_restart_hw(tp, 0);
5945 if (!err)
5946 tg3_netif_start(tp);
5947 tg3_full_unlock(tp);
5948 } else {
5949 spin_lock_bh(&tp->lock);
5950 __tg3_set_mac_addr(tp);
5951 spin_unlock_bh(&tp->lock);
5952 }
5953
5954 return err;
5955 }
5956
5957 /* tp->lock is held. */
5958 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5959 dma_addr_t mapping, u32 maxlen_flags,
5960 u32 nic_addr)
5961 {
5962 tg3_write_mem(tp,
5963 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5964 ((u64) mapping >> 32));
5965 tg3_write_mem(tp,
5966 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5967 ((u64) mapping & 0xffffffff));
5968 tg3_write_mem(tp,
5969 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5970 maxlen_flags);
5971
5972 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5973 tg3_write_mem(tp,
5974 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5975 nic_addr);
5976 }
5977
5978 static void __tg3_set_rx_mode(struct net_device *);
5979 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5980 {
5981 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5982 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5983 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5984 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5985 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5986 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5987 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5988 }
5989 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5990 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5991 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5992 u32 val = ec->stats_block_coalesce_usecs;
5993
5994 if (!netif_carrier_ok(tp->dev))
5995 val = 0;
5996
5997 tw32(HOSTCC_STAT_COAL_TICKS, val);
5998 }
5999 }
6000
6001 /* tp->lock is held. */
6002 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6003 {
6004 u32 val, rdmac_mode;
6005 int i, err, limit;
6006
6007 tg3_disable_ints(tp);
6008
6009 tg3_stop_fw(tp);
6010
6011 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6012
6013 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6014 tg3_abort_hw(tp, 1);
6015 }
6016
6017 if (reset_phy)
6018 tg3_phy_reset(tp);
6019
6020 err = tg3_chip_reset(tp);
6021 if (err)
6022 return err;
6023
6024 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6025
6026 /* This works around an issue with Athlon chipsets on
6027 * B3 tigon3 silicon. This bit has no effect on any
6028 * other revision. But do not set this on PCI Express
6029 * chips.
6030 */
6031 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6032 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6033 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6034
6035 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6036 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6037 val = tr32(TG3PCI_PCISTATE);
6038 val |= PCISTATE_RETRY_SAME_DMA;
6039 tw32(TG3PCI_PCISTATE, val);
6040 }
6041
6042 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6043 /* Enable some hw fixes. */
6044 val = tr32(TG3PCI_MSI_DATA);
6045 val |= (1 << 26) | (1 << 28) | (1 << 29);
6046 tw32(TG3PCI_MSI_DATA, val);
6047 }
6048
6049 /* Descriptor ring init may make accesses to the
6050 * NIC SRAM area to setup the TX descriptors, so we
6051 * can only do this after the hardware has been
6052 * successfully reset.
6053 */
6054 err = tg3_init_rings(tp);
6055 if (err)
6056 return err;
6057
6058 /* This value is determined during the probe time DMA
6059 * engine test, tg3_test_dma.
6060 */
6061 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6062
6063 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6064 GRC_MODE_4X_NIC_SEND_RINGS |
6065 GRC_MODE_NO_TX_PHDR_CSUM |
6066 GRC_MODE_NO_RX_PHDR_CSUM);
6067 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6068
6069 /* Pseudo-header checksum is done by hardware logic and not
6070 * the offload processers, so make the chip do the pseudo-
6071 * header checksums on receive. For transmit it is more
6072 * convenient to do the pseudo-header checksum in software
6073 * as Linux does that on transmit for us in all cases.
6074 */
6075 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6076
6077 tw32(GRC_MODE,
6078 tp->grc_mode |
6079 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6080
6081 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6082 val = tr32(GRC_MISC_CFG);
6083 val &= ~0xff;
6084 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6085 tw32(GRC_MISC_CFG, val);
6086
6087 /* Initialize MBUF/DESC pool. */
6088 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6089 /* Do nothing. */
6090 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6091 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6092 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6093 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6094 else
6095 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6096 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6097 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6098 }
6099 #if TG3_TSO_SUPPORT != 0
6100 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6101 int fw_len;
6102
6103 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6104 TG3_TSO5_FW_RODATA_LEN +
6105 TG3_TSO5_FW_DATA_LEN +
6106 TG3_TSO5_FW_SBSS_LEN +
6107 TG3_TSO5_FW_BSS_LEN);
6108 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6109 tw32(BUFMGR_MB_POOL_ADDR,
6110 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6111 tw32(BUFMGR_MB_POOL_SIZE,
6112 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6113 }
6114 #endif
6115
6116 if (tp->dev->mtu <= ETH_DATA_LEN) {
6117 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6118 tp->bufmgr_config.mbuf_read_dma_low_water);
6119 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6120 tp->bufmgr_config.mbuf_mac_rx_low_water);
6121 tw32(BUFMGR_MB_HIGH_WATER,
6122 tp->bufmgr_config.mbuf_high_water);
6123 } else {
6124 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6125 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6126 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6127 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6128 tw32(BUFMGR_MB_HIGH_WATER,
6129 tp->bufmgr_config.mbuf_high_water_jumbo);
6130 }
6131 tw32(BUFMGR_DMA_LOW_WATER,
6132 tp->bufmgr_config.dma_low_water);
6133 tw32(BUFMGR_DMA_HIGH_WATER,
6134 tp->bufmgr_config.dma_high_water);
6135
6136 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6137 for (i = 0; i < 2000; i++) {
6138 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6139 break;
6140 udelay(10);
6141 }
6142 if (i >= 2000) {
6143 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6144 tp->dev->name);
6145 return -ENODEV;
6146 }
6147
6148 /* Setup replenish threshold. */
6149 val = tp->rx_pending / 8;
6150 if (val == 0)
6151 val = 1;
6152 else if (val > tp->rx_std_max_post)
6153 val = tp->rx_std_max_post;
6154 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6155 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6156 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6157
6158 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6159 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6160 }
6161
6162 tw32(RCVBDI_STD_THRESH, val);
6163
6164 /* Initialize TG3_BDINFO's at:
6165 * RCVDBDI_STD_BD: standard eth size rx ring
6166 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6167 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6168 *
6169 * like so:
6170 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6171 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6172 * ring attribute flags
6173 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6174 *
6175 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6176 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6177 *
6178 * The size of each ring is fixed in the firmware, but the location is
6179 * configurable.
6180 */
6181 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6182 ((u64) tp->rx_std_mapping >> 32));
6183 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6184 ((u64) tp->rx_std_mapping & 0xffffffff));
6185 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6186 NIC_SRAM_RX_BUFFER_DESC);
6187
6188 /* Don't even try to program the JUMBO/MINI buffer descriptor
6189 * configs on 5705.
6190 */
6191 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6192 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6193 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6194 } else {
6195 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6196 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6197
6198 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6199 BDINFO_FLAGS_DISABLED);
6200
6201 /* Setup replenish threshold. */
6202 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6203
6204 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6205 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6206 ((u64) tp->rx_jumbo_mapping >> 32));
6207 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6208 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6209 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6210 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6211 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6212 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6213 } else {
6214 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6215 BDINFO_FLAGS_DISABLED);
6216 }
6217
6218 }
6219
6220 /* There is only one send ring on 5705/5750, no need to explicitly
6221 * disable the others.
6222 */
6223 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6224 /* Clear out send RCB ring in SRAM. */
6225 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6226 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6227 BDINFO_FLAGS_DISABLED);
6228 }
6229
6230 tp->tx_prod = 0;
6231 tp->tx_cons = 0;
6232 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6233 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6234
6235 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6236 tp->tx_desc_mapping,
6237 (TG3_TX_RING_SIZE <<
6238 BDINFO_FLAGS_MAXLEN_SHIFT),
6239 NIC_SRAM_TX_BUFFER_DESC);
6240
6241 /* There is only one receive return ring on 5705/5750, no need
6242 * to explicitly disable the others.
6243 */
6244 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6245 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6246 i += TG3_BDINFO_SIZE) {
6247 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6248 BDINFO_FLAGS_DISABLED);
6249 }
6250 }
6251
6252 tp->rx_rcb_ptr = 0;
6253 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6254
6255 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6256 tp->rx_rcb_mapping,
6257 (TG3_RX_RCB_RING_SIZE(tp) <<
6258 BDINFO_FLAGS_MAXLEN_SHIFT),
6259 0);
6260
6261 tp->rx_std_ptr = tp->rx_pending;
6262 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6263 tp->rx_std_ptr);
6264
6265 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6266 tp->rx_jumbo_pending : 0;
6267 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6268 tp->rx_jumbo_ptr);
6269
6270 /* Initialize MAC address and backoff seed. */
6271 __tg3_set_mac_addr(tp);
6272
6273 /* MTU + ethernet header + FCS + optional VLAN tag */
6274 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6275
6276 /* The slot time is changed by tg3_setup_phy if we
6277 * run at gigabit with half duplex.
6278 */
6279 tw32(MAC_TX_LENGTHS,
6280 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6281 (6 << TX_LENGTHS_IPG_SHIFT) |
6282 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6283
6284 /* Receive rules. */
6285 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6286 tw32(RCVLPC_CONFIG, 0x0181);
6287
6288 /* Calculate RDMAC_MODE setting early, we need it to determine
6289 * the RCVLPC_STATE_ENABLE mask.
6290 */
6291 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6292 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6293 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6294 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6295 RDMAC_MODE_LNGREAD_ENAB);
6296 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6297 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6298
6299 /* If statement applies to 5705 and 5750 PCI devices only */
6300 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6301 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6302 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6303 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6304 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6305 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6306 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6307 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6308 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6309 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6310 }
6311 }
6312
6313 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6314 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6315
6316 #if TG3_TSO_SUPPORT != 0
6317 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6318 rdmac_mode |= (1 << 27);
6319 #endif
6320
6321 /* Receive/send statistics. */
6322 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6323 val = tr32(RCVLPC_STATS_ENABLE);
6324 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6325 tw32(RCVLPC_STATS_ENABLE, val);
6326 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6327 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6328 val = tr32(RCVLPC_STATS_ENABLE);
6329 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6330 tw32(RCVLPC_STATS_ENABLE, val);
6331 } else {
6332 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6333 }
6334 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6335 tw32(SNDDATAI_STATSENAB, 0xffffff);
6336 tw32(SNDDATAI_STATSCTRL,
6337 (SNDDATAI_SCTRL_ENABLE |
6338 SNDDATAI_SCTRL_FASTUPD));
6339
6340 /* Setup host coalescing engine. */
6341 tw32(HOSTCC_MODE, 0);
6342 for (i = 0; i < 2000; i++) {
6343 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6344 break;
6345 udelay(10);
6346 }
6347
6348 __tg3_set_coalesce(tp, &tp->coal);
6349
6350 /* set status block DMA address */
6351 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6352 ((u64) tp->status_mapping >> 32));
6353 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6354 ((u64) tp->status_mapping & 0xffffffff));
6355
6356 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6357 /* Status/statistics block address. See tg3_timer,
6358 * the tg3_periodic_fetch_stats call there, and
6359 * tg3_get_stats to see how this works for 5705/5750 chips.
6360 */
6361 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6362 ((u64) tp->stats_mapping >> 32));
6363 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6364 ((u64) tp->stats_mapping & 0xffffffff));
6365 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6366 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6367 }
6368
6369 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6370
6371 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6372 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6374 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6375
6376 /* Clear statistics/status block in chip, and status block in ram. */
6377 for (i = NIC_SRAM_STATS_BLK;
6378 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6379 i += sizeof(u32)) {
6380 tg3_write_mem(tp, i, 0);
6381 udelay(40);
6382 }
6383 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6384
6385 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6386 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6387 /* reset to prevent losing 1st rx packet intermittently */
6388 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6389 udelay(10);
6390 }
6391
6392 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6393 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6394 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6395 udelay(40);
6396
6397 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6398 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
6399 * register to preserve the GPIO settings for LOMs. The GPIOs,
6400 * whether used as inputs or outputs, are set by boot code after
6401 * reset.
6402 */
6403 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
6404 u32 gpio_mask;
6405
6406 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
6407 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
6408
6409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6410 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6411 GRC_LCLCTRL_GPIO_OUTPUT3;
6412
6413 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6414 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6415
6416 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6417
6418 /* GPIO1 must be driven high for eeprom write protect */
6419 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6420 GRC_LCLCTRL_GPIO_OUTPUT1);
6421 }
6422 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6423 udelay(100);
6424
6425 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6426 tp->last_tag = 0;
6427
6428 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6429 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6430 udelay(40);
6431 }
6432
6433 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6434 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6435 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6436 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6437 WDMAC_MODE_LNGREAD_ENAB);
6438
6439 /* If statement applies to 5705 and 5750 PCI devices only */
6440 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6441 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6442 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6443 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6444 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6445 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6446 /* nothing */
6447 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6448 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6449 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6450 val |= WDMAC_MODE_RX_ACCEL;
6451 }
6452 }
6453
6454 /* Enable host coalescing bug fix */
6455 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6456 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6457 val |= (1 << 29);
6458
6459 tw32_f(WDMAC_MODE, val);
6460 udelay(40);
6461
6462 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6463 val = tr32(TG3PCI_X_CAPS);
6464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6465 val &= ~PCIX_CAPS_BURST_MASK;
6466 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6467 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6468 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6469 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6470 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6471 val |= (tp->split_mode_max_reqs <<
6472 PCIX_CAPS_SPLIT_SHIFT);
6473 }
6474 tw32(TG3PCI_X_CAPS, val);
6475 }
6476
6477 tw32_f(RDMAC_MODE, rdmac_mode);
6478 udelay(40);
6479
6480 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6481 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6482 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6483 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6484 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6485 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6486 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6487 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6488 #if TG3_TSO_SUPPORT != 0
6489 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6490 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6491 #endif
6492 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6493 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6494
6495 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6496 err = tg3_load_5701_a0_firmware_fix(tp);
6497 if (err)
6498 return err;
6499 }
6500
6501 #if TG3_TSO_SUPPORT != 0
6502 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6503 err = tg3_load_tso_firmware(tp);
6504 if (err)
6505 return err;
6506 }
6507 #endif
6508
6509 tp->tx_mode = TX_MODE_ENABLE;
6510 tw32_f(MAC_TX_MODE, tp->tx_mode);
6511 udelay(100);
6512
6513 tp->rx_mode = RX_MODE_ENABLE;
6514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6515 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6516
6517 tw32_f(MAC_RX_MODE, tp->rx_mode);
6518 udelay(10);
6519
6520 if (tp->link_config.phy_is_low_power) {
6521 tp->link_config.phy_is_low_power = 0;
6522 tp->link_config.speed = tp->link_config.orig_speed;
6523 tp->link_config.duplex = tp->link_config.orig_duplex;
6524 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6525 }
6526
6527 tp->mi_mode = MAC_MI_MODE_BASE;
6528 tw32_f(MAC_MI_MODE, tp->mi_mode);
6529 udelay(80);
6530
6531 tw32(MAC_LED_CTRL, tp->led_ctrl);
6532
6533 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6534 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6535 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6536 udelay(10);
6537 }
6538 tw32_f(MAC_RX_MODE, tp->rx_mode);
6539 udelay(10);
6540
6541 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6542 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6543 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6544 /* Set drive transmission level to 1.2V */
6545 /* only if the signal pre-emphasis bit is not set */
6546 val = tr32(MAC_SERDES_CFG);
6547 val &= 0xfffff000;
6548 val |= 0x880;
6549 tw32(MAC_SERDES_CFG, val);
6550 }
6551 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6552 tw32(MAC_SERDES_CFG, 0x616000);
6553 }
6554
6555 /* Prevent chip from dropping frames when flow control
6556 * is enabled.
6557 */
6558 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6559
6560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6561 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6562 /* Use hardware link auto-negotiation */
6563 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6564 }
6565
6566 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6567 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6568 u32 tmp;
6569
6570 tmp = tr32(SERDES_RX_CTRL);
6571 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6572 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6573 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6574 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6575 }
6576
6577 err = tg3_setup_phy(tp, 0);
6578 if (err)
6579 return err;
6580
6581 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6582 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6583 u32 tmp;
6584
6585 /* Clear CRC stats. */
6586 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6587 tg3_writephy(tp, 0x1e, tmp | 0x8000);
6588 tg3_readphy(tp, 0x14, &tmp);
6589 }
6590 }
6591
6592 __tg3_set_rx_mode(tp->dev);
6593
6594 /* Initialize receive rules. */
6595 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6596 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6597 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6598 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6599
6600 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6601 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6602 limit = 8;
6603 else
6604 limit = 16;
6605 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6606 limit -= 4;
6607 switch (limit) {
6608 case 16:
6609 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6610 case 15:
6611 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6612 case 14:
6613 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6614 case 13:
6615 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6616 case 12:
6617 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6618 case 11:
6619 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6620 case 10:
6621 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6622 case 9:
6623 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6624 case 8:
6625 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6626 case 7:
6627 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6628 case 6:
6629 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6630 case 5:
6631 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6632 case 4:
6633 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6634 case 3:
6635 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6636 case 2:
6637 case 1:
6638
6639 default:
6640 break;
6641 };
6642
6643 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6644
6645 return 0;
6646 }
6647
6648 /* Called at device open time to get the chip ready for
6649 * packet processing. Invoked with tp->lock held.
6650 */
6651 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6652 {
6653 int err;
6654
6655 /* Force the chip into D0. */
6656 err = tg3_set_power_state(tp, PCI_D0);
6657 if (err)
6658 goto out;
6659
6660 tg3_switch_clocks(tp);
6661
6662 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6663
6664 err = tg3_reset_hw(tp, reset_phy);
6665
6666 out:
6667 return err;
6668 }
6669
6670 #define TG3_STAT_ADD32(PSTAT, REG) \
6671 do { u32 __val = tr32(REG); \
6672 (PSTAT)->low += __val; \
6673 if ((PSTAT)->low < __val) \
6674 (PSTAT)->high += 1; \
6675 } while (0)
6676
6677 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6678 {
6679 struct tg3_hw_stats *sp = tp->hw_stats;
6680
6681 if (!netif_carrier_ok(tp->dev))
6682 return;
6683
6684 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6685 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6686 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6687 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6688 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6689 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6690 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6691 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6692 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6693 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6694 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6695 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6696 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6697
6698 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6699 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6700 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6701 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6702 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6703 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6704 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6705 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6706 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6707 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6708 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6709 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6710 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6711 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6712
6713 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6714 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6715 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6716 }
6717
6718 static void tg3_timer(unsigned long __opaque)
6719 {
6720 struct tg3 *tp = (struct tg3 *) __opaque;
6721
6722 if (tp->irq_sync)
6723 goto restart_timer;
6724
6725 spin_lock(&tp->lock);
6726
6727 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6728 /* All of this garbage is because when using non-tagged
6729 * IRQ status the mailbox/status_block protocol the chip
6730 * uses with the cpu is race prone.
6731 */
6732 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6733 tw32(GRC_LOCAL_CTRL,
6734 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6735 } else {
6736 tw32(HOSTCC_MODE, tp->coalesce_mode |
6737 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6738 }
6739
6740 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6741 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6742 spin_unlock(&tp->lock);
6743 schedule_work(&tp->reset_task);
6744 return;
6745 }
6746 }
6747
6748 /* This part only runs once per second. */
6749 if (!--tp->timer_counter) {
6750 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6751 tg3_periodic_fetch_stats(tp);
6752
6753 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6754 u32 mac_stat;
6755 int phy_event;
6756
6757 mac_stat = tr32(MAC_STATUS);
6758
6759 phy_event = 0;
6760 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6761 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6762 phy_event = 1;
6763 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6764 phy_event = 1;
6765
6766 if (phy_event)
6767 tg3_setup_phy(tp, 0);
6768 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6769 u32 mac_stat = tr32(MAC_STATUS);
6770 int need_setup = 0;
6771
6772 if (netif_carrier_ok(tp->dev) &&
6773 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6774 need_setup = 1;
6775 }
6776 if (! netif_carrier_ok(tp->dev) &&
6777 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6778 MAC_STATUS_SIGNAL_DET))) {
6779 need_setup = 1;
6780 }
6781 if (need_setup) {
6782 if (!tp->serdes_counter) {
6783 tw32_f(MAC_MODE,
6784 (tp->mac_mode &
6785 ~MAC_MODE_PORT_MODE_MASK));
6786 udelay(40);
6787 tw32_f(MAC_MODE, tp->mac_mode);
6788 udelay(40);
6789 }
6790 tg3_setup_phy(tp, 0);
6791 }
6792 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6793 tg3_serdes_parallel_detect(tp);
6794
6795 tp->timer_counter = tp->timer_multiplier;
6796 }
6797
6798 /* Heartbeat is only sent once every 2 seconds.
6799 *
6800 * The heartbeat is to tell the ASF firmware that the host
6801 * driver is still alive. In the event that the OS crashes,
6802 * ASF needs to reset the hardware to free up the FIFO space
6803 * that may be filled with rx packets destined for the host.
6804 * If the FIFO is full, ASF will no longer function properly.
6805 *
6806 * Unintended resets have been reported on real time kernels
6807 * where the timer doesn't run on time. Netpoll will also have
6808 * same problem.
6809 *
6810 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6811 * to check the ring condition when the heartbeat is expiring
6812 * before doing the reset. This will prevent most unintended
6813 * resets.
6814 */
6815 if (!--tp->asf_counter) {
6816 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6817 u32 val;
6818
6819 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6820 FWCMD_NICDRV_ALIVE3);
6821 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6822 /* 5 seconds timeout */
6823 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6824 val = tr32(GRC_RX_CPU_EVENT);
6825 val |= (1 << 14);
6826 tw32(GRC_RX_CPU_EVENT, val);
6827 }
6828 tp->asf_counter = tp->asf_multiplier;
6829 }
6830
6831 spin_unlock(&tp->lock);
6832
6833 restart_timer:
6834 tp->timer.expires = jiffies + tp->timer_offset;
6835 add_timer(&tp->timer);
6836 }
6837
6838 static int tg3_request_irq(struct tg3 *tp)
6839 {
6840 irq_handler_t fn;
6841 unsigned long flags;
6842 struct net_device *dev = tp->dev;
6843
6844 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6845 fn = tg3_msi;
6846 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6847 fn = tg3_msi_1shot;
6848 flags = IRQF_SAMPLE_RANDOM;
6849 } else {
6850 fn = tg3_interrupt;
6851 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6852 fn = tg3_interrupt_tagged;
6853 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6854 }
6855 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6856 }
6857
6858 static int tg3_test_interrupt(struct tg3 *tp)
6859 {
6860 struct net_device *dev = tp->dev;
6861 int err, i, intr_ok = 0;
6862
6863 if (!netif_running(dev))
6864 return -ENODEV;
6865
6866 tg3_disable_ints(tp);
6867
6868 free_irq(tp->pdev->irq, dev);
6869
6870 err = request_irq(tp->pdev->irq, tg3_test_isr,
6871 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6872 if (err)
6873 return err;
6874
6875 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6876 tg3_enable_ints(tp);
6877
6878 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6879 HOSTCC_MODE_NOW);
6880
6881 for (i = 0; i < 5; i++) {
6882 u32 int_mbox, misc_host_ctrl;
6883
6884 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6885 TG3_64BIT_REG_LOW);
6886 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6887
6888 if ((int_mbox != 0) ||
6889 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6890 intr_ok = 1;
6891 break;
6892 }
6893
6894 msleep(10);
6895 }
6896
6897 tg3_disable_ints(tp);
6898
6899 free_irq(tp->pdev->irq, dev);
6900
6901 err = tg3_request_irq(tp);
6902
6903 if (err)
6904 return err;
6905
6906 if (intr_ok)
6907 return 0;
6908
6909 return -EIO;
6910 }
6911
6912 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6913 * successfully restored
6914 */
6915 static int tg3_test_msi(struct tg3 *tp)
6916 {
6917 struct net_device *dev = tp->dev;
6918 int err;
6919 u16 pci_cmd;
6920
6921 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6922 return 0;
6923
6924 /* Turn off SERR reporting in case MSI terminates with Master
6925 * Abort.
6926 */
6927 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6928 pci_write_config_word(tp->pdev, PCI_COMMAND,
6929 pci_cmd & ~PCI_COMMAND_SERR);
6930
6931 err = tg3_test_interrupt(tp);
6932
6933 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6934
6935 if (!err)
6936 return 0;
6937
6938 /* other failures */
6939 if (err != -EIO)
6940 return err;
6941
6942 /* MSI test failed, go back to INTx mode */
6943 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6944 "switching to INTx mode. Please report this failure to "
6945 "the PCI maintainer and include system chipset information.\n",
6946 tp->dev->name);
6947
6948 free_irq(tp->pdev->irq, dev);
6949 pci_disable_msi(tp->pdev);
6950
6951 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6952
6953 err = tg3_request_irq(tp);
6954 if (err)
6955 return err;
6956
6957 /* Need to reset the chip because the MSI cycle may have terminated
6958 * with Master Abort.
6959 */
6960 tg3_full_lock(tp, 1);
6961
6962 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6963 err = tg3_init_hw(tp, 1);
6964
6965 tg3_full_unlock(tp);
6966
6967 if (err)
6968 free_irq(tp->pdev->irq, dev);
6969
6970 return err;
6971 }
6972
6973 static int tg3_open(struct net_device *dev)
6974 {
6975 struct tg3 *tp = netdev_priv(dev);
6976 int err;
6977
6978 tg3_full_lock(tp, 0);
6979
6980 err = tg3_set_power_state(tp, PCI_D0);
6981 if (err)
6982 return err;
6983
6984 tg3_disable_ints(tp);
6985 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6986
6987 tg3_full_unlock(tp);
6988
6989 /* The placement of this call is tied
6990 * to the setup and use of Host TX descriptors.
6991 */
6992 err = tg3_alloc_consistent(tp);
6993 if (err)
6994 return err;
6995
6996 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6997 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6998 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
6999 !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7000 (tp->pdev_peer == tp->pdev))) {
7001 /* All MSI supporting chips should support tagged
7002 * status. Assert that this is the case.
7003 */
7004 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7005 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7006 "Not using MSI.\n", tp->dev->name);
7007 } else if (pci_enable_msi(tp->pdev) == 0) {
7008 u32 msi_mode;
7009
7010 msi_mode = tr32(MSGINT_MODE);
7011 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7012 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7013 }
7014 }
7015 err = tg3_request_irq(tp);
7016
7017 if (err) {
7018 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7019 pci_disable_msi(tp->pdev);
7020 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7021 }
7022 tg3_free_consistent(tp);
7023 return err;
7024 }
7025
7026 tg3_full_lock(tp, 0);
7027
7028 err = tg3_init_hw(tp, 1);
7029 if (err) {
7030 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7031 tg3_free_rings(tp);
7032 } else {
7033 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7034 tp->timer_offset = HZ;
7035 else
7036 tp->timer_offset = HZ / 10;
7037
7038 BUG_ON(tp->timer_offset > HZ);
7039 tp->timer_counter = tp->timer_multiplier =
7040 (HZ / tp->timer_offset);
7041 tp->asf_counter = tp->asf_multiplier =
7042 ((HZ / tp->timer_offset) * 2);
7043
7044 init_timer(&tp->timer);
7045 tp->timer.expires = jiffies + tp->timer_offset;
7046 tp->timer.data = (unsigned long) tp;
7047 tp->timer.function = tg3_timer;
7048 }
7049
7050 tg3_full_unlock(tp);
7051
7052 if (err) {
7053 free_irq(tp->pdev->irq, dev);
7054 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7055 pci_disable_msi(tp->pdev);
7056 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7057 }
7058 tg3_free_consistent(tp);
7059 return err;
7060 }
7061
7062 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7063 err = tg3_test_msi(tp);
7064
7065 if (err) {
7066 tg3_full_lock(tp, 0);
7067
7068 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7069 pci_disable_msi(tp->pdev);
7070 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7071 }
7072 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7073 tg3_free_rings(tp);
7074 tg3_free_consistent(tp);
7075
7076 tg3_full_unlock(tp);
7077
7078 return err;
7079 }
7080
7081 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7082 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7083 u32 val = tr32(PCIE_TRANSACTION_CFG);
7084
7085 tw32(PCIE_TRANSACTION_CFG,
7086 val | PCIE_TRANS_CFG_1SHOT_MSI);
7087 }
7088 }
7089 }
7090
7091 tg3_full_lock(tp, 0);
7092
7093 add_timer(&tp->timer);
7094 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7095 tg3_enable_ints(tp);
7096
7097 tg3_full_unlock(tp);
7098
7099 netif_start_queue(dev);
7100
7101 return 0;
7102 }
7103
7104 #if 0
7105 /*static*/ void tg3_dump_state(struct tg3 *tp)
7106 {
7107 u32 val32, val32_2, val32_3, val32_4, val32_5;
7108 u16 val16;
7109 int i;
7110
7111 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7112 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7113 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7114 val16, val32);
7115
7116 /* MAC block */
7117 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7118 tr32(MAC_MODE), tr32(MAC_STATUS));
7119 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7120 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7121 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7122 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7123 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7124 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7125
7126 /* Send data initiator control block */
7127 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7128 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7129 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7130 tr32(SNDDATAI_STATSCTRL));
7131
7132 /* Send data completion control block */
7133 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7134
7135 /* Send BD ring selector block */
7136 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7137 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7138
7139 /* Send BD initiator control block */
7140 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7141 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7142
7143 /* Send BD completion control block */
7144 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7145
7146 /* Receive list placement control block */
7147 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7148 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7149 printk(" RCVLPC_STATSCTRL[%08x]\n",
7150 tr32(RCVLPC_STATSCTRL));
7151
7152 /* Receive data and receive BD initiator control block */
7153 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7154 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7155
7156 /* Receive data completion control block */
7157 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7158 tr32(RCVDCC_MODE));
7159
7160 /* Receive BD initiator control block */
7161 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7162 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7163
7164 /* Receive BD completion control block */
7165 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7166 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7167
7168 /* Receive list selector control block */
7169 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7170 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7171
7172 /* Mbuf cluster free block */
7173 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7174 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7175
7176 /* Host coalescing control block */
7177 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7178 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7179 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7180 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7181 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7182 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7183 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7184 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7185 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7186 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7187 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7188 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7189
7190 /* Memory arbiter control block */
7191 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7192 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7193
7194 /* Buffer manager control block */
7195 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7196 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7197 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7198 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7199 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7200 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7201 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7202 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7203
7204 /* Read DMA control block */
7205 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7206 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7207
7208 /* Write DMA control block */
7209 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7210 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7211
7212 /* DMA completion block */
7213 printk("DEBUG: DMAC_MODE[%08x]\n",
7214 tr32(DMAC_MODE));
7215
7216 /* GRC block */
7217 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7218 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7219 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7220 tr32(GRC_LOCAL_CTRL));
7221
7222 /* TG3_BDINFOs */
7223 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7224 tr32(RCVDBDI_JUMBO_BD + 0x0),
7225 tr32(RCVDBDI_JUMBO_BD + 0x4),
7226 tr32(RCVDBDI_JUMBO_BD + 0x8),
7227 tr32(RCVDBDI_JUMBO_BD + 0xc));
7228 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7229 tr32(RCVDBDI_STD_BD + 0x0),
7230 tr32(RCVDBDI_STD_BD + 0x4),
7231 tr32(RCVDBDI_STD_BD + 0x8),
7232 tr32(RCVDBDI_STD_BD + 0xc));
7233 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7234 tr32(RCVDBDI_MINI_BD + 0x0),
7235 tr32(RCVDBDI_MINI_BD + 0x4),
7236 tr32(RCVDBDI_MINI_BD + 0x8),
7237 tr32(RCVDBDI_MINI_BD + 0xc));
7238
7239 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7240 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7241 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7242 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7243 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7244 val32, val32_2, val32_3, val32_4);
7245
7246 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7247 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7248 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7249 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7250 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7251 val32, val32_2, val32_3, val32_4);
7252
7253 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7254 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7255 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7256 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7257 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7258 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7259 val32, val32_2, val32_3, val32_4, val32_5);
7260
7261 /* SW status block */
7262 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7263 tp->hw_status->status,
7264 tp->hw_status->status_tag,
7265 tp->hw_status->rx_jumbo_consumer,
7266 tp->hw_status->rx_consumer,
7267 tp->hw_status->rx_mini_consumer,
7268 tp->hw_status->idx[0].rx_producer,
7269 tp->hw_status->idx[0].tx_consumer);
7270
7271 /* SW statistics block */
7272 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7273 ((u32 *)tp->hw_stats)[0],
7274 ((u32 *)tp->hw_stats)[1],
7275 ((u32 *)tp->hw_stats)[2],
7276 ((u32 *)tp->hw_stats)[3]);
7277
7278 /* Mailboxes */
7279 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7280 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7281 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7282 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7283 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7284
7285 /* NIC side send descriptors. */
7286 for (i = 0; i < 6; i++) {
7287 unsigned long txd;
7288
7289 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7290 + (i * sizeof(struct tg3_tx_buffer_desc));
7291 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7292 i,
7293 readl(txd + 0x0), readl(txd + 0x4),
7294 readl(txd + 0x8), readl(txd + 0xc));
7295 }
7296
7297 /* NIC side RX descriptors. */
7298 for (i = 0; i < 6; i++) {
7299 unsigned long rxd;
7300
7301 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7302 + (i * sizeof(struct tg3_rx_buffer_desc));
7303 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7304 i,
7305 readl(rxd + 0x0), readl(rxd + 0x4),
7306 readl(rxd + 0x8), readl(rxd + 0xc));
7307 rxd += (4 * sizeof(u32));
7308 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7309 i,
7310 readl(rxd + 0x0), readl(rxd + 0x4),
7311 readl(rxd + 0x8), readl(rxd + 0xc));
7312 }
7313
7314 for (i = 0; i < 6; i++) {
7315 unsigned long rxd;
7316
7317 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7318 + (i * sizeof(struct tg3_rx_buffer_desc));
7319 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7320 i,
7321 readl(rxd + 0x0), readl(rxd + 0x4),
7322 readl(rxd + 0x8), readl(rxd + 0xc));
7323 rxd += (4 * sizeof(u32));
7324 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7325 i,
7326 readl(rxd + 0x0), readl(rxd + 0x4),
7327 readl(rxd + 0x8), readl(rxd + 0xc));
7328 }
7329 }
7330 #endif
7331
7332 static struct net_device_stats *tg3_get_stats(struct net_device *);
7333 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7334
7335 static int tg3_close(struct net_device *dev)
7336 {
7337 struct tg3 *tp = netdev_priv(dev);
7338
7339 /* Calling flush_scheduled_work() may deadlock because
7340 * linkwatch_event() may be on the workqueue and it will try to get
7341 * the rtnl_lock which we are holding.
7342 */
7343 while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7344 msleep(1);
7345
7346 netif_stop_queue(dev);
7347
7348 del_timer_sync(&tp->timer);
7349
7350 tg3_full_lock(tp, 1);
7351 #if 0
7352 tg3_dump_state(tp);
7353 #endif
7354
7355 tg3_disable_ints(tp);
7356
7357 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7358 tg3_free_rings(tp);
7359 tp->tg3_flags &=
7360 ~(TG3_FLAG_INIT_COMPLETE |
7361 TG3_FLAG_GOT_SERDES_FLOWCTL);
7362
7363 tg3_full_unlock(tp);
7364
7365 free_irq(tp->pdev->irq, dev);
7366 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7367 pci_disable_msi(tp->pdev);
7368 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7369 }
7370
7371 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7372 sizeof(tp->net_stats_prev));
7373 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7374 sizeof(tp->estats_prev));
7375
7376 tg3_free_consistent(tp);
7377
7378 tg3_set_power_state(tp, PCI_D3hot);
7379
7380 netif_carrier_off(tp->dev);
7381
7382 return 0;
7383 }
7384
7385 static inline unsigned long get_stat64(tg3_stat64_t *val)
7386 {
7387 unsigned long ret;
7388
7389 #if (BITS_PER_LONG == 32)
7390 ret = val->low;
7391 #else
7392 ret = ((u64)val->high << 32) | ((u64)val->low);
7393 #endif
7394 return ret;
7395 }
7396
7397 static unsigned long calc_crc_errors(struct tg3 *tp)
7398 {
7399 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7400
7401 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7402 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7403 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7404 u32 val;
7405
7406 spin_lock_bh(&tp->lock);
7407 if (!tg3_readphy(tp, 0x1e, &val)) {
7408 tg3_writephy(tp, 0x1e, val | 0x8000);
7409 tg3_readphy(tp, 0x14, &val);
7410 } else
7411 val = 0;
7412 spin_unlock_bh(&tp->lock);
7413
7414 tp->phy_crc_errors += val;
7415
7416 return tp->phy_crc_errors;
7417 }
7418
7419 return get_stat64(&hw_stats->rx_fcs_errors);
7420 }
7421
7422 #define ESTAT_ADD(member) \
7423 estats->member = old_estats->member + \
7424 get_stat64(&hw_stats->member)
7425
7426 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7427 {
7428 struct tg3_ethtool_stats *estats = &tp->estats;
7429 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7430 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7431
7432 if (!hw_stats)
7433 return old_estats;
7434
7435 ESTAT_ADD(rx_octets);
7436 ESTAT_ADD(rx_fragments);
7437 ESTAT_ADD(rx_ucast_packets);
7438 ESTAT_ADD(rx_mcast_packets);
7439 ESTAT_ADD(rx_bcast_packets);
7440 ESTAT_ADD(rx_fcs_errors);
7441 ESTAT_ADD(rx_align_errors);
7442 ESTAT_ADD(rx_xon_pause_rcvd);
7443 ESTAT_ADD(rx_xoff_pause_rcvd);
7444 ESTAT_ADD(rx_mac_ctrl_rcvd);
7445 ESTAT_ADD(rx_xoff_entered);
7446 ESTAT_ADD(rx_frame_too_long_errors);
7447 ESTAT_ADD(rx_jabbers);
7448 ESTAT_ADD(rx_undersize_packets);
7449 ESTAT_ADD(rx_in_length_errors);
7450 ESTAT_ADD(rx_out_length_errors);
7451 ESTAT_ADD(rx_64_or_less_octet_packets);
7452 ESTAT_ADD(rx_65_to_127_octet_packets);
7453 ESTAT_ADD(rx_128_to_255_octet_packets);
7454 ESTAT_ADD(rx_256_to_511_octet_packets);
7455 ESTAT_ADD(rx_512_to_1023_octet_packets);
7456 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7457 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7458 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7459 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7460 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7461
7462 ESTAT_ADD(tx_octets);
7463 ESTAT_ADD(tx_collisions);
7464 ESTAT_ADD(tx_xon_sent);
7465 ESTAT_ADD(tx_xoff_sent);
7466 ESTAT_ADD(tx_flow_control);
7467 ESTAT_ADD(tx_mac_errors);
7468 ESTAT_ADD(tx_single_collisions);
7469 ESTAT_ADD(tx_mult_collisions);
7470 ESTAT_ADD(tx_deferred);
7471 ESTAT_ADD(tx_excessive_collisions);
7472 ESTAT_ADD(tx_late_collisions);
7473 ESTAT_ADD(tx_collide_2times);
7474 ESTAT_ADD(tx_collide_3times);
7475 ESTAT_ADD(tx_collide_4times);
7476 ESTAT_ADD(tx_collide_5times);
7477 ESTAT_ADD(tx_collide_6times);
7478 ESTAT_ADD(tx_collide_7times);
7479 ESTAT_ADD(tx_collide_8times);
7480 ESTAT_ADD(tx_collide_9times);
7481 ESTAT_ADD(tx_collide_10times);
7482 ESTAT_ADD(tx_collide_11times);
7483 ESTAT_ADD(tx_collide_12times);
7484 ESTAT_ADD(tx_collide_13times);
7485 ESTAT_ADD(tx_collide_14times);
7486 ESTAT_ADD(tx_collide_15times);
7487 ESTAT_ADD(tx_ucast_packets);
7488 ESTAT_ADD(tx_mcast_packets);
7489 ESTAT_ADD(tx_bcast_packets);
7490 ESTAT_ADD(tx_carrier_sense_errors);
7491 ESTAT_ADD(tx_discards);
7492 ESTAT_ADD(tx_errors);
7493
7494 ESTAT_ADD(dma_writeq_full);
7495 ESTAT_ADD(dma_write_prioq_full);
7496 ESTAT_ADD(rxbds_empty);
7497 ESTAT_ADD(rx_discards);
7498 ESTAT_ADD(rx_errors);
7499 ESTAT_ADD(rx_threshold_hit);
7500
7501 ESTAT_ADD(dma_readq_full);
7502 ESTAT_ADD(dma_read_prioq_full);
7503 ESTAT_ADD(tx_comp_queue_full);
7504
7505 ESTAT_ADD(ring_set_send_prod_index);
7506 ESTAT_ADD(ring_status_update);
7507 ESTAT_ADD(nic_irqs);
7508 ESTAT_ADD(nic_avoided_irqs);
7509 ESTAT_ADD(nic_tx_threshold_hit);
7510
7511 return estats;
7512 }
7513
7514 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7515 {
7516 struct tg3 *tp = netdev_priv(dev);
7517 struct net_device_stats *stats = &tp->net_stats;
7518 struct net_device_stats *old_stats = &tp->net_stats_prev;
7519 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7520
7521 if (!hw_stats)
7522 return old_stats;
7523
7524 stats->rx_packets = old_stats->rx_packets +
7525 get_stat64(&hw_stats->rx_ucast_packets) +
7526 get_stat64(&hw_stats->rx_mcast_packets) +
7527 get_stat64(&hw_stats->rx_bcast_packets);
7528
7529 stats->tx_packets = old_stats->tx_packets +
7530 get_stat64(&hw_stats->tx_ucast_packets) +
7531 get_stat64(&hw_stats->tx_mcast_packets) +
7532 get_stat64(&hw_stats->tx_bcast_packets);
7533
7534 stats->rx_bytes = old_stats->rx_bytes +
7535 get_stat64(&hw_stats->rx_octets);
7536 stats->tx_bytes = old_stats->tx_bytes +
7537 get_stat64(&hw_stats->tx_octets);
7538
7539 stats->rx_errors = old_stats->rx_errors +
7540 get_stat64(&hw_stats->rx_errors);
7541 stats->tx_errors = old_stats->tx_errors +
7542 get_stat64(&hw_stats->tx_errors) +
7543 get_stat64(&hw_stats->tx_mac_errors) +
7544 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7545 get_stat64(&hw_stats->tx_discards);
7546
7547 stats->multicast = old_stats->multicast +
7548 get_stat64(&hw_stats->rx_mcast_packets);
7549 stats->collisions = old_stats->collisions +
7550 get_stat64(&hw_stats->tx_collisions);
7551
7552 stats->rx_length_errors = old_stats->rx_length_errors +
7553 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7554 get_stat64(&hw_stats->rx_undersize_packets);
7555
7556 stats->rx_over_errors = old_stats->rx_over_errors +
7557 get_stat64(&hw_stats->rxbds_empty);
7558 stats->rx_frame_errors = old_stats->rx_frame_errors +
7559 get_stat64(&hw_stats->rx_align_errors);
7560 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7561 get_stat64(&hw_stats->tx_discards);
7562 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7563 get_stat64(&hw_stats->tx_carrier_sense_errors);
7564
7565 stats->rx_crc_errors = old_stats->rx_crc_errors +
7566 calc_crc_errors(tp);
7567
7568 stats->rx_missed_errors = old_stats->rx_missed_errors +
7569 get_stat64(&hw_stats->rx_discards);
7570
7571 return stats;
7572 }
7573
7574 static inline u32 calc_crc(unsigned char *buf, int len)
7575 {
7576 u32 reg;
7577 u32 tmp;
7578 int j, k;
7579
7580 reg = 0xffffffff;
7581
7582 for (j = 0; j < len; j++) {
7583 reg ^= buf[j];
7584
7585 for (k = 0; k < 8; k++) {
7586 tmp = reg & 0x01;
7587
7588 reg >>= 1;
7589
7590 if (tmp) {
7591 reg ^= 0xedb88320;
7592 }
7593 }
7594 }
7595
7596 return ~reg;
7597 }
7598
7599 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7600 {
7601 /* accept or reject all multicast frames */
7602 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7603 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7604 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7605 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7606 }
7607
7608 static void __tg3_set_rx_mode(struct net_device *dev)
7609 {
7610 struct tg3 *tp = netdev_priv(dev);
7611 u32 rx_mode;
7612
7613 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7614 RX_MODE_KEEP_VLAN_TAG);
7615
7616 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7617 * flag clear.
7618 */
7619 #if TG3_VLAN_TAG_USED
7620 if (!tp->vlgrp &&
7621 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7622 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7623 #else
7624 /* By definition, VLAN is disabled always in this
7625 * case.
7626 */
7627 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7628 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7629 #endif
7630
7631 if (dev->flags & IFF_PROMISC) {
7632 /* Promiscuous mode. */
7633 rx_mode |= RX_MODE_PROMISC;
7634 } else if (dev->flags & IFF_ALLMULTI) {
7635 /* Accept all multicast. */
7636 tg3_set_multi (tp, 1);
7637 } else if (dev->mc_count < 1) {
7638 /* Reject all multicast. */
7639 tg3_set_multi (tp, 0);
7640 } else {
7641 /* Accept one or more multicast(s). */
7642 struct dev_mc_list *mclist;
7643 unsigned int i;
7644 u32 mc_filter[4] = { 0, };
7645 u32 regidx;
7646 u32 bit;
7647 u32 crc;
7648
7649 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7650 i++, mclist = mclist->next) {
7651
7652 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7653 bit = ~crc & 0x7f;
7654 regidx = (bit & 0x60) >> 5;
7655 bit &= 0x1f;
7656 mc_filter[regidx] |= (1 << bit);
7657 }
7658
7659 tw32(MAC_HASH_REG_0, mc_filter[0]);
7660 tw32(MAC_HASH_REG_1, mc_filter[1]);
7661 tw32(MAC_HASH_REG_2, mc_filter[2]);
7662 tw32(MAC_HASH_REG_3, mc_filter[3]);
7663 }
7664
7665 if (rx_mode != tp->rx_mode) {
7666 tp->rx_mode = rx_mode;
7667 tw32_f(MAC_RX_MODE, rx_mode);
7668 udelay(10);
7669 }
7670 }
7671
7672 static void tg3_set_rx_mode(struct net_device *dev)
7673 {
7674 struct tg3 *tp = netdev_priv(dev);
7675
7676 if (!netif_running(dev))
7677 return;
7678
7679 tg3_full_lock(tp, 0);
7680 __tg3_set_rx_mode(dev);
7681 tg3_full_unlock(tp);
7682 }
7683
7684 #define TG3_REGDUMP_LEN (32 * 1024)
7685
7686 static int tg3_get_regs_len(struct net_device *dev)
7687 {
7688 return TG3_REGDUMP_LEN;
7689 }
7690
7691 static void tg3_get_regs(struct net_device *dev,
7692 struct ethtool_regs *regs, void *_p)
7693 {
7694 u32 *p = _p;
7695 struct tg3 *tp = netdev_priv(dev);
7696 u8 *orig_p = _p;
7697 int i;
7698
7699 regs->version = 0;
7700
7701 memset(p, 0, TG3_REGDUMP_LEN);
7702
7703 if (tp->link_config.phy_is_low_power)
7704 return;
7705
7706 tg3_full_lock(tp, 0);
7707
7708 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7709 #define GET_REG32_LOOP(base,len) \
7710 do { p = (u32 *)(orig_p + (base)); \
7711 for (i = 0; i < len; i += 4) \
7712 __GET_REG32((base) + i); \
7713 } while (0)
7714 #define GET_REG32_1(reg) \
7715 do { p = (u32 *)(orig_p + (reg)); \
7716 __GET_REG32((reg)); \
7717 } while (0)
7718
7719 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7720 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7721 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7722 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7723 GET_REG32_1(SNDDATAC_MODE);
7724 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7725 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7726 GET_REG32_1(SNDBDC_MODE);
7727 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7728 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7729 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7730 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7731 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7732 GET_REG32_1(RCVDCC_MODE);
7733 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7734 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7735 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7736 GET_REG32_1(MBFREE_MODE);
7737 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7738 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7739 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7740 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7741 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7742 GET_REG32_1(RX_CPU_MODE);
7743 GET_REG32_1(RX_CPU_STATE);
7744 GET_REG32_1(RX_CPU_PGMCTR);
7745 GET_REG32_1(RX_CPU_HWBKPT);
7746 GET_REG32_1(TX_CPU_MODE);
7747 GET_REG32_1(TX_CPU_STATE);
7748 GET_REG32_1(TX_CPU_PGMCTR);
7749 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7750 GET_REG32_LOOP(FTQ_RESET, 0x120);
7751 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7752 GET_REG32_1(DMAC_MODE);
7753 GET_REG32_LOOP(GRC_MODE, 0x4c);
7754 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7755 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7756
7757 #undef __GET_REG32
7758 #undef GET_REG32_LOOP
7759 #undef GET_REG32_1
7760
7761 tg3_full_unlock(tp);
7762 }
7763
7764 static int tg3_get_eeprom_len(struct net_device *dev)
7765 {
7766 struct tg3 *tp = netdev_priv(dev);
7767
7768 return tp->nvram_size;
7769 }
7770
7771 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7772 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7773
7774 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7775 {
7776 struct tg3 *tp = netdev_priv(dev);
7777 int ret;
7778 u8 *pd;
7779 u32 i, offset, len, val, b_offset, b_count;
7780
7781 if (tp->link_config.phy_is_low_power)
7782 return -EAGAIN;
7783
7784 offset = eeprom->offset;
7785 len = eeprom->len;
7786 eeprom->len = 0;
7787
7788 eeprom->magic = TG3_EEPROM_MAGIC;
7789
7790 if (offset & 3) {
7791 /* adjustments to start on required 4 byte boundary */
7792 b_offset = offset & 3;
7793 b_count = 4 - b_offset;
7794 if (b_count > len) {
7795 /* i.e. offset=1 len=2 */
7796 b_count = len;
7797 }
7798 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7799 if (ret)
7800 return ret;
7801 val = cpu_to_le32(val);
7802 memcpy(data, ((char*)&val) + b_offset, b_count);
7803 len -= b_count;
7804 offset += b_count;
7805 eeprom->len += b_count;
7806 }
7807
7808 /* read bytes upto the last 4 byte boundary */
7809 pd = &data[eeprom->len];
7810 for (i = 0; i < (len - (len & 3)); i += 4) {
7811 ret = tg3_nvram_read(tp, offset + i, &val);
7812 if (ret) {
7813 eeprom->len += i;
7814 return ret;
7815 }
7816 val = cpu_to_le32(val);
7817 memcpy(pd + i, &val, 4);
7818 }
7819 eeprom->len += i;
7820
7821 if (len & 3) {
7822 /* read last bytes not ending on 4 byte boundary */
7823 pd = &data[eeprom->len];
7824 b_count = len & 3;
7825 b_offset = offset + len - b_count;
7826 ret = tg3_nvram_read(tp, b_offset, &val);
7827 if (ret)
7828 return ret;
7829 val = cpu_to_le32(val);
7830 memcpy(pd, ((char*)&val), b_count);
7831 eeprom->len += b_count;
7832 }
7833 return 0;
7834 }
7835
7836 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7837
7838 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7839 {
7840 struct tg3 *tp = netdev_priv(dev);
7841 int ret;
7842 u32 offset, len, b_offset, odd_len, start, end;
7843 u8 *buf;
7844
7845 if (tp->link_config.phy_is_low_power)
7846 return -EAGAIN;
7847
7848 if (eeprom->magic != TG3_EEPROM_MAGIC)
7849 return -EINVAL;
7850
7851 offset = eeprom->offset;
7852 len = eeprom->len;
7853
7854 if ((b_offset = (offset & 3))) {
7855 /* adjustments to start on required 4 byte boundary */
7856 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7857 if (ret)
7858 return ret;
7859 start = cpu_to_le32(start);
7860 len += b_offset;
7861 offset &= ~3;
7862 if (len < 4)
7863 len = 4;
7864 }
7865
7866 odd_len = 0;
7867 if (len & 3) {
7868 /* adjustments to end on required 4 byte boundary */
7869 odd_len = 1;
7870 len = (len + 3) & ~3;
7871 ret = tg3_nvram_read(tp, offset+len-4, &end);
7872 if (ret)
7873 return ret;
7874 end = cpu_to_le32(end);
7875 }
7876
7877 buf = data;
7878 if (b_offset || odd_len) {
7879 buf = kmalloc(len, GFP_KERNEL);
7880 if (buf == 0)
7881 return -ENOMEM;
7882 if (b_offset)
7883 memcpy(buf, &start, 4);
7884 if (odd_len)
7885 memcpy(buf+len-4, &end, 4);
7886 memcpy(buf + b_offset, data, eeprom->len);
7887 }
7888
7889 ret = tg3_nvram_write_block(tp, offset, len, buf);
7890
7891 if (buf != data)
7892 kfree(buf);
7893
7894 return ret;
7895 }
7896
7897 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7898 {
7899 struct tg3 *tp = netdev_priv(dev);
7900
7901 cmd->supported = (SUPPORTED_Autoneg);
7902
7903 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7904 cmd->supported |= (SUPPORTED_1000baseT_Half |
7905 SUPPORTED_1000baseT_Full);
7906
7907 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7908 cmd->supported |= (SUPPORTED_100baseT_Half |
7909 SUPPORTED_100baseT_Full |
7910 SUPPORTED_10baseT_Half |
7911 SUPPORTED_10baseT_Full |
7912 SUPPORTED_MII);
7913 cmd->port = PORT_TP;
7914 } else {
7915 cmd->supported |= SUPPORTED_FIBRE;
7916 cmd->port = PORT_FIBRE;
7917 }
7918
7919 cmd->advertising = tp->link_config.advertising;
7920 if (netif_running(dev)) {
7921 cmd->speed = tp->link_config.active_speed;
7922 cmd->duplex = tp->link_config.active_duplex;
7923 }
7924 cmd->phy_address = PHY_ADDR;
7925 cmd->transceiver = 0;
7926 cmd->autoneg = tp->link_config.autoneg;
7927 cmd->maxtxpkt = 0;
7928 cmd->maxrxpkt = 0;
7929 return 0;
7930 }
7931
7932 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7933 {
7934 struct tg3 *tp = netdev_priv(dev);
7935
7936 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7937 /* These are the only valid advertisement bits allowed. */
7938 if (cmd->autoneg == AUTONEG_ENABLE &&
7939 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7940 ADVERTISED_1000baseT_Full |
7941 ADVERTISED_Autoneg |
7942 ADVERTISED_FIBRE)))
7943 return -EINVAL;
7944 /* Fiber can only do SPEED_1000. */
7945 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7946 (cmd->speed != SPEED_1000))
7947 return -EINVAL;
7948 /* Copper cannot force SPEED_1000. */
7949 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7950 (cmd->speed == SPEED_1000))
7951 return -EINVAL;
7952 else if ((cmd->speed == SPEED_1000) &&
7953 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7954 return -EINVAL;
7955
7956 tg3_full_lock(tp, 0);
7957
7958 tp->link_config.autoneg = cmd->autoneg;
7959 if (cmd->autoneg == AUTONEG_ENABLE) {
7960 tp->link_config.advertising = cmd->advertising;
7961 tp->link_config.speed = SPEED_INVALID;
7962 tp->link_config.duplex = DUPLEX_INVALID;
7963 } else {
7964 tp->link_config.advertising = 0;
7965 tp->link_config.speed = cmd->speed;
7966 tp->link_config.duplex = cmd->duplex;
7967 }
7968
7969 if (netif_running(dev))
7970 tg3_setup_phy(tp, 1);
7971
7972 tg3_full_unlock(tp);
7973
7974 return 0;
7975 }
7976
7977 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7978 {
7979 struct tg3 *tp = netdev_priv(dev);
7980
7981 strcpy(info->driver, DRV_MODULE_NAME);
7982 strcpy(info->version, DRV_MODULE_VERSION);
7983 strcpy(info->fw_version, tp->fw_ver);
7984 strcpy(info->bus_info, pci_name(tp->pdev));
7985 }
7986
7987 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7988 {
7989 struct tg3 *tp = netdev_priv(dev);
7990
7991 wol->supported = WAKE_MAGIC;
7992 wol->wolopts = 0;
7993 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7994 wol->wolopts = WAKE_MAGIC;
7995 memset(&wol->sopass, 0, sizeof(wol->sopass));
7996 }
7997
7998 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7999 {
8000 struct tg3 *tp = netdev_priv(dev);
8001
8002 if (wol->wolopts & ~WAKE_MAGIC)
8003 return -EINVAL;
8004 if ((wol->wolopts & WAKE_MAGIC) &&
8005 tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8006 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8007 return -EINVAL;
8008
8009 spin_lock_bh(&tp->lock);
8010 if (wol->wolopts & WAKE_MAGIC)
8011 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8012 else
8013 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8014 spin_unlock_bh(&tp->lock);
8015
8016 return 0;
8017 }
8018
8019 static u32 tg3_get_msglevel(struct net_device *dev)
8020 {
8021 struct tg3 *tp = netdev_priv(dev);
8022 return tp->msg_enable;
8023 }
8024
8025 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8026 {
8027 struct tg3 *tp = netdev_priv(dev);
8028 tp->msg_enable = value;
8029 }
8030
8031 #if TG3_TSO_SUPPORT != 0
8032 static int tg3_set_tso(struct net_device *dev, u32 value)
8033 {
8034 struct tg3 *tp = netdev_priv(dev);
8035
8036 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8037 if (value)
8038 return -EINVAL;
8039 return 0;
8040 }
8041 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8042 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8043 if (value)
8044 dev->features |= NETIF_F_TSO6;
8045 else
8046 dev->features &= ~NETIF_F_TSO6;
8047 }
8048 return ethtool_op_set_tso(dev, value);
8049 }
8050 #endif
8051
8052 static int tg3_nway_reset(struct net_device *dev)
8053 {
8054 struct tg3 *tp = netdev_priv(dev);
8055 u32 bmcr;
8056 int r;
8057
8058 if (!netif_running(dev))
8059 return -EAGAIN;
8060
8061 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8062 return -EINVAL;
8063
8064 spin_lock_bh(&tp->lock);
8065 r = -EINVAL;
8066 tg3_readphy(tp, MII_BMCR, &bmcr);
8067 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8068 ((bmcr & BMCR_ANENABLE) ||
8069 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8070 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8071 BMCR_ANENABLE);
8072 r = 0;
8073 }
8074 spin_unlock_bh(&tp->lock);
8075
8076 return r;
8077 }
8078
8079 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8080 {
8081 struct tg3 *tp = netdev_priv(dev);
8082
8083 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8084 ering->rx_mini_max_pending = 0;
8085 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8086 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8087 else
8088 ering->rx_jumbo_max_pending = 0;
8089
8090 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8091
8092 ering->rx_pending = tp->rx_pending;
8093 ering->rx_mini_pending = 0;
8094 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8095 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8096 else
8097 ering->rx_jumbo_pending = 0;
8098
8099 ering->tx_pending = tp->tx_pending;
8100 }
8101
8102 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8103 {
8104 struct tg3 *tp = netdev_priv(dev);
8105 int irq_sync = 0, err = 0;
8106
8107 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8108 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8109 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8110 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8111 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8112 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8113 return -EINVAL;
8114
8115 if (netif_running(dev)) {
8116 tg3_netif_stop(tp);
8117 irq_sync = 1;
8118 }
8119
8120 tg3_full_lock(tp, irq_sync);
8121
8122 tp->rx_pending = ering->rx_pending;
8123
8124 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8125 tp->rx_pending > 63)
8126 tp->rx_pending = 63;
8127 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8128 tp->tx_pending = ering->tx_pending;
8129
8130 if (netif_running(dev)) {
8131 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8132 err = tg3_restart_hw(tp, 1);
8133 if (!err)
8134 tg3_netif_start(tp);
8135 }
8136
8137 tg3_full_unlock(tp);
8138
8139 return err;
8140 }
8141
8142 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8143 {
8144 struct tg3 *tp = netdev_priv(dev);
8145
8146 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8147 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8148 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8149 }
8150
8151 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8152 {
8153 struct tg3 *tp = netdev_priv(dev);
8154 int irq_sync = 0, err = 0;
8155
8156 if (netif_running(dev)) {
8157 tg3_netif_stop(tp);
8158 irq_sync = 1;
8159 }
8160
8161 tg3_full_lock(tp, irq_sync);
8162
8163 if (epause->autoneg)
8164 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8165 else
8166 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8167 if (epause->rx_pause)
8168 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8169 else
8170 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8171 if (epause->tx_pause)
8172 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8173 else
8174 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8175
8176 if (netif_running(dev)) {
8177 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8178 err = tg3_restart_hw(tp, 1);
8179 if (!err)
8180 tg3_netif_start(tp);
8181 }
8182
8183 tg3_full_unlock(tp);
8184
8185 return err;
8186 }
8187
8188 static u32 tg3_get_rx_csum(struct net_device *dev)
8189 {
8190 struct tg3 *tp = netdev_priv(dev);
8191 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8192 }
8193
8194 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8195 {
8196 struct tg3 *tp = netdev_priv(dev);
8197
8198 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8199 if (data != 0)
8200 return -EINVAL;
8201 return 0;
8202 }
8203
8204 spin_lock_bh(&tp->lock);
8205 if (data)
8206 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8207 else
8208 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8209 spin_unlock_bh(&tp->lock);
8210
8211 return 0;
8212 }
8213
8214 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8215 {
8216 struct tg3 *tp = netdev_priv(dev);
8217
8218 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8219 if (data != 0)
8220 return -EINVAL;
8221 return 0;
8222 }
8223
8224 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8226 ethtool_op_set_tx_hw_csum(dev, data);
8227 else
8228 ethtool_op_set_tx_csum(dev, data);
8229
8230 return 0;
8231 }
8232
8233 static int tg3_get_stats_count (struct net_device *dev)
8234 {
8235 return TG3_NUM_STATS;
8236 }
8237
8238 static int tg3_get_test_count (struct net_device *dev)
8239 {
8240 return TG3_NUM_TEST;
8241 }
8242
8243 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8244 {
8245 switch (stringset) {
8246 case ETH_SS_STATS:
8247 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8248 break;
8249 case ETH_SS_TEST:
8250 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8251 break;
8252 default:
8253 WARN_ON(1); /* we need a WARN() */
8254 break;
8255 }
8256 }
8257
8258 static int tg3_phys_id(struct net_device *dev, u32 data)
8259 {
8260 struct tg3 *tp = netdev_priv(dev);
8261 int i;
8262
8263 if (!netif_running(tp->dev))
8264 return -EAGAIN;
8265
8266 if (data == 0)
8267 data = 2;
8268
8269 for (i = 0; i < (data * 2); i++) {
8270 if ((i % 2) == 0)
8271 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8272 LED_CTRL_1000MBPS_ON |
8273 LED_CTRL_100MBPS_ON |
8274 LED_CTRL_10MBPS_ON |
8275 LED_CTRL_TRAFFIC_OVERRIDE |
8276 LED_CTRL_TRAFFIC_BLINK |
8277 LED_CTRL_TRAFFIC_LED);
8278
8279 else
8280 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8281 LED_CTRL_TRAFFIC_OVERRIDE);
8282
8283 if (msleep_interruptible(500))
8284 break;
8285 }
8286 tw32(MAC_LED_CTRL, tp->led_ctrl);
8287 return 0;
8288 }
8289
8290 static void tg3_get_ethtool_stats (struct net_device *dev,
8291 struct ethtool_stats *estats, u64 *tmp_stats)
8292 {
8293 struct tg3 *tp = netdev_priv(dev);
8294 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8295 }
8296
8297 #define NVRAM_TEST_SIZE 0x100
8298 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8299 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8300 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8301
8302 static int tg3_test_nvram(struct tg3 *tp)
8303 {
8304 u32 *buf, csum, magic;
8305 int i, j, err = 0, size;
8306
8307 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8308 return -EIO;
8309
8310 if (magic == TG3_EEPROM_MAGIC)
8311 size = NVRAM_TEST_SIZE;
8312 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8313 if ((magic & 0xe00000) == 0x200000)
8314 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8315 else
8316 return 0;
8317 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8318 size = NVRAM_SELFBOOT_HW_SIZE;
8319 else
8320 return -EIO;
8321
8322 buf = kmalloc(size, GFP_KERNEL);
8323 if (buf == NULL)
8324 return -ENOMEM;
8325
8326 err = -EIO;
8327 for (i = 0, j = 0; i < size; i += 4, j++) {
8328 u32 val;
8329
8330 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8331 break;
8332 buf[j] = cpu_to_le32(val);
8333 }
8334 if (i < size)
8335 goto out;
8336
8337 /* Selfboot format */
8338 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8339 TG3_EEPROM_MAGIC_FW) {
8340 u8 *buf8 = (u8 *) buf, csum8 = 0;
8341
8342 for (i = 0; i < size; i++)
8343 csum8 += buf8[i];
8344
8345 if (csum8 == 0) {
8346 err = 0;
8347 goto out;
8348 }
8349
8350 err = -EIO;
8351 goto out;
8352 }
8353
8354 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8355 TG3_EEPROM_MAGIC_HW) {
8356 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8357 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8358 u8 *buf8 = (u8 *) buf;
8359 int j, k;
8360
8361 /* Separate the parity bits and the data bytes. */
8362 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8363 if ((i == 0) || (i == 8)) {
8364 int l;
8365 u8 msk;
8366
8367 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8368 parity[k++] = buf8[i] & msk;
8369 i++;
8370 }
8371 else if (i == 16) {
8372 int l;
8373 u8 msk;
8374
8375 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8376 parity[k++] = buf8[i] & msk;
8377 i++;
8378
8379 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8380 parity[k++] = buf8[i] & msk;
8381 i++;
8382 }
8383 data[j++] = buf8[i];
8384 }
8385
8386 err = -EIO;
8387 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8388 u8 hw8 = hweight8(data[i]);
8389
8390 if ((hw8 & 0x1) && parity[i])
8391 goto out;
8392 else if (!(hw8 & 0x1) && !parity[i])
8393 goto out;
8394 }
8395 err = 0;
8396 goto out;
8397 }
8398
8399 /* Bootstrap checksum at offset 0x10 */
8400 csum = calc_crc((unsigned char *) buf, 0x10);
8401 if(csum != cpu_to_le32(buf[0x10/4]))
8402 goto out;
8403
8404 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8405 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8406 if (csum != cpu_to_le32(buf[0xfc/4]))
8407 goto out;
8408
8409 err = 0;
8410
8411 out:
8412 kfree(buf);
8413 return err;
8414 }
8415
8416 #define TG3_SERDES_TIMEOUT_SEC 2
8417 #define TG3_COPPER_TIMEOUT_SEC 6
8418
8419 static int tg3_test_link(struct tg3 *tp)
8420 {
8421 int i, max;
8422
8423 if (!netif_running(tp->dev))
8424 return -ENODEV;
8425
8426 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8427 max = TG3_SERDES_TIMEOUT_SEC;
8428 else
8429 max = TG3_COPPER_TIMEOUT_SEC;
8430
8431 for (i = 0; i < max; i++) {
8432 if (netif_carrier_ok(tp->dev))
8433 return 0;
8434
8435 if (msleep_interruptible(1000))
8436 break;
8437 }
8438
8439 return -EIO;
8440 }
8441
8442 /* Only test the commonly used registers */
8443 static int tg3_test_registers(struct tg3 *tp)
8444 {
8445 int i, is_5705, is_5750;
8446 u32 offset, read_mask, write_mask, val, save_val, read_val;
8447 static struct {
8448 u16 offset;
8449 u16 flags;
8450 #define TG3_FL_5705 0x1
8451 #define TG3_FL_NOT_5705 0x2
8452 #define TG3_FL_NOT_5788 0x4
8453 #define TG3_FL_NOT_5750 0x8
8454 u32 read_mask;
8455 u32 write_mask;
8456 } reg_tbl[] = {
8457 /* MAC Control Registers */
8458 { MAC_MODE, TG3_FL_NOT_5705,
8459 0x00000000, 0x00ef6f8c },
8460 { MAC_MODE, TG3_FL_5705,
8461 0x00000000, 0x01ef6b8c },
8462 { MAC_STATUS, TG3_FL_NOT_5705,
8463 0x03800107, 0x00000000 },
8464 { MAC_STATUS, TG3_FL_5705,
8465 0x03800100, 0x00000000 },
8466 { MAC_ADDR_0_HIGH, 0x0000,
8467 0x00000000, 0x0000ffff },
8468 { MAC_ADDR_0_LOW, 0x0000,
8469 0x00000000, 0xffffffff },
8470 { MAC_RX_MTU_SIZE, 0x0000,
8471 0x00000000, 0x0000ffff },
8472 { MAC_TX_MODE, 0x0000,
8473 0x00000000, 0x00000070 },
8474 { MAC_TX_LENGTHS, 0x0000,
8475 0x00000000, 0x00003fff },
8476 { MAC_RX_MODE, TG3_FL_NOT_5705,
8477 0x00000000, 0x000007fc },
8478 { MAC_RX_MODE, TG3_FL_5705,
8479 0x00000000, 0x000007dc },
8480 { MAC_HASH_REG_0, 0x0000,
8481 0x00000000, 0xffffffff },
8482 { MAC_HASH_REG_1, 0x0000,
8483 0x00000000, 0xffffffff },
8484 { MAC_HASH_REG_2, 0x0000,
8485 0x00000000, 0xffffffff },
8486 { MAC_HASH_REG_3, 0x0000,
8487 0x00000000, 0xffffffff },
8488
8489 /* Receive Data and Receive BD Initiator Control Registers. */
8490 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8491 0x00000000, 0xffffffff },
8492 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8493 0x00000000, 0xffffffff },
8494 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8495 0x00000000, 0x00000003 },
8496 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8497 0x00000000, 0xffffffff },
8498 { RCVDBDI_STD_BD+0, 0x0000,
8499 0x00000000, 0xffffffff },
8500 { RCVDBDI_STD_BD+4, 0x0000,
8501 0x00000000, 0xffffffff },
8502 { RCVDBDI_STD_BD+8, 0x0000,
8503 0x00000000, 0xffff0002 },
8504 { RCVDBDI_STD_BD+0xc, 0x0000,
8505 0x00000000, 0xffffffff },
8506
8507 /* Receive BD Initiator Control Registers. */
8508 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8509 0x00000000, 0xffffffff },
8510 { RCVBDI_STD_THRESH, TG3_FL_5705,
8511 0x00000000, 0x000003ff },
8512 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8513 0x00000000, 0xffffffff },
8514
8515 /* Host Coalescing Control Registers. */
8516 { HOSTCC_MODE, TG3_FL_NOT_5705,
8517 0x00000000, 0x00000004 },
8518 { HOSTCC_MODE, TG3_FL_5705,
8519 0x00000000, 0x000000f6 },
8520 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8521 0x00000000, 0xffffffff },
8522 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8523 0x00000000, 0x000003ff },
8524 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8525 0x00000000, 0xffffffff },
8526 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8527 0x00000000, 0x000003ff },
8528 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8529 0x00000000, 0xffffffff },
8530 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8531 0x00000000, 0x000000ff },
8532 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8533 0x00000000, 0xffffffff },
8534 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8535 0x00000000, 0x000000ff },
8536 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8537 0x00000000, 0xffffffff },
8538 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8539 0x00000000, 0xffffffff },
8540 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8541 0x00000000, 0xffffffff },
8542 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8543 0x00000000, 0x000000ff },
8544 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8545 0x00000000, 0xffffffff },
8546 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8547 0x00000000, 0x000000ff },
8548 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8549 0x00000000, 0xffffffff },
8550 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8551 0x00000000, 0xffffffff },
8552 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8553 0x00000000, 0xffffffff },
8554 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8555 0x00000000, 0xffffffff },
8556 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8557 0x00000000, 0xffffffff },
8558 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8559 0xffffffff, 0x00000000 },
8560 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8561 0xffffffff, 0x00000000 },
8562
8563 /* Buffer Manager Control Registers. */
8564 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8565 0x00000000, 0x007fff80 },
8566 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8567 0x00000000, 0x007fffff },
8568 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8569 0x00000000, 0x0000003f },
8570 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8571 0x00000000, 0x000001ff },
8572 { BUFMGR_MB_HIGH_WATER, 0x0000,
8573 0x00000000, 0x000001ff },
8574 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8575 0xffffffff, 0x00000000 },
8576 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8577 0xffffffff, 0x00000000 },
8578
8579 /* Mailbox Registers */
8580 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8581 0x00000000, 0x000001ff },
8582 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8583 0x00000000, 0x000001ff },
8584 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8585 0x00000000, 0x000007ff },
8586 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8587 0x00000000, 0x000001ff },
8588
8589 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8590 };
8591
8592 is_5705 = is_5750 = 0;
8593 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8594 is_5705 = 1;
8595 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8596 is_5750 = 1;
8597 }
8598
8599 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8600 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8601 continue;
8602
8603 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8604 continue;
8605
8606 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8607 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8608 continue;
8609
8610 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8611 continue;
8612
8613 offset = (u32) reg_tbl[i].offset;
8614 read_mask = reg_tbl[i].read_mask;
8615 write_mask = reg_tbl[i].write_mask;
8616
8617 /* Save the original register content */
8618 save_val = tr32(offset);
8619
8620 /* Determine the read-only value. */
8621 read_val = save_val & read_mask;
8622
8623 /* Write zero to the register, then make sure the read-only bits
8624 * are not changed and the read/write bits are all zeros.
8625 */
8626 tw32(offset, 0);
8627
8628 val = tr32(offset);
8629
8630 /* Test the read-only and read/write bits. */
8631 if (((val & read_mask) != read_val) || (val & write_mask))
8632 goto out;
8633
8634 /* Write ones to all the bits defined by RdMask and WrMask, then
8635 * make sure the read-only bits are not changed and the
8636 * read/write bits are all ones.
8637 */
8638 tw32(offset, read_mask | write_mask);
8639
8640 val = tr32(offset);
8641
8642 /* Test the read-only bits. */
8643 if ((val & read_mask) != read_val)
8644 goto out;
8645
8646 /* Test the read/write bits. */
8647 if ((val & write_mask) != write_mask)
8648 goto out;
8649
8650 tw32(offset, save_val);
8651 }
8652
8653 return 0;
8654
8655 out:
8656 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8657 tw32(offset, save_val);
8658 return -EIO;
8659 }
8660
8661 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8662 {
8663 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8664 int i;
8665 u32 j;
8666
8667 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8668 for (j = 0; j < len; j += 4) {
8669 u32 val;
8670
8671 tg3_write_mem(tp, offset + j, test_pattern[i]);
8672 tg3_read_mem(tp, offset + j, &val);
8673 if (val != test_pattern[i])
8674 return -EIO;
8675 }
8676 }
8677 return 0;
8678 }
8679
8680 static int tg3_test_memory(struct tg3 *tp)
8681 {
8682 static struct mem_entry {
8683 u32 offset;
8684 u32 len;
8685 } mem_tbl_570x[] = {
8686 { 0x00000000, 0x00b50},
8687 { 0x00002000, 0x1c000},
8688 { 0xffffffff, 0x00000}
8689 }, mem_tbl_5705[] = {
8690 { 0x00000100, 0x0000c},
8691 { 0x00000200, 0x00008},
8692 { 0x00004000, 0x00800},
8693 { 0x00006000, 0x01000},
8694 { 0x00008000, 0x02000},
8695 { 0x00010000, 0x0e000},
8696 { 0xffffffff, 0x00000}
8697 }, mem_tbl_5755[] = {
8698 { 0x00000200, 0x00008},
8699 { 0x00004000, 0x00800},
8700 { 0x00006000, 0x00800},
8701 { 0x00008000, 0x02000},
8702 { 0x00010000, 0x0c000},
8703 { 0xffffffff, 0x00000}
8704 }, mem_tbl_5906[] = {
8705 { 0x00000200, 0x00008},
8706 { 0x00004000, 0x00400},
8707 { 0x00006000, 0x00400},
8708 { 0x00008000, 0x01000},
8709 { 0x00010000, 0x01000},
8710 { 0xffffffff, 0x00000}
8711 };
8712 struct mem_entry *mem_tbl;
8713 int err = 0;
8714 int i;
8715
8716 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8717 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8718 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8719 mem_tbl = mem_tbl_5755;
8720 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8721 mem_tbl = mem_tbl_5906;
8722 else
8723 mem_tbl = mem_tbl_5705;
8724 } else
8725 mem_tbl = mem_tbl_570x;
8726
8727 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8728 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8729 mem_tbl[i].len)) != 0)
8730 break;
8731 }
8732
8733 return err;
8734 }
8735
8736 #define TG3_MAC_LOOPBACK 0
8737 #define TG3_PHY_LOOPBACK 1
8738
8739 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8740 {
8741 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8742 u32 desc_idx;
8743 struct sk_buff *skb, *rx_skb;
8744 u8 *tx_data;
8745 dma_addr_t map;
8746 int num_pkts, tx_len, rx_len, i, err;
8747 struct tg3_rx_buffer_desc *desc;
8748
8749 if (loopback_mode == TG3_MAC_LOOPBACK) {
8750 /* HW errata - mac loopback fails in some cases on 5780.
8751 * Normal traffic and PHY loopback are not affected by
8752 * errata.
8753 */
8754 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8755 return 0;
8756
8757 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8758 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8759 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8760 mac_mode |= MAC_MODE_PORT_MODE_MII;
8761 else
8762 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8763 tw32(MAC_MODE, mac_mode);
8764 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8765 u32 val;
8766
8767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8768 u32 phytest;
8769
8770 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8771 u32 phy;
8772
8773 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8774 phytest | MII_TG3_EPHY_SHADOW_EN);
8775 if (!tg3_readphy(tp, 0x1b, &phy))
8776 tg3_writephy(tp, 0x1b, phy & ~0x20);
8777 if (!tg3_readphy(tp, 0x10, &phy))
8778 tg3_writephy(tp, 0x10, phy & ~0x4000);
8779 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8780 }
8781 }
8782 val = BMCR_LOOPBACK | BMCR_FULLDPLX;
8783 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8784 val |= BMCR_SPEED100;
8785 else
8786 val |= BMCR_SPEED1000;
8787
8788 tg3_writephy(tp, MII_BMCR, val);
8789 udelay(40);
8790 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8791 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8792
8793 /* reset to prevent losing 1st rx packet intermittently */
8794 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8795 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8796 udelay(10);
8797 tw32_f(MAC_RX_MODE, tp->rx_mode);
8798 }
8799 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8800 MAC_MODE_LINK_POLARITY;
8801 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8802 mac_mode |= MAC_MODE_PORT_MODE_MII;
8803 else
8804 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8805 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8806 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8807 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8808 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8809 }
8810 tw32(MAC_MODE, mac_mode);
8811 }
8812 else
8813 return -EINVAL;
8814
8815 err = -EIO;
8816
8817 tx_len = 1514;
8818 skb = netdev_alloc_skb(tp->dev, tx_len);
8819 if (!skb)
8820 return -ENOMEM;
8821
8822 tx_data = skb_put(skb, tx_len);
8823 memcpy(tx_data, tp->dev->dev_addr, 6);
8824 memset(tx_data + 6, 0x0, 8);
8825
8826 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8827
8828 for (i = 14; i < tx_len; i++)
8829 tx_data[i] = (u8) (i & 0xff);
8830
8831 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8832
8833 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8834 HOSTCC_MODE_NOW);
8835
8836 udelay(10);
8837
8838 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8839
8840 num_pkts = 0;
8841
8842 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8843
8844 tp->tx_prod++;
8845 num_pkts++;
8846
8847 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8848 tp->tx_prod);
8849 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8850
8851 udelay(10);
8852
8853 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8854 for (i = 0; i < 25; i++) {
8855 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8856 HOSTCC_MODE_NOW);
8857
8858 udelay(10);
8859
8860 tx_idx = tp->hw_status->idx[0].tx_consumer;
8861 rx_idx = tp->hw_status->idx[0].rx_producer;
8862 if ((tx_idx == tp->tx_prod) &&
8863 (rx_idx == (rx_start_idx + num_pkts)))
8864 break;
8865 }
8866
8867 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8868 dev_kfree_skb(skb);
8869
8870 if (tx_idx != tp->tx_prod)
8871 goto out;
8872
8873 if (rx_idx != rx_start_idx + num_pkts)
8874 goto out;
8875
8876 desc = &tp->rx_rcb[rx_start_idx];
8877 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8878 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8879 if (opaque_key != RXD_OPAQUE_RING_STD)
8880 goto out;
8881
8882 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8883 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8884 goto out;
8885
8886 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8887 if (rx_len != tx_len)
8888 goto out;
8889
8890 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8891
8892 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8893 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8894
8895 for (i = 14; i < tx_len; i++) {
8896 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8897 goto out;
8898 }
8899 err = 0;
8900
8901 /* tg3_free_rings will unmap and free the rx_skb */
8902 out:
8903 return err;
8904 }
8905
8906 #define TG3_MAC_LOOPBACK_FAILED 1
8907 #define TG3_PHY_LOOPBACK_FAILED 2
8908 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
8909 TG3_PHY_LOOPBACK_FAILED)
8910
8911 static int tg3_test_loopback(struct tg3 *tp)
8912 {
8913 int err = 0;
8914
8915 if (!netif_running(tp->dev))
8916 return TG3_LOOPBACK_FAILED;
8917
8918 err = tg3_reset_hw(tp, 1);
8919 if (err)
8920 return TG3_LOOPBACK_FAILED;
8921
8922 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8923 err |= TG3_MAC_LOOPBACK_FAILED;
8924 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8925 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8926 err |= TG3_PHY_LOOPBACK_FAILED;
8927 }
8928
8929 return err;
8930 }
8931
8932 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8933 u64 *data)
8934 {
8935 struct tg3 *tp = netdev_priv(dev);
8936
8937 if (tp->link_config.phy_is_low_power)
8938 tg3_set_power_state(tp, PCI_D0);
8939
8940 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8941
8942 if (tg3_test_nvram(tp) != 0) {
8943 etest->flags |= ETH_TEST_FL_FAILED;
8944 data[0] = 1;
8945 }
8946 if (tg3_test_link(tp) != 0) {
8947 etest->flags |= ETH_TEST_FL_FAILED;
8948 data[1] = 1;
8949 }
8950 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8951 int err, irq_sync = 0;
8952
8953 if (netif_running(dev)) {
8954 tg3_netif_stop(tp);
8955 irq_sync = 1;
8956 }
8957
8958 tg3_full_lock(tp, irq_sync);
8959
8960 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8961 err = tg3_nvram_lock(tp);
8962 tg3_halt_cpu(tp, RX_CPU_BASE);
8963 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8964 tg3_halt_cpu(tp, TX_CPU_BASE);
8965 if (!err)
8966 tg3_nvram_unlock(tp);
8967
8968 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8969 tg3_phy_reset(tp);
8970
8971 if (tg3_test_registers(tp) != 0) {
8972 etest->flags |= ETH_TEST_FL_FAILED;
8973 data[2] = 1;
8974 }
8975 if (tg3_test_memory(tp) != 0) {
8976 etest->flags |= ETH_TEST_FL_FAILED;
8977 data[3] = 1;
8978 }
8979 if ((data[4] = tg3_test_loopback(tp)) != 0)
8980 etest->flags |= ETH_TEST_FL_FAILED;
8981
8982 tg3_full_unlock(tp);
8983
8984 if (tg3_test_interrupt(tp) != 0) {
8985 etest->flags |= ETH_TEST_FL_FAILED;
8986 data[5] = 1;
8987 }
8988
8989 tg3_full_lock(tp, 0);
8990
8991 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8992 if (netif_running(dev)) {
8993 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8994 if (!tg3_restart_hw(tp, 1))
8995 tg3_netif_start(tp);
8996 }
8997
8998 tg3_full_unlock(tp);
8999 }
9000 if (tp->link_config.phy_is_low_power)
9001 tg3_set_power_state(tp, PCI_D3hot);
9002
9003 }
9004
9005 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9006 {
9007 struct mii_ioctl_data *data = if_mii(ifr);
9008 struct tg3 *tp = netdev_priv(dev);
9009 int err;
9010
9011 switch(cmd) {
9012 case SIOCGMIIPHY:
9013 data->phy_id = PHY_ADDR;
9014
9015 /* fallthru */
9016 case SIOCGMIIREG: {
9017 u32 mii_regval;
9018
9019 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9020 break; /* We have no PHY */
9021
9022 if (tp->link_config.phy_is_low_power)
9023 return -EAGAIN;
9024
9025 spin_lock_bh(&tp->lock);
9026 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9027 spin_unlock_bh(&tp->lock);
9028
9029 data->val_out = mii_regval;
9030
9031 return err;
9032 }
9033
9034 case SIOCSMIIREG:
9035 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9036 break; /* We have no PHY */
9037
9038 if (!capable(CAP_NET_ADMIN))
9039 return -EPERM;
9040
9041 if (tp->link_config.phy_is_low_power)
9042 return -EAGAIN;
9043
9044 spin_lock_bh(&tp->lock);
9045 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9046 spin_unlock_bh(&tp->lock);
9047
9048 return err;
9049
9050 default:
9051 /* do nothing */
9052 break;
9053 }
9054 return -EOPNOTSUPP;
9055 }
9056
9057 #if TG3_VLAN_TAG_USED
9058 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9059 {
9060 struct tg3 *tp = netdev_priv(dev);
9061
9062 if (netif_running(dev))
9063 tg3_netif_stop(tp);
9064
9065 tg3_full_lock(tp, 0);
9066
9067 tp->vlgrp = grp;
9068
9069 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9070 __tg3_set_rx_mode(dev);
9071
9072 tg3_full_unlock(tp);
9073
9074 if (netif_running(dev))
9075 tg3_netif_start(tp);
9076 }
9077
9078 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9079 {
9080 struct tg3 *tp = netdev_priv(dev);
9081
9082 if (netif_running(dev))
9083 tg3_netif_stop(tp);
9084
9085 tg3_full_lock(tp, 0);
9086 if (tp->vlgrp)
9087 tp->vlgrp->vlan_devices[vid] = NULL;
9088 tg3_full_unlock(tp);
9089
9090 if (netif_running(dev))
9091 tg3_netif_start(tp);
9092 }
9093 #endif
9094
9095 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9096 {
9097 struct tg3 *tp = netdev_priv(dev);
9098
9099 memcpy(ec, &tp->coal, sizeof(*ec));
9100 return 0;
9101 }
9102
9103 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9104 {
9105 struct tg3 *tp = netdev_priv(dev);
9106 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9107 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9108
9109 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9110 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9111 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9112 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9113 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9114 }
9115
9116 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9117 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9118 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9119 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9120 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9121 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9122 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9123 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9124 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9125 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9126 return -EINVAL;
9127
9128 /* No rx interrupts will be generated if both are zero */
9129 if ((ec->rx_coalesce_usecs == 0) &&
9130 (ec->rx_max_coalesced_frames == 0))
9131 return -EINVAL;
9132
9133 /* No tx interrupts will be generated if both are zero */
9134 if ((ec->tx_coalesce_usecs == 0) &&
9135 (ec->tx_max_coalesced_frames == 0))
9136 return -EINVAL;
9137
9138 /* Only copy relevant parameters, ignore all others. */
9139 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9140 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9141 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9142 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9143 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9144 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9145 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9146 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9147 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9148
9149 if (netif_running(dev)) {
9150 tg3_full_lock(tp, 0);
9151 __tg3_set_coalesce(tp, &tp->coal);
9152 tg3_full_unlock(tp);
9153 }
9154 return 0;
9155 }
9156
9157 static const struct ethtool_ops tg3_ethtool_ops = {
9158 .get_settings = tg3_get_settings,
9159 .set_settings = tg3_set_settings,
9160 .get_drvinfo = tg3_get_drvinfo,
9161 .get_regs_len = tg3_get_regs_len,
9162 .get_regs = tg3_get_regs,
9163 .get_wol = tg3_get_wol,
9164 .set_wol = tg3_set_wol,
9165 .get_msglevel = tg3_get_msglevel,
9166 .set_msglevel = tg3_set_msglevel,
9167 .nway_reset = tg3_nway_reset,
9168 .get_link = ethtool_op_get_link,
9169 .get_eeprom_len = tg3_get_eeprom_len,
9170 .get_eeprom = tg3_get_eeprom,
9171 .set_eeprom = tg3_set_eeprom,
9172 .get_ringparam = tg3_get_ringparam,
9173 .set_ringparam = tg3_set_ringparam,
9174 .get_pauseparam = tg3_get_pauseparam,
9175 .set_pauseparam = tg3_set_pauseparam,
9176 .get_rx_csum = tg3_get_rx_csum,
9177 .set_rx_csum = tg3_set_rx_csum,
9178 .get_tx_csum = ethtool_op_get_tx_csum,
9179 .set_tx_csum = tg3_set_tx_csum,
9180 .get_sg = ethtool_op_get_sg,
9181 .set_sg = ethtool_op_set_sg,
9182 #if TG3_TSO_SUPPORT != 0
9183 .get_tso = ethtool_op_get_tso,
9184 .set_tso = tg3_set_tso,
9185 #endif
9186 .self_test_count = tg3_get_test_count,
9187 .self_test = tg3_self_test,
9188 .get_strings = tg3_get_strings,
9189 .phys_id = tg3_phys_id,
9190 .get_stats_count = tg3_get_stats_count,
9191 .get_ethtool_stats = tg3_get_ethtool_stats,
9192 .get_coalesce = tg3_get_coalesce,
9193 .set_coalesce = tg3_set_coalesce,
9194 .get_perm_addr = ethtool_op_get_perm_addr,
9195 };
9196
9197 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9198 {
9199 u32 cursize, val, magic;
9200
9201 tp->nvram_size = EEPROM_CHIP_SIZE;
9202
9203 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9204 return;
9205
9206 if ((magic != TG3_EEPROM_MAGIC) &&
9207 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9208 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9209 return;
9210
9211 /*
9212 * Size the chip by reading offsets at increasing powers of two.
9213 * When we encounter our validation signature, we know the addressing
9214 * has wrapped around, and thus have our chip size.
9215 */
9216 cursize = 0x10;
9217
9218 while (cursize < tp->nvram_size) {
9219 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9220 return;
9221
9222 if (val == magic)
9223 break;
9224
9225 cursize <<= 1;
9226 }
9227
9228 tp->nvram_size = cursize;
9229 }
9230
9231 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9232 {
9233 u32 val;
9234
9235 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9236 return;
9237
9238 /* Selfboot format */
9239 if (val != TG3_EEPROM_MAGIC) {
9240 tg3_get_eeprom_size(tp);
9241 return;
9242 }
9243
9244 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9245 if (val != 0) {
9246 tp->nvram_size = (val >> 16) * 1024;
9247 return;
9248 }
9249 }
9250 tp->nvram_size = 0x20000;
9251 }
9252
9253 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9254 {
9255 u32 nvcfg1;
9256
9257 nvcfg1 = tr32(NVRAM_CFG1);
9258 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9259 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9260 }
9261 else {
9262 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9263 tw32(NVRAM_CFG1, nvcfg1);
9264 }
9265
9266 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9267 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9268 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9269 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9270 tp->nvram_jedecnum = JEDEC_ATMEL;
9271 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9272 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9273 break;
9274 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9275 tp->nvram_jedecnum = JEDEC_ATMEL;
9276 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9277 break;
9278 case FLASH_VENDOR_ATMEL_EEPROM:
9279 tp->nvram_jedecnum = JEDEC_ATMEL;
9280 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9281 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9282 break;
9283 case FLASH_VENDOR_ST:
9284 tp->nvram_jedecnum = JEDEC_ST;
9285 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9286 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9287 break;
9288 case FLASH_VENDOR_SAIFUN:
9289 tp->nvram_jedecnum = JEDEC_SAIFUN;
9290 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9291 break;
9292 case FLASH_VENDOR_SST_SMALL:
9293 case FLASH_VENDOR_SST_LARGE:
9294 tp->nvram_jedecnum = JEDEC_SST;
9295 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9296 break;
9297 }
9298 }
9299 else {
9300 tp->nvram_jedecnum = JEDEC_ATMEL;
9301 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9302 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9303 }
9304 }
9305
9306 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9307 {
9308 u32 nvcfg1;
9309
9310 nvcfg1 = tr32(NVRAM_CFG1);
9311
9312 /* NVRAM protection for TPM */
9313 if (nvcfg1 & (1 << 27))
9314 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9315
9316 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9317 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9318 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9319 tp->nvram_jedecnum = JEDEC_ATMEL;
9320 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9321 break;
9322 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9323 tp->nvram_jedecnum = JEDEC_ATMEL;
9324 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9325 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9326 break;
9327 case FLASH_5752VENDOR_ST_M45PE10:
9328 case FLASH_5752VENDOR_ST_M45PE20:
9329 case FLASH_5752VENDOR_ST_M45PE40:
9330 tp->nvram_jedecnum = JEDEC_ST;
9331 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9332 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9333 break;
9334 }
9335
9336 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9337 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9338 case FLASH_5752PAGE_SIZE_256:
9339 tp->nvram_pagesize = 256;
9340 break;
9341 case FLASH_5752PAGE_SIZE_512:
9342 tp->nvram_pagesize = 512;
9343 break;
9344 case FLASH_5752PAGE_SIZE_1K:
9345 tp->nvram_pagesize = 1024;
9346 break;
9347 case FLASH_5752PAGE_SIZE_2K:
9348 tp->nvram_pagesize = 2048;
9349 break;
9350 case FLASH_5752PAGE_SIZE_4K:
9351 tp->nvram_pagesize = 4096;
9352 break;
9353 case FLASH_5752PAGE_SIZE_264:
9354 tp->nvram_pagesize = 264;
9355 break;
9356 }
9357 }
9358 else {
9359 /* For eeprom, set pagesize to maximum eeprom size */
9360 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9361
9362 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9363 tw32(NVRAM_CFG1, nvcfg1);
9364 }
9365 }
9366
9367 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9368 {
9369 u32 nvcfg1;
9370
9371 nvcfg1 = tr32(NVRAM_CFG1);
9372
9373 /* NVRAM protection for TPM */
9374 if (nvcfg1 & (1 << 27))
9375 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9376
9377 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9378 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9379 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9380 tp->nvram_jedecnum = JEDEC_ATMEL;
9381 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9383
9384 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9385 tw32(NVRAM_CFG1, nvcfg1);
9386 break;
9387 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9388 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9389 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9390 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9391 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9392 tp->nvram_jedecnum = JEDEC_ATMEL;
9393 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9394 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9395 tp->nvram_pagesize = 264;
9396 break;
9397 case FLASH_5752VENDOR_ST_M45PE10:
9398 case FLASH_5752VENDOR_ST_M45PE20:
9399 case FLASH_5752VENDOR_ST_M45PE40:
9400 tp->nvram_jedecnum = JEDEC_ST;
9401 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9402 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9403 tp->nvram_pagesize = 256;
9404 break;
9405 }
9406 }
9407
9408 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9409 {
9410 u32 nvcfg1;
9411
9412 nvcfg1 = tr32(NVRAM_CFG1);
9413
9414 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9415 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9416 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9417 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9418 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9419 tp->nvram_jedecnum = JEDEC_ATMEL;
9420 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9421 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9422
9423 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9424 tw32(NVRAM_CFG1, nvcfg1);
9425 break;
9426 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9427 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9428 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9429 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9430 tp->nvram_jedecnum = JEDEC_ATMEL;
9431 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9432 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9433 tp->nvram_pagesize = 264;
9434 break;
9435 case FLASH_5752VENDOR_ST_M45PE10:
9436 case FLASH_5752VENDOR_ST_M45PE20:
9437 case FLASH_5752VENDOR_ST_M45PE40:
9438 tp->nvram_jedecnum = JEDEC_ST;
9439 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9440 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9441 tp->nvram_pagesize = 256;
9442 break;
9443 }
9444 }
9445
9446 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9447 {
9448 tp->nvram_jedecnum = JEDEC_ATMEL;
9449 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9450 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9451 }
9452
9453 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9454 static void __devinit tg3_nvram_init(struct tg3 *tp)
9455 {
9456 int j;
9457
9458 tw32_f(GRC_EEPROM_ADDR,
9459 (EEPROM_ADDR_FSM_RESET |
9460 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9461 EEPROM_ADDR_CLKPERD_SHIFT)));
9462
9463 /* XXX schedule_timeout() ... */
9464 for (j = 0; j < 100; j++)
9465 udelay(10);
9466
9467 /* Enable seeprom accesses. */
9468 tw32_f(GRC_LOCAL_CTRL,
9469 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9470 udelay(100);
9471
9472 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9473 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9474 tp->tg3_flags |= TG3_FLAG_NVRAM;
9475
9476 if (tg3_nvram_lock(tp)) {
9477 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9478 "tg3_nvram_init failed.\n", tp->dev->name);
9479 return;
9480 }
9481 tg3_enable_nvram_access(tp);
9482
9483 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9484 tg3_get_5752_nvram_info(tp);
9485 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9486 tg3_get_5755_nvram_info(tp);
9487 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9488 tg3_get_5787_nvram_info(tp);
9489 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9490 tg3_get_5906_nvram_info(tp);
9491 else
9492 tg3_get_nvram_info(tp);
9493
9494 tg3_get_nvram_size(tp);
9495
9496 tg3_disable_nvram_access(tp);
9497 tg3_nvram_unlock(tp);
9498
9499 } else {
9500 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9501
9502 tg3_get_eeprom_size(tp);
9503 }
9504 }
9505
9506 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9507 u32 offset, u32 *val)
9508 {
9509 u32 tmp;
9510 int i;
9511
9512 if (offset > EEPROM_ADDR_ADDR_MASK ||
9513 (offset % 4) != 0)
9514 return -EINVAL;
9515
9516 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9517 EEPROM_ADDR_DEVID_MASK |
9518 EEPROM_ADDR_READ);
9519 tw32(GRC_EEPROM_ADDR,
9520 tmp |
9521 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9522 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9523 EEPROM_ADDR_ADDR_MASK) |
9524 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9525
9526 for (i = 0; i < 10000; i++) {
9527 tmp = tr32(GRC_EEPROM_ADDR);
9528
9529 if (tmp & EEPROM_ADDR_COMPLETE)
9530 break;
9531 udelay(100);
9532 }
9533 if (!(tmp & EEPROM_ADDR_COMPLETE))
9534 return -EBUSY;
9535
9536 *val = tr32(GRC_EEPROM_DATA);
9537 return 0;
9538 }
9539
9540 #define NVRAM_CMD_TIMEOUT 10000
9541
9542 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9543 {
9544 int i;
9545
9546 tw32(NVRAM_CMD, nvram_cmd);
9547 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9548 udelay(10);
9549 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9550 udelay(10);
9551 break;
9552 }
9553 }
9554 if (i == NVRAM_CMD_TIMEOUT) {
9555 return -EBUSY;
9556 }
9557 return 0;
9558 }
9559
9560 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9561 {
9562 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9563 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9564 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9565 (tp->nvram_jedecnum == JEDEC_ATMEL))
9566
9567 addr = ((addr / tp->nvram_pagesize) <<
9568 ATMEL_AT45DB0X1B_PAGE_POS) +
9569 (addr % tp->nvram_pagesize);
9570
9571 return addr;
9572 }
9573
9574 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9575 {
9576 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9577 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9578 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9579 (tp->nvram_jedecnum == JEDEC_ATMEL))
9580
9581 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9582 tp->nvram_pagesize) +
9583 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9584
9585 return addr;
9586 }
9587
9588 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9589 {
9590 int ret;
9591
9592 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9593 return tg3_nvram_read_using_eeprom(tp, offset, val);
9594
9595 offset = tg3_nvram_phys_addr(tp, offset);
9596
9597 if (offset > NVRAM_ADDR_MSK)
9598 return -EINVAL;
9599
9600 ret = tg3_nvram_lock(tp);
9601 if (ret)
9602 return ret;
9603
9604 tg3_enable_nvram_access(tp);
9605
9606 tw32(NVRAM_ADDR, offset);
9607 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9608 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9609
9610 if (ret == 0)
9611 *val = swab32(tr32(NVRAM_RDDATA));
9612
9613 tg3_disable_nvram_access(tp);
9614
9615 tg3_nvram_unlock(tp);
9616
9617 return ret;
9618 }
9619
9620 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9621 {
9622 int err;
9623 u32 tmp;
9624
9625 err = tg3_nvram_read(tp, offset, &tmp);
9626 *val = swab32(tmp);
9627 return err;
9628 }
9629
9630 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9631 u32 offset, u32 len, u8 *buf)
9632 {
9633 int i, j, rc = 0;
9634 u32 val;
9635
9636 for (i = 0; i < len; i += 4) {
9637 u32 addr, data;
9638
9639 addr = offset + i;
9640
9641 memcpy(&data, buf + i, 4);
9642
9643 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9644
9645 val = tr32(GRC_EEPROM_ADDR);
9646 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9647
9648 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9649 EEPROM_ADDR_READ);
9650 tw32(GRC_EEPROM_ADDR, val |
9651 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9652 (addr & EEPROM_ADDR_ADDR_MASK) |
9653 EEPROM_ADDR_START |
9654 EEPROM_ADDR_WRITE);
9655
9656 for (j = 0; j < 10000; j++) {
9657 val = tr32(GRC_EEPROM_ADDR);
9658
9659 if (val & EEPROM_ADDR_COMPLETE)
9660 break;
9661 udelay(100);
9662 }
9663 if (!(val & EEPROM_ADDR_COMPLETE)) {
9664 rc = -EBUSY;
9665 break;
9666 }
9667 }
9668
9669 return rc;
9670 }
9671
9672 /* offset and length are dword aligned */
9673 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9674 u8 *buf)
9675 {
9676 int ret = 0;
9677 u32 pagesize = tp->nvram_pagesize;
9678 u32 pagemask = pagesize - 1;
9679 u32 nvram_cmd;
9680 u8 *tmp;
9681
9682 tmp = kmalloc(pagesize, GFP_KERNEL);
9683 if (tmp == NULL)
9684 return -ENOMEM;
9685
9686 while (len) {
9687 int j;
9688 u32 phy_addr, page_off, size;
9689
9690 phy_addr = offset & ~pagemask;
9691
9692 for (j = 0; j < pagesize; j += 4) {
9693 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9694 (u32 *) (tmp + j))))
9695 break;
9696 }
9697 if (ret)
9698 break;
9699
9700 page_off = offset & pagemask;
9701 size = pagesize;
9702 if (len < size)
9703 size = len;
9704
9705 len -= size;
9706
9707 memcpy(tmp + page_off, buf, size);
9708
9709 offset = offset + (pagesize - page_off);
9710
9711 tg3_enable_nvram_access(tp);
9712
9713 /*
9714 * Before we can erase the flash page, we need
9715 * to issue a special "write enable" command.
9716 */
9717 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9718
9719 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9720 break;
9721
9722 /* Erase the target page */
9723 tw32(NVRAM_ADDR, phy_addr);
9724
9725 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9726 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9727
9728 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9729 break;
9730
9731 /* Issue another write enable to start the write. */
9732 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9733
9734 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9735 break;
9736
9737 for (j = 0; j < pagesize; j += 4) {
9738 u32 data;
9739
9740 data = *((u32 *) (tmp + j));
9741 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9742
9743 tw32(NVRAM_ADDR, phy_addr + j);
9744
9745 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9746 NVRAM_CMD_WR;
9747
9748 if (j == 0)
9749 nvram_cmd |= NVRAM_CMD_FIRST;
9750 else if (j == (pagesize - 4))
9751 nvram_cmd |= NVRAM_CMD_LAST;
9752
9753 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9754 break;
9755 }
9756 if (ret)
9757 break;
9758 }
9759
9760 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9761 tg3_nvram_exec_cmd(tp, nvram_cmd);
9762
9763 kfree(tmp);
9764
9765 return ret;
9766 }
9767
9768 /* offset and length are dword aligned */
9769 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9770 u8 *buf)
9771 {
9772 int i, ret = 0;
9773
9774 for (i = 0; i < len; i += 4, offset += 4) {
9775 u32 data, page_off, phy_addr, nvram_cmd;
9776
9777 memcpy(&data, buf + i, 4);
9778 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9779
9780 page_off = offset % tp->nvram_pagesize;
9781
9782 phy_addr = tg3_nvram_phys_addr(tp, offset);
9783
9784 tw32(NVRAM_ADDR, phy_addr);
9785
9786 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9787
9788 if ((page_off == 0) || (i == 0))
9789 nvram_cmd |= NVRAM_CMD_FIRST;
9790 if (page_off == (tp->nvram_pagesize - 4))
9791 nvram_cmd |= NVRAM_CMD_LAST;
9792
9793 if (i == (len - 4))
9794 nvram_cmd |= NVRAM_CMD_LAST;
9795
9796 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9797 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9798 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9799 (tp->nvram_jedecnum == JEDEC_ST) &&
9800 (nvram_cmd & NVRAM_CMD_FIRST)) {
9801
9802 if ((ret = tg3_nvram_exec_cmd(tp,
9803 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9804 NVRAM_CMD_DONE)))
9805
9806 break;
9807 }
9808 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9809 /* We always do complete word writes to eeprom. */
9810 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9811 }
9812
9813 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9814 break;
9815 }
9816 return ret;
9817 }
9818
9819 /* offset and length are dword aligned */
9820 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9821 {
9822 int ret;
9823
9824 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9825 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9826 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9827 udelay(40);
9828 }
9829
9830 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9831 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9832 }
9833 else {
9834 u32 grc_mode;
9835
9836 ret = tg3_nvram_lock(tp);
9837 if (ret)
9838 return ret;
9839
9840 tg3_enable_nvram_access(tp);
9841 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9842 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9843 tw32(NVRAM_WRITE1, 0x406);
9844
9845 grc_mode = tr32(GRC_MODE);
9846 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9847
9848 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9849 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9850
9851 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9852 buf);
9853 }
9854 else {
9855 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9856 buf);
9857 }
9858
9859 grc_mode = tr32(GRC_MODE);
9860 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9861
9862 tg3_disable_nvram_access(tp);
9863 tg3_nvram_unlock(tp);
9864 }
9865
9866 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9867 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9868 udelay(40);
9869 }
9870
9871 return ret;
9872 }
9873
9874 struct subsys_tbl_ent {
9875 u16 subsys_vendor, subsys_devid;
9876 u32 phy_id;
9877 };
9878
9879 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9880 /* Broadcom boards. */
9881 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9882 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9883 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9884 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9885 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9886 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9887 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9888 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9889 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9890 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9891 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9892
9893 /* 3com boards. */
9894 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9895 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9896 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9897 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9898 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9899
9900 /* DELL boards. */
9901 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9902 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9903 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9904 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9905
9906 /* Compaq boards. */
9907 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9908 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9909 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9910 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9911 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9912
9913 /* IBM boards. */
9914 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9915 };
9916
9917 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9918 {
9919 int i;
9920
9921 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9922 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9923 tp->pdev->subsystem_vendor) &&
9924 (subsys_id_to_phy_id[i].subsys_devid ==
9925 tp->pdev->subsystem_device))
9926 return &subsys_id_to_phy_id[i];
9927 }
9928 return NULL;
9929 }
9930
9931 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9932 {
9933 u32 val;
9934 u16 pmcsr;
9935
9936 /* On some early chips the SRAM cannot be accessed in D3hot state,
9937 * so need make sure we're in D0.
9938 */
9939 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9940 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9941 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9942 msleep(1);
9943
9944 /* Make sure register accesses (indirect or otherwise)
9945 * will function correctly.
9946 */
9947 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9948 tp->misc_host_ctrl);
9949
9950 /* The memory arbiter has to be enabled in order for SRAM accesses
9951 * to succeed. Normally on powerup the tg3 chip firmware will make
9952 * sure it is enabled, but other entities such as system netboot
9953 * code might disable it.
9954 */
9955 val = tr32(MEMARB_MODE);
9956 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9957
9958 tp->phy_id = PHY_ID_INVALID;
9959 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9960
9961 /* Assume an onboard device by default. */
9962 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9963
9964 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9965 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM))
9966 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9967 return;
9968 }
9969
9970 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9971 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9972 u32 nic_cfg, led_cfg;
9973 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9974 int eeprom_phy_serdes = 0;
9975
9976 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9977 tp->nic_sram_data_cfg = nic_cfg;
9978
9979 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9980 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9981 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9982 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9983 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9984 (ver > 0) && (ver < 0x100))
9985 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9986
9987 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9988 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9989 eeprom_phy_serdes = 1;
9990
9991 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9992 if (nic_phy_id != 0) {
9993 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9994 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9995
9996 eeprom_phy_id = (id1 >> 16) << 10;
9997 eeprom_phy_id |= (id2 & 0xfc00) << 16;
9998 eeprom_phy_id |= (id2 & 0x03ff) << 0;
9999 } else
10000 eeprom_phy_id = 0;
10001
10002 tp->phy_id = eeprom_phy_id;
10003 if (eeprom_phy_serdes) {
10004 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10005 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10006 else
10007 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10008 }
10009
10010 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10011 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10012 SHASTA_EXT_LED_MODE_MASK);
10013 else
10014 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10015
10016 switch (led_cfg) {
10017 default:
10018 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10019 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10020 break;
10021
10022 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10023 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10024 break;
10025
10026 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10027 tp->led_ctrl = LED_CTRL_MODE_MAC;
10028
10029 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10030 * read on some older 5700/5701 bootcode.
10031 */
10032 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10033 ASIC_REV_5700 ||
10034 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10035 ASIC_REV_5701)
10036 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10037
10038 break;
10039
10040 case SHASTA_EXT_LED_SHARED:
10041 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10042 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10043 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10044 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10045 LED_CTRL_MODE_PHY_2);
10046 break;
10047
10048 case SHASTA_EXT_LED_MAC:
10049 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10050 break;
10051
10052 case SHASTA_EXT_LED_COMBO:
10053 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10054 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10055 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10056 LED_CTRL_MODE_PHY_2);
10057 break;
10058
10059 };
10060
10061 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10063 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10064 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10065
10066 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
10067 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10068 else
10069 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10070
10071 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10072 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10073 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10074 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10075 }
10076 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10077 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10078
10079 if (cfg2 & (1 << 17))
10080 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10081
10082 /* serdes signal pre-emphasis in register 0x590 set by */
10083 /* bootcode if bit 18 is set */
10084 if (cfg2 & (1 << 18))
10085 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10086 }
10087 }
10088
10089 static int __devinit tg3_phy_probe(struct tg3 *tp)
10090 {
10091 u32 hw_phy_id_1, hw_phy_id_2;
10092 u32 hw_phy_id, hw_phy_id_masked;
10093 int err;
10094
10095 /* Reading the PHY ID register can conflict with ASF
10096 * firwmare access to the PHY hardware.
10097 */
10098 err = 0;
10099 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10100 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10101 } else {
10102 /* Now read the physical PHY_ID from the chip and verify
10103 * that it is sane. If it doesn't look good, we fall back
10104 * to either the hard-coded table based PHY_ID and failing
10105 * that the value found in the eeprom area.
10106 */
10107 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10108 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10109
10110 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10111 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10112 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10113
10114 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10115 }
10116
10117 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10118 tp->phy_id = hw_phy_id;
10119 if (hw_phy_id_masked == PHY_ID_BCM8002)
10120 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10121 else
10122 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10123 } else {
10124 if (tp->phy_id != PHY_ID_INVALID) {
10125 /* Do nothing, phy ID already set up in
10126 * tg3_get_eeprom_hw_cfg().
10127 */
10128 } else {
10129 struct subsys_tbl_ent *p;
10130
10131 /* No eeprom signature? Try the hardcoded
10132 * subsys device table.
10133 */
10134 p = lookup_by_subsys(tp);
10135 if (!p)
10136 return -ENODEV;
10137
10138 tp->phy_id = p->phy_id;
10139 if (!tp->phy_id ||
10140 tp->phy_id == PHY_ID_BCM8002)
10141 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10142 }
10143 }
10144
10145 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10146 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10147 u32 bmsr, adv_reg, tg3_ctrl;
10148
10149 tg3_readphy(tp, MII_BMSR, &bmsr);
10150 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10151 (bmsr & BMSR_LSTATUS))
10152 goto skip_phy_reset;
10153
10154 err = tg3_phy_reset(tp);
10155 if (err)
10156 return err;
10157
10158 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10159 ADVERTISE_100HALF | ADVERTISE_100FULL |
10160 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10161 tg3_ctrl = 0;
10162 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10163 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10164 MII_TG3_CTRL_ADV_1000_FULL);
10165 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10166 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10167 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10168 MII_TG3_CTRL_ENABLE_AS_MASTER);
10169 }
10170
10171 if (!tg3_copper_is_advertising_all(tp)) {
10172 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10173
10174 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10175 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10176
10177 tg3_writephy(tp, MII_BMCR,
10178 BMCR_ANENABLE | BMCR_ANRESTART);
10179 }
10180 tg3_phy_set_wirespeed(tp);
10181
10182 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10183 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10184 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10185 }
10186
10187 skip_phy_reset:
10188 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10189 err = tg3_init_5401phy_dsp(tp);
10190 if (err)
10191 return err;
10192 }
10193
10194 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10195 err = tg3_init_5401phy_dsp(tp);
10196 }
10197
10198 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10199 tp->link_config.advertising =
10200 (ADVERTISED_1000baseT_Half |
10201 ADVERTISED_1000baseT_Full |
10202 ADVERTISED_Autoneg |
10203 ADVERTISED_FIBRE);
10204 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10205 tp->link_config.advertising &=
10206 ~(ADVERTISED_1000baseT_Half |
10207 ADVERTISED_1000baseT_Full);
10208
10209 return err;
10210 }
10211
10212 static void __devinit tg3_read_partno(struct tg3 *tp)
10213 {
10214 unsigned char vpd_data[256];
10215 int i;
10216 u32 magic;
10217
10218 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10219 goto out_not_found;
10220
10221 if (magic == TG3_EEPROM_MAGIC) {
10222 for (i = 0; i < 256; i += 4) {
10223 u32 tmp;
10224
10225 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10226 goto out_not_found;
10227
10228 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10229 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10230 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10231 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10232 }
10233 } else {
10234 int vpd_cap;
10235
10236 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10237 for (i = 0; i < 256; i += 4) {
10238 u32 tmp, j = 0;
10239 u16 tmp16;
10240
10241 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10242 i);
10243 while (j++ < 100) {
10244 pci_read_config_word(tp->pdev, vpd_cap +
10245 PCI_VPD_ADDR, &tmp16);
10246 if (tmp16 & 0x8000)
10247 break;
10248 msleep(1);
10249 }
10250 if (!(tmp16 & 0x8000))
10251 goto out_not_found;
10252
10253 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10254 &tmp);
10255 tmp = cpu_to_le32(tmp);
10256 memcpy(&vpd_data[i], &tmp, 4);
10257 }
10258 }
10259
10260 /* Now parse and find the part number. */
10261 for (i = 0; i < 256; ) {
10262 unsigned char val = vpd_data[i];
10263 int block_end;
10264
10265 if (val == 0x82 || val == 0x91) {
10266 i = (i + 3 +
10267 (vpd_data[i + 1] +
10268 (vpd_data[i + 2] << 8)));
10269 continue;
10270 }
10271
10272 if (val != 0x90)
10273 goto out_not_found;
10274
10275 block_end = (i + 3 +
10276 (vpd_data[i + 1] +
10277 (vpd_data[i + 2] << 8)));
10278 i += 3;
10279 while (i < block_end) {
10280 if (vpd_data[i + 0] == 'P' &&
10281 vpd_data[i + 1] == 'N') {
10282 int partno_len = vpd_data[i + 2];
10283
10284 if (partno_len > 24)
10285 goto out_not_found;
10286
10287 memcpy(tp->board_part_number,
10288 &vpd_data[i + 3],
10289 partno_len);
10290
10291 /* Success. */
10292 return;
10293 }
10294 }
10295
10296 /* Part number not found. */
10297 goto out_not_found;
10298 }
10299
10300 out_not_found:
10301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10302 strcpy(tp->board_part_number, "BCM95906");
10303 else
10304 strcpy(tp->board_part_number, "none");
10305 }
10306
10307 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10308 {
10309 u32 val, offset, start;
10310
10311 if (tg3_nvram_read_swab(tp, 0, &val))
10312 return;
10313
10314 if (val != TG3_EEPROM_MAGIC)
10315 return;
10316
10317 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10318 tg3_nvram_read_swab(tp, 0x4, &start))
10319 return;
10320
10321 offset = tg3_nvram_logical_addr(tp, offset);
10322 if (tg3_nvram_read_swab(tp, offset, &val))
10323 return;
10324
10325 if ((val & 0xfc000000) == 0x0c000000) {
10326 u32 ver_offset, addr;
10327 int i;
10328
10329 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10330 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10331 return;
10332
10333 if (val != 0)
10334 return;
10335
10336 addr = offset + ver_offset - start;
10337 for (i = 0; i < 16; i += 4) {
10338 if (tg3_nvram_read(tp, addr + i, &val))
10339 return;
10340
10341 val = cpu_to_le32(val);
10342 memcpy(tp->fw_ver + i, &val, 4);
10343 }
10344 }
10345 }
10346
10347 static int __devinit tg3_get_invariants(struct tg3 *tp)
10348 {
10349 static struct pci_device_id write_reorder_chipsets[] = {
10350 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10351 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10352 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10353 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10354 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10355 PCI_DEVICE_ID_VIA_8385_0) },
10356 { },
10357 };
10358 u32 misc_ctrl_reg;
10359 u32 cacheline_sz_reg;
10360 u32 pci_state_reg, grc_misc_cfg;
10361 u32 val;
10362 u16 pci_cmd;
10363 int err;
10364
10365 /* Force memory write invalidate off. If we leave it on,
10366 * then on 5700_BX chips we have to enable a workaround.
10367 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10368 * to match the cacheline size. The Broadcom driver have this
10369 * workaround but turns MWI off all the times so never uses
10370 * it. This seems to suggest that the workaround is insufficient.
10371 */
10372 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10373 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10374 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10375
10376 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10377 * has the register indirect write enable bit set before
10378 * we try to access any of the MMIO registers. It is also
10379 * critical that the PCI-X hw workaround situation is decided
10380 * before that as well.
10381 */
10382 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10383 &misc_ctrl_reg);
10384
10385 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10386 MISC_HOST_CTRL_CHIPREV_SHIFT);
10387
10388 /* Wrong chip ID in 5752 A0. This code can be removed later
10389 * as A0 is not in production.
10390 */
10391 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10392 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10393
10394 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10395 * we need to disable memory and use config. cycles
10396 * only to access all registers. The 5702/03 chips
10397 * can mistakenly decode the special cycles from the
10398 * ICH chipsets as memory write cycles, causing corruption
10399 * of register and memory space. Only certain ICH bridges
10400 * will drive special cycles with non-zero data during the
10401 * address phase which can fall within the 5703's address
10402 * range. This is not an ICH bug as the PCI spec allows
10403 * non-zero address during special cycles. However, only
10404 * these ICH bridges are known to drive non-zero addresses
10405 * during special cycles.
10406 *
10407 * Since special cycles do not cross PCI bridges, we only
10408 * enable this workaround if the 5703 is on the secondary
10409 * bus of these ICH bridges.
10410 */
10411 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10412 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10413 static struct tg3_dev_id {
10414 u32 vendor;
10415 u32 device;
10416 u32 rev;
10417 } ich_chipsets[] = {
10418 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10419 PCI_ANY_ID },
10420 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10421 PCI_ANY_ID },
10422 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10423 0xa },
10424 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10425 PCI_ANY_ID },
10426 { },
10427 };
10428 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10429 struct pci_dev *bridge = NULL;
10430
10431 while (pci_id->vendor != 0) {
10432 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10433 bridge);
10434 if (!bridge) {
10435 pci_id++;
10436 continue;
10437 }
10438 if (pci_id->rev != PCI_ANY_ID) {
10439 u8 rev;
10440
10441 pci_read_config_byte(bridge, PCI_REVISION_ID,
10442 &rev);
10443 if (rev > pci_id->rev)
10444 continue;
10445 }
10446 if (bridge->subordinate &&
10447 (bridge->subordinate->number ==
10448 tp->pdev->bus->number)) {
10449
10450 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10451 pci_dev_put(bridge);
10452 break;
10453 }
10454 }
10455 }
10456
10457 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10458 * DMA addresses > 40-bit. This bridge may have other additional
10459 * 57xx devices behind it in some 4-port NIC designs for example.
10460 * Any tg3 device found behind the bridge will also need the 40-bit
10461 * DMA workaround.
10462 */
10463 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10464 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10465 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10466 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10467 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10468 }
10469 else {
10470 struct pci_dev *bridge = NULL;
10471
10472 do {
10473 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10474 PCI_DEVICE_ID_SERVERWORKS_EPB,
10475 bridge);
10476 if (bridge && bridge->subordinate &&
10477 (bridge->subordinate->number <=
10478 tp->pdev->bus->number) &&
10479 (bridge->subordinate->subordinate >=
10480 tp->pdev->bus->number)) {
10481 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10482 pci_dev_put(bridge);
10483 break;
10484 }
10485 } while (bridge);
10486 }
10487
10488 /* Initialize misc host control in PCI block. */
10489 tp->misc_host_ctrl |= (misc_ctrl_reg &
10490 MISC_HOST_CTRL_CHIPREV);
10491 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10492 tp->misc_host_ctrl);
10493
10494 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10495 &cacheline_sz_reg);
10496
10497 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10498 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10499 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10500 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10501
10502 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10503 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10504 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10505 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10506 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10507 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10508 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10509
10510 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10511 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10512 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10513
10514 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10516 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10517 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10518 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10519 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10520 } else {
10521 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10522 TG3_FLG2_HW_TSO_1_BUG;
10523 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10524 ASIC_REV_5750 &&
10525 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10526 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10527 }
10528 }
10529
10530 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10531 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10532 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10533 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10534 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10535 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10536 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10537
10538 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
10539 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10540
10541 /* If we have an AMD 762 or VIA K8T800 chipset, write
10542 * reordering to the mailbox registers done by the host
10543 * controller can cause major troubles. We read back from
10544 * every mailbox register write to force the writes to be
10545 * posted to the chip in order.
10546 */
10547 if (pci_dev_present(write_reorder_chipsets) &&
10548 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10549 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10550
10551 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10552 tp->pci_lat_timer < 64) {
10553 tp->pci_lat_timer = 64;
10554
10555 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10556 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10557 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10558 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10559
10560 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10561 cacheline_sz_reg);
10562 }
10563
10564 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10565 &pci_state_reg);
10566
10567 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10568 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10569
10570 /* If this is a 5700 BX chipset, and we are in PCI-X
10571 * mode, enable register write workaround.
10572 *
10573 * The workaround is to use indirect register accesses
10574 * for all chip writes not to mailbox registers.
10575 */
10576 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10577 u32 pm_reg;
10578 u16 pci_cmd;
10579
10580 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10581
10582 /* The chip can have it's power management PCI config
10583 * space registers clobbered due to this bug.
10584 * So explicitly force the chip into D0 here.
10585 */
10586 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10587 &pm_reg);
10588 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10589 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10590 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10591 pm_reg);
10592
10593 /* Also, force SERR#/PERR# in PCI command. */
10594 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10595 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10596 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10597 }
10598 }
10599
10600 /* 5700 BX chips need to have their TX producer index mailboxes
10601 * written twice to workaround a bug.
10602 */
10603 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10604 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10605
10606 /* Back to back register writes can cause problems on this chip,
10607 * the workaround is to read back all reg writes except those to
10608 * mailbox regs. See tg3_write_indirect_reg32().
10609 *
10610 * PCI Express 5750_A0 rev chips need this workaround too.
10611 */
10612 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10613 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10614 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10615 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10616
10617 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10618 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10619 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10620 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10621
10622 /* Chip-specific fixup from Broadcom driver */
10623 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10624 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10625 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10626 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10627 }
10628
10629 /* Default fast path register access methods */
10630 tp->read32 = tg3_read32;
10631 tp->write32 = tg3_write32;
10632 tp->read32_mbox = tg3_read32;
10633 tp->write32_mbox = tg3_write32;
10634 tp->write32_tx_mbox = tg3_write32;
10635 tp->write32_rx_mbox = tg3_write32;
10636
10637 /* Various workaround register access methods */
10638 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10639 tp->write32 = tg3_write_indirect_reg32;
10640 else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10641 tp->write32 = tg3_write_flush_reg32;
10642
10643 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10644 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10645 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10646 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10647 tp->write32_rx_mbox = tg3_write_flush_reg32;
10648 }
10649
10650 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10651 tp->read32 = tg3_read_indirect_reg32;
10652 tp->write32 = tg3_write_indirect_reg32;
10653 tp->read32_mbox = tg3_read_indirect_mbox;
10654 tp->write32_mbox = tg3_write_indirect_mbox;
10655 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10656 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10657
10658 iounmap(tp->regs);
10659 tp->regs = NULL;
10660
10661 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10662 pci_cmd &= ~PCI_COMMAND_MEMORY;
10663 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10664 }
10665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10666 tp->read32_mbox = tg3_read32_mbox_5906;
10667 tp->write32_mbox = tg3_write32_mbox_5906;
10668 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10669 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10670 }
10671
10672 if (tp->write32 == tg3_write_indirect_reg32 ||
10673 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10674 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10675 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10676 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10677
10678 /* Get eeprom hw config before calling tg3_set_power_state().
10679 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
10680 * determined before calling tg3_set_power_state() so that
10681 * we know whether or not to switch out of Vaux power.
10682 * When the flag is set, it means that GPIO1 is used for eeprom
10683 * write protect and also implies that it is a LOM where GPIOs
10684 * are not used to switch power.
10685 */
10686 tg3_get_eeprom_hw_cfg(tp);
10687
10688 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10689 * GPIO1 driven high will bring 5700's external PHY out of reset.
10690 * It is also used as eeprom write protect on LOMs.
10691 */
10692 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10693 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10694 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10695 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10696 GRC_LCLCTRL_GPIO_OUTPUT1);
10697 /* Unused GPIO3 must be driven as output on 5752 because there
10698 * are no pull-up resistors on unused GPIO pins.
10699 */
10700 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10701 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10702
10703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10704 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10705
10706 /* Force the chip into D0. */
10707 err = tg3_set_power_state(tp, PCI_D0);
10708 if (err) {
10709 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10710 pci_name(tp->pdev));
10711 return err;
10712 }
10713
10714 /* 5700 B0 chips do not support checksumming correctly due
10715 * to hardware bugs.
10716 */
10717 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10718 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10719
10720 /* Derive initial jumbo mode from MTU assigned in
10721 * ether_setup() via the alloc_etherdev() call
10722 */
10723 if (tp->dev->mtu > ETH_DATA_LEN &&
10724 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10725 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10726
10727 /* Determine WakeOnLan speed to use. */
10728 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10729 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10730 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10731 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10732 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10733 } else {
10734 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10735 }
10736
10737 /* A few boards don't want Ethernet@WireSpeed phy feature */
10738 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10739 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10740 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10741 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10742 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10743 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10744 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10745
10746 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10747 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10748 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10749 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10750 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10751
10752 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10753 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10754 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10755 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10756 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10757 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10758 }
10759
10760 tp->coalesce_mode = 0;
10761 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10762 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10763 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10764
10765 /* Initialize MAC MI mode, polling disabled. */
10766 tw32_f(MAC_MI_MODE, tp->mi_mode);
10767 udelay(80);
10768
10769 /* Initialize data/descriptor byte/word swapping. */
10770 val = tr32(GRC_MODE);
10771 val &= GRC_MODE_HOST_STACKUP;
10772 tw32(GRC_MODE, val | tp->grc_mode);
10773
10774 tg3_switch_clocks(tp);
10775
10776 /* Clear this out for sanity. */
10777 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10778
10779 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10780 &pci_state_reg);
10781 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10782 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10783 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10784
10785 if (chiprevid == CHIPREV_ID_5701_A0 ||
10786 chiprevid == CHIPREV_ID_5701_B0 ||
10787 chiprevid == CHIPREV_ID_5701_B2 ||
10788 chiprevid == CHIPREV_ID_5701_B5) {
10789 void __iomem *sram_base;
10790
10791 /* Write some dummy words into the SRAM status block
10792 * area, see if it reads back correctly. If the return
10793 * value is bad, force enable the PCIX workaround.
10794 */
10795 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10796
10797 writel(0x00000000, sram_base);
10798 writel(0x00000000, sram_base + 4);
10799 writel(0xffffffff, sram_base + 4);
10800 if (readl(sram_base) != 0x00000000)
10801 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10802 }
10803 }
10804
10805 udelay(50);
10806 tg3_nvram_init(tp);
10807
10808 grc_misc_cfg = tr32(GRC_MISC_CFG);
10809 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10810
10811 /* Broadcom's driver says that CIOBE multisplit has a bug */
10812 #if 0
10813 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10814 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10815 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10816 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10817 }
10818 #endif
10819 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10820 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10821 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10822 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10823
10824 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10825 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10826 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10827 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10828 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10829 HOSTCC_MODE_CLRTICK_TXBD);
10830
10831 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10832 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10833 tp->misc_host_ctrl);
10834 }
10835
10836 /* these are limited to 10/100 only */
10837 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10838 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10839 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10840 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10841 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10842 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10843 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10844 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10845 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10846 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)) ||
10847 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10848 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10849
10850 err = tg3_phy_probe(tp);
10851 if (err) {
10852 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10853 pci_name(tp->pdev), err);
10854 /* ... but do not return immediately ... */
10855 }
10856
10857 tg3_read_partno(tp);
10858 tg3_read_fw_ver(tp);
10859
10860 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10861 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10862 } else {
10863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10864 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10865 else
10866 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10867 }
10868
10869 /* 5700 {AX,BX} chips have a broken status block link
10870 * change bit implementation, so we must use the
10871 * status register in those cases.
10872 */
10873 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10874 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10875 else
10876 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10877
10878 /* The led_ctrl is set during tg3_phy_probe, here we might
10879 * have to force the link status polling mechanism based
10880 * upon subsystem IDs.
10881 */
10882 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10883 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10884 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10885 TG3_FLAG_USE_LINKCHG_REG);
10886 }
10887
10888 /* For all SERDES we poll the MAC status register. */
10889 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10890 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10891 else
10892 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10893
10894 /* All chips before 5787 can get confused if TX buffers
10895 * straddle the 4GB address boundary in some cases.
10896 */
10897 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10899 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10900 tp->dev->hard_start_xmit = tg3_start_xmit;
10901 else
10902 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10903
10904 tp->rx_offset = 2;
10905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10906 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10907 tp->rx_offset = 0;
10908
10909 tp->rx_std_max_post = TG3_RX_RING_SIZE;
10910
10911 /* Increment the rx prod index on the rx std ring by at most
10912 * 8 for these chips to workaround hw errata.
10913 */
10914 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10915 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10916 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10917 tp->rx_std_max_post = 8;
10918
10919 /* By default, disable wake-on-lan. User can change this
10920 * using ETHTOOL_SWOL.
10921 */
10922 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10923
10924 return err;
10925 }
10926
10927 #ifdef CONFIG_SPARC64
10928 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10929 {
10930 struct net_device *dev = tp->dev;
10931 struct pci_dev *pdev = tp->pdev;
10932 struct pcidev_cookie *pcp = pdev->sysdata;
10933
10934 if (pcp != NULL) {
10935 unsigned char *addr;
10936 int len;
10937
10938 addr = of_get_property(pcp->prom_node, "local-mac-address",
10939 &len);
10940 if (addr && len == 6) {
10941 memcpy(dev->dev_addr, addr, 6);
10942 memcpy(dev->perm_addr, dev->dev_addr, 6);
10943 return 0;
10944 }
10945 }
10946 return -ENODEV;
10947 }
10948
10949 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10950 {
10951 struct net_device *dev = tp->dev;
10952
10953 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10954 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10955 return 0;
10956 }
10957 #endif
10958
10959 static int __devinit tg3_get_device_address(struct tg3 *tp)
10960 {
10961 struct net_device *dev = tp->dev;
10962 u32 hi, lo, mac_offset;
10963 int addr_ok = 0;
10964
10965 #ifdef CONFIG_SPARC64
10966 if (!tg3_get_macaddr_sparc(tp))
10967 return 0;
10968 #endif
10969
10970 mac_offset = 0x7c;
10971 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10972 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10973 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10974 mac_offset = 0xcc;
10975 if (tg3_nvram_lock(tp))
10976 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
10977 else
10978 tg3_nvram_unlock(tp);
10979 }
10980 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10981 mac_offset = 0x10;
10982
10983 /* First try to get it from MAC address mailbox. */
10984 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
10985 if ((hi >> 16) == 0x484b) {
10986 dev->dev_addr[0] = (hi >> 8) & 0xff;
10987 dev->dev_addr[1] = (hi >> 0) & 0xff;
10988
10989 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
10990 dev->dev_addr[2] = (lo >> 24) & 0xff;
10991 dev->dev_addr[3] = (lo >> 16) & 0xff;
10992 dev->dev_addr[4] = (lo >> 8) & 0xff;
10993 dev->dev_addr[5] = (lo >> 0) & 0xff;
10994
10995 /* Some old bootcode may report a 0 MAC address in SRAM */
10996 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
10997 }
10998 if (!addr_ok) {
10999 /* Next, try NVRAM. */
11000 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11001 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11002 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11003 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11004 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11005 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11006 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11007 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11008 }
11009 /* Finally just fetch it out of the MAC control regs. */
11010 else {
11011 hi = tr32(MAC_ADDR_0_HIGH);
11012 lo = tr32(MAC_ADDR_0_LOW);
11013
11014 dev->dev_addr[5] = lo & 0xff;
11015 dev->dev_addr[4] = (lo >> 8) & 0xff;
11016 dev->dev_addr[3] = (lo >> 16) & 0xff;
11017 dev->dev_addr[2] = (lo >> 24) & 0xff;
11018 dev->dev_addr[1] = hi & 0xff;
11019 dev->dev_addr[0] = (hi >> 8) & 0xff;
11020 }
11021 }
11022
11023 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11024 #ifdef CONFIG_SPARC64
11025 if (!tg3_get_default_macaddr_sparc(tp))
11026 return 0;
11027 #endif
11028 return -EINVAL;
11029 }
11030 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11031 return 0;
11032 }
11033
11034 #define BOUNDARY_SINGLE_CACHELINE 1
11035 #define BOUNDARY_MULTI_CACHELINE 2
11036
11037 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11038 {
11039 int cacheline_size;
11040 u8 byte;
11041 int goal;
11042
11043 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11044 if (byte == 0)
11045 cacheline_size = 1024;
11046 else
11047 cacheline_size = (int) byte * 4;
11048
11049 /* On 5703 and later chips, the boundary bits have no
11050 * effect.
11051 */
11052 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11053 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11054 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11055 goto out;
11056
11057 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11058 goal = BOUNDARY_MULTI_CACHELINE;
11059 #else
11060 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11061 goal = BOUNDARY_SINGLE_CACHELINE;
11062 #else
11063 goal = 0;
11064 #endif
11065 #endif
11066
11067 if (!goal)
11068 goto out;
11069
11070 /* PCI controllers on most RISC systems tend to disconnect
11071 * when a device tries to burst across a cache-line boundary.
11072 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11073 *
11074 * Unfortunately, for PCI-E there are only limited
11075 * write-side controls for this, and thus for reads
11076 * we will still get the disconnects. We'll also waste
11077 * these PCI cycles for both read and write for chips
11078 * other than 5700 and 5701 which do not implement the
11079 * boundary bits.
11080 */
11081 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11082 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11083 switch (cacheline_size) {
11084 case 16:
11085 case 32:
11086 case 64:
11087 case 128:
11088 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11089 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11090 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11091 } else {
11092 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11093 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11094 }
11095 break;
11096
11097 case 256:
11098 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11099 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11100 break;
11101
11102 default:
11103 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11104 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11105 break;
11106 };
11107 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11108 switch (cacheline_size) {
11109 case 16:
11110 case 32:
11111 case 64:
11112 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11113 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11114 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11115 break;
11116 }
11117 /* fallthrough */
11118 case 128:
11119 default:
11120 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11121 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11122 break;
11123 };
11124 } else {
11125 switch (cacheline_size) {
11126 case 16:
11127 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11128 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11129 DMA_RWCTRL_WRITE_BNDRY_16);
11130 break;
11131 }
11132 /* fallthrough */
11133 case 32:
11134 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11135 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11136 DMA_RWCTRL_WRITE_BNDRY_32);
11137 break;
11138 }
11139 /* fallthrough */
11140 case 64:
11141 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11142 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11143 DMA_RWCTRL_WRITE_BNDRY_64);
11144 break;
11145 }
11146 /* fallthrough */
11147 case 128:
11148 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11149 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11150 DMA_RWCTRL_WRITE_BNDRY_128);
11151 break;
11152 }
11153 /* fallthrough */
11154 case 256:
11155 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11156 DMA_RWCTRL_WRITE_BNDRY_256);
11157 break;
11158 case 512:
11159 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11160 DMA_RWCTRL_WRITE_BNDRY_512);
11161 break;
11162 case 1024:
11163 default:
11164 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11165 DMA_RWCTRL_WRITE_BNDRY_1024);
11166 break;
11167 };
11168 }
11169
11170 out:
11171 return val;
11172 }
11173
11174 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11175 {
11176 struct tg3_internal_buffer_desc test_desc;
11177 u32 sram_dma_descs;
11178 int i, ret;
11179
11180 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11181
11182 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11183 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11184 tw32(RDMAC_STATUS, 0);
11185 tw32(WDMAC_STATUS, 0);
11186
11187 tw32(BUFMGR_MODE, 0);
11188 tw32(FTQ_RESET, 0);
11189
11190 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11191 test_desc.addr_lo = buf_dma & 0xffffffff;
11192 test_desc.nic_mbuf = 0x00002100;
11193 test_desc.len = size;
11194
11195 /*
11196 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11197 * the *second* time the tg3 driver was getting loaded after an
11198 * initial scan.
11199 *
11200 * Broadcom tells me:
11201 * ...the DMA engine is connected to the GRC block and a DMA
11202 * reset may affect the GRC block in some unpredictable way...
11203 * The behavior of resets to individual blocks has not been tested.
11204 *
11205 * Broadcom noted the GRC reset will also reset all sub-components.
11206 */
11207 if (to_device) {
11208 test_desc.cqid_sqid = (13 << 8) | 2;
11209
11210 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11211 udelay(40);
11212 } else {
11213 test_desc.cqid_sqid = (16 << 8) | 7;
11214
11215 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11216 udelay(40);
11217 }
11218 test_desc.flags = 0x00000005;
11219
11220 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11221 u32 val;
11222
11223 val = *(((u32 *)&test_desc) + i);
11224 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11225 sram_dma_descs + (i * sizeof(u32)));
11226 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11227 }
11228 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11229
11230 if (to_device) {
11231 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11232 } else {
11233 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11234 }
11235
11236 ret = -ENODEV;
11237 for (i = 0; i < 40; i++) {
11238 u32 val;
11239
11240 if (to_device)
11241 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11242 else
11243 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11244 if ((val & 0xffff) == sram_dma_descs) {
11245 ret = 0;
11246 break;
11247 }
11248
11249 udelay(100);
11250 }
11251
11252 return ret;
11253 }
11254
11255 #define TEST_BUFFER_SIZE 0x2000
11256
11257 static int __devinit tg3_test_dma(struct tg3 *tp)
11258 {
11259 dma_addr_t buf_dma;
11260 u32 *buf, saved_dma_rwctrl;
11261 int ret;
11262
11263 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11264 if (!buf) {
11265 ret = -ENOMEM;
11266 goto out_nofree;
11267 }
11268
11269 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11270 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11271
11272 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11273
11274 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11275 /* DMA read watermark not used on PCIE */
11276 tp->dma_rwctrl |= 0x00180000;
11277 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11278 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11279 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11280 tp->dma_rwctrl |= 0x003f0000;
11281 else
11282 tp->dma_rwctrl |= 0x003f000f;
11283 } else {
11284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11286 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11287
11288 /* If the 5704 is behind the EPB bridge, we can
11289 * do the less restrictive ONE_DMA workaround for
11290 * better performance.
11291 */
11292 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11293 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11294 tp->dma_rwctrl |= 0x8000;
11295 else if (ccval == 0x6 || ccval == 0x7)
11296 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11297
11298 /* Set bit 23 to enable PCIX hw bug fix */
11299 tp->dma_rwctrl |= 0x009f0000;
11300 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11301 /* 5780 always in PCIX mode */
11302 tp->dma_rwctrl |= 0x00144000;
11303 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11304 /* 5714 always in PCIX mode */
11305 tp->dma_rwctrl |= 0x00148000;
11306 } else {
11307 tp->dma_rwctrl |= 0x001b000f;
11308 }
11309 }
11310
11311 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11313 tp->dma_rwctrl &= 0xfffffff0;
11314
11315 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11316 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11317 /* Remove this if it causes problems for some boards. */
11318 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11319
11320 /* On 5700/5701 chips, we need to set this bit.
11321 * Otherwise the chip will issue cacheline transactions
11322 * to streamable DMA memory with not all the byte
11323 * enables turned on. This is an error on several
11324 * RISC PCI controllers, in particular sparc64.
11325 *
11326 * On 5703/5704 chips, this bit has been reassigned
11327 * a different meaning. In particular, it is used
11328 * on those chips to enable a PCI-X workaround.
11329 */
11330 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11331 }
11332
11333 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11334
11335 #if 0
11336 /* Unneeded, already done by tg3_get_invariants. */
11337 tg3_switch_clocks(tp);
11338 #endif
11339
11340 ret = 0;
11341 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11342 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11343 goto out;
11344
11345 /* It is best to perform DMA test with maximum write burst size
11346 * to expose the 5700/5701 write DMA bug.
11347 */
11348 saved_dma_rwctrl = tp->dma_rwctrl;
11349 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11350 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11351
11352 while (1) {
11353 u32 *p = buf, i;
11354
11355 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11356 p[i] = i;
11357
11358 /* Send the buffer to the chip. */
11359 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11360 if (ret) {
11361 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11362 break;
11363 }
11364
11365 #if 0
11366 /* validate data reached card RAM correctly. */
11367 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11368 u32 val;
11369 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11370 if (le32_to_cpu(val) != p[i]) {
11371 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11372 /* ret = -ENODEV here? */
11373 }
11374 p[i] = 0;
11375 }
11376 #endif
11377 /* Now read it back. */
11378 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11379 if (ret) {
11380 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11381
11382 break;
11383 }
11384
11385 /* Verify it. */
11386 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11387 if (p[i] == i)
11388 continue;
11389
11390 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11391 DMA_RWCTRL_WRITE_BNDRY_16) {
11392 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11393 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11394 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11395 break;
11396 } else {
11397 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11398 ret = -ENODEV;
11399 goto out;
11400 }
11401 }
11402
11403 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11404 /* Success. */
11405 ret = 0;
11406 break;
11407 }
11408 }
11409 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11410 DMA_RWCTRL_WRITE_BNDRY_16) {
11411 static struct pci_device_id dma_wait_state_chipsets[] = {
11412 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11413 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11414 { },
11415 };
11416
11417 /* DMA test passed without adjusting DMA boundary,
11418 * now look for chipsets that are known to expose the
11419 * DMA bug without failing the test.
11420 */
11421 if (pci_dev_present(dma_wait_state_chipsets)) {
11422 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11423 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11424 }
11425 else
11426 /* Safe to use the calculated DMA boundary. */
11427 tp->dma_rwctrl = saved_dma_rwctrl;
11428
11429 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11430 }
11431
11432 out:
11433 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11434 out_nofree:
11435 return ret;
11436 }
11437
11438 static void __devinit tg3_init_link_config(struct tg3 *tp)
11439 {
11440 tp->link_config.advertising =
11441 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11442 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11443 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11444 ADVERTISED_Autoneg | ADVERTISED_MII);
11445 tp->link_config.speed = SPEED_INVALID;
11446 tp->link_config.duplex = DUPLEX_INVALID;
11447 tp->link_config.autoneg = AUTONEG_ENABLE;
11448 tp->link_config.active_speed = SPEED_INVALID;
11449 tp->link_config.active_duplex = DUPLEX_INVALID;
11450 tp->link_config.phy_is_low_power = 0;
11451 tp->link_config.orig_speed = SPEED_INVALID;
11452 tp->link_config.orig_duplex = DUPLEX_INVALID;
11453 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11454 }
11455
11456 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11457 {
11458 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11459 tp->bufmgr_config.mbuf_read_dma_low_water =
11460 DEFAULT_MB_RDMA_LOW_WATER_5705;
11461 tp->bufmgr_config.mbuf_mac_rx_low_water =
11462 DEFAULT_MB_MACRX_LOW_WATER_5705;
11463 tp->bufmgr_config.mbuf_high_water =
11464 DEFAULT_MB_HIGH_WATER_5705;
11465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11466 tp->bufmgr_config.mbuf_mac_rx_low_water =
11467 DEFAULT_MB_MACRX_LOW_WATER_5906;
11468 tp->bufmgr_config.mbuf_high_water =
11469 DEFAULT_MB_HIGH_WATER_5906;
11470 }
11471
11472 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11473 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11474 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11475 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11476 tp->bufmgr_config.mbuf_high_water_jumbo =
11477 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11478 } else {
11479 tp->bufmgr_config.mbuf_read_dma_low_water =
11480 DEFAULT_MB_RDMA_LOW_WATER;
11481 tp->bufmgr_config.mbuf_mac_rx_low_water =
11482 DEFAULT_MB_MACRX_LOW_WATER;
11483 tp->bufmgr_config.mbuf_high_water =
11484 DEFAULT_MB_HIGH_WATER;
11485
11486 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11487 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11488 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11489 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11490 tp->bufmgr_config.mbuf_high_water_jumbo =
11491 DEFAULT_MB_HIGH_WATER_JUMBO;
11492 }
11493
11494 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11495 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11496 }
11497
11498 static char * __devinit tg3_phy_string(struct tg3 *tp)
11499 {
11500 switch (tp->phy_id & PHY_ID_MASK) {
11501 case PHY_ID_BCM5400: return "5400";
11502 case PHY_ID_BCM5401: return "5401";
11503 case PHY_ID_BCM5411: return "5411";
11504 case PHY_ID_BCM5701: return "5701";
11505 case PHY_ID_BCM5703: return "5703";
11506 case PHY_ID_BCM5704: return "5704";
11507 case PHY_ID_BCM5705: return "5705";
11508 case PHY_ID_BCM5750: return "5750";
11509 case PHY_ID_BCM5752: return "5752";
11510 case PHY_ID_BCM5714: return "5714";
11511 case PHY_ID_BCM5780: return "5780";
11512 case PHY_ID_BCM5755: return "5755";
11513 case PHY_ID_BCM5787: return "5787";
11514 case PHY_ID_BCM5756: return "5722/5756";
11515 case PHY_ID_BCM5906: return "5906";
11516 case PHY_ID_BCM8002: return "8002/serdes";
11517 case 0: return "serdes";
11518 default: return "unknown";
11519 };
11520 }
11521
11522 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11523 {
11524 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11525 strcpy(str, "PCI Express");
11526 return str;
11527 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11528 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11529
11530 strcpy(str, "PCIX:");
11531
11532 if ((clock_ctrl == 7) ||
11533 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11534 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11535 strcat(str, "133MHz");
11536 else if (clock_ctrl == 0)
11537 strcat(str, "33MHz");
11538 else if (clock_ctrl == 2)
11539 strcat(str, "50MHz");
11540 else if (clock_ctrl == 4)
11541 strcat(str, "66MHz");
11542 else if (clock_ctrl == 6)
11543 strcat(str, "100MHz");
11544 } else {
11545 strcpy(str, "PCI:");
11546 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11547 strcat(str, "66MHz");
11548 else
11549 strcat(str, "33MHz");
11550 }
11551 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11552 strcat(str, ":32-bit");
11553 else
11554 strcat(str, ":64-bit");
11555 return str;
11556 }
11557
11558 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11559 {
11560 struct pci_dev *peer;
11561 unsigned int func, devnr = tp->pdev->devfn & ~7;
11562
11563 for (func = 0; func < 8; func++) {
11564 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11565 if (peer && peer != tp->pdev)
11566 break;
11567 pci_dev_put(peer);
11568 }
11569 /* 5704 can be configured in single-port mode, set peer to
11570 * tp->pdev in that case.
11571 */
11572 if (!peer) {
11573 peer = tp->pdev;
11574 return peer;
11575 }
11576
11577 /*
11578 * We don't need to keep the refcount elevated; there's no way
11579 * to remove one half of this device without removing the other
11580 */
11581 pci_dev_put(peer);
11582
11583 return peer;
11584 }
11585
11586 static void __devinit tg3_init_coal(struct tg3 *tp)
11587 {
11588 struct ethtool_coalesce *ec = &tp->coal;
11589
11590 memset(ec, 0, sizeof(*ec));
11591 ec->cmd = ETHTOOL_GCOALESCE;
11592 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11593 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11594 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11595 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11596 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11597 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11598 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11599 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11600 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11601
11602 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11603 HOSTCC_MODE_CLRTICK_TXBD)) {
11604 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11605 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11606 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11607 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11608 }
11609
11610 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11611 ec->rx_coalesce_usecs_irq = 0;
11612 ec->tx_coalesce_usecs_irq = 0;
11613 ec->stats_block_coalesce_usecs = 0;
11614 }
11615 }
11616
11617 static int __devinit tg3_init_one(struct pci_dev *pdev,
11618 const struct pci_device_id *ent)
11619 {
11620 static int tg3_version_printed = 0;
11621 unsigned long tg3reg_base, tg3reg_len;
11622 struct net_device *dev;
11623 struct tg3 *tp;
11624 int i, err, pm_cap;
11625 char str[40];
11626 u64 dma_mask, persist_dma_mask;
11627
11628 if (tg3_version_printed++ == 0)
11629 printk(KERN_INFO "%s", version);
11630
11631 err = pci_enable_device(pdev);
11632 if (err) {
11633 printk(KERN_ERR PFX "Cannot enable PCI device, "
11634 "aborting.\n");
11635 return err;
11636 }
11637
11638 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11639 printk(KERN_ERR PFX "Cannot find proper PCI device "
11640 "base address, aborting.\n");
11641 err = -ENODEV;
11642 goto err_out_disable_pdev;
11643 }
11644
11645 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11646 if (err) {
11647 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11648 "aborting.\n");
11649 goto err_out_disable_pdev;
11650 }
11651
11652 pci_set_master(pdev);
11653
11654 /* Find power-management capability. */
11655 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11656 if (pm_cap == 0) {
11657 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11658 "aborting.\n");
11659 err = -EIO;
11660 goto err_out_free_res;
11661 }
11662
11663 tg3reg_base = pci_resource_start(pdev, 0);
11664 tg3reg_len = pci_resource_len(pdev, 0);
11665
11666 dev = alloc_etherdev(sizeof(*tp));
11667 if (!dev) {
11668 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11669 err = -ENOMEM;
11670 goto err_out_free_res;
11671 }
11672
11673 SET_MODULE_OWNER(dev);
11674 SET_NETDEV_DEV(dev, &pdev->dev);
11675
11676 #if TG3_VLAN_TAG_USED
11677 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11678 dev->vlan_rx_register = tg3_vlan_rx_register;
11679 dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11680 #endif
11681
11682 tp = netdev_priv(dev);
11683 tp->pdev = pdev;
11684 tp->dev = dev;
11685 tp->pm_cap = pm_cap;
11686 tp->mac_mode = TG3_DEF_MAC_MODE;
11687 tp->rx_mode = TG3_DEF_RX_MODE;
11688 tp->tx_mode = TG3_DEF_TX_MODE;
11689 tp->mi_mode = MAC_MI_MODE_BASE;
11690 if (tg3_debug > 0)
11691 tp->msg_enable = tg3_debug;
11692 else
11693 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11694
11695 /* The word/byte swap controls here control register access byte
11696 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11697 * setting below.
11698 */
11699 tp->misc_host_ctrl =
11700 MISC_HOST_CTRL_MASK_PCI_INT |
11701 MISC_HOST_CTRL_WORD_SWAP |
11702 MISC_HOST_CTRL_INDIR_ACCESS |
11703 MISC_HOST_CTRL_PCISTATE_RW;
11704
11705 /* The NONFRM (non-frame) byte/word swap controls take effect
11706 * on descriptor entries, anything which isn't packet data.
11707 *
11708 * The StrongARM chips on the board (one for tx, one for rx)
11709 * are running in big-endian mode.
11710 */
11711 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11712 GRC_MODE_WSWAP_NONFRM_DATA);
11713 #ifdef __BIG_ENDIAN
11714 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11715 #endif
11716 spin_lock_init(&tp->lock);
11717 spin_lock_init(&tp->indirect_lock);
11718 INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
11719
11720 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11721 if (tp->regs == 0UL) {
11722 printk(KERN_ERR PFX "Cannot map device registers, "
11723 "aborting.\n");
11724 err = -ENOMEM;
11725 goto err_out_free_dev;
11726 }
11727
11728 tg3_init_link_config(tp);
11729
11730 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11731 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11732 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11733
11734 dev->open = tg3_open;
11735 dev->stop = tg3_close;
11736 dev->get_stats = tg3_get_stats;
11737 dev->set_multicast_list = tg3_set_rx_mode;
11738 dev->set_mac_address = tg3_set_mac_addr;
11739 dev->do_ioctl = tg3_ioctl;
11740 dev->tx_timeout = tg3_tx_timeout;
11741 dev->poll = tg3_poll;
11742 dev->ethtool_ops = &tg3_ethtool_ops;
11743 dev->weight = 64;
11744 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11745 dev->change_mtu = tg3_change_mtu;
11746 dev->irq = pdev->irq;
11747 #ifdef CONFIG_NET_POLL_CONTROLLER
11748 dev->poll_controller = tg3_poll_controller;
11749 #endif
11750
11751 err = tg3_get_invariants(tp);
11752 if (err) {
11753 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11754 "aborting.\n");
11755 goto err_out_iounmap;
11756 }
11757
11758 /* The EPB bridge inside 5714, 5715, and 5780 and any
11759 * device behind the EPB cannot support DMA addresses > 40-bit.
11760 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11761 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11762 * do DMA address check in tg3_start_xmit().
11763 */
11764 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11765 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11766 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11767 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11768 #ifdef CONFIG_HIGHMEM
11769 dma_mask = DMA_64BIT_MASK;
11770 #endif
11771 } else
11772 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11773
11774 /* Configure DMA attributes. */
11775 if (dma_mask > DMA_32BIT_MASK) {
11776 err = pci_set_dma_mask(pdev, dma_mask);
11777 if (!err) {
11778 dev->features |= NETIF_F_HIGHDMA;
11779 err = pci_set_consistent_dma_mask(pdev,
11780 persist_dma_mask);
11781 if (err < 0) {
11782 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11783 "DMA for consistent allocations\n");
11784 goto err_out_iounmap;
11785 }
11786 }
11787 }
11788 if (err || dma_mask == DMA_32BIT_MASK) {
11789 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11790 if (err) {
11791 printk(KERN_ERR PFX "No usable DMA configuration, "
11792 "aborting.\n");
11793 goto err_out_iounmap;
11794 }
11795 }
11796
11797 tg3_init_bufmgr_config(tp);
11798
11799 #if TG3_TSO_SUPPORT != 0
11800 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11801 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11802 }
11803 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11804 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11805 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11806 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11807 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11808 } else {
11809 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11810 }
11811
11812 /* TSO is on by default on chips that support hardware TSO.
11813 * Firmware TSO on older chips gives lower performance, so it
11814 * is off by default, but can be enabled using ethtool.
11815 */
11816 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11817 dev->features |= NETIF_F_TSO;
11818 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11819 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11820 dev->features |= NETIF_F_TSO6;
11821 }
11822
11823 #endif
11824
11825 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11826 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11827 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11828 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11829 tp->rx_pending = 63;
11830 }
11831
11832 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11833 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11834 tp->pdev_peer = tg3_find_peer(tp);
11835
11836 err = tg3_get_device_address(tp);
11837 if (err) {
11838 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11839 "aborting.\n");
11840 goto err_out_iounmap;
11841 }
11842
11843 /*
11844 * Reset chip in case UNDI or EFI driver did not shutdown
11845 * DMA self test will enable WDMAC and we'll see (spurious)
11846 * pending DMA on the PCI bus at that point.
11847 */
11848 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11849 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11850 pci_save_state(tp->pdev);
11851 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11852 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11853 }
11854
11855 err = tg3_test_dma(tp);
11856 if (err) {
11857 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11858 goto err_out_iounmap;
11859 }
11860
11861 /* Tigon3 can do ipv4 only... and some chips have buggy
11862 * checksumming.
11863 */
11864 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11867 dev->features |= NETIF_F_HW_CSUM;
11868 else
11869 dev->features |= NETIF_F_IP_CSUM;
11870 dev->features |= NETIF_F_SG;
11871 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11872 } else
11873 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11874
11875 /* flow control autonegotiation is default behavior */
11876 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11877
11878 tg3_init_coal(tp);
11879
11880 /* Now that we have fully setup the chip, save away a snapshot
11881 * of the PCI config space. We need to restore this after
11882 * GRC_MISC_CFG core clock resets and some resume events.
11883 */
11884 pci_save_state(tp->pdev);
11885
11886 err = register_netdev(dev);
11887 if (err) {
11888 printk(KERN_ERR PFX "Cannot register net device, "
11889 "aborting.\n");
11890 goto err_out_iounmap;
11891 }
11892
11893 pci_set_drvdata(pdev, dev);
11894
11895 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11896 dev->name,
11897 tp->board_part_number,
11898 tp->pci_chip_rev_id,
11899 tg3_phy_string(tp),
11900 tg3_bus_string(tp, str),
11901 (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11902
11903 for (i = 0; i < 6; i++)
11904 printk("%2.2x%c", dev->dev_addr[i],
11905 i == 5 ? '\n' : ':');
11906
11907 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11908 "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11909 "TSOcap[%d] \n",
11910 dev->name,
11911 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11912 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11913 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11914 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11915 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11916 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11917 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11918 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11919 dev->name, tp->dma_rwctrl,
11920 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11921 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11922
11923 netif_carrier_off(tp->dev);
11924
11925 return 0;
11926
11927 err_out_iounmap:
11928 if (tp->regs) {
11929 iounmap(tp->regs);
11930 tp->regs = NULL;
11931 }
11932
11933 err_out_free_dev:
11934 free_netdev(dev);
11935
11936 err_out_free_res:
11937 pci_release_regions(pdev);
11938
11939 err_out_disable_pdev:
11940 pci_disable_device(pdev);
11941 pci_set_drvdata(pdev, NULL);
11942 return err;
11943 }
11944
11945 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11946 {
11947 struct net_device *dev = pci_get_drvdata(pdev);
11948
11949 if (dev) {
11950 struct tg3 *tp = netdev_priv(dev);
11951
11952 flush_scheduled_work();
11953 unregister_netdev(dev);
11954 if (tp->regs) {
11955 iounmap(tp->regs);
11956 tp->regs = NULL;
11957 }
11958 free_netdev(dev);
11959 pci_release_regions(pdev);
11960 pci_disable_device(pdev);
11961 pci_set_drvdata(pdev, NULL);
11962 }
11963 }
11964
11965 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
11966 {
11967 struct net_device *dev = pci_get_drvdata(pdev);
11968 struct tg3 *tp = netdev_priv(dev);
11969 int err;
11970
11971 if (!netif_running(dev))
11972 return 0;
11973
11974 flush_scheduled_work();
11975 tg3_netif_stop(tp);
11976
11977 del_timer_sync(&tp->timer);
11978
11979 tg3_full_lock(tp, 1);
11980 tg3_disable_ints(tp);
11981 tg3_full_unlock(tp);
11982
11983 netif_device_detach(dev);
11984
11985 tg3_full_lock(tp, 0);
11986 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11987 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
11988 tg3_full_unlock(tp);
11989
11990 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
11991 if (err) {
11992 tg3_full_lock(tp, 0);
11993
11994 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11995 if (tg3_restart_hw(tp, 1))
11996 goto out;
11997
11998 tp->timer.expires = jiffies + tp->timer_offset;
11999 add_timer(&tp->timer);
12000
12001 netif_device_attach(dev);
12002 tg3_netif_start(tp);
12003
12004 out:
12005 tg3_full_unlock(tp);
12006 }
12007
12008 return err;
12009 }
12010
12011 static int tg3_resume(struct pci_dev *pdev)
12012 {
12013 struct net_device *dev = pci_get_drvdata(pdev);
12014 struct tg3 *tp = netdev_priv(dev);
12015 int err;
12016
12017 if (!netif_running(dev))
12018 return 0;
12019
12020 pci_restore_state(tp->pdev);
12021
12022 err = tg3_set_power_state(tp, PCI_D0);
12023 if (err)
12024 return err;
12025
12026 netif_device_attach(dev);
12027
12028 tg3_full_lock(tp, 0);
12029
12030 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12031 err = tg3_restart_hw(tp, 1);
12032 if (err)
12033 goto out;
12034
12035 tp->timer.expires = jiffies + tp->timer_offset;
12036 add_timer(&tp->timer);
12037
12038 tg3_netif_start(tp);
12039
12040 out:
12041 tg3_full_unlock(tp);
12042
12043 return err;
12044 }
12045
12046 static struct pci_driver tg3_driver = {
12047 .name = DRV_MODULE_NAME,
12048 .id_table = tg3_pci_tbl,
12049 .probe = tg3_init_one,
12050 .remove = __devexit_p(tg3_remove_one),
12051 .suspend = tg3_suspend,
12052 .resume = tg3_resume
12053 };
12054
12055 static int __init tg3_init(void)
12056 {
12057 return pci_register_driver(&tg3_driver);
12058 }
12059
12060 static void __exit tg3_cleanup(void)
12061 {
12062 pci_unregister_driver(&tg3_driver);
12063 }
12064
12065 module_init(tg3_init);
12066 module_exit(tg3_cleanup);
Support for the Chinese Samsung S3C2440 based development boards