2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
33 #include <asm/atomic.h>
36 #include <asm/mpspec.h>
38 #include <asm/arch_hooks.h>
40 #include <asm/i8253.h>
43 #include <mach_apic.h>
44 #include <mach_apicdef.h>
52 #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
53 # error SPURIOUS_APIC_VECTOR definition error
57 * Knob to control our willingness to enable the local APIC.
59 * -1=force-disable, +1=force-enable
61 static int enable_local_apic __initdata
= 0;
63 /* Local APIC timer verification ok */
64 static int local_apic_timer_verify_ok
;
65 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
66 static int local_apic_timer_disabled
;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok
;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
72 * Debug level, exported for io_apic.c
76 static unsigned int calibration_result
;
78 static int lapic_next_event(unsigned long delta
,
79 struct clock_event_device
*evt
);
80 static void lapic_timer_setup(enum clock_event_mode mode
,
81 struct clock_event_device
*evt
);
82 static void lapic_timer_broadcast(cpumask_t mask
);
83 static void apic_pm_activate(void);
86 * The local apic timer can be used for any function which is CPU local.
88 static struct clock_event_device lapic_clockevent
= {
90 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
91 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
93 .set_mode
= lapic_timer_setup
,
94 .set_next_event
= lapic_next_event
,
95 .broadcast
= lapic_timer_broadcast
,
99 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
101 /* Local APIC was disabled by the BIOS and enabled by the kernel */
102 static int enabled_via_apicbase
;
105 * Get the LAPIC version
107 static inline int lapic_get_version(void)
109 return GET_APIC_VERSION(apic_read(APIC_LVR
));
113 * Check, if the APIC is integrated or a seperate chip
115 static inline int lapic_is_integrated(void)
117 return APIC_INTEGRATED(lapic_get_version());
121 * Check, whether this is a modern or a first generation APIC
123 static int modern_apic(void)
125 /* AMD systems use old APIC versions, so check the CPU */
126 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
127 boot_cpu_data
.x86
>= 0xf)
129 return lapic_get_version() >= 0x14;
133 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
135 void enable_NMI_through_LVT0 (void * dummy
)
137 unsigned int v
= APIC_DM_NMI
;
139 /* Level triggered for 82489DX */
140 if (!lapic_is_integrated())
141 v
|= APIC_LVT_LEVEL_TRIGGER
;
142 apic_write_around(APIC_LVT0
, v
);
146 * get_physical_broadcast - Get number of physical broadcast IDs
148 int get_physical_broadcast(void)
150 return modern_apic() ? 0xff : 0xf;
154 * lapic_get_maxlvt - get the maximum number of local vector table entries
156 int lapic_get_maxlvt(void)
158 unsigned int v
= apic_read(APIC_LVR
);
160 /* 82489DXs do not report # of LVT entries. */
161 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
168 /* Clock divisor is set to 16 */
169 #define APIC_DIVISOR 16
172 * This function sets up the local APIC timer, with a timeout of
173 * 'clocks' APIC bus clock. During calibration we actually call
174 * this function twice on the boot CPU, once with a bogus timeout
175 * value, second time for real. The other (noncalibrating) CPUs
176 * call this function only once, with the real, calibrated value.
178 * We do reads before writes even if unnecessary, to get around the
179 * P5 APIC double write bug.
181 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
183 unsigned int lvtt_value
, tmp_value
;
185 lvtt_value
= LOCAL_TIMER_VECTOR
;
187 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
188 if (!lapic_is_integrated())
189 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
192 lvtt_value
|= APIC_LVT_MASKED
;
194 apic_write_around(APIC_LVTT
, lvtt_value
);
199 tmp_value
= apic_read(APIC_TDCR
);
200 apic_write_around(APIC_TDCR
, (tmp_value
201 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
205 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
209 * Program the next event, relative to now
211 static int lapic_next_event(unsigned long delta
,
212 struct clock_event_device
*evt
)
214 apic_write_around(APIC_TMICT
, delta
);
219 * Setup the lapic timer in periodic or oneshot mode
221 static void lapic_timer_setup(enum clock_event_mode mode
,
222 struct clock_event_device
*evt
)
227 /* Lapic used for broadcast ? */
228 if (!local_apic_timer_verify_ok
)
231 local_irq_save(flags
);
234 case CLOCK_EVT_MODE_PERIODIC
:
235 case CLOCK_EVT_MODE_ONESHOT
:
236 __setup_APIC_LVTT(calibration_result
,
237 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
239 case CLOCK_EVT_MODE_UNUSED
:
240 case CLOCK_EVT_MODE_SHUTDOWN
:
241 v
= apic_read(APIC_LVTT
);
242 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
243 apic_write_around(APIC_LVTT
, v
);
247 local_irq_restore(flags
);
251 * Local APIC timer broadcast function
253 static void lapic_timer_broadcast(cpumask_t mask
)
256 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
261 * Setup the local APIC timer for this CPU. Copy the initilized values
262 * of the boot CPU and register the clock event in the framework.
264 static void __devinit
setup_APIC_timer(void)
266 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
268 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
269 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
271 clockevents_register_device(levt
);
275 * In this functions we calibrate APIC bus clocks to the external timer.
277 * We want to do the calibration only once since we want to have local timer
278 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
281 * This was previously done by reading the PIT/HPET and waiting for a wrap
282 * around to find out, that a tick has elapsed. I have a box, where the PIT
283 * readout is broken, so it never gets out of the wait loop again. This was
284 * also reported by others.
286 * Monitoring the jiffies value is inaccurate and the clockevents
287 * infrastructure allows us to do a simple substitution of the interrupt
290 * The calibration routine also uses the pm_timer when possible, as the PIT
291 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
292 * back to normal later in the boot process).
295 #define LAPIC_CAL_LOOPS (HZ/10)
297 static __initdata
volatile int lapic_cal_loops
= -1;
298 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
299 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
300 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
301 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
304 * Temporary interrupt handler.
306 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
308 unsigned long long tsc
= 0;
309 long tapic
= apic_read(APIC_TMCCT
);
310 unsigned long pm
= acpi_pm_read_early();
315 switch (lapic_cal_loops
++) {
317 lapic_cal_t1
= tapic
;
318 lapic_cal_tsc1
= tsc
;
320 lapic_cal_j1
= jiffies
;
323 case LAPIC_CAL_LOOPS
:
324 lapic_cal_t2
= tapic
;
325 lapic_cal_tsc2
= tsc
;
326 if (pm
< lapic_cal_pm1
)
327 pm
+= ACPI_PM_OVRRUN
;
329 lapic_cal_j2
= jiffies
;
335 * Setup the boot APIC
337 * Calibrate and verify the result.
339 void __init
setup_boot_APIC_clock(void)
341 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
342 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
343 const long pm_thresh
= pm_100ms
/100;
344 void (*real_handler
)(struct clock_event_device
*dev
);
345 unsigned long deltaj
;
347 int pm_referenced
= 0;
349 if (boot_cpu_has(X86_FEATURE_LAPIC_TIMER_BROKEN
))
350 local_apic_timer_disabled
= 1;
353 * The local apic timer can be disabled via the kernel
354 * commandline or from the test above. Register the lapic
355 * timer as a dummy clock event source on SMP systems, so the
356 * broadcast mechanism is used. On UP systems simply ignore it.
358 if (local_apic_timer_disabled
) {
359 /* No broadcast on UP ! */
360 if (num_possible_cpus() > 1)
365 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
366 "calibrating APIC timer ...\n");
370 /* Replace the global interrupt handler */
371 real_handler
= global_clock_event
->event_handler
;
372 global_clock_event
->event_handler
= lapic_cal_handler
;
375 * Setup the APIC counter to 1e9. There is no way the lapic
376 * can underflow in the 100ms detection time frame
378 __setup_APIC_LVTT(1000000000, 0, 0);
380 /* Let the interrupts run */
383 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
388 /* Restore the real event handler */
389 global_clock_event
->event_handler
= real_handler
;
391 /* Build delta t1-t2 as apic timer counts down */
392 delta
= lapic_cal_t1
- lapic_cal_t2
;
393 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
395 /* Check, if the PM timer is available */
396 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
397 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
403 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
405 if (deltapm
> (pm_100ms
- pm_thresh
) &&
406 deltapm
< (pm_100ms
+ pm_thresh
)) {
407 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
409 res
= (((u64
) deltapm
) * mult
) >> 22;
410 do_div(res
, 1000000);
411 printk(KERN_WARNING
"APIC calibration not consistent "
412 "with PM Timer: %ldms instead of 100ms\n",
414 /* Correct the lapic counter value */
415 res
= (((u64
) delta
) * pm_100ms
);
416 do_div(res
, deltapm
);
417 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
418 "%lu (%ld)\n", (unsigned long) res
, delta
);
424 /* Calculate the scaled math multiplication factor */
425 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
, 32);
426 lapic_clockevent
.max_delta_ns
=
427 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
428 lapic_clockevent
.min_delta_ns
=
429 clockevent_delta2ns(0xF, &lapic_clockevent
);
431 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
433 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
434 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
435 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
439 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
440 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
442 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
443 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
446 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
448 calibration_result
/ (1000000 / HZ
),
449 calibration_result
% (1000000 / HZ
));
451 local_apic_timer_verify_ok
= 1;
453 /* We trust the pm timer based calibration */
454 if (!pm_referenced
) {
455 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
458 * Setup the apic timer manually
460 levt
->event_handler
= lapic_cal_handler
;
461 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
462 lapic_cal_loops
= -1;
464 /* Let the interrupts run */
467 while(lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
472 /* Stop the lapic timer */
473 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
478 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
479 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
481 /* Check, if the jiffies result is consistent */
482 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
483 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
485 local_apic_timer_verify_ok
= 0;
489 if (!local_apic_timer_verify_ok
) {
491 "APIC timer disabled due to verification failure.\n");
492 /* No broadcast on UP ! */
493 if (num_possible_cpus() == 1)
497 * If nmi_watchdog is set to IO_APIC, we need the
498 * PIT/HPET going. Otherwise register lapic as a dummy
501 if (nmi_watchdog
!= NMI_IO_APIC
)
502 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
505 /* Setup the lapic or request the broadcast */
509 void __devinit
setup_secondary_APIC_clock(void)
515 * The guts of the apic timer interrupt
517 static void local_apic_timer_interrupt(void)
519 int cpu
= smp_processor_id();
520 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
523 * Normally we should not be here till LAPIC has been initialized but
524 * in some cases like kdump, its possible that there is a pending LAPIC
525 * timer interrupt from previous kernel's context and is delivered in
526 * new kernel the moment interrupts are enabled.
528 * Interrupts are enabled early and LAPIC is setup much later, hence
529 * its possible that when we get here evt->event_handler is NULL.
530 * Check for event_handler being NULL and discard the interrupt as
533 if (!evt
->event_handler
) {
535 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
537 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
541 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
543 evt
->event_handler(evt
);
547 * Local APIC timer interrupt. This is the most natural way for doing
548 * local interrupts, but local timer interrupts can be emulated by
549 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
551 * [ if a single-CPU system runs an SMP kernel then we call the local
552 * interrupt as well. Thus we cannot inline the local irq ... ]
555 void fastcall
smp_apic_timer_interrupt(struct pt_regs
*regs
)
557 struct pt_regs
*old_regs
= set_irq_regs(regs
);
560 * NOTE! We'd better ACK the irq immediately,
561 * because timer handling can be slow.
565 * update_process_times() expects us to have done irq_enter().
566 * Besides, if we don't timer interrupts ignore the global
567 * interrupt lock, which is the WrongThing (tm) to do.
570 local_apic_timer_interrupt();
573 set_irq_regs(old_regs
);
576 int setup_profiling_timer(unsigned int multiplier
)
582 * Local APIC start and shutdown
586 * clear_local_APIC - shutdown the local APIC
588 * This is called, when a CPU is disabled and before rebooting, so the state of
589 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
590 * leftovers during boot.
592 void clear_local_APIC(void)
594 int maxlvt
= lapic_get_maxlvt();
598 * Masking an LVT entry can trigger a local APIC error
599 * if the vector is zero. Mask LVTERR first to prevent this.
602 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
603 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
606 * Careful: we have to set masks only first to deassert
607 * any level-triggered sources.
609 v
= apic_read(APIC_LVTT
);
610 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
611 v
= apic_read(APIC_LVT0
);
612 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
613 v
= apic_read(APIC_LVT1
);
614 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
616 v
= apic_read(APIC_LVTPC
);
617 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
620 /* lets not touch this if we didn't frob it */
621 #ifdef CONFIG_X86_MCE_P4THERMAL
623 v
= apic_read(APIC_LVTTHMR
);
624 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
628 * Clean APIC state for other OSs:
630 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
631 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
632 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
634 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
636 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
638 #ifdef CONFIG_X86_MCE_P4THERMAL
640 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
642 /* Integrated APIC (!82489DX) ? */
643 if (lapic_is_integrated()) {
645 /* Clear ESR due to Pentium errata 3AP and 11AP */
646 apic_write(APIC_ESR
, 0);
652 * disable_local_APIC - clear and disable the local APIC
654 void disable_local_APIC(void)
661 * Disable APIC (implies clearing of registers
664 value
= apic_read(APIC_SPIV
);
665 value
&= ~APIC_SPIV_APIC_ENABLED
;
666 apic_write_around(APIC_SPIV
, value
);
669 * When LAPIC was disabled by the BIOS and enabled by the kernel,
670 * restore the disabled state.
672 if (enabled_via_apicbase
) {
675 rdmsr(MSR_IA32_APICBASE
, l
, h
);
676 l
&= ~MSR_IA32_APICBASE_ENABLE
;
677 wrmsr(MSR_IA32_APICBASE
, l
, h
);
682 * If Linux enabled the LAPIC against the BIOS default disable it down before
683 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
684 * not power-off. Additionally clear all LVT entries before disable_local_APIC
685 * for the case where Linux didn't enable the LAPIC.
687 void lapic_shutdown(void)
694 local_irq_save(flags
);
697 if (enabled_via_apicbase
)
698 disable_local_APIC();
700 local_irq_restore(flags
);
704 * This is to verify that we're looking at a real local APIC.
705 * Check these against your board if the CPUs aren't getting
706 * started for no apparent reason.
708 int __init
verify_local_APIC(void)
710 unsigned int reg0
, reg1
;
713 * The version register is read-only in a real APIC.
715 reg0
= apic_read(APIC_LVR
);
716 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
717 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
718 reg1
= apic_read(APIC_LVR
);
719 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
722 * The two version reads above should print the same
723 * numbers. If the second one is different, then we
724 * poke at a non-APIC.
730 * Check if the version looks reasonably.
732 reg1
= GET_APIC_VERSION(reg0
);
733 if (reg1
== 0x00 || reg1
== 0xff)
735 reg1
= lapic_get_maxlvt();
736 if (reg1
< 0x02 || reg1
== 0xff)
740 * The ID register is read/write in a real APIC.
742 reg0
= apic_read(APIC_ID
);
743 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
746 * The next two are just to see if we have sane values.
747 * They're only really relevant if we're in Virtual Wire
748 * compatibility mode, but most boxes are anymore.
750 reg0
= apic_read(APIC_LVT0
);
751 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
752 reg1
= apic_read(APIC_LVT1
);
753 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
759 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
761 void __init
sync_Arb_IDs(void)
764 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
772 apic_wait_icr_idle();
774 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
775 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
780 * An initial setup of the virtual wire mode.
782 void __init
init_bsp_APIC(void)
787 * Don't do the setup now if we have a SMP BIOS as the
788 * through-I/O-APIC virtual wire mode might be active.
790 if (smp_found_config
|| !cpu_has_apic
)
794 * Do not trust the local APIC being empty at bootup.
801 value
= apic_read(APIC_SPIV
);
802 value
&= ~APIC_VECTOR_MASK
;
803 value
|= APIC_SPIV_APIC_ENABLED
;
805 /* This bit is reserved on P4/Xeon and should be cleared */
806 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
807 (boot_cpu_data
.x86
== 15))
808 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
810 value
|= APIC_SPIV_FOCUS_DISABLED
;
811 value
|= SPURIOUS_APIC_VECTOR
;
812 apic_write_around(APIC_SPIV
, value
);
815 * Set up the virtual wire mode.
817 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
819 if (!lapic_is_integrated()) /* 82489DX */
820 value
|= APIC_LVT_LEVEL_TRIGGER
;
821 apic_write_around(APIC_LVT1
, value
);
825 * setup_local_APIC - setup the local APIC
827 void __devinit
setup_local_APIC(void)
829 unsigned long oldvalue
, value
, maxlvt
, integrated
;
832 /* Pound the ESR really hard over the head with a big hammer - mbligh */
834 apic_write(APIC_ESR
, 0);
835 apic_write(APIC_ESR
, 0);
836 apic_write(APIC_ESR
, 0);
837 apic_write(APIC_ESR
, 0);
840 integrated
= lapic_is_integrated();
843 * Double-check whether this APIC is really registered.
845 if (!apic_id_registered())
849 * Intel recommends to set DFR, LDR and TPR before enabling
850 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
851 * document number 292116). So here it goes...
856 * Set Task Priority to 'accept all'. We never change this
859 value
= apic_read(APIC_TASKPRI
);
860 value
&= ~APIC_TPRI_MASK
;
861 apic_write_around(APIC_TASKPRI
, value
);
864 * After a crash, we no longer service the interrupts and a pending
865 * interrupt from previous kernel might still have ISR bit set.
867 * Most probably by now CPU has serviced that pending interrupt and
868 * it might not have done the ack_APIC_irq() because it thought,
869 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
870 * does not clear the ISR bit and cpu thinks it has already serivced
871 * the interrupt. Hence a vector might get locked. It was noticed
872 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
874 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
875 value
= apic_read(APIC_ISR
+ i
*0x10);
876 for (j
= 31; j
>= 0; j
--) {
883 * Now that we are all set up, enable the APIC
885 value
= apic_read(APIC_SPIV
);
886 value
&= ~APIC_VECTOR_MASK
;
890 value
|= APIC_SPIV_APIC_ENABLED
;
893 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
894 * certain networking cards. If high frequency interrupts are
895 * happening on a particular IOAPIC pin, plus the IOAPIC routing
896 * entry is masked/unmasked at a high rate as well then sooner or
897 * later IOAPIC line gets 'stuck', no more interrupts are received
898 * from the device. If focus CPU is disabled then the hang goes
901 * [ This bug can be reproduced easily with a level-triggered
902 * PCI Ne2000 networking cards and PII/PIII processors, dual
906 * Actually disabling the focus CPU check just makes the hang less
907 * frequent as it makes the interrupt distributon model be more
908 * like LRU than MRU (the short-term load is more even across CPUs).
909 * See also the comment in end_level_ioapic_irq(). --macro
912 /* Enable focus processor (bit==0) */
913 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
916 * Set spurious IRQ vector
918 value
|= SPURIOUS_APIC_VECTOR
;
919 apic_write_around(APIC_SPIV
, value
);
924 * set up through-local-APIC on the BP's LINT0. This is not
925 * strictly necessery in pure symmetric-IO mode, but sometimes
926 * we delegate interrupts to the 8259A.
929 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
931 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
932 if (!smp_processor_id() && (pic_mode
|| !value
)) {
933 value
= APIC_DM_EXTINT
;
934 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
937 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
938 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
941 apic_write_around(APIC_LVT0
, value
);
944 * only the BP should see the LINT1 NMI signal, obviously.
946 if (!smp_processor_id())
949 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
950 if (!integrated
) /* 82489DX */
951 value
|= APIC_LVT_LEVEL_TRIGGER
;
952 apic_write_around(APIC_LVT1
, value
);
954 if (integrated
&& !esr_disable
) { /* !82489DX */
955 maxlvt
= lapic_get_maxlvt();
956 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
957 apic_write(APIC_ESR
, 0);
958 oldvalue
= apic_read(APIC_ESR
);
960 /* enables sending errors */
961 value
= ERROR_APIC_VECTOR
;
962 apic_write_around(APIC_LVTERR
, value
);
964 * spec says clear errors after enabling vector.
967 apic_write(APIC_ESR
, 0);
968 value
= apic_read(APIC_ESR
);
969 if (value
!= oldvalue
)
970 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
971 "vector: 0x%08lx after: 0x%08lx\n",
976 * Something untraceble is creating bad interrupts on
977 * secondary quads ... for the moment, just leave the
978 * ESR disabled - we can't do anything useful with the
979 * errors anyway - mbligh
981 printk(KERN_INFO
"Leaving ESR disabled.\n");
983 printk(KERN_INFO
"No ESR for 82489DX.\n");
986 /* Disable the local apic timer */
987 value
= apic_read(APIC_LVTT
);
988 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
989 apic_write_around(APIC_LVTT
, value
);
991 setup_apic_nmi_watchdog(NULL
);
996 * Detect and initialize APIC
998 static int __init
detect_init_APIC (void)
1002 /* Disabled by kernel option? */
1003 if (enable_local_apic
< 0)
1006 switch (boot_cpu_data
.x86_vendor
) {
1007 case X86_VENDOR_AMD
:
1008 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1009 (boot_cpu_data
.x86
== 15))
1012 case X86_VENDOR_INTEL
:
1013 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1014 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1021 if (!cpu_has_apic
) {
1023 * Over-ride BIOS and try to enable the local APIC only if
1024 * "lapic" specified.
1026 if (enable_local_apic
<= 0) {
1027 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1028 "you can enable it with \"lapic\"\n");
1032 * Some BIOSes disable the local APIC in the APIC_BASE
1033 * MSR. This can only be done in software for Intel P6 or later
1034 * and AMD K7 (Model > 1) or later.
1036 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1037 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1039 "Local APIC disabled by BIOS -- reenabling.\n");
1040 l
&= ~MSR_IA32_APICBASE_BASE
;
1041 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1042 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1043 enabled_via_apicbase
= 1;
1047 * The APIC feature bit should now be enabled
1050 features
= cpuid_edx(1);
1051 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1052 printk(KERN_WARNING
"Could not enable APIC!\n");
1055 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1056 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1058 /* The BIOS may have set up the APIC at some other address */
1059 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1060 if (l
& MSR_IA32_APICBASE_ENABLE
)
1061 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1063 if (nmi_watchdog
!= NMI_NONE
)
1064 nmi_watchdog
= NMI_LOCAL_APIC
;
1066 printk(KERN_INFO
"Found and enabled local APIC!\n");
1073 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1078 * init_apic_mappings - initialize APIC mappings
1080 void __init
init_apic_mappings(void)
1082 unsigned long apic_phys
;
1085 * If no local APIC can be found then set up a fake all
1086 * zeroes page to simulate the local APIC and another
1087 * one for the IO-APIC.
1089 if (!smp_found_config
&& detect_init_APIC()) {
1090 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1091 apic_phys
= __pa(apic_phys
);
1093 apic_phys
= mp_lapic_addr
;
1095 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1096 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1100 * Fetch the APIC ID of the BSP in case we have a
1101 * default configuration (or the MP table is broken).
1103 if (boot_cpu_physical_apicid
== -1U)
1104 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1106 #ifdef CONFIG_X86_IO_APIC
1108 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
1111 for (i
= 0; i
< nr_ioapics
; i
++) {
1112 if (smp_found_config
) {
1113 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
1116 "WARNING: bogus zero IO-APIC "
1117 "address found in MPTABLE, "
1118 "disabling IO/APIC support!\n");
1119 smp_found_config
= 0;
1120 skip_ioapic_setup
= 1;
1121 goto fake_ioapic_page
;
1125 ioapic_phys
= (unsigned long)
1126 alloc_bootmem_pages(PAGE_SIZE
);
1127 ioapic_phys
= __pa(ioapic_phys
);
1129 set_fixmap_nocache(idx
, ioapic_phys
);
1130 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
1131 __fix_to_virt(idx
), ioapic_phys
);
1139 * This initializes the IO-APIC and APIC hardware if this is
1142 int __init
APIC_init_uniprocessor (void)
1144 if (enable_local_apic
< 0)
1145 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1147 if (!smp_found_config
&& !cpu_has_apic
)
1151 * Complain if the BIOS pretends there is one.
1153 if (!cpu_has_apic
&&
1154 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1155 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1156 boot_cpu_physical_apicid
);
1157 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1161 verify_local_APIC();
1166 * Hack: In case of kdump, after a crash, kernel might be booting
1167 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1168 * might be zero if read from MP tables. Get it from LAPIC.
1170 #ifdef CONFIG_CRASH_DUMP
1171 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1173 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1177 #ifdef CONFIG_X86_IO_APIC
1178 if (smp_found_config
)
1179 if (!skip_ioapic_setup
&& nr_ioapics
)
1188 * APIC command line parameters
1190 static int __init
parse_lapic(char *arg
)
1192 enable_local_apic
= 1;
1195 early_param("lapic", parse_lapic
);
1197 static int __init
parse_nolapic(char *arg
)
1199 enable_local_apic
= -1;
1200 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1203 early_param("nolapic", parse_nolapic
);
1205 static int __init
parse_disable_lapic_timer(char *arg
)
1207 local_apic_timer_disabled
= 1;
1210 early_param("nolapic_timer", parse_disable_lapic_timer
);
1212 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1214 local_apic_timer_c2_ok
= 1;
1217 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1219 static int __init
apic_set_verbosity(char *str
)
1221 if (strcmp("debug", str
) == 0)
1222 apic_verbosity
= APIC_DEBUG
;
1223 else if (strcmp("verbose", str
) == 0)
1224 apic_verbosity
= APIC_VERBOSE
;
1228 __setup("apic=", apic_set_verbosity
);
1232 * Local APIC interrupts
1236 * This interrupt should _never_ happen with our APIC/SMP architecture
1238 void smp_spurious_interrupt(struct pt_regs
*regs
)
1244 * Check if this really is a spurious interrupt and ACK it
1245 * if it is a vectored one. Just in case...
1246 * Spurious interrupts should not be ACKed.
1248 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1249 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1252 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1253 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1254 "should never happen.\n", smp_processor_id());
1259 * This interrupt should never happen with our APIC/SMP architecture
1261 void smp_error_interrupt(struct pt_regs
*regs
)
1263 unsigned long v
, v1
;
1266 /* First tickle the hardware, only then report what went on. -- REW */
1267 v
= apic_read(APIC_ESR
);
1268 apic_write(APIC_ESR
, 0);
1269 v1
= apic_read(APIC_ESR
);
1271 atomic_inc(&irq_err_count
);
1273 /* Here is what the APIC error bits mean:
1276 2: Send accept error
1277 3: Receive accept error
1279 5: Send illegal vector
1280 6: Received illegal vector
1281 7: Illegal register address
1283 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1284 smp_processor_id(), v
, v1
);
1289 * Initialize APIC interrupts
1291 void __init
apic_intr_init(void)
1296 /* self generated IPI for local APIC timer */
1297 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1299 /* IPI vectors for APIC spurious and error interrupts */
1300 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1301 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1303 /* thermal monitor LVT interrupt */
1304 #ifdef CONFIG_X86_MCE_P4THERMAL
1305 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1310 * connect_bsp_APIC - attach the APIC to the interrupt system
1312 void __init
connect_bsp_APIC(void)
1316 * Do not trust the local APIC being empty at bootup.
1320 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1321 * local APIC to INT and NMI lines.
1323 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1324 "enabling APIC mode.\n");
1332 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1333 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1335 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1338 void disconnect_bsp_APIC(int virt_wire_setup
)
1342 * Put the board back into PIC mode (has an effect only on
1343 * certain older boards). Note that APIC interrupts, including
1344 * IPIs, won't work beyond this point! The only exception are
1347 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1348 "entering PIC mode.\n");
1352 /* Go back to Virtual Wire compatibility mode */
1353 unsigned long value
;
1355 /* For the spurious interrupt use vector F, and enable it */
1356 value
= apic_read(APIC_SPIV
);
1357 value
&= ~APIC_VECTOR_MASK
;
1358 value
|= APIC_SPIV_APIC_ENABLED
;
1360 apic_write_around(APIC_SPIV
, value
);
1362 if (!virt_wire_setup
) {
1364 * For LVT0 make it edge triggered, active high,
1365 * external and enabled
1367 value
= apic_read(APIC_LVT0
);
1368 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1369 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1370 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1371 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1372 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1373 apic_write_around(APIC_LVT0
, value
);
1376 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1380 * For LVT1 make it edge triggered, active high, nmi and
1383 value
= apic_read(APIC_LVT1
);
1385 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1386 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1387 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1388 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1389 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1390 apic_write_around(APIC_LVT1
, value
);
1401 /* r/w apic fields */
1402 unsigned int apic_id
;
1403 unsigned int apic_taskpri
;
1404 unsigned int apic_ldr
;
1405 unsigned int apic_dfr
;
1406 unsigned int apic_spiv
;
1407 unsigned int apic_lvtt
;
1408 unsigned int apic_lvtpc
;
1409 unsigned int apic_lvt0
;
1410 unsigned int apic_lvt1
;
1411 unsigned int apic_lvterr
;
1412 unsigned int apic_tmict
;
1413 unsigned int apic_tdcr
;
1414 unsigned int apic_thmr
;
1417 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1419 unsigned long flags
;
1422 if (!apic_pm_state
.active
)
1425 maxlvt
= lapic_get_maxlvt();
1427 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1428 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1429 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1430 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1431 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1432 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1434 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1435 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1436 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1437 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1438 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1439 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1440 #ifdef CONFIG_X86_MCE_P4THERMAL
1442 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1445 local_irq_save(flags
);
1446 disable_local_APIC();
1447 local_irq_restore(flags
);
1451 static int lapic_resume(struct sys_device
*dev
)
1454 unsigned long flags
;
1457 if (!apic_pm_state
.active
)
1460 maxlvt
= lapic_get_maxlvt();
1462 local_irq_save(flags
);
1465 * Make sure the APICBASE points to the right address
1467 * FIXME! This will be wrong if we ever support suspend on
1468 * SMP! We'll need to do this as part of the CPU restore!
1470 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1471 l
&= ~MSR_IA32_APICBASE_BASE
;
1472 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1473 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1475 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1476 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1477 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1478 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1479 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1480 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1481 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1482 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1483 #ifdef CONFIG_X86_MCE_P4THERMAL
1485 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1488 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1489 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1490 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1491 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1492 apic_write(APIC_ESR
, 0);
1493 apic_read(APIC_ESR
);
1494 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1495 apic_write(APIC_ESR
, 0);
1496 apic_read(APIC_ESR
);
1497 local_irq_restore(flags
);
1502 * This device has no shutdown method - fully functioning local APICs
1503 * are needed on every CPU up until machine_halt/restart/poweroff.
1506 static struct sysdev_class lapic_sysclass
= {
1507 set_kset_name("lapic"),
1508 .resume
= lapic_resume
,
1509 .suspend
= lapic_suspend
,
1512 static struct sys_device device_lapic
= {
1514 .cls
= &lapic_sysclass
,
1517 static void __devinit
apic_pm_activate(void)
1519 apic_pm_state
.active
= 1;
1522 static int __init
init_lapic_sysfs(void)
1528 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1530 error
= sysdev_class_register(&lapic_sysclass
);
1532 error
= sysdev_register(&device_lapic
);
1535 device_initcall(init_lapic_sysfs
);
1537 #else /* CONFIG_PM */
1539 static void apic_pm_activate(void) { }
1541 #endif /* CONFIG_PM */