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Kconfig: Typos in net/sched/Kconfig
[linux-2.6/mini2440.git] / sound / pci / rme32.c
blob2cb9fe98db2f51f43ba2bbe1ba51c929f9d1c667
1 /*
2 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3 *
4 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5 * Pilo Chambert <pilo.c@wanadoo.fr>
6 *
7 * Thanks to : Anders Torger <torger@ludd.luth.se>,
8 * Henk Hesselink <henk@anda.nl>
9 * for writing the digi96-driver
10 * and RME for all informations.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * ****************************************************************************
28 *
29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
30 *
31 * Identical soundcards by Sek'd were labeled:
32 * RME Digi 32 = Sek'd Prodif 32
33 * RME Digi 32 Pro = Sek'd Prodif 96
34 * RME Digi 32/8 = Sek'd Prodif Gold
35 *
36 * ****************************************************************************
37 *
38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
39 *
40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41 * in this mode. Rec data and play data are using the same buffer therefore. At
42 * first you have got the playing bits in the buffer and then (after playing
43 * them) they were overwitten by the captured sound of the CS8412/14. Both
44 * modes (play/record) are running harmonically hand in hand in the same buffer
45 * and you have only one start bit plus one interrupt bit to control this
46 * paired action.
47 * This is opposite to the latter rme96 where playing and capturing is totally
48 * separated and so their full duplex mode is supported by alsa (using two
49 * start bits and two interrupts for two different buffers).
50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
52 * able to solve it. Are you motivated enough to solve this problem now? Your
53 * patch would be welcome!
54 *
55 * ****************************************************************************
56 *
57 * "The story after the long seeking" -- tiwai
58 *
59 * Ok, the situation regarding the full duplex is now improved a bit.
60 * In the fullduplex mode (given by the module parameter), the hardware buffer
61 * is split to halves for read and write directions at the DMA pointer.
62 * That is, the half above the current DMA pointer is used for write, and
63 * the half below is used for read. To mangle this strange behavior, an
64 * software intermediate buffer is introduced. This is, of course, not good
65 * from the viewpoint of the data transfer efficiency. However, this allows
66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67 *
68 * ****************************************************************************
69 */
70
71
72 #include <sound/driver.h>
73 #include <linux/delay.h>
74 #include <linux/init.h>
75 #include <linux/interrupt.h>
76 #include <linux/pci.h>
77 #include <linux/slab.h>
78 #include <linux/moduleparam.h>
79
80 #include <sound/core.h>
81 #include <sound/info.h>
82 #include <sound/control.h>
83 #include <sound/pcm.h>
84 #include <sound/pcm_params.h>
85 #include <sound/pcm-indirect.h>
86 #include <sound/asoundef.h>
87 #include <sound/initval.h>
88
89 #include <asm/io.h>
90
91 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
92 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
93 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
94 static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
95
96 module_param_array(index, int, NULL, 0444);
97 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
98 module_param_array(id, charp, NULL, 0444);
99 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
100 module_param_array(enable, bool, NULL, 0444);
101 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
102 module_param_array(fullduplex, bool, NULL, 0444);
103 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
104 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
105 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
106 MODULE_LICENSE("GPL");
107 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
108
109 /* Defines for RME Digi32 series */
110 #define RME32_SPDIF_NCHANNELS 2
111
112 /* Playback and capture buffer size */
113 #define RME32_BUFFER_SIZE 0x20000
114
115 /* IO area size */
116 #define RME32_IO_SIZE 0x30000
117
118 /* IO area offsets */
119 #define RME32_IO_DATA_BUFFER 0x0
120 #define RME32_IO_CONTROL_REGISTER 0x20000
121 #define RME32_IO_GET_POS 0x20000
122 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
123 #define RME32_IO_RESET_POS 0x20100
124
125 /* Write control register bits */
126 #define RME32_WCR_START (1 << 0) /* startbit */
127 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
128 Setting the whole card to mono
129 doesn't seem to be very useful.
130 A software-solution can handle
131 full-duplex with one direction in
132 stereo and the other way in mono.
133 So, the hardware should work all
134 the time in stereo! */
135 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
136 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
137 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
138 #define RME32_WCR_FREQ_1 (1 << 5)
139 #define RME32_WCR_INP_0 (1 << 6) /* input switch */
140 #define RME32_WCR_INP_1 (1 << 7)
141 #define RME32_WCR_RESET (1 << 8) /* Reset address */
142 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
143 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
144 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
145 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
146 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
147 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
148 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
149
150 #define RME32_WCR_BITPOS_FREQ_0 4
151 #define RME32_WCR_BITPOS_FREQ_1 5
152 #define RME32_WCR_BITPOS_INP_0 6
153 #define RME32_WCR_BITPOS_INP_1 7
154
155 /* Read control register bits */
156 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
157 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
158 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
159 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
160 #define RME32_RCR_FREQ_1 (1 << 28)
161 #define RME32_RCR_FREQ_2 (1 << 29)
162 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
163 #define RME32_RCR_IRQ (1 << 31) /* interrupt */
164
165 #define RME32_RCR_BITPOS_F0 27
166 #define RME32_RCR_BITPOS_F1 28
167 #define RME32_RCR_BITPOS_F2 29
168
169 /* Input types */
170 #define RME32_INPUT_OPTICAL 0
171 #define RME32_INPUT_COAXIAL 1
172 #define RME32_INPUT_INTERNAL 2
173 #define RME32_INPUT_XLR 3
174
175 /* Clock modes */
176 #define RME32_CLOCKMODE_SLAVE 0
177 #define RME32_CLOCKMODE_MASTER_32 1
178 #define RME32_CLOCKMODE_MASTER_44 2
179 #define RME32_CLOCKMODE_MASTER_48 3
180
181 /* Block sizes in bytes */
182 #define RME32_BLOCK_SIZE 8192
183
184 /* Software intermediate buffer (max) size */
185 #define RME32_MID_BUFFER_SIZE (1024*1024)
186
187 /* Hardware revisions */
188 #define RME32_32_REVISION 192
189 #define RME32_328_REVISION_OLD 100
190 #define RME32_328_REVISION_NEW 101
191 #define RME32_PRO_REVISION_WITH_8412 192
192 #define RME32_PRO_REVISION_WITH_8414 150
193
194
195 struct rme32 {
196 spinlock_t lock;
197 int irq;
198 unsigned long port;
199 void __iomem *iobase;
200
201 u32 wcreg; /* cached write control register value */
202 u32 wcreg_spdif; /* S/PDIF setup */
203 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
204 u32 rcreg; /* cached read control register value */
205
206 u8 rev; /* card revision number */
207
208 struct snd_pcm_substream *playback_substream;
209 struct snd_pcm_substream *capture_substream;
210
211 int playback_frlog; /* log2 of framesize */
212 int capture_frlog;
213
214 size_t playback_periodsize; /* in bytes, zero if not used */
215 size_t capture_periodsize; /* in bytes, zero if not used */
216
217 unsigned int fullduplex_mode;
218 int running;
219
220 struct snd_pcm_indirect playback_pcm;
221 struct snd_pcm_indirect capture_pcm;
222
223 struct snd_card *card;
224 struct snd_pcm *spdif_pcm;
225 struct snd_pcm *adat_pcm;
226 struct pci_dev *pci;
227 struct snd_kcontrol *spdif_ctl;
228 };
229
230 static struct pci_device_id snd_rme32_ids[] __devinitdata = {
231 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
233 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
235 {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
237 {0,}
238 };
239
240 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
241
242 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
243 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
244
245 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
246
247 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
248
249 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
250
251 static void snd_rme32_proc_init(struct rme32 * rme32);
252
253 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
254
255 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
256 {
257 return (readl(rme32->iobase + RME32_IO_GET_POS)
258 & RME32_RCR_AUDIO_ADDR_MASK);
259 }
260
261 static int snd_rme32_ratecode(int rate)
262 {
263 switch (rate) {
264 case 32000: return SNDRV_PCM_RATE_32000;
265 case 44100: return SNDRV_PCM_RATE_44100;
266 case 48000: return SNDRV_PCM_RATE_48000;
267 case 64000: return SNDRV_PCM_RATE_64000;
268 case 88200: return SNDRV_PCM_RATE_88200;
269 case 96000: return SNDRV_PCM_RATE_96000;
270 }
271 return 0;
272 }
273
274 /* silence callback for halfduplex mode */
275 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
276 snd_pcm_uframes_t pos,
277 snd_pcm_uframes_t count)
278 {
279 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
280 count <<= rme32->playback_frlog;
281 pos <<= rme32->playback_frlog;
282 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
283 return 0;
284 }
285
286 /* copy callback for halfduplex mode */
287 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
288 snd_pcm_uframes_t pos,
289 void __user *src, snd_pcm_uframes_t count)
290 {
291 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
292 count <<= rme32->playback_frlog;
293 pos <<= rme32->playback_frlog;
294 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
295 src, count))
296 return -EFAULT;
297 return 0;
298 }
299
300 /* copy callback for halfduplex mode */
301 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
302 snd_pcm_uframes_t pos,
303 void __user *dst, snd_pcm_uframes_t count)
304 {
305 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
306 count <<= rme32->capture_frlog;
307 pos <<= rme32->capture_frlog;
308 if (copy_to_user_fromio(dst,
309 rme32->iobase + RME32_IO_DATA_BUFFER + pos,
310 count))
311 return -EFAULT;
312 return 0;
313 }
314
315 /*
316 * SPDIF I/O capabilities (half-duplex mode)
317 */
318 static struct snd_pcm_hardware snd_rme32_spdif_info = {
319 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
320 SNDRV_PCM_INFO_MMAP_VALID |
321 SNDRV_PCM_INFO_INTERLEAVED |
322 SNDRV_PCM_INFO_PAUSE |
323 SNDRV_PCM_INFO_SYNC_START),
324 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
325 SNDRV_PCM_FMTBIT_S32_LE),
326 .rates = (SNDRV_PCM_RATE_32000 |
327 SNDRV_PCM_RATE_44100 |
328 SNDRV_PCM_RATE_48000),
329 .rate_min = 32000,
330 .rate_max = 48000,
331 .channels_min = 2,
332 .channels_max = 2,
333 .buffer_bytes_max = RME32_BUFFER_SIZE,
334 .period_bytes_min = RME32_BLOCK_SIZE,
335 .period_bytes_max = RME32_BLOCK_SIZE,
336 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
337 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
338 .fifo_size = 0,
339 };
340
341 /*
342 * ADAT I/O capabilities (half-duplex mode)
343 */
344 static struct snd_pcm_hardware snd_rme32_adat_info =
345 {
346 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
347 SNDRV_PCM_INFO_MMAP_VALID |
348 SNDRV_PCM_INFO_INTERLEAVED |
349 SNDRV_PCM_INFO_PAUSE |
350 SNDRV_PCM_INFO_SYNC_START),
351 .formats= SNDRV_PCM_FMTBIT_S16_LE,
352 .rates = (SNDRV_PCM_RATE_44100 |
353 SNDRV_PCM_RATE_48000),
354 .rate_min = 44100,
355 .rate_max = 48000,
356 .channels_min = 8,
357 .channels_max = 8,
358 .buffer_bytes_max = RME32_BUFFER_SIZE,
359 .period_bytes_min = RME32_BLOCK_SIZE,
360 .period_bytes_max = RME32_BLOCK_SIZE,
361 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
362 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
363 .fifo_size = 0,
364 };
365
366 /*
367 * SPDIF I/O capabilities (full-duplex mode)
368 */
369 static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
370 .info = (SNDRV_PCM_INFO_MMAP |
371 SNDRV_PCM_INFO_MMAP_VALID |
372 SNDRV_PCM_INFO_INTERLEAVED |
373 SNDRV_PCM_INFO_PAUSE |
374 SNDRV_PCM_INFO_SYNC_START),
375 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
376 SNDRV_PCM_FMTBIT_S32_LE),
377 .rates = (SNDRV_PCM_RATE_32000 |
378 SNDRV_PCM_RATE_44100 |
379 SNDRV_PCM_RATE_48000),
380 .rate_min = 32000,
381 .rate_max = 48000,
382 .channels_min = 2,
383 .channels_max = 2,
384 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
385 .period_bytes_min = RME32_BLOCK_SIZE,
386 .period_bytes_max = RME32_BLOCK_SIZE,
387 .periods_min = 2,
388 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
389 .fifo_size = 0,
390 };
391
392 /*
393 * ADAT I/O capabilities (full-duplex mode)
394 */
395 static struct snd_pcm_hardware snd_rme32_adat_fd_info =
396 {
397 .info = (SNDRV_PCM_INFO_MMAP |
398 SNDRV_PCM_INFO_MMAP_VALID |
399 SNDRV_PCM_INFO_INTERLEAVED |
400 SNDRV_PCM_INFO_PAUSE |
401 SNDRV_PCM_INFO_SYNC_START),
402 .formats= SNDRV_PCM_FMTBIT_S16_LE,
403 .rates = (SNDRV_PCM_RATE_44100 |
404 SNDRV_PCM_RATE_48000),
405 .rate_min = 44100,
406 .rate_max = 48000,
407 .channels_min = 8,
408 .channels_max = 8,
409 .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
410 .period_bytes_min = RME32_BLOCK_SIZE,
411 .period_bytes_max = RME32_BLOCK_SIZE,
412 .periods_min = 2,
413 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
414 .fifo_size = 0,
415 };
416
417 static void snd_rme32_reset_dac(struct rme32 *rme32)
418 {
419 writel(rme32->wcreg | RME32_WCR_PD,
420 rme32->iobase + RME32_IO_CONTROL_REGISTER);
421 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
422 }
423
424 static int snd_rme32_playback_getrate(struct rme32 * rme32)
425 {
426 int rate;
427
428 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
429 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
430 switch (rate) {
431 case 1:
432 rate = 32000;
433 break;
434 case 2:
435 rate = 44100;
436 break;
437 case 3:
438 rate = 48000;
439 break;
440 default:
441 return -1;
442 }
443 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
444 }
445
446 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
447 {
448 int n;
449
450 *is_adat = 0;
451 if (rme32->rcreg & RME32_RCR_LOCK) {
452 /* ADAT rate */
453 *is_adat = 1;
454 }
455 if (rme32->rcreg & RME32_RCR_ERF) {
456 return -1;
457 }
458
459 /* S/PDIF rate */
460 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
461 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
462 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
463
464 if (RME32_PRO_WITH_8414(rme32))
465 switch (n) { /* supporting the CS8414 */
466 case 0:
467 case 1:
468 case 2:
469 return -1;
470 case 3:
471 return 96000;
472 case 4:
473 return 88200;
474 case 5:
475 return 48000;
476 case 6:
477 return 44100;
478 case 7:
479 return 32000;
480 default:
481 return -1;
482 break;
483 }
484 else
485 switch (n) { /* supporting the CS8412 */
486 case 0:
487 return -1;
488 case 1:
489 return 48000;
490 case 2:
491 return 44100;
492 case 3:
493 return 32000;
494 case 4:
495 return 48000;
496 case 5:
497 return 44100;
498 case 6:
499 return 44056;
500 case 7:
501 return 32000;
502 default:
503 break;
504 }
505 return -1;
506 }
507
508 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
509 {
510 int ds;
511
512 ds = rme32->wcreg & RME32_WCR_DS_BM;
513 switch (rate) {
514 case 32000:
515 rme32->wcreg &= ~RME32_WCR_DS_BM;
516 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
517 ~RME32_WCR_FREQ_1;
518 break;
519 case 44100:
520 rme32->wcreg &= ~RME32_WCR_DS_BM;
521 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
522 ~RME32_WCR_FREQ_0;
523 break;
524 case 48000:
525 rme32->wcreg &= ~RME32_WCR_DS_BM;
526 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
527 RME32_WCR_FREQ_1;
528 break;
529 case 64000:
530 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
531 return -EINVAL;
532 rme32->wcreg |= RME32_WCR_DS_BM;
533 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
534 ~RME32_WCR_FREQ_1;
535 break;
536 case 88200:
537 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
538 return -EINVAL;
539 rme32->wcreg |= RME32_WCR_DS_BM;
540 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
541 ~RME32_WCR_FREQ_0;
542 break;
543 case 96000:
544 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
545 return -EINVAL;
546 rme32->wcreg |= RME32_WCR_DS_BM;
547 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
548 RME32_WCR_FREQ_1;
549 break;
550 default:
551 return -EINVAL;
552 }
553 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
554 (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
555 {
556 /* change to/from double-speed: reset the DAC (if available) */
557 snd_rme32_reset_dac(rme32);
558 } else {
559 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
560 }
561 return 0;
562 }
563
564 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
565 {
566 switch (mode) {
567 case RME32_CLOCKMODE_SLAVE:
568 /* AutoSync */
569 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
570 ~RME32_WCR_FREQ_1;
571 break;
572 case RME32_CLOCKMODE_MASTER_32:
573 /* Internal 32.0kHz */
574 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
575 ~RME32_WCR_FREQ_1;
576 break;
577 case RME32_CLOCKMODE_MASTER_44:
578 /* Internal 44.1kHz */
579 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
580 RME32_WCR_FREQ_1;
581 break;
582 case RME32_CLOCKMODE_MASTER_48:
583 /* Internal 48.0kHz */
584 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
585 RME32_WCR_FREQ_1;
586 break;
587 default:
588 return -EINVAL;
589 }
590 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
591 return 0;
592 }
593
594 static int snd_rme32_getclockmode(struct rme32 * rme32)
595 {
596 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
597 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
598 }
599
600 static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
601 {
602 switch (type) {
603 case RME32_INPUT_OPTICAL:
604 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
605 ~RME32_WCR_INP_1;
606 break;
607 case RME32_INPUT_COAXIAL:
608 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
609 ~RME32_WCR_INP_1;
610 break;
611 case RME32_INPUT_INTERNAL:
612 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
613 RME32_WCR_INP_1;
614 break;
615 case RME32_INPUT_XLR:
616 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
617 RME32_WCR_INP_1;
618 break;
619 default:
620 return -EINVAL;
621 }
622 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
623 return 0;
624 }
625
626 static int snd_rme32_getinputtype(struct rme32 * rme32)
627 {
628 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
629 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
630 }
631
632 static void
633 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
634 {
635 int frlog;
636
637 if (n_channels == 2) {
638 frlog = 1;
639 } else {
640 /* assume 8 channels */
641 frlog = 3;
642 }
643 if (is_playback) {
644 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
645 rme32->playback_frlog = frlog;
646 } else {
647 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
648 rme32->capture_frlog = frlog;
649 }
650 }
651
652 static int snd_rme32_setformat(struct rme32 * rme32, int format)
653 {
654 switch (format) {
655 case SNDRV_PCM_FORMAT_S16_LE:
656 rme32->wcreg &= ~RME32_WCR_MODE24;
657 break;
658 case SNDRV_PCM_FORMAT_S32_LE:
659 rme32->wcreg |= RME32_WCR_MODE24;
660 break;
661 default:
662 return -EINVAL;
663 }
664 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
665 return 0;
666 }
667
668 static int
669 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
670 struct snd_pcm_hw_params *params)
671 {
672 int err, rate, dummy;
673 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
674 struct snd_pcm_runtime *runtime = substream->runtime;
675
676 if (rme32->fullduplex_mode) {
677 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
678 if (err < 0)
679 return err;
680 } else {
681 runtime->dma_area = (void __force *)(rme32->iobase +
682 RME32_IO_DATA_BUFFER);
683 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
684 runtime->dma_bytes = RME32_BUFFER_SIZE;
685 }
686
687 spin_lock_irq(&rme32->lock);
688 if ((rme32->rcreg & RME32_RCR_KMODE) &&
689 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
690 /* AutoSync */
691 if ((int)params_rate(params) != rate) {
692 spin_unlock_irq(&rme32->lock);
693 return -EIO;
694 }
695 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
696 spin_unlock_irq(&rme32->lock);
697 return err;
698 }
699 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
700 spin_unlock_irq(&rme32->lock);
701 return err;
702 }
703
704 snd_rme32_setframelog(rme32, params_channels(params), 1);
705 if (rme32->capture_periodsize != 0) {
706 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
707 spin_unlock_irq(&rme32->lock);
708 return -EBUSY;
709 }
710 }
711 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
712 /* S/PDIF setup */
713 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
714 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
715 rme32->wcreg |= rme32->wcreg_spdif_stream;
716 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
717 }
718 spin_unlock_irq(&rme32->lock);
719
720 return 0;
721 }
722
723 static int
724 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
725 struct snd_pcm_hw_params *params)
726 {
727 int err, isadat, rate;
728 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
729 struct snd_pcm_runtime *runtime = substream->runtime;
730
731 if (rme32->fullduplex_mode) {
732 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
733 if (err < 0)
734 return err;
735 } else {
736 runtime->dma_area = (void __force *)rme32->iobase +
737 RME32_IO_DATA_BUFFER;
738 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
739 runtime->dma_bytes = RME32_BUFFER_SIZE;
740 }
741
742 spin_lock_irq(&rme32->lock);
743 /* enable AutoSync for record-preparing */
744 rme32->wcreg |= RME32_WCR_AUTOSYNC;
745 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
746
747 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
748 spin_unlock_irq(&rme32->lock);
749 return err;
750 }
751 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
752 spin_unlock_irq(&rme32->lock);
753 return err;
754 }
755 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
756 if ((int)params_rate(params) != rate) {
757 spin_unlock_irq(&rme32->lock);
758 return -EIO;
759 }
760 if ((isadat && runtime->hw.channels_min == 2) ||
761 (!isadat && runtime->hw.channels_min == 8)) {
762 spin_unlock_irq(&rme32->lock);
763 return -EIO;
764 }
765 }
766 /* AutoSync off for recording */
767 rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
768 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
769
770 snd_rme32_setframelog(rme32, params_channels(params), 0);
771 if (rme32->playback_periodsize != 0) {
772 if (params_period_size(params) << rme32->capture_frlog !=
773 rme32->playback_periodsize) {
774 spin_unlock_irq(&rme32->lock);
775 return -EBUSY;
776 }
777 }
778 rme32->capture_periodsize =
779 params_period_size(params) << rme32->capture_frlog;
780 spin_unlock_irq(&rme32->lock);
781
782 return 0;
783 }
784
785 static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
786 {
787 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
788 if (! rme32->fullduplex_mode)
789 return 0;
790 return snd_pcm_lib_free_pages(substream);
791 }
792
793 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
794 {
795 if (!from_pause) {
796 writel(0, rme32->iobase + RME32_IO_RESET_POS);
797 }
798
799 rme32->wcreg |= RME32_WCR_START;
800 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
801 }
802
803 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
804 {
805 /*
806 * Check if there is an unconfirmed IRQ, if so confirm it, or else
807 * the hardware will not stop generating interrupts
808 */
809 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
810 if (rme32->rcreg & RME32_RCR_IRQ) {
811 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
812 }
813 rme32->wcreg &= ~RME32_WCR_START;
814 if (rme32->wcreg & RME32_WCR_SEL)
815 rme32->wcreg |= RME32_WCR_MUTE;
816 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
817 if (! to_pause)
818 writel(0, rme32->iobase + RME32_IO_RESET_POS);
819 }
820
821 static irqreturn_t
822 snd_rme32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
823 {
824 struct rme32 *rme32 = (struct rme32 *) dev_id;
825
826 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
827 if (!(rme32->rcreg & RME32_RCR_IRQ)) {
828 return IRQ_NONE;
829 } else {
830 if (rme32->capture_substream) {
831 snd_pcm_period_elapsed(rme32->capture_substream);
832 }
833 if (rme32->playback_substream) {
834 snd_pcm_period_elapsed(rme32->playback_substream);
835 }
836 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
837 }
838 return IRQ_HANDLED;
839 }
840
841 static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
842
843
844 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
845 .count = ARRAY_SIZE(period_bytes),
846 .list = period_bytes,
847 .mask = 0
848 };
849
850 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
851 {
852 if (! rme32->fullduplex_mode) {
853 snd_pcm_hw_constraint_minmax(runtime,
854 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
855 RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
856 snd_pcm_hw_constraint_list(runtime, 0,
857 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
858 &hw_constraints_period_bytes);
859 }
860 }
861
862 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
863 {
864 int rate, dummy;
865 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
866 struct snd_pcm_runtime *runtime = substream->runtime;
867
868 snd_pcm_set_sync(substream);
869
870 spin_lock_irq(&rme32->lock);
871 if (rme32->playback_substream != NULL) {
872 spin_unlock_irq(&rme32->lock);
873 return -EBUSY;
874 }
875 rme32->wcreg &= ~RME32_WCR_ADAT;
876 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
877 rme32->playback_substream = substream;
878 spin_unlock_irq(&rme32->lock);
879
880 if (rme32->fullduplex_mode)
881 runtime->hw = snd_rme32_spdif_fd_info;
882 else
883 runtime->hw = snd_rme32_spdif_info;
884 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
885 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
886 runtime->hw.rate_max = 96000;
887 }
888 if ((rme32->rcreg & RME32_RCR_KMODE) &&
889 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
890 /* AutoSync */
891 runtime->hw.rates = snd_rme32_ratecode(rate);
892 runtime->hw.rate_min = rate;
893 runtime->hw.rate_max = rate;
894 }
895
896 snd_rme32_set_buffer_constraint(rme32, runtime);
897
898 rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
899 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
900 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
901 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
902 return 0;
903 }
904
905 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
906 {
907 int isadat, rate;
908 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
909 struct snd_pcm_runtime *runtime = substream->runtime;
910
911 snd_pcm_set_sync(substream);
912
913 spin_lock_irq(&rme32->lock);
914 if (rme32->capture_substream != NULL) {
915 spin_unlock_irq(&rme32->lock);
916 return -EBUSY;
917 }
918 rme32->capture_substream = substream;
919 spin_unlock_irq(&rme32->lock);
920
921 if (rme32->fullduplex_mode)
922 runtime->hw = snd_rme32_spdif_fd_info;
923 else
924 runtime->hw = snd_rme32_spdif_info;
925 if (RME32_PRO_WITH_8414(rme32)) {
926 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
927 runtime->hw.rate_max = 96000;
928 }
929 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
930 if (isadat) {
931 return -EIO;
932 }
933 runtime->hw.rates = snd_rme32_ratecode(rate);
934 runtime->hw.rate_min = rate;
935 runtime->hw.rate_max = rate;
936 }
937
938 snd_rme32_set_buffer_constraint(rme32, runtime);
939
940 return 0;
941 }
942
943 static int
944 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
945 {
946 int rate, dummy;
947 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
948 struct snd_pcm_runtime *runtime = substream->runtime;
949
950 snd_pcm_set_sync(substream);
951
952 spin_lock_irq(&rme32->lock);
953 if (rme32->playback_substream != NULL) {
954 spin_unlock_irq(&rme32->lock);
955 return -EBUSY;
956 }
957 rme32->wcreg |= RME32_WCR_ADAT;
958 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
959 rme32->playback_substream = substream;
960 spin_unlock_irq(&rme32->lock);
961
962 if (rme32->fullduplex_mode)
963 runtime->hw = snd_rme32_adat_fd_info;
964 else
965 runtime->hw = snd_rme32_adat_info;
966 if ((rme32->rcreg & RME32_RCR_KMODE) &&
967 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
968 /* AutoSync */
969 runtime->hw.rates = snd_rme32_ratecode(rate);
970 runtime->hw.rate_min = rate;
971 runtime->hw.rate_max = rate;
972 }
973
974 snd_rme32_set_buffer_constraint(rme32, runtime);
975 return 0;
976 }
977
978 static int
979 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
980 {
981 int isadat, rate;
982 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
983 struct snd_pcm_runtime *runtime = substream->runtime;
984
985 if (rme32->fullduplex_mode)
986 runtime->hw = snd_rme32_adat_fd_info;
987 else
988 runtime->hw = snd_rme32_adat_info;
989 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
990 if (!isadat) {
991 return -EIO;
992 }
993 runtime->hw.rates = snd_rme32_ratecode(rate);
994 runtime->hw.rate_min = rate;
995 runtime->hw.rate_max = rate;
996 }
997
998 snd_pcm_set_sync(substream);
999
1000 spin_lock_irq(&rme32->lock);
1001 if (rme32->capture_substream != NULL) {
1002 spin_unlock_irq(&rme32->lock);
1003 return -EBUSY;
1004 }
1005 rme32->capture_substream = substream;
1006 spin_unlock_irq(&rme32->lock);
1007
1008 snd_rme32_set_buffer_constraint(rme32, runtime);
1009 return 0;
1010 }
1011
1012 static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
1013 {
1014 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1015 int spdif = 0;
1016
1017 spin_lock_irq(&rme32->lock);
1018 rme32->playback_substream = NULL;
1019 rme32->playback_periodsize = 0;
1020 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1021 spin_unlock_irq(&rme32->lock);
1022 if (spdif) {
1023 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1024 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1025 SNDRV_CTL_EVENT_MASK_INFO,
1026 &rme32->spdif_ctl->id);
1027 }
1028 return 0;
1029 }
1030
1031 static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1032 {
1033 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1034
1035 spin_lock_irq(&rme32->lock);
1036 rme32->capture_substream = NULL;
1037 rme32->capture_periodsize = 0;
1038 spin_unlock(&rme32->lock);
1039 return 0;
1040 }
1041
1042 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1043 {
1044 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1045
1046 spin_lock_irq(&rme32->lock);
1047 if (rme32->fullduplex_mode) {
1048 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1049 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1050 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1051 } else {
1052 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1053 }
1054 if (rme32->wcreg & RME32_WCR_SEL)
1055 rme32->wcreg &= ~RME32_WCR_MUTE;
1056 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1057 spin_unlock_irq(&rme32->lock);
1058 return 0;
1059 }
1060
1061 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1062 {
1063 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1064
1065 spin_lock_irq(&rme32->lock);
1066 if (rme32->fullduplex_mode) {
1067 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1068 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1069 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1070 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1071 } else {
1072 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1073 }
1074 spin_unlock_irq(&rme32->lock);
1075 return 0;
1076 }
1077
1078 static int
1079 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1080 {
1081 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1082 struct list_head *pos;
1083 struct snd_pcm_substream *s;
1084
1085 spin_lock(&rme32->lock);
1086 snd_pcm_group_for_each(pos, substream) {
1087 s = snd_pcm_group_substream_entry(pos);
1088 if (s != rme32->playback_substream &&
1089 s != rme32->capture_substream)
1090 continue;
1091 switch (cmd) {
1092 case SNDRV_PCM_TRIGGER_START:
1093 rme32->running |= (1 << s->stream);
1094 if (rme32->fullduplex_mode) {
1095 /* remember the current DMA position */
1096 if (s == rme32->playback_substream) {
1097 rme32->playback_pcm.hw_io =
1098 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1099 } else {
1100 rme32->capture_pcm.hw_io =
1101 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1102 }
1103 }
1104 break;
1105 case SNDRV_PCM_TRIGGER_STOP:
1106 rme32->running &= ~(1 << s->stream);
1107 break;
1108 }
1109 snd_pcm_trigger_done(s, substream);
1110 }
1111
1112 /* prefill playback buffer */
1113 if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1114 snd_pcm_group_for_each(pos, substream) {
1115 s = snd_pcm_group_substream_entry(pos);
1116 if (s == rme32->playback_substream) {
1117 s->ops->ack(s);
1118 break;
1119 }
1120 }
1121 }
1122
1123 switch (cmd) {
1124 case SNDRV_PCM_TRIGGER_START:
1125 if (rme32->running && ! RME32_ISWORKING(rme32))
1126 snd_rme32_pcm_start(rme32, 0);
1127 break;
1128 case SNDRV_PCM_TRIGGER_STOP:
1129 if (! rme32->running && RME32_ISWORKING(rme32))
1130 snd_rme32_pcm_stop(rme32, 0);
1131 break;
1132 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1133 if (rme32->running && RME32_ISWORKING(rme32))
1134 snd_rme32_pcm_stop(rme32, 1);
1135 break;
1136 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1137 if (rme32->running && ! RME32_ISWORKING(rme32))
1138 snd_rme32_pcm_start(rme32, 1);
1139 break;
1140 }
1141 spin_unlock(&rme32->lock);
1142 return 0;
1143 }
1144
1145 /* pointer callback for halfduplex mode */
1146 static snd_pcm_uframes_t
1147 snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1148 {
1149 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1150 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1151 }
1152
1153 static snd_pcm_uframes_t
1154 snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1155 {
1156 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1157 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1158 }
1159
1160
1161 /* ack and pointer callbacks for fullduplex mode */
1162 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1163 struct snd_pcm_indirect *rec, size_t bytes)
1164 {
1165 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1166 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1167 substream->runtime->dma_area + rec->sw_data, bytes);
1168 }
1169
1170 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1171 {
1172 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1173 struct snd_pcm_indirect *rec, *cprec;
1174
1175 rec = &rme32->playback_pcm;
1176 cprec = &rme32->capture_pcm;
1177 spin_lock(&rme32->lock);
1178 rec->hw_queue_size = RME32_BUFFER_SIZE;
1179 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1180 rec->hw_queue_size -= cprec->hw_ready;
1181 spin_unlock(&rme32->lock);
1182 snd_pcm_indirect_playback_transfer(substream, rec,
1183 snd_rme32_pb_trans_copy);
1184 return 0;
1185 }
1186
1187 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1188 struct snd_pcm_indirect *rec, size_t bytes)
1189 {
1190 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1191 memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1192 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1193 bytes);
1194 }
1195
1196 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1197 {
1198 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1199 snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1200 snd_rme32_cp_trans_copy);
1201 return 0;
1202 }
1203
1204 static snd_pcm_uframes_t
1205 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1206 {
1207 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1208 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1209 snd_rme32_pcm_byteptr(rme32));
1210 }
1211
1212 static snd_pcm_uframes_t
1213 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1214 {
1215 struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1216 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1217 snd_rme32_pcm_byteptr(rme32));
1218 }
1219
1220 /* for halfduplex mode */
1221 static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1222 .open = snd_rme32_playback_spdif_open,
1223 .close = snd_rme32_playback_close,
1224 .ioctl = snd_pcm_lib_ioctl,
1225 .hw_params = snd_rme32_playback_hw_params,
1226 .hw_free = snd_rme32_pcm_hw_free,
1227 .prepare = snd_rme32_playback_prepare,
1228 .trigger = snd_rme32_pcm_trigger,
1229 .pointer = snd_rme32_playback_pointer,
1230 .copy = snd_rme32_playback_copy,
1231 .silence = snd_rme32_playback_silence,
1232 .mmap = snd_pcm_lib_mmap_iomem,
1233 };
1234
1235 static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1236 .open = snd_rme32_capture_spdif_open,
1237 .close = snd_rme32_capture_close,
1238 .ioctl = snd_pcm_lib_ioctl,
1239 .hw_params = snd_rme32_capture_hw_params,
1240 .hw_free = snd_rme32_pcm_hw_free,
1241 .prepare = snd_rme32_capture_prepare,
1242 .trigger = snd_rme32_pcm_trigger,
1243 .pointer = snd_rme32_capture_pointer,
1244 .copy = snd_rme32_capture_copy,
1245 .mmap = snd_pcm_lib_mmap_iomem,
1246 };
1247
1248 static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1249 .open = snd_rme32_playback_adat_open,
1250 .close = snd_rme32_playback_close,
1251 .ioctl = snd_pcm_lib_ioctl,
1252 .hw_params = snd_rme32_playback_hw_params,
1253 .prepare = snd_rme32_playback_prepare,
1254 .trigger = snd_rme32_pcm_trigger,
1255 .pointer = snd_rme32_playback_pointer,
1256 .copy = snd_rme32_playback_copy,
1257 .silence = snd_rme32_playback_silence,
1258 .mmap = snd_pcm_lib_mmap_iomem,
1259 };
1260
1261 static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1262 .open = snd_rme32_capture_adat_open,
1263 .close = snd_rme32_capture_close,
1264 .ioctl = snd_pcm_lib_ioctl,
1265 .hw_params = snd_rme32_capture_hw_params,
1266 .prepare = snd_rme32_capture_prepare,
1267 .trigger = snd_rme32_pcm_trigger,
1268 .pointer = snd_rme32_capture_pointer,
1269 .copy = snd_rme32_capture_copy,
1270 .mmap = snd_pcm_lib_mmap_iomem,
1271 };
1272
1273 /* for fullduplex mode */
1274 static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1275 .open = snd_rme32_playback_spdif_open,
1276 .close = snd_rme32_playback_close,
1277 .ioctl = snd_pcm_lib_ioctl,
1278 .hw_params = snd_rme32_playback_hw_params,
1279 .hw_free = snd_rme32_pcm_hw_free,
1280 .prepare = snd_rme32_playback_prepare,
1281 .trigger = snd_rme32_pcm_trigger,
1282 .pointer = snd_rme32_playback_fd_pointer,
1283 .ack = snd_rme32_playback_fd_ack,
1284 };
1285
1286 static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1287 .open = snd_rme32_capture_spdif_open,
1288 .close = snd_rme32_capture_close,
1289 .ioctl = snd_pcm_lib_ioctl,
1290 .hw_params = snd_rme32_capture_hw_params,
1291 .hw_free = snd_rme32_pcm_hw_free,
1292 .prepare = snd_rme32_capture_prepare,
1293 .trigger = snd_rme32_pcm_trigger,
1294 .pointer = snd_rme32_capture_fd_pointer,
1295 .ack = snd_rme32_capture_fd_ack,
1296 };
1297
1298 static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1299 .open = snd_rme32_playback_adat_open,
1300 .close = snd_rme32_playback_close,
1301 .ioctl = snd_pcm_lib_ioctl,
1302 .hw_params = snd_rme32_playback_hw_params,
1303 .prepare = snd_rme32_playback_prepare,
1304 .trigger = snd_rme32_pcm_trigger,
1305 .pointer = snd_rme32_playback_fd_pointer,
1306 .ack = snd_rme32_playback_fd_ack,
1307 };
1308
1309 static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1310 .open = snd_rme32_capture_adat_open,
1311 .close = snd_rme32_capture_close,
1312 .ioctl = snd_pcm_lib_ioctl,
1313 .hw_params = snd_rme32_capture_hw_params,
1314 .prepare = snd_rme32_capture_prepare,
1315 .trigger = snd_rme32_pcm_trigger,
1316 .pointer = snd_rme32_capture_fd_pointer,
1317 .ack = snd_rme32_capture_fd_ack,
1318 };
1319
1320 static void snd_rme32_free(void *private_data)
1321 {
1322 struct rme32 *rme32 = (struct rme32 *) private_data;
1323
1324 if (rme32 == NULL) {
1325 return;
1326 }
1327 if (rme32->irq >= 0) {
1328 snd_rme32_pcm_stop(rme32, 0);
1329 free_irq(rme32->irq, (void *) rme32);
1330 rme32->irq = -1;
1331 }
1332 if (rme32->iobase) {
1333 iounmap(rme32->iobase);
1334 rme32->iobase = NULL;
1335 }
1336 if (rme32->port) {
1337 pci_release_regions(rme32->pci);
1338 rme32->port = 0;
1339 }
1340 pci_disable_device(rme32->pci);
1341 }
1342
1343 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1344 {
1345 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1346 rme32->spdif_pcm = NULL;
1347 }
1348
1349 static void
1350 snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1351 {
1352 struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1353 rme32->adat_pcm = NULL;
1354 }
1355
1356 static int __devinit snd_rme32_create(struct rme32 * rme32)
1357 {
1358 struct pci_dev *pci = rme32->pci;
1359 int err;
1360
1361 rme32->irq = -1;
1362 spin_lock_init(&rme32->lock);
1363
1364 if ((err = pci_enable_device(pci)) < 0)
1365 return err;
1366
1367 if ((err = pci_request_regions(pci, "RME32")) < 0)
1368 return err;
1369 rme32->port = pci_resource_start(rme32->pci, 0);
1370
1371 if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
1372 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n",
1373 rme32->port, rme32->port + RME32_IO_SIZE - 1);
1374 return -ENOMEM;
1375 }
1376
1377 if (request_irq(pci->irq, snd_rme32_interrupt, SA_INTERRUPT | SA_SHIRQ, "RME32", (void *) rme32)) {
1378 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1379 return -EBUSY;
1380 }
1381 rme32->irq = pci->irq;
1382
1383 /* read the card's revision number */
1384 pci_read_config_byte(pci, 8, &rme32->rev);
1385
1386 /* set up ALSA pcm device for S/PDIF */
1387 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1388 return err;
1389 }
1390 rme32->spdif_pcm->private_data = rme32;
1391 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1392 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1393 if (rme32->fullduplex_mode) {
1394 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1395 &snd_rme32_playback_spdif_fd_ops);
1396 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1397 &snd_rme32_capture_spdif_fd_ops);
1398 snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1399 snd_dma_continuous_data(GFP_KERNEL),
1400 0, RME32_MID_BUFFER_SIZE);
1401 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1402 } else {
1403 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1404 &snd_rme32_playback_spdif_ops);
1405 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1406 &snd_rme32_capture_spdif_ops);
1407 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1408 }
1409
1410 /* set up ALSA pcm device for ADAT */
1411 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1412 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1413 /* ADAT is not available on DIGI32 and DIGI32 Pro */
1414 rme32->adat_pcm = NULL;
1415 }
1416 else {
1417 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1418 1, 1, &rme32->adat_pcm)) < 0)
1419 {
1420 return err;
1421 }
1422 rme32->adat_pcm->private_data = rme32;
1423 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1424 strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1425 if (rme32->fullduplex_mode) {
1426 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1427 &snd_rme32_playback_adat_fd_ops);
1428 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1429 &snd_rme32_capture_adat_fd_ops);
1430 snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1431 snd_dma_continuous_data(GFP_KERNEL),
1432 0, RME32_MID_BUFFER_SIZE);
1433 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1434 } else {
1435 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1436 &snd_rme32_playback_adat_ops);
1437 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1438 &snd_rme32_capture_adat_ops);
1439 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1440 }
1441 }
1442
1443
1444 rme32->playback_periodsize = 0;
1445 rme32->capture_periodsize = 0;
1446
1447 /* make sure playback/capture is stopped, if by some reason active */
1448 snd_rme32_pcm_stop(rme32, 0);
1449
1450 /* reset DAC */
1451 snd_rme32_reset_dac(rme32);
1452
1453 /* reset buffer pointer */
1454 writel(0, rme32->iobase + RME32_IO_RESET_POS);
1455
1456 /* set default values in registers */
1457 rme32->wcreg = RME32_WCR_SEL | /* normal playback */
1458 RME32_WCR_INP_0 | /* input select */
1459 RME32_WCR_MUTE; /* muting on */
1460 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1461
1462
1463 /* init switch interface */
1464 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1465 return err;
1466 }
1467
1468 /* init proc interface */
1469 snd_rme32_proc_init(rme32);
1470
1471 rme32->capture_substream = NULL;
1472 rme32->playback_substream = NULL;
1473
1474 return 0;
1475 }
1476
1477 /*
1478 * proc interface
1479 */
1480
1481 static void
1482 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1483 {
1484 int n;
1485 struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1486
1487 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1488
1489 snd_iprintf(buffer, rme32->card->longname);
1490 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1491
1492 snd_iprintf(buffer, "\nGeneral settings\n");
1493 if (rme32->fullduplex_mode)
1494 snd_iprintf(buffer, " Full-duplex mode\n");
1495 else
1496 snd_iprintf(buffer, " Half-duplex mode\n");
1497 if (RME32_PRO_WITH_8414(rme32)) {
1498 snd_iprintf(buffer, " receiver: CS8414\n");
1499 } else {
1500 snd_iprintf(buffer, " receiver: CS8412\n");
1501 }
1502 if (rme32->wcreg & RME32_WCR_MODE24) {
1503 snd_iprintf(buffer, " format: 24 bit");
1504 } else {
1505 snd_iprintf(buffer, " format: 16 bit");
1506 }
1507 if (rme32->wcreg & RME32_WCR_MONO) {
1508 snd_iprintf(buffer, ", Mono\n");
1509 } else {
1510 snd_iprintf(buffer, ", Stereo\n");
1511 }
1512
1513 snd_iprintf(buffer, "\nInput settings\n");
1514 switch (snd_rme32_getinputtype(rme32)) {
1515 case RME32_INPUT_OPTICAL:
1516 snd_iprintf(buffer, " input: optical");
1517 break;
1518 case RME32_INPUT_COAXIAL:
1519 snd_iprintf(buffer, " input: coaxial");
1520 break;
1521 case RME32_INPUT_INTERNAL:
1522 snd_iprintf(buffer, " input: internal");
1523 break;
1524 case RME32_INPUT_XLR:
1525 snd_iprintf(buffer, " input: XLR");
1526 break;
1527 }
1528 if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1529 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1530 } else {
1531 if (n) {
1532 snd_iprintf(buffer, " (8 channels)\n");
1533 } else {
1534 snd_iprintf(buffer, " (2 channels)\n");
1535 }
1536 snd_iprintf(buffer, " sample rate: %d Hz\n",
1537 snd_rme32_capture_getrate(rme32, &n));
1538 }
1539
1540 snd_iprintf(buffer, "\nOutput settings\n");
1541 if (rme32->wcreg & RME32_WCR_SEL) {
1542 snd_iprintf(buffer, " output signal: normal playback");
1543 } else {
1544 snd_iprintf(buffer, " output signal: same as input");
1545 }
1546 if (rme32->wcreg & RME32_WCR_MUTE) {
1547 snd_iprintf(buffer, " (muted)\n");
1548 } else {
1549 snd_iprintf(buffer, "\n");
1550 }
1551
1552 /* master output frequency */
1553 if (!
1554 ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1555 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1556 snd_iprintf(buffer, " sample rate: %d Hz\n",
1557 snd_rme32_playback_getrate(rme32));
1558 }
1559 if (rme32->rcreg & RME32_RCR_KMODE) {
1560 snd_iprintf(buffer, " sample clock source: AutoSync\n");
1561 } else {
1562 snd_iprintf(buffer, " sample clock source: Internal\n");
1563 }
1564 if (rme32->wcreg & RME32_WCR_PRO) {
1565 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1566 } else {
1567 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1568 }
1569 if (rme32->wcreg & RME32_WCR_EMP) {
1570 snd_iprintf(buffer, " emphasis: on\n");
1571 } else {
1572 snd_iprintf(buffer, " emphasis: off\n");
1573 }
1574 }
1575
1576 static void __devinit snd_rme32_proc_init(struct rme32 * rme32)
1577 {
1578 struct snd_info_entry *entry;
1579
1580 if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1581 snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1582 }
1583
1584 /*
1585 * control interface
1586 */
1587
1588 static int
1589 snd_rme32_info_loopback_control(struct snd_kcontrol *kcontrol,
1590 struct snd_ctl_elem_info *uinfo)
1591 {
1592 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1593 uinfo->count = 1;
1594 uinfo->value.integer.min = 0;
1595 uinfo->value.integer.max = 1;
1596 return 0;
1597 }
1598 static int
1599 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1600 struct snd_ctl_elem_value *ucontrol)
1601 {
1602 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1603
1604 spin_lock_irq(&rme32->lock);
1605 ucontrol->value.integer.value[0] =
1606 rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1607 spin_unlock_irq(&rme32->lock);
1608 return 0;
1609 }
1610 static int
1611 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1612 struct snd_ctl_elem_value *ucontrol)
1613 {
1614 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1615 unsigned int val;
1616 int change;
1617
1618 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1619 spin_lock_irq(&rme32->lock);
1620 val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1621 change = val != rme32->wcreg;
1622 if (ucontrol->value.integer.value[0])
1623 val &= ~RME32_WCR_MUTE;
1624 else
1625 val |= RME32_WCR_MUTE;
1626 rme32->wcreg = val;
1627 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1628 spin_unlock_irq(&rme32->lock);
1629 return change;
1630 }
1631
1632 static int
1633 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1634 struct snd_ctl_elem_info *uinfo)
1635 {
1636 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1637 static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1638
1639 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1640 uinfo->count = 1;
1641 switch (rme32->pci->device) {
1642 case PCI_DEVICE_ID_RME_DIGI32:
1643 case PCI_DEVICE_ID_RME_DIGI32_8:
1644 uinfo->value.enumerated.items = 3;
1645 break;
1646 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1647 uinfo->value.enumerated.items = 4;
1648 break;
1649 default:
1650 snd_BUG();
1651 break;
1652 }
1653 if (uinfo->value.enumerated.item >
1654 uinfo->value.enumerated.items - 1) {
1655 uinfo->value.enumerated.item =
1656 uinfo->value.enumerated.items - 1;
1657 }
1658 strcpy(uinfo->value.enumerated.name,
1659 texts[uinfo->value.enumerated.item]);
1660 return 0;
1661 }
1662 static int
1663 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1664 struct snd_ctl_elem_value *ucontrol)
1665 {
1666 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1667 unsigned int items = 3;
1668
1669 spin_lock_irq(&rme32->lock);
1670 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1671
1672 switch (rme32->pci->device) {
1673 case PCI_DEVICE_ID_RME_DIGI32:
1674 case PCI_DEVICE_ID_RME_DIGI32_8:
1675 items = 3;
1676 break;
1677 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1678 items = 4;
1679 break;
1680 default:
1681 snd_BUG();
1682 break;
1683 }
1684 if (ucontrol->value.enumerated.item[0] >= items) {
1685 ucontrol->value.enumerated.item[0] = items - 1;
1686 }
1687
1688 spin_unlock_irq(&rme32->lock);
1689 return 0;
1690 }
1691 static int
1692 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1693 struct snd_ctl_elem_value *ucontrol)
1694 {
1695 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1696 unsigned int val;
1697 int change, items = 3;
1698
1699 switch (rme32->pci->device) {
1700 case PCI_DEVICE_ID_RME_DIGI32:
1701 case PCI_DEVICE_ID_RME_DIGI32_8:
1702 items = 3;
1703 break;
1704 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1705 items = 4;
1706 break;
1707 default:
1708 snd_BUG();
1709 break;
1710 }
1711 val = ucontrol->value.enumerated.item[0] % items;
1712
1713 spin_lock_irq(&rme32->lock);
1714 change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1715 snd_rme32_setinputtype(rme32, val);
1716 spin_unlock_irq(&rme32->lock);
1717 return change;
1718 }
1719
1720 static int
1721 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1722 struct snd_ctl_elem_info *uinfo)
1723 {
1724 static char *texts[4] = { "AutoSync",
1725 "Internal 32.0kHz",
1726 "Internal 44.1kHz",
1727 "Internal 48.0kHz" };
1728
1729 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1730 uinfo->count = 1;
1731 uinfo->value.enumerated.items = 4;
1732 if (uinfo->value.enumerated.item > 3) {
1733 uinfo->value.enumerated.item = 3;
1734 }
1735 strcpy(uinfo->value.enumerated.name,
1736 texts[uinfo->value.enumerated.item]);
1737 return 0;
1738 }
1739 static int
1740 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1741 struct snd_ctl_elem_value *ucontrol)
1742 {
1743 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1744
1745 spin_lock_irq(&rme32->lock);
1746 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1747 spin_unlock_irq(&rme32->lock);
1748 return 0;
1749 }
1750 static int
1751 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1752 struct snd_ctl_elem_value *ucontrol)
1753 {
1754 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1755 unsigned int val;
1756 int change;
1757
1758 val = ucontrol->value.enumerated.item[0] % 3;
1759 spin_lock_irq(&rme32->lock);
1760 change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1761 snd_rme32_setclockmode(rme32, val);
1762 spin_unlock_irq(&rme32->lock);
1763 return change;
1764 }
1765
1766 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1767 {
1768 u32 val = 0;
1769 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1770 if (val & RME32_WCR_PRO)
1771 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1772 else
1773 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1774 return val;
1775 }
1776
1777 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1778 {
1779 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1780 if (val & RME32_WCR_PRO)
1781 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1782 else
1783 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1784 }
1785
1786 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1787 struct snd_ctl_elem_info *uinfo)
1788 {
1789 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1790 uinfo->count = 1;
1791 return 0;
1792 }
1793
1794 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1795 struct snd_ctl_elem_value *ucontrol)
1796 {
1797 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1798
1799 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1800 rme32->wcreg_spdif);
1801 return 0;
1802 }
1803
1804 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1805 struct snd_ctl_elem_value *ucontrol)
1806 {
1807 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1808 int change;
1809 u32 val;
1810
1811 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1812 spin_lock_irq(&rme32->lock);
1813 change = val != rme32->wcreg_spdif;
1814 rme32->wcreg_spdif = val;
1815 spin_unlock_irq(&rme32->lock);
1816 return change;
1817 }
1818
1819 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1820 struct snd_ctl_elem_info *uinfo)
1821 {
1822 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1823 uinfo->count = 1;
1824 return 0;
1825 }
1826
1827 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1828 struct snd_ctl_elem_value *
1829 ucontrol)
1830 {
1831 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1832
1833 snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1834 rme32->wcreg_spdif_stream);
1835 return 0;
1836 }
1837
1838 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1839 struct snd_ctl_elem_value *
1840 ucontrol)
1841 {
1842 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1843 int change;
1844 u32 val;
1845
1846 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1847 spin_lock_irq(&rme32->lock);
1848 change = val != rme32->wcreg_spdif_stream;
1849 rme32->wcreg_spdif_stream = val;
1850 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1851 rme32->wcreg |= val;
1852 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1853 spin_unlock_irq(&rme32->lock);
1854 return change;
1855 }
1856
1857 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1858 struct snd_ctl_elem_info *uinfo)
1859 {
1860 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1861 uinfo->count = 1;
1862 return 0;
1863 }
1864
1865 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1866 struct snd_ctl_elem_value *
1867 ucontrol)
1868 {
1869 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1870 return 0;
1871 }
1872
1873 static struct snd_kcontrol_new snd_rme32_controls[] = {
1874 {
1875 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1876 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1877 .info = snd_rme32_control_spdif_info,
1878 .get = snd_rme32_control_spdif_get,
1879 .put = snd_rme32_control_spdif_put
1880 },
1881 {
1882 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1883 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1884 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1885 .info = snd_rme32_control_spdif_stream_info,
1886 .get = snd_rme32_control_spdif_stream_get,
1887 .put = snd_rme32_control_spdif_stream_put
1888 },
1889 {
1890 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1891 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1892 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1893 .info = snd_rme32_control_spdif_mask_info,
1894 .get = snd_rme32_control_spdif_mask_get,
1895 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1896 },
1897 {
1898 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1899 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1900 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1901 .info = snd_rme32_control_spdif_mask_info,
1902 .get = snd_rme32_control_spdif_mask_get,
1903 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1904 },
1905 {
1906 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1907 .name = "Input Connector",
1908 .info = snd_rme32_info_inputtype_control,
1909 .get = snd_rme32_get_inputtype_control,
1910 .put = snd_rme32_put_inputtype_control
1911 },
1912 {
1913 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1914 .name = "Loopback Input",
1915 .info = snd_rme32_info_loopback_control,
1916 .get = snd_rme32_get_loopback_control,
1917 .put = snd_rme32_put_loopback_control
1918 },
1919 {
1920 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1921 .name = "Sample Clock Source",
1922 .info = snd_rme32_info_clockmode_control,
1923 .get = snd_rme32_get_clockmode_control,
1924 .put = snd_rme32_put_clockmode_control
1925 }
1926 };
1927
1928 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1929 {
1930 int idx, err;
1931 struct snd_kcontrol *kctl;
1932
1933 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1934 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1935 return err;
1936 if (idx == 1) /* IEC958 (S/PDIF) Stream */
1937 rme32->spdif_ctl = kctl;
1938 }
1939
1940 return 0;
1941 }
1942
1943 /*
1944 * Card initialisation
1945 */
1946
1947 static void snd_rme32_card_free(struct snd_card *card)
1948 {
1949 snd_rme32_free(card->private_data);
1950 }
1951
1952 static int __devinit
1953 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1954 {
1955 static int dev;
1956 struct rme32 *rme32;
1957 struct snd_card *card;
1958 int err;
1959
1960 if (dev >= SNDRV_CARDS) {
1961 return -ENODEV;
1962 }
1963 if (!enable[dev]) {
1964 dev++;
1965 return -ENOENT;
1966 }
1967
1968 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
1969 sizeof(struct rme32))) == NULL)
1970 return -ENOMEM;
1971 card->private_free = snd_rme32_card_free;
1972 rme32 = (struct rme32 *) card->private_data;
1973 rme32->card = card;
1974 rme32->pci = pci;
1975 snd_card_set_dev(card, &pci->dev);
1976 if (fullduplex[dev])
1977 rme32->fullduplex_mode = 1;
1978 if ((err = snd_rme32_create(rme32)) < 0) {
1979 snd_card_free(card);
1980 return err;
1981 }
1982
1983 strcpy(card->driver, "Digi32");
1984 switch (rme32->pci->device) {
1985 case PCI_DEVICE_ID_RME_DIGI32:
1986 strcpy(card->shortname, "RME Digi32");
1987 break;
1988 case PCI_DEVICE_ID_RME_DIGI32_8:
1989 strcpy(card->shortname, "RME Digi32/8");
1990 break;
1991 case PCI_DEVICE_ID_RME_DIGI32_PRO:
1992 strcpy(card->shortname, "RME Digi32 PRO");
1993 break;
1994 }
1995 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1996 card->shortname, rme32->rev, rme32->port, rme32->irq);
1997
1998 if ((err = snd_card_register(card)) < 0) {
1999 snd_card_free(card);
2000 return err;
2001 }
2002 pci_set_drvdata(pci, card);
2003 dev++;
2004 return 0;
2005 }
2006
2007 static void __devexit snd_rme32_remove(struct pci_dev *pci)
2008 {
2009 snd_card_free(pci_get_drvdata(pci));
2010 pci_set_drvdata(pci, NULL);
2011 }
2012
2013 static struct pci_driver driver = {
2014 .name = "RME Digi32",
2015 .id_table = snd_rme32_ids,
2016 .probe = snd_rme32_probe,
2017 .remove = __devexit_p(snd_rme32_remove),
2018 };
2019
2020 static int __init alsa_card_rme32_init(void)
2021 {
2022 return pci_register_driver(&driver);
2023 }
2024
2025 static void __exit alsa_card_rme32_exit(void)
2026 {
2027 pci_unregister_driver(&driver);
2028 }
2029
2030 module_init(alsa_card_rme32_init)
2031 module_exit(alsa_card_rme32_exit)
Support for the Chinese Samsung S3C2440 based development boards