arch/i386/kernel/cpu/cyrix.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/delay.h>
   4 #include <linux/pci.h>
   5 #include <asm/dma.h>
   6 #include <asm/io.h>
   7 #include <asm/processor.h>
   8 #include <asm/timer.h>
   9 #include <asm/pci-direct.h>
  10
  11 #include "cpu.h"
  12
  13 /*
  14  * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
  15  */
  16 static void __cpuinit do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
  17 {
  18         unsigned char ccr2, ccr3;
  19         unsigned long flags;
  20
  21         /* we test for DEVID by checking whether CCR3 is writable */
  22         local_irq_save(flags);
  23         ccr3 = getCx86(CX86_CCR3);
  24         setCx86(CX86_CCR3, ccr3 ^ 0x80);
  25         getCx86(0xc0);   /* dummy to change bus */
  26
  27         if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
  28                 ccr2 = getCx86(CX86_CCR2);
  29                 setCx86(CX86_CCR2, ccr2 ^ 0x04);
  30                 getCx86(0xc0);  /* dummy */
  31
  32                 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
  33                         *dir0 = 0xfd;
  34                 else {                          /* Cx486S A step */
  35                         setCx86(CX86_CCR2, ccr2);
  36                         *dir0 = 0xfe;
  37                 }
  38         }
  39         else {
  40                 setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */
  41
  42                 /* read DIR0 and DIR1 CPU registers */
  43                 *dir0 = getCx86(CX86_DIR0);
  44                 *dir1 = getCx86(CX86_DIR1);
  45         }
  46         local_irq_restore(flags);
  47 }
  48
  49 /*
  50  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
  51  * order to identify the Cyrix CPU model after we're out of setup.c
  52  *
  53  * Actually since bugs.h doesn't even reference this perhaps someone should
  54  * fix the documentation ???
  55  */
  56 static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
  57
  58 static char Cx86_model[][9] __cpuinitdata = {
  59         "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
  60         "M II ", "Unknown"
  61 };
  62 static char Cx486_name[][5] __cpuinitdata = {
  63         "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
  64         "SRx2", "DRx2"
  65 };
  66 static char Cx486S_name[][4] __cpuinitdata = {
  67         "S", "S2", "Se", "S2e"
  68 };
  69 static char Cx486D_name[][4] __cpuinitdata = {
  70         "DX", "DX2", "?", "?", "?", "DX4"
  71 };
  72 static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
  73 static char cyrix_model_mult1[] __cpuinitdata = "12??43";
  74 static char cyrix_model_mult2[] __cpuinitdata = "12233445";
  75
  76 /*
  77  * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
  78  * BIOSes for compatibility with DOS games.  This makes the udelay loop
  79  * work correctly, and improves performance.
  80  *
  81  * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
  82  */
  83
  84 extern void calibrate_delay(void) __init;
  85
  86 static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
  87 {
  88         unsigned long flags;
  89
  90         if (Cx86_dir0_msb == 3) {
  91                 unsigned char ccr3, ccr5;
  92
  93                 local_irq_save(flags);
  94                 ccr3 = getCx86(CX86_CCR3);
  95                 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
  96                 ccr5 = getCx86(CX86_CCR5);
  97                 if (ccr5 & 2)
  98                         setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
  99                 setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
 100                 local_irq_restore(flags);
 101
 102                 if (ccr5 & 2) { /* possible wrong calibration done */
 103                         printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
 104                         calibrate_delay();
 105                         c->loops_per_jiffy = loops_per_jiffy;
 106                 }
 107         }
 108 }
 109
 110
 111 static void __cpuinit set_cx86_reorder(void)
 112 {
 113         u8 ccr3;
 114
 115         printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
 116         ccr3 = getCx86(CX86_CCR3);
 117         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
 118
 119         /* Load/Store Serialize to mem access disable (=reorder it)  */
 120         setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
 121         /* set load/store serialize from 1GB to 4GB */
 122         ccr3 |= 0xe0;
 123         setCx86(CX86_CCR3, ccr3);
 124 }
 125
 126 static void __cpuinit set_cx86_memwb(void)
 127 {
 128         u32 cr0;
 129
 130         printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
 131
 132         /* CCR2 bit 2: unlock NW bit */
 133         setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
 134         /* set 'Not Write-through' */
 135         cr0 = 0x20000000;
 136         write_cr0(read_cr0() | cr0);
 137         /* CCR2 bit 2: lock NW bit and set WT1 */
 138         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
 139 }
 140
 141 static void __cpuinit set_cx86_inc(void)
 142 {
 143         unsigned char ccr3;
 144
 145         printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
 146
 147         ccr3 = getCx86(CX86_CCR3);
 148         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
 149         /* PCR1 -- Performance Control */
 150         /* Incrementor on, whatever that is */
 151         setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
 152         /* PCR0 -- Performance Control */
 153         /* Incrementor Margin 10 */
 154         setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
 155         setCx86(CX86_CCR3, ccr3);       /* disable MAPEN */
 156 }
 157
 158 /*
 159  *      Configure later MediaGX and/or Geode processor.
 160  */
 161
 162 static void __cpuinit geode_configure(void)
 163 {
 164         unsigned long flags;
 165         u8 ccr3;
 166         local_irq_save(flags);
 167
 168         /* Suspend on halt power saving and enable #SUSP pin */
 169         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
 170
 171         ccr3 = getCx86(CX86_CCR3);
 172         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN */
 173
 174
 175         /* FPU fast, DTE cache, Mem bypass */
 176         setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
 177         setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
 178
 179         set_cx86_memwb();
 180         set_cx86_reorder();
 181         set_cx86_inc();
 182
 183         local_irq_restore(flags);
 184 }
 185
 186
 187 static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
 188 {
 189         unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
 190         char *buf = c->x86_model_id;
 191         const char *p = NULL;
 192
 193         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 194            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 195         clear_bit(0*32+31, c->x86_capability);
 196
 197         /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
 198         if ( test_bit(1*32+24, c->x86_capability) ) {
 199                 clear_bit(1*32+24, c->x86_capability);
 200                 set_bit(X86_FEATURE_CXMMX, c->x86_capability);
 201         }
 202
 203         do_cyrix_devid(&dir0, &dir1);
 204
 205         check_cx686_slop(c);
 206
 207         Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
 208         dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */
 209
 210         /* common case step number/rev -- exceptions handled below */
 211         c->x86_model = (dir1 >> 4) + 1;
 212         c->x86_mask = dir1 & 0xf;
 213
 214         /* Now cook; the original recipe is by Channing Corn, from Cyrix.
 215          * We do the same thing for each generation: we work out
 216          * the model, multiplier and stepping.  Black magic included,
 217          * to make the silicon step/rev numbers match the printed ones.
 218          */
 219
 220         switch (dir0_msn) {
 221                 unsigned char tmp;
 222
 223         case 0: /* Cx486SLC/DLC/SRx/DRx */
 224                 p = Cx486_name[dir0_lsn & 7];
 225                 break;
 226
 227         case 1: /* Cx486S/DX/DX2/DX4 */
 228                 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
 229                         : Cx486S_name[dir0_lsn & 3];
 230                 break;
 231
 232         case 2: /* 5x86 */
 233                 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
 234                 p = Cx86_cb+2;
 235                 break;
 236
 237         case 3: /* 6x86/6x86L */
 238                 Cx86_cb[1] = ' ';
 239                 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
 240                 if (dir1 > 0x21) { /* 686L */
 241                         Cx86_cb[0] = 'L';
 242                         p = Cx86_cb;
 243                         (c->x86_model)++;
 244                 } else             /* 686 */
 245                         p = Cx86_cb+1;
 246                 /* Emulate MTRRs using Cyrix's ARRs. */
 247                 set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
 248                 /* 6x86's contain this bug */
 249                 c->coma_bug = 1;
 250                 break;
 251
 252         case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
 253 #ifdef CONFIG_PCI
 254         {
 255                 u32 vendor, device;
 256                 /* It isn't really a PCI quirk directly, but the cure is the
 257                    same. The MediaGX has deep magic SMM stuff that handles the
 258                    SB emulation. It thows away the fifo on disable_dma() which
 259                    is wrong and ruins the audio.
 260
 261                    Bug2: VSA1 has a wrap bug so that using maximum sized DMA
 262                    causes bad things. According to NatSemi VSA2 has another
 263                    bug to do with 'hlt'. I've not seen any boards using VSA2
 264                    and X doesn't seem to support it either so who cares 8).
 265                    VSA1 we work around however.
 266                 */
 267
 268                 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
 269                 isa_dma_bridge_buggy = 2;
 270
 271                 /* We do this before the PCI layer is running. However we
 272                    are safe here as we know the bridge must be a Cyrix
 273                    companion and must be present */
 274                 vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
 275                 device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
 276
 277                 /*
 278                  *  The 5510/5520 companion chips have a funky PIT.
 279                  */
 280                 if (vendor == PCI_VENDOR_ID_CYRIX &&
 281          (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520))
 282                         mark_tsc_unstable("cyrix 5510/5520 detected");
 283         }
 284 #endif
 285                 c->x86_cache_size=16;   /* Yep 16K integrated cache thats it */
 286
 287                 /* GXm supports extended cpuid levels 'ala' AMD */
 288                 if (c->cpuid_level == 2) {
 289                         /* Enable cxMMX extensions (GX1 Datasheet 54) */
 290                         setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
 291
 292                         /*
 293                          * GXm : 0x30 ... 0x5f GXm  datasheet 51
 294                          * GXlv: 0x6x          GXlv datasheet 54
 295                          *  ?  : 0x7x
 296                          * GX1 : 0x8x          GX1  datasheet 56
 297                          */
 298                         if((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <=dir1 && dir1 <= 0x8f))
 299                                 geode_configure();
 300                         get_model_name(c);  /* get CPU marketing name */
 301                         return;
 302                 }
 303                 else {  /* MediaGX */
 304                         Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
 305                         p = Cx86_cb+2;
 306                         c->x86_model = (dir1 & 0x20) ? 1 : 2;
 307                 }
 308                 break;
 309
 310         case 5: /* 6x86MX/M II */
 311                 if (dir1 > 7)
 312                 {
 313                         dir0_msn++;  /* M II */
 314                         /* Enable MMX extensions (App note 108) */
 315                         setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
 316                 }
 317                 else
 318                 {
 319                         c->coma_bug = 1;      /* 6x86MX, it has the bug. */
 320                 }
 321                 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
 322                 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
 323                 p = Cx86_cb+tmp;
 324                 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
 325                         (c->x86_model)++;
 326                 /* Emulate MTRRs using Cyrix's ARRs. */
 327                 set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
 328                 break;
 329
 330         case 0xf:  /* Cyrix 486 without DEVID registers */
 331                 switch (dir0_lsn) {
 332                 case 0xd:  /* either a 486SLC or DLC w/o DEVID */
 333                         dir0_msn = 0;
 334                         p = Cx486_name[(c->hard_math) ? 1 : 0];
 335                         break;
 336
 337                 case 0xe:  /* a 486S A step */
 338                         dir0_msn = 0;
 339                         p = Cx486S_name[0];
 340                         break;
 341                 }
 342                 break;
 343
 344         default:  /* unknown (shouldn't happen, we know everyone ;-) */
 345                 dir0_msn = 7;
 346                 break;
 347         }
 348         strcpy(buf, Cx86_model[dir0_msn & 7]);
 349         if (p) strcat(buf, p);
 350         return;
 351 }
 352
 353 /*
 354  * Handle National Semiconductor branded processors
 355  */
 356 static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
 357 {
 358         /* There may be GX1 processors in the wild that are branded
 359          * NSC and not Cyrix.
 360          *
 361          * This function only handles the GX processor, and kicks every
 362          * thing else to the Cyrix init function above - that should
 363          * cover any processors that might have been branded differently
 364          * after NSC acquired Cyrix.
 365          *
 366          * If this breaks your GX1 horribly, please e-mail
 367          * info-linux@ldcmail.amd.com to tell us.
 368          */
 369
 370         /* Handle the GX (Formally known as the GX2) */
 371
 372         if (c->x86 == 5 && c->x86_model == 5)
 373                 display_cacheinfo(c);
 374         else
 375                 init_cyrix(c);
 376 }
 377
 378 /*
 379  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 380  * by the fact that they preserve the flags across the division of 5/2.
 381  * PII and PPro exhibit this behavior too, but they have cpuid available.
 382  */
 383
 384 /*
 385  * Perform the Cyrix 5/2 test. A Cyrix won't change
 386  * the flags, while other 486 chips will.
 387  */
 388 static inline int test_cyrix_52div(void)
 389 {
 390         unsigned int test;
 391
 392         __asm__ __volatile__(
 393              "sahf\n\t"         /* clear flags (%eax = 0x0005) */
 394              "div %b2\n\t"      /* divide 5 by 2 */
 395              "lahf"             /* store flags into %ah */
 396              : "=a" (test)
 397              : "0" (5), "q" (2)
 398              : "cc");
 399
 400         /* AH is 0x02 on Cyrix after the divide.. */
 401         return (unsigned char) (test >> 8) == 0x02;
 402 }
 403
 404 static void __cpuinit cyrix_identify(struct cpuinfo_x86 * c)
 405 {
 406         /* Detect Cyrix with disabled CPUID */
 407         if ( c->x86 == 4 && test_cyrix_52div() ) {
 408                 unsigned char dir0, dir1;
 409
 410                 strcpy(c->x86_vendor_id, "CyrixInstead");
 411                 c->x86_vendor = X86_VENDOR_CYRIX;
 412
 413                 /* Actually enable cpuid on the older cyrix */
 414
 415                 /* Retrieve CPU revisions */
 416
 417                 do_cyrix_devid(&dir0, &dir1);
 418
 419                 dir0>>=4;
 420
 421                 /* Check it is an affected model */
 422
 423                 if (dir0 == 5 || dir0 == 3)
 424                 {
 425                         unsigned char ccr3;
 426                         unsigned long flags;
 427                         printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
 428                         local_irq_save(flags);
 429                         ccr3 = getCx86(CX86_CCR3);
 430                         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN  */
 431                         setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80);  /* enable cpuid  */
 432                         setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
 433                         local_irq_restore(flags);
 434                 }
 435         }
 436 }
 437
 438 static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
 439         .c_vendor       = "Cyrix",
 440         .c_ident        = { "CyrixInstead" },
 441         .c_init         = init_cyrix,
 442         .c_identify     = cyrix_identify,
 443 };
 444
 445 int __init cyrix_init_cpu(void)
 446 {
 447         cpu_devs[X86_VENDOR_CYRIX] = &cyrix_cpu_dev;
 448         return 0;
 449 }
 450
 451 static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
 452         .c_vendor       = "NSC",
 453         .c_ident        = { "Geode by NSC" },
 454         .c_init         = init_nsc,
 455 };
 456
 457 int __init nsc_init_cpu(void)
 458 {
 459         cpu_devs[X86_VENDOR_NSC] = &nsc_cpu_dev;
 460         return 0;
 461 }
 462