1 #include <linux/init.h>
2 #include <linux/bitops.h>
5 #include <asm/processor.h>
10 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
11 * misexecution of code under Linux. Owners of such processors should
12 * contact AMD for precise details and a CPU swap.
14 * See http://www.multimania.com/poulot/k6bug.html
15 * http://www.amd.com/K6/k6docs/revgd.html
17 * The following test is erm.. interesting. AMD neglected to up
18 * the chip setting when fixing the bug but they also tweaked some
19 * performance at the same time..
22 extern void vide(void);
23 __asm__(".align 4\nvide: ret");
25 #define ENABLE_C1E_MASK 0x18000000
26 #define CPUID_PROCESSOR_SIGNATURE 1
27 #define CPUID_XFAM 0x0ff00000
28 #define CPUID_XFAM_K8 0x00000000
29 #define CPUID_XFAM_10H 0x00100000
30 #define CPUID_XFAM_11H 0x00200000
31 #define CPUID_XMOD 0x000f0000
32 #define CPUID_XMOD_REV_F 0x00040000
34 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
35 static __cpuinit
int amd_apic_timer_broken(void)
38 u32 eax
= cpuid_eax(CPUID_PROCESSOR_SIGNATURE
);
39 switch (eax
& CPUID_XFAM
) {
41 if ((eax
& CPUID_XMOD
) < CPUID_XMOD_REV_F
)
45 rdmsr(MSR_K8_ENABLE_C1E
, lo
, hi
);
46 if (lo
& ENABLE_C1E_MASK
)
50 /* err on the side of caution */
56 int force_mwait __cpuinitdata
;
58 static void __cpuinit
init_amd(struct cpuinfo_x86
*c
)
61 int mbytes
= num_physpages
>> (20-PAGE_SHIFT
);
65 unsigned long long value
;
67 /* Disable TLB flush filter by setting HWCR.FFDIS on K8
68 * bit 6 of msr C001_0015
70 * Errata 63 for SH-B3 steppings
71 * Errata 122 for all steppings (F+ have it disabled by default)
74 rdmsrl(MSR_K7_HWCR
, value
);
76 wrmsrl(MSR_K7_HWCR
, value
);
81 * FIXME: We should handle the K5 here. Set up the write
82 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
86 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
87 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
88 clear_bit(0*32+31, c
->x86_capability
);
90 r
= get_model_name(c
);
96 * General Systems BIOSen alias the cpu frequency registers
97 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
98 * drivers subsequently pokes it, and changes the CPU speed.
99 * Workaround : Remove the unneeded alias.
101 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
102 #define CBAR_ENB (0x80000000)
103 #define CBAR_KEY (0X000000CB)
104 if (c
->x86_model
==9 || c
->x86_model
== 10) {
105 if (inl (CBAR
) & CBAR_ENB
)
106 outl (0 | CBAR_KEY
, CBAR
);
110 if( c
->x86_model
< 6 )
112 /* Based on AMD doc 20734R - June 2000 */
113 if ( c
->x86_model
== 0 ) {
114 clear_bit(X86_FEATURE_APIC
, c
->x86_capability
);
115 set_bit(X86_FEATURE_PGE
, c
->x86_capability
);
120 if ( c
->x86_model
== 6 && c
->x86_mask
== 1 ) {
121 const int K6_BUG_LOOP
= 1000000;
123 void (*f_vide
)(void);
126 printk(KERN_INFO
"AMD K6 stepping B detected - ");
129 * It looks like AMD fixed the 2.6.2 bug and improved indirect
130 * calls at the same time.
141 if (d
> 20*K6_BUG_LOOP
)
142 printk("system stability may be impaired when more than 32 MB are used.\n");
144 printk("probably OK (after B9730xxxx).\n");
145 printk(KERN_INFO
"Please see http://membres.lycos.fr/poulot/k6bug.html\n");
148 /* K6 with old style WHCR */
149 if (c
->x86_model
< 8 ||
150 (c
->x86_model
== 8 && c
->x86_mask
< 8)) {
151 /* We can only write allocate on the low 508Mb */
155 rdmsr(MSR_K6_WHCR
, l
, h
);
156 if ((l
&0x0000FFFF)==0) {
158 l
=(1<<0)|((mbytes
/4)<<1);
159 local_irq_save(flags
);
161 wrmsr(MSR_K6_WHCR
, l
, h
);
162 local_irq_restore(flags
);
163 printk(KERN_INFO
"Enabling old style K6 write allocation for %d Mb\n",
169 if ((c
->x86_model
== 8 && c
->x86_mask
>7) ||
170 c
->x86_model
== 9 || c
->x86_model
== 13) {
171 /* The more serious chips .. */
176 rdmsr(MSR_K6_WHCR
, l
, h
);
177 if ((l
&0xFFFF0000)==0) {
179 l
=((mbytes
>>2)<<22)|(1<<16);
180 local_irq_save(flags
);
182 wrmsr(MSR_K6_WHCR
, l
, h
);
183 local_irq_restore(flags
);
184 printk(KERN_INFO
"Enabling new style K6 write allocation for %d Mb\n",
188 /* Set MTRR capability flag if appropriate */
189 if (c
->x86_model
== 13 || c
->x86_model
== 9 ||
190 (c
->x86_model
== 8 && c
->x86_mask
>= 8))
191 set_bit(X86_FEATURE_K6_MTRR
, c
->x86_capability
);
195 if (c
->x86_model
== 10) {
196 /* AMD Geode LX is model 10 */
197 /* placeholder for any needed mods */
201 case 6: /* An Athlon/Duron */
203 /* Bit 15 of Athlon specific MSR 15, needs to be 0
204 * to enable SSE on Palomino/Morgan/Barton CPU's.
205 * If the BIOS didn't enable it already, enable it here.
207 if (c
->x86_model
>= 6 && c
->x86_model
<= 10) {
208 if (!cpu_has(c
, X86_FEATURE_XMM
)) {
209 printk(KERN_INFO
"Enabling disabled K7/SSE Support.\n");
210 rdmsr(MSR_K7_HWCR
, l
, h
);
212 wrmsr(MSR_K7_HWCR
, l
, h
);
213 set_bit(X86_FEATURE_XMM
, c
->x86_capability
);
217 /* It's been determined by AMD that Athlons since model 8 stepping 1
218 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
219 * As per AMD technical note 27212 0.2
221 if ((c
->x86_model
== 8 && c
->x86_mask
>=1) || (c
->x86_model
> 8)) {
222 rdmsr(MSR_K7_CLK_CTL
, l
, h
);
223 if ((l
& 0xfff00000) != 0x20000000) {
224 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l
,
225 ((l
& 0x000fffff)|0x20000000));
226 wrmsr(MSR_K7_CLK_CTL
, (l
& 0x000fffff)|0x20000000, h
);
234 set_bit(X86_FEATURE_K8
, c
->x86_capability
);
237 set_bit(X86_FEATURE_K7
, c
->x86_capability
);
241 set_bit(X86_FEATURE_FXSAVE_LEAK
, c
->x86_capability
);
243 display_cacheinfo(c
);
245 if (cpuid_eax(0x80000000) >= 0x80000008) {
246 c
->x86_max_cores
= (cpuid_ecx(0x80000008) & 0xff) + 1;
249 if (cpuid_eax(0x80000000) >= 0x80000007) {
250 c
->x86_power
= cpuid_edx(0x80000007);
251 if (c
->x86_power
& (1<<8))
252 set_bit(X86_FEATURE_CONSTANT_TSC
, c
->x86_capability
);
257 * On a AMD multi core setup the lower bits of the APIC id
258 * distingush the cores.
260 if (c
->x86_max_cores
> 1) {
261 int cpu
= smp_processor_id();
262 unsigned bits
= (cpuid_ecx(0x80000008) >> 12) & 0xf;
265 while ((1 << bits
) < c
->x86_max_cores
)
268 c
->cpu_core_id
= c
->phys_proc_id
& ((1<<bits
)-1);
269 c
->phys_proc_id
>>= bits
;
270 printk(KERN_INFO
"CPU %d(%d) -> Core %d\n",
271 cpu
, c
->x86_max_cores
, c
->cpu_core_id
);
275 if (cpuid_eax(0x80000000) >= 0x80000006)
276 num_cache_leaves
= 3;
278 if (amd_apic_timer_broken())
279 set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN
, c
->x86_capability
);
281 if (c
->x86
== 0x10 && !force_mwait
)
282 clear_bit(X86_FEATURE_MWAIT
, c
->x86_capability
);
285 static unsigned int __cpuinit
amd_size_cache(struct cpuinfo_x86
* c
, unsigned int size
)
287 /* AMD errata T13 (order #21922) */
289 if (c
->x86_model
== 3 && c
->x86_mask
== 0) /* Duron Rev A0 */
291 if (c
->x86_model
== 4 &&
292 (c
->x86_mask
==0 || c
->x86_mask
==1)) /* Tbird rev A1/A2 */
298 static struct cpu_dev amd_cpu_dev __cpuinitdata
= {
300 .c_ident
= { "AuthenticAMD" },
302 { .vendor
= X86_VENDOR_AMD
, .family
= 4, .model_names
=
314 .c_size_cache
= amd_size_cache
,
317 int __init
amd_init_cpu(void)
319 cpu_devs
[X86_VENDOR_AMD
] = &amd_cpu_dev
;