2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
33 #include <linux/ftrace.h>
35 #include <asm/atomic.h>
38 #include <asm/mpspec.h>
40 #include <asm/arch_hooks.h>
42 #include <asm/pgalloc.h>
43 #include <asm/i8253.h>
46 #include <asm/proto.h>
47 #include <asm/timex.h>
49 #include <asm/i8259.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
58 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
59 # error SPURIOUS_APIC_VECTOR definition error
64 * Knob to control our willingness to enable the local APIC.
68 static int force_enable_local_apic
;
70 * APIC command line parameters
72 static int __init
parse_lapic(char *arg
)
74 force_enable_local_apic
= 1;
77 early_param("lapic", parse_lapic
);
78 /* Local APIC was disabled by the BIOS and enabled by the kernel */
79 static int enabled_via_apicbase
;
84 static int apic_calibrate_pmtmr __initdata
;
85 static __init
int setup_apicpmtimer(char *s
)
87 apic_calibrate_pmtmr
= 1;
91 __setup("apicpmtimer", setup_apicpmtimer
);
100 /* x2apic enabled before OS handover */
101 int x2apic_preenabled
;
103 static __init
int setup_nox2apic(char *str
)
106 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
109 early_param("nox2apic", setup_nox2apic
);
112 unsigned long mp_lapic_addr
;
114 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
115 static int disable_apic_timer __cpuinitdata
;
116 /* Local APIC timer works in C2 */
117 int local_apic_timer_c2_ok
;
118 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
120 int first_system_vector
= 0xfe;
122 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
125 * Debug level, exported for io_apic.c
127 unsigned int apic_verbosity
;
131 /* Have we found an MP table */
132 int smp_found_config
;
134 static struct resource lapic_resource
= {
135 .name
= "Local APIC",
136 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
139 static unsigned int calibration_result
;
141 static int lapic_next_event(unsigned long delta
,
142 struct clock_event_device
*evt
);
143 static void lapic_timer_setup(enum clock_event_mode mode
,
144 struct clock_event_device
*evt
);
145 static void lapic_timer_broadcast(const struct cpumask
*mask
);
146 static void apic_pm_activate(void);
149 * The local apic timer can be used for any function which is CPU local.
151 static struct clock_event_device lapic_clockevent
= {
153 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
154 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
156 .set_mode
= lapic_timer_setup
,
157 .set_next_event
= lapic_next_event
,
158 .broadcast
= lapic_timer_broadcast
,
162 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
164 static unsigned long apic_phys
;
167 * Get the LAPIC version
169 static inline int lapic_get_version(void)
171 return GET_APIC_VERSION(apic_read(APIC_LVR
));
175 * Check, if the APIC is integrated or a separate chip
177 static inline int lapic_is_integrated(void)
182 return APIC_INTEGRATED(lapic_get_version());
187 * Check, whether this is a modern or a first generation APIC
189 static int modern_apic(void)
191 /* AMD systems use old APIC versions, so check the CPU */
192 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
193 boot_cpu_data
.x86
>= 0xf)
195 return lapic_get_version() >= 0x14;
199 * Paravirt kernels also might be using these below ops. So we still
200 * use generic apic_read()/apic_write(), which might be pointing to different
201 * ops in PARAVIRT case.
203 void xapic_wait_icr_idle(void)
205 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
209 u32
safe_xapic_wait_icr_idle(void)
216 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
220 } while (timeout
++ < 1000);
225 void xapic_icr_write(u32 low
, u32 id
)
227 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
228 apic_write(APIC_ICR
, low
);
231 u64
xapic_icr_read(void)
235 icr2
= apic_read(APIC_ICR2
);
236 icr1
= apic_read(APIC_ICR
);
238 return icr1
| ((u64
)icr2
<< 32);
241 static struct apic_ops xapic_ops
= {
242 .read
= native_apic_mem_read
,
243 .write
= native_apic_mem_write
,
244 .icr_read
= xapic_icr_read
,
245 .icr_write
= xapic_icr_write
,
246 .wait_icr_idle
= xapic_wait_icr_idle
,
247 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
250 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
251 EXPORT_SYMBOL_GPL(apic_ops
);
254 static void x2apic_wait_icr_idle(void)
256 /* no need to wait for icr idle in x2apic */
260 static u32
safe_x2apic_wait_icr_idle(void)
262 /* no need to wait for icr idle in x2apic */
266 void x2apic_icr_write(u32 low
, u32 id
)
268 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
271 u64
x2apic_icr_read(void)
275 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
279 static struct apic_ops x2apic_ops
= {
280 .read
= native_apic_msr_read
,
281 .write
= native_apic_msr_write
,
282 .icr_read
= x2apic_icr_read
,
283 .icr_write
= x2apic_icr_write
,
284 .wait_icr_idle
= x2apic_wait_icr_idle
,
285 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
290 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
292 void __cpuinit
enable_NMI_through_LVT0(void)
296 /* unmask and set to NMI */
299 /* Level triggered for 82489DX (32bit mode) */
300 if (!lapic_is_integrated())
301 v
|= APIC_LVT_LEVEL_TRIGGER
;
303 apic_write(APIC_LVT0
, v
);
308 * get_physical_broadcast - Get number of physical broadcast IDs
310 int get_physical_broadcast(void)
312 return modern_apic() ? 0xff : 0xf;
317 * lapic_get_maxlvt - get the maximum number of local vector table entries
319 int lapic_get_maxlvt(void)
323 v
= apic_read(APIC_LVR
);
325 * - we always have APIC integrated on 64bit mode
326 * - 82489DXs do not report # of LVT entries
328 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
336 #define APIC_DIVISOR 16
339 * This function sets up the local APIC timer, with a timeout of
340 * 'clocks' APIC bus clock. During calibration we actually call
341 * this function twice on the boot CPU, once with a bogus timeout
342 * value, second time for real. The other (noncalibrating) CPUs
343 * call this function only once, with the real, calibrated value.
345 * We do reads before writes even if unnecessary, to get around the
346 * P5 APIC double write bug.
348 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
350 unsigned int lvtt_value
, tmp_value
;
352 lvtt_value
= LOCAL_TIMER_VECTOR
;
354 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
355 if (!lapic_is_integrated())
356 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
359 lvtt_value
|= APIC_LVT_MASKED
;
361 apic_write(APIC_LVTT
, lvtt_value
);
366 tmp_value
= apic_read(APIC_TDCR
);
367 apic_write(APIC_TDCR
,
368 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
372 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
376 * Setup extended LVT, AMD specific (K8, family 10h)
378 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
379 * MCE interrupts are supported. Thus MCE offset must be set to 0.
381 * If mask=1, the LVT entry does not generate interrupts while mask=0
382 * enables the vector. See also the BKDGs.
385 #define APIC_EILVT_LVTOFF_MCE 0
386 #define APIC_EILVT_LVTOFF_IBS 1
388 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
390 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
391 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
396 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
398 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
399 return APIC_EILVT_LVTOFF_MCE
;
402 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
404 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
405 return APIC_EILVT_LVTOFF_IBS
;
407 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
410 * Program the next event, relative to now
412 static int lapic_next_event(unsigned long delta
,
413 struct clock_event_device
*evt
)
415 apic_write(APIC_TMICT
, delta
);
420 * Setup the lapic timer in periodic or oneshot mode
422 static void lapic_timer_setup(enum clock_event_mode mode
,
423 struct clock_event_device
*evt
)
428 /* Lapic used as dummy for broadcast ? */
429 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
432 local_irq_save(flags
);
435 case CLOCK_EVT_MODE_PERIODIC
:
436 case CLOCK_EVT_MODE_ONESHOT
:
437 __setup_APIC_LVTT(calibration_result
,
438 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
440 case CLOCK_EVT_MODE_UNUSED
:
441 case CLOCK_EVT_MODE_SHUTDOWN
:
442 v
= apic_read(APIC_LVTT
);
443 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
444 apic_write(APIC_LVTT
, v
);
445 apic_write(APIC_TMICT
, 0xffffffff);
447 case CLOCK_EVT_MODE_RESUME
:
448 /* Nothing to do here */
452 local_irq_restore(flags
);
456 * Local APIC timer broadcast function
458 static void lapic_timer_broadcast(const struct cpumask
*mask
)
461 send_IPI_mask(*mask
, LOCAL_TIMER_VECTOR
);
466 * Setup the local APIC timer for this CPU. Copy the initilized values
467 * of the boot CPU and register the clock event in the framework.
469 static void __cpuinit
setup_APIC_timer(void)
471 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
473 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
474 levt
->cpumask
= cpumask_of(smp_processor_id());
476 clockevents_register_device(levt
);
480 * In this functions we calibrate APIC bus clocks to the external timer.
482 * We want to do the calibration only once since we want to have local timer
483 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
486 * This was previously done by reading the PIT/HPET and waiting for a wrap
487 * around to find out, that a tick has elapsed. I have a box, where the PIT
488 * readout is broken, so it never gets out of the wait loop again. This was
489 * also reported by others.
491 * Monitoring the jiffies value is inaccurate and the clockevents
492 * infrastructure allows us to do a simple substitution of the interrupt
495 * The calibration routine also uses the pm_timer when possible, as the PIT
496 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
497 * back to normal later in the boot process).
500 #define LAPIC_CAL_LOOPS (HZ/10)
502 static __initdata
int lapic_cal_loops
= -1;
503 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
504 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
505 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
506 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
509 * Temporary interrupt handler.
511 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
513 unsigned long long tsc
= 0;
514 long tapic
= apic_read(APIC_TMCCT
);
515 unsigned long pm
= acpi_pm_read_early();
520 switch (lapic_cal_loops
++) {
522 lapic_cal_t1
= tapic
;
523 lapic_cal_tsc1
= tsc
;
525 lapic_cal_j1
= jiffies
;
528 case LAPIC_CAL_LOOPS
:
529 lapic_cal_t2
= tapic
;
530 lapic_cal_tsc2
= tsc
;
531 if (pm
< lapic_cal_pm1
)
532 pm
+= ACPI_PM_OVRRUN
;
534 lapic_cal_j2
= jiffies
;
539 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
541 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
542 const long pm_thresh
= pm_100ms
/ 100;
546 #ifndef CONFIG_X86_PM_TIMER
550 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
552 /* Check, if the PM timer is available */
556 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
558 if (deltapm
> (pm_100ms
- pm_thresh
) &&
559 deltapm
< (pm_100ms
+ pm_thresh
)) {
560 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
562 res
= (((u64
)deltapm
) * mult
) >> 22;
563 do_div(res
, 1000000);
564 pr_warning("APIC calibration not consistent "
565 "with PM Timer: %ldms instead of 100ms\n",
567 /* Correct the lapic counter value */
568 res
= (((u64
)(*delta
)) * pm_100ms
);
569 do_div(res
, deltapm
);
570 pr_info("APIC delta adjusted to PM-Timer: "
571 "%lu (%ld)\n", (unsigned long)res
, *delta
);
578 static int __init
calibrate_APIC_clock(void)
580 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
581 void (*real_handler
)(struct clock_event_device
*dev
);
582 unsigned long deltaj
;
584 int pm_referenced
= 0;
588 /* Replace the global interrupt handler */
589 real_handler
= global_clock_event
->event_handler
;
590 global_clock_event
->event_handler
= lapic_cal_handler
;
593 * Setup the APIC counter to maximum. There is no way the lapic
594 * can underflow in the 100ms detection time frame
596 __setup_APIC_LVTT(0xffffffff, 0, 0);
598 /* Let the interrupts run */
601 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
606 /* Restore the real event handler */
607 global_clock_event
->event_handler
= real_handler
;
609 /* Build delta t1-t2 as apic timer counts down */
610 delta
= lapic_cal_t1
- lapic_cal_t2
;
611 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
613 /* we trust the PM based calibration if possible */
614 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
617 /* Calculate the scaled math multiplication factor */
618 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
619 lapic_clockevent
.shift
);
620 lapic_clockevent
.max_delta_ns
=
621 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
622 lapic_clockevent
.min_delta_ns
=
623 clockevent_delta2ns(0xF, &lapic_clockevent
);
625 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
627 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
628 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
629 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
633 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
634 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
636 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
637 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
640 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
642 calibration_result
/ (1000000 / HZ
),
643 calibration_result
% (1000000 / HZ
));
646 * Do a sanity check on the APIC calibration result
648 if (calibration_result
< (1000000 / HZ
)) {
650 pr_warning("APIC frequency too slow, disabling apic timer\n");
654 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
657 * PM timer calibration failed or not turned on
658 * so lets try APIC timer based calibration
660 if (!pm_referenced
) {
661 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
664 * Setup the apic timer manually
666 levt
->event_handler
= lapic_cal_handler
;
667 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
668 lapic_cal_loops
= -1;
670 /* Let the interrupts run */
673 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
676 /* Stop the lapic timer */
677 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
680 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
681 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
683 /* Check, if the jiffies result is consistent */
684 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
685 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
687 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
691 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
692 pr_warning("APIC timer disabled due to verification failure.\n");
700 * Setup the boot APIC
702 * Calibrate and verify the result.
704 void __init
setup_boot_APIC_clock(void)
707 * The local apic timer can be disabled via the kernel
708 * commandline or from the CPU detection code. Register the lapic
709 * timer as a dummy clock event source on SMP systems, so the
710 * broadcast mechanism is used. On UP systems simply ignore it.
712 if (disable_apic_timer
) {
713 pr_info("Disabling APIC timer\n");
714 /* No broadcast on UP ! */
715 if (num_possible_cpus() > 1) {
716 lapic_clockevent
.mult
= 1;
722 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
723 "calibrating APIC timer ...\n");
725 if (calibrate_APIC_clock()) {
726 /* No broadcast on UP ! */
727 if (num_possible_cpus() > 1)
733 * If nmi_watchdog is set to IO_APIC, we need the
734 * PIT/HPET going. Otherwise register lapic as a dummy
737 if (nmi_watchdog
!= NMI_IO_APIC
)
738 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
740 pr_warning("APIC timer registered as dummy,"
741 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
743 /* Setup the lapic or request the broadcast */
747 void __cpuinit
setup_secondary_APIC_clock(void)
753 * The guts of the apic timer interrupt
755 static void local_apic_timer_interrupt(void)
757 int cpu
= smp_processor_id();
758 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
761 * Normally we should not be here till LAPIC has been initialized but
762 * in some cases like kdump, its possible that there is a pending LAPIC
763 * timer interrupt from previous kernel's context and is delivered in
764 * new kernel the moment interrupts are enabled.
766 * Interrupts are enabled early and LAPIC is setup much later, hence
767 * its possible that when we get here evt->event_handler is NULL.
768 * Check for event_handler being NULL and discard the interrupt as
771 if (!evt
->event_handler
) {
772 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
774 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
779 * the NMI deadlock-detector uses this.
781 inc_irq_stat(apic_timer_irqs
);
783 evt
->event_handler(evt
);
787 * Local APIC timer interrupt. This is the most natural way for doing
788 * local interrupts, but local timer interrupts can be emulated by
789 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
791 * [ if a single-CPU system runs an SMP kernel then we call the local
792 * interrupt as well. Thus we cannot inline the local irq ... ]
794 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
796 struct pt_regs
*old_regs
= set_irq_regs(regs
);
799 * NOTE! We'd better ACK the irq immediately,
800 * because timer handling can be slow.
804 * update_process_times() expects us to have done irq_enter().
805 * Besides, if we don't timer interrupts ignore the global
806 * interrupt lock, which is the WrongThing (tm) to do.
810 local_apic_timer_interrupt();
813 set_irq_regs(old_regs
);
816 int setup_profiling_timer(unsigned int multiplier
)
822 * Local APIC start and shutdown
826 * clear_local_APIC - shutdown the local APIC
828 * This is called, when a CPU is disabled and before rebooting, so the state of
829 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
830 * leftovers during boot.
832 void clear_local_APIC(void)
837 /* APIC hasn't been mapped yet */
841 maxlvt
= lapic_get_maxlvt();
843 * Masking an LVT entry can trigger a local APIC error
844 * if the vector is zero. Mask LVTERR first to prevent this.
847 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
848 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
851 * Careful: we have to set masks only first to deassert
852 * any level-triggered sources.
854 v
= apic_read(APIC_LVTT
);
855 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
856 v
= apic_read(APIC_LVT0
);
857 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
858 v
= apic_read(APIC_LVT1
);
859 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
861 v
= apic_read(APIC_LVTPC
);
862 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
865 /* lets not touch this if we didn't frob it */
866 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
868 v
= apic_read(APIC_LVTTHMR
);
869 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
873 * Clean APIC state for other OSs:
875 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
876 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
877 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
879 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
881 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
883 /* Integrated APIC (!82489DX) ? */
884 if (lapic_is_integrated()) {
886 /* Clear ESR due to Pentium errata 3AP and 11AP */
887 apic_write(APIC_ESR
, 0);
893 * disable_local_APIC - clear and disable the local APIC
895 void disable_local_APIC(void)
902 * Disable APIC (implies clearing of registers
905 value
= apic_read(APIC_SPIV
);
906 value
&= ~APIC_SPIV_APIC_ENABLED
;
907 apic_write(APIC_SPIV
, value
);
911 * When LAPIC was disabled by the BIOS and enabled by the kernel,
912 * restore the disabled state.
914 if (enabled_via_apicbase
) {
917 rdmsr(MSR_IA32_APICBASE
, l
, h
);
918 l
&= ~MSR_IA32_APICBASE_ENABLE
;
919 wrmsr(MSR_IA32_APICBASE
, l
, h
);
925 * If Linux enabled the LAPIC against the BIOS default disable it down before
926 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
927 * not power-off. Additionally clear all LVT entries before disable_local_APIC
928 * for the case where Linux didn't enable the LAPIC.
930 void lapic_shutdown(void)
937 local_irq_save(flags
);
940 if (!enabled_via_apicbase
)
944 disable_local_APIC();
947 local_irq_restore(flags
);
951 * This is to verify that we're looking at a real local APIC.
952 * Check these against your board if the CPUs aren't getting
953 * started for no apparent reason.
955 int __init
verify_local_APIC(void)
957 unsigned int reg0
, reg1
;
960 * The version register is read-only in a real APIC.
962 reg0
= apic_read(APIC_LVR
);
963 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
964 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
965 reg1
= apic_read(APIC_LVR
);
966 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
969 * The two version reads above should print the same
970 * numbers. If the second one is different, then we
971 * poke at a non-APIC.
977 * Check if the version looks reasonably.
979 reg1
= GET_APIC_VERSION(reg0
);
980 if (reg1
== 0x00 || reg1
== 0xff)
982 reg1
= lapic_get_maxlvt();
983 if (reg1
< 0x02 || reg1
== 0xff)
987 * The ID register is read/write in a real APIC.
989 reg0
= apic_read(APIC_ID
);
990 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
991 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
992 reg1
= apic_read(APIC_ID
);
993 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
994 apic_write(APIC_ID
, reg0
);
995 if (reg1
!= (reg0
^ APIC_ID_MASK
))
999 * The next two are just to see if we have sane values.
1000 * They're only really relevant if we're in Virtual Wire
1001 * compatibility mode, but most boxes are anymore.
1003 reg0
= apic_read(APIC_LVT0
);
1004 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1005 reg1
= apic_read(APIC_LVT1
);
1006 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1012 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1014 void __init
sync_Arb_IDs(void)
1017 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1020 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1026 apic_wait_icr_idle();
1028 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1029 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1030 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1034 * An initial setup of the virtual wire mode.
1036 void __init
init_bsp_APIC(void)
1041 * Don't do the setup now if we have a SMP BIOS as the
1042 * through-I/O-APIC virtual wire mode might be active.
1044 if (smp_found_config
|| !cpu_has_apic
)
1048 * Do not trust the local APIC being empty at bootup.
1055 value
= apic_read(APIC_SPIV
);
1056 value
&= ~APIC_VECTOR_MASK
;
1057 value
|= APIC_SPIV_APIC_ENABLED
;
1059 #ifdef CONFIG_X86_32
1060 /* This bit is reserved on P4/Xeon and should be cleared */
1061 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1062 (boot_cpu_data
.x86
== 15))
1063 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1066 value
|= APIC_SPIV_FOCUS_DISABLED
;
1067 value
|= SPURIOUS_APIC_VECTOR
;
1068 apic_write(APIC_SPIV
, value
);
1071 * Set up the virtual wire mode.
1073 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1074 value
= APIC_DM_NMI
;
1075 if (!lapic_is_integrated()) /* 82489DX */
1076 value
|= APIC_LVT_LEVEL_TRIGGER
;
1077 apic_write(APIC_LVT1
, value
);
1080 static void __cpuinit
lapic_setup_esr(void)
1082 unsigned int oldvalue
, value
, maxlvt
;
1084 if (!lapic_is_integrated()) {
1085 pr_info("No ESR for 82489DX.\n");
1091 * Something untraceable is creating bad interrupts on
1092 * secondary quads ... for the moment, just leave the
1093 * ESR disabled - we can't do anything useful with the
1094 * errors anyway - mbligh
1096 pr_info("Leaving ESR disabled.\n");
1100 maxlvt
= lapic_get_maxlvt();
1101 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1102 apic_write(APIC_ESR
, 0);
1103 oldvalue
= apic_read(APIC_ESR
);
1105 /* enables sending errors */
1106 value
= ERROR_APIC_VECTOR
;
1107 apic_write(APIC_LVTERR
, value
);
1110 * spec says clear errors after enabling vector.
1113 apic_write(APIC_ESR
, 0);
1114 value
= apic_read(APIC_ESR
);
1115 if (value
!= oldvalue
)
1116 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1117 "vector: 0x%08x after: 0x%08x\n",
1123 * setup_local_APIC - setup the local APIC
1125 void __cpuinit
setup_local_APIC(void)
1130 #ifdef CONFIG_X86_32
1131 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1132 if (lapic_is_integrated() && esr_disable
) {
1133 apic_write(APIC_ESR
, 0);
1134 apic_write(APIC_ESR
, 0);
1135 apic_write(APIC_ESR
, 0);
1136 apic_write(APIC_ESR
, 0);
1143 * Double-check whether this APIC is really registered.
1144 * This is meaningless in clustered apic mode, so we skip it.
1146 if (!apic_id_registered())
1150 * Intel recommends to set DFR, LDR and TPR before enabling
1151 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1152 * document number 292116). So here it goes...
1157 * Set Task Priority to 'accept all'. We never change this
1160 value
= apic_read(APIC_TASKPRI
);
1161 value
&= ~APIC_TPRI_MASK
;
1162 apic_write(APIC_TASKPRI
, value
);
1165 * After a crash, we no longer service the interrupts and a pending
1166 * interrupt from previous kernel might still have ISR bit set.
1168 * Most probably by now CPU has serviced that pending interrupt and
1169 * it might not have done the ack_APIC_irq() because it thought,
1170 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1171 * does not clear the ISR bit and cpu thinks it has already serivced
1172 * the interrupt. Hence a vector might get locked. It was noticed
1173 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1175 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1176 value
= apic_read(APIC_ISR
+ i
*0x10);
1177 for (j
= 31; j
>= 0; j
--) {
1184 * Now that we are all set up, enable the APIC
1186 value
= apic_read(APIC_SPIV
);
1187 value
&= ~APIC_VECTOR_MASK
;
1191 value
|= APIC_SPIV_APIC_ENABLED
;
1193 #ifdef CONFIG_X86_32
1195 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1196 * certain networking cards. If high frequency interrupts are
1197 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1198 * entry is masked/unmasked at a high rate as well then sooner or
1199 * later IOAPIC line gets 'stuck', no more interrupts are received
1200 * from the device. If focus CPU is disabled then the hang goes
1203 * [ This bug can be reproduced easily with a level-triggered
1204 * PCI Ne2000 networking cards and PII/PIII processors, dual
1208 * Actually disabling the focus CPU check just makes the hang less
1209 * frequent as it makes the interrupt distributon model be more
1210 * like LRU than MRU (the short-term load is more even across CPUs).
1211 * See also the comment in end_level_ioapic_irq(). --macro
1215 * - enable focus processor (bit==0)
1216 * - 64bit mode always use processor focus
1217 * so no need to set it
1219 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1223 * Set spurious IRQ vector
1225 value
|= SPURIOUS_APIC_VECTOR
;
1226 apic_write(APIC_SPIV
, value
);
1229 * Set up LVT0, LVT1:
1231 * set up through-local-APIC on the BP's LINT0. This is not
1232 * strictly necessary in pure symmetric-IO mode, but sometimes
1233 * we delegate interrupts to the 8259A.
1236 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1238 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1239 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1240 value
= APIC_DM_EXTINT
;
1241 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1242 smp_processor_id());
1244 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1245 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1246 smp_processor_id());
1248 apic_write(APIC_LVT0
, value
);
1251 * only the BP should see the LINT1 NMI signal, obviously.
1253 if (!smp_processor_id())
1254 value
= APIC_DM_NMI
;
1256 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1257 if (!lapic_is_integrated()) /* 82489DX */
1258 value
|= APIC_LVT_LEVEL_TRIGGER
;
1259 apic_write(APIC_LVT1
, value
);
1264 void __cpuinit
end_local_APIC_setup(void)
1268 #ifdef CONFIG_X86_32
1271 /* Disable the local apic timer */
1272 value
= apic_read(APIC_LVTT
);
1273 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1274 apic_write(APIC_LVTT
, value
);
1278 setup_apic_nmi_watchdog(NULL
);
1283 void check_x2apic(void)
1287 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1289 if (msr
& X2APIC_ENABLE
) {
1290 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1291 x2apic_preenabled
= x2apic
= 1;
1292 apic_ops
= &x2apic_ops
;
1296 void enable_x2apic(void)
1300 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1301 if (!(msr
& X2APIC_ENABLE
)) {
1302 pr_info("Enabling x2apic\n");
1303 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1307 void __init
enable_IR_x2apic(void)
1309 #ifdef CONFIG_INTR_REMAP
1311 unsigned long flags
;
1313 if (!cpu_has_x2apic
)
1316 if (!x2apic_preenabled
&& disable_x2apic
) {
1317 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1318 "because of nox2apic\n");
1322 if (x2apic_preenabled
&& disable_x2apic
)
1323 panic("Bios already enabled x2apic, can't enforce nox2apic");
1325 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1326 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1327 "because of skipping io-apic setup\n");
1331 ret
= dmar_table_init();
1333 pr_info("dmar_table_init() failed with %d:\n", ret
);
1335 if (x2apic_preenabled
)
1336 panic("x2apic enabled by bios. But IR enabling failed");
1338 pr_info("Not enabling x2apic,Intr-remapping\n");
1342 local_irq_save(flags
);
1345 ret
= save_mask_IO_APIC_setup();
1347 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1351 ret
= enable_intr_remapping(1);
1353 if (ret
&& x2apic_preenabled
) {
1354 local_irq_restore(flags
);
1355 panic("x2apic enabled by bios. But IR enabling failed");
1363 apic_ops
= &x2apic_ops
;
1370 * IR enabling failed
1372 restore_IO_APIC_setup();
1374 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1378 local_irq_restore(flags
);
1381 if (!x2apic_preenabled
)
1382 pr_info("Enabled x2apic and interrupt-remapping\n");
1384 pr_info("Enabled Interrupt-remapping\n");
1386 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1388 if (!cpu_has_x2apic
)
1391 if (x2apic_preenabled
)
1392 panic("x2apic enabled prior OS handover,"
1393 " enable CONFIG_INTR_REMAP");
1395 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1401 #endif /* HAVE_X2APIC */
1403 #ifdef CONFIG_X86_64
1405 * Detect and enable local APICs on non-SMP boards.
1406 * Original code written by Keir Fraser.
1407 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1408 * not correctly set up (usually the APIC timer won't work etc.)
1410 static int __init
detect_init_APIC(void)
1412 if (!cpu_has_apic
) {
1413 pr_info("No local APIC present\n");
1417 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1418 boot_cpu_physical_apicid
= 0;
1423 * Detect and initialize APIC
1425 static int __init
detect_init_APIC(void)
1429 /* Disabled by kernel option? */
1433 switch (boot_cpu_data
.x86_vendor
) {
1434 case X86_VENDOR_AMD
:
1435 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1436 (boot_cpu_data
.x86
== 15))
1439 case X86_VENDOR_INTEL
:
1440 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1441 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1448 if (!cpu_has_apic
) {
1450 * Over-ride BIOS and try to enable the local APIC only if
1451 * "lapic" specified.
1453 if (!force_enable_local_apic
) {
1454 pr_info("Local APIC disabled by BIOS -- "
1455 "you can enable it with \"lapic\"\n");
1459 * Some BIOSes disable the local APIC in the APIC_BASE
1460 * MSR. This can only be done in software for Intel P6 or later
1461 * and AMD K7 (Model > 1) or later.
1463 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1464 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1465 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1466 l
&= ~MSR_IA32_APICBASE_BASE
;
1467 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1468 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1469 enabled_via_apicbase
= 1;
1473 * The APIC feature bit should now be enabled
1476 features
= cpuid_edx(1);
1477 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1478 pr_warning("Could not enable APIC!\n");
1481 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1482 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1484 /* The BIOS may have set up the APIC at some other address */
1485 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1486 if (l
& MSR_IA32_APICBASE_ENABLE
)
1487 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1489 pr_info("Found and enabled local APIC!\n");
1496 pr_info("No local APIC present or hardware disabled\n");
1501 #ifdef CONFIG_X86_64
1502 void __init
early_init_lapic_mapping(void)
1504 unsigned long phys_addr
;
1507 * If no local APIC can be found then go out
1508 * : it means there is no mpatable and MADT
1510 if (!smp_found_config
)
1513 phys_addr
= mp_lapic_addr
;
1515 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1516 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1517 APIC_BASE
, phys_addr
);
1520 * Fetch the APIC ID of the BSP in case we have a
1521 * default configuration (or the MP table is broken).
1523 boot_cpu_physical_apicid
= read_apic_id();
1528 * init_apic_mappings - initialize APIC mappings
1530 void __init
init_apic_mappings(void)
1534 boot_cpu_physical_apicid
= read_apic_id();
1540 * If no local APIC can be found then set up a fake all
1541 * zeroes page to simulate the local APIC and another
1542 * one for the IO-APIC.
1544 if (!smp_found_config
&& detect_init_APIC()) {
1545 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1546 apic_phys
= __pa(apic_phys
);
1548 apic_phys
= mp_lapic_addr
;
1550 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1551 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1552 APIC_BASE
, apic_phys
);
1555 * Fetch the APIC ID of the BSP in case we have a
1556 * default configuration (or the MP table is broken).
1558 if (boot_cpu_physical_apicid
== -1U)
1559 boot_cpu_physical_apicid
= read_apic_id();
1563 * This initializes the IO-APIC and APIC hardware if this is
1566 int apic_version
[MAX_APICS
];
1568 int __init
APIC_init_uniprocessor(void)
1570 #ifdef CONFIG_X86_64
1572 pr_info("Apic disabled\n");
1575 if (!cpu_has_apic
) {
1577 pr_info("Apic disabled by BIOS\n");
1581 if (!smp_found_config
&& !cpu_has_apic
)
1585 * Complain if the BIOS pretends there is one.
1587 if (!cpu_has_apic
&&
1588 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1589 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1590 boot_cpu_physical_apicid
);
1591 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1599 #ifdef CONFIG_X86_64
1600 setup_apic_routing();
1603 verify_local_APIC();
1606 #ifdef CONFIG_X86_64
1607 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1610 * Hack: In case of kdump, after a crash, kernel might be booting
1611 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1612 * might be zero if read from MP tables. Get it from LAPIC.
1614 # ifdef CONFIG_CRASH_DUMP
1615 boot_cpu_physical_apicid
= read_apic_id();
1618 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1621 #ifdef CONFIG_X86_64
1623 * Now enable IO-APICs, actually call clear_IO_APIC
1624 * We need clear_IO_APIC before enabling vector on BP
1626 if (!skip_ioapic_setup
&& nr_ioapics
)
1630 #ifdef CONFIG_X86_IO_APIC
1631 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1633 localise_nmi_watchdog();
1634 end_local_APIC_setup();
1636 #ifdef CONFIG_X86_IO_APIC
1637 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1639 # ifdef CONFIG_X86_64
1645 #ifdef CONFIG_X86_64
1646 setup_boot_APIC_clock();
1647 check_nmi_watchdog();
1656 * Local APIC interrupts
1660 * This interrupt should _never_ happen with our APIC/SMP architecture
1662 void smp_spurious_interrupt(struct pt_regs
*regs
)
1669 * Check if this really is a spurious interrupt and ACK it
1670 * if it is a vectored one. Just in case...
1671 * Spurious interrupts should not be ACKed.
1673 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1674 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1677 inc_irq_stat(irq_spurious_count
);
1679 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1680 pr_info("spurious APIC interrupt on CPU#%d, "
1681 "should never happen.\n", smp_processor_id());
1686 * This interrupt should never happen with our APIC/SMP architecture
1688 void smp_error_interrupt(struct pt_regs
*regs
)
1694 /* First tickle the hardware, only then report what went on. -- REW */
1695 v
= apic_read(APIC_ESR
);
1696 apic_write(APIC_ESR
, 0);
1697 v1
= apic_read(APIC_ESR
);
1699 atomic_inc(&irq_err_count
);
1702 * Here is what the APIC error bits mean:
1704 * 1: Receive CS error
1705 * 2: Send accept error
1706 * 3: Receive accept error
1708 * 5: Send illegal vector
1709 * 6: Received illegal vector
1710 * 7: Illegal register address
1712 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1713 smp_processor_id(), v
, v1
);
1718 * connect_bsp_APIC - attach the APIC to the interrupt system
1720 void __init
connect_bsp_APIC(void)
1722 #ifdef CONFIG_X86_32
1725 * Do not trust the local APIC being empty at bootup.
1729 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1730 * local APIC to INT and NMI lines.
1732 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1733 "enabling APIC mode.\n");
1742 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1743 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1745 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1748 void disconnect_bsp_APIC(int virt_wire_setup
)
1752 #ifdef CONFIG_X86_32
1755 * Put the board back into PIC mode (has an effect only on
1756 * certain older boards). Note that APIC interrupts, including
1757 * IPIs, won't work beyond this point! The only exception are
1760 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1761 "entering PIC mode.\n");
1768 /* Go back to Virtual Wire compatibility mode */
1770 /* For the spurious interrupt use vector F, and enable it */
1771 value
= apic_read(APIC_SPIV
);
1772 value
&= ~APIC_VECTOR_MASK
;
1773 value
|= APIC_SPIV_APIC_ENABLED
;
1775 apic_write(APIC_SPIV
, value
);
1777 if (!virt_wire_setup
) {
1779 * For LVT0 make it edge triggered, active high,
1780 * external and enabled
1782 value
= apic_read(APIC_LVT0
);
1783 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1784 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1785 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1786 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1787 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1788 apic_write(APIC_LVT0
, value
);
1791 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1795 * For LVT1 make it edge triggered, active high,
1798 value
= apic_read(APIC_LVT1
);
1799 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1800 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1801 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1802 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1803 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1804 apic_write(APIC_LVT1
, value
);
1807 void __cpuinit
generic_processor_info(int apicid
, int version
)
1815 if (version
== 0x0) {
1816 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1817 "fixing up to 0x10. (tell your hw vendor)\n",
1821 apic_version
[apicid
] = version
;
1823 if (num_processors
>= NR_CPUS
) {
1824 pr_warning("WARNING: NR_CPUS limit of %i reached."
1825 " Processor ignored.\n", NR_CPUS
);
1830 cpus_complement(tmp_map
, cpu_present_map
);
1831 cpu
= first_cpu(tmp_map
);
1833 physid_set(apicid
, phys_cpu_present_map
);
1834 if (apicid
== boot_cpu_physical_apicid
) {
1836 * x86_bios_cpu_apicid is required to have processors listed
1837 * in same order as logical cpu numbers. Hence the first
1838 * entry is BSP, and so on.
1842 if (apicid
> max_physical_apicid
)
1843 max_physical_apicid
= apicid
;
1845 #ifdef CONFIG_X86_32
1847 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1848 * but we need to work other dependencies like SMP_SUSPEND etc
1849 * before this can be done without some confusion.
1850 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1851 * - Ashok Raj <ashok.raj@intel.com>
1853 if (max_physical_apicid
>= 8) {
1854 switch (boot_cpu_data
.x86_vendor
) {
1855 case X86_VENDOR_INTEL
:
1856 if (!APIC_XAPIC(version
)) {
1860 /* If P4 and above fall through */
1861 case X86_VENDOR_AMD
:
1867 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1868 /* are we being called early in kernel startup? */
1869 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1870 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1871 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1873 cpu_to_apicid
[cpu
] = apicid
;
1874 bios_cpu_apicid
[cpu
] = apicid
;
1876 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1877 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1881 cpu_set(cpu
, cpu_possible_map
);
1882 cpu_set(cpu
, cpu_present_map
);
1885 #ifdef CONFIG_X86_64
1886 int hard_smp_processor_id(void)
1888 return read_apic_id();
1899 * 'active' is true if the local APIC was enabled by us and
1900 * not the BIOS; this signifies that we are also responsible
1901 * for disabling it before entering apm/acpi suspend
1904 /* r/w apic fields */
1905 unsigned int apic_id
;
1906 unsigned int apic_taskpri
;
1907 unsigned int apic_ldr
;
1908 unsigned int apic_dfr
;
1909 unsigned int apic_spiv
;
1910 unsigned int apic_lvtt
;
1911 unsigned int apic_lvtpc
;
1912 unsigned int apic_lvt0
;
1913 unsigned int apic_lvt1
;
1914 unsigned int apic_lvterr
;
1915 unsigned int apic_tmict
;
1916 unsigned int apic_tdcr
;
1917 unsigned int apic_thmr
;
1920 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1922 unsigned long flags
;
1925 if (!apic_pm_state
.active
)
1928 maxlvt
= lapic_get_maxlvt();
1930 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1931 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1932 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1933 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1934 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1935 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1937 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1938 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1939 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1940 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1941 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1942 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1943 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1945 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1948 local_irq_save(flags
);
1949 disable_local_APIC();
1950 local_irq_restore(flags
);
1954 static int lapic_resume(struct sys_device
*dev
)
1957 unsigned long flags
;
1960 if (!apic_pm_state
.active
)
1963 maxlvt
= lapic_get_maxlvt();
1965 local_irq_save(flags
);
1974 * Make sure the APICBASE points to the right address
1976 * FIXME! This will be wrong if we ever support suspend on
1977 * SMP! We'll need to do this as part of the CPU restore!
1979 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1980 l
&= ~MSR_IA32_APICBASE_BASE
;
1981 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1982 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1985 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1986 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1987 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1988 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1989 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1990 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1991 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1992 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1993 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1995 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1998 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1999 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2000 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2001 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2002 apic_write(APIC_ESR
, 0);
2003 apic_read(APIC_ESR
);
2004 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2005 apic_write(APIC_ESR
, 0);
2006 apic_read(APIC_ESR
);
2008 local_irq_restore(flags
);
2014 * This device has no shutdown method - fully functioning local APICs
2015 * are needed on every CPU up until machine_halt/restart/poweroff.
2018 static struct sysdev_class lapic_sysclass
= {
2020 .resume
= lapic_resume
,
2021 .suspend
= lapic_suspend
,
2024 static struct sys_device device_lapic
= {
2026 .cls
= &lapic_sysclass
,
2029 static void __cpuinit
apic_pm_activate(void)
2031 apic_pm_state
.active
= 1;
2034 static int __init
init_lapic_sysfs(void)
2040 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2042 error
= sysdev_class_register(&lapic_sysclass
);
2044 error
= sysdev_register(&device_lapic
);
2047 device_initcall(init_lapic_sysfs
);
2049 #else /* CONFIG_PM */
2051 static void apic_pm_activate(void) { }
2053 #endif /* CONFIG_PM */
2055 #ifdef CONFIG_X86_64
2057 * apic_is_clustered_box() -- Check if we can expect good TSC
2059 * Thus far, the major user of this is IBM's Summit2 series:
2061 * Clustered boxes may have unsynced TSC problems if they are
2062 * multi-chassis. Use available data to take a good guess.
2063 * If in doubt, go HPET.
2065 __cpuinit
int apic_is_clustered_box(void)
2067 int i
, clusters
, zeros
;
2069 u16
*bios_cpu_apicid
;
2070 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2073 * there is not this kind of box with AMD CPU yet.
2074 * Some AMD box with quadcore cpu and 8 sockets apicid
2075 * will be [4, 0x23] or [8, 0x27] could be thought to
2076 * vsmp box still need checking...
2078 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2081 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2082 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2084 for (i
= 0; i
< NR_CPUS
; i
++) {
2085 /* are we being called early in kernel startup? */
2086 if (bios_cpu_apicid
) {
2087 id
= bios_cpu_apicid
[i
];
2089 else if (i
< nr_cpu_ids
) {
2091 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2098 if (id
!= BAD_APICID
)
2099 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2102 /* Problem: Partially populated chassis may not have CPUs in some of
2103 * the APIC clusters they have been allocated. Only present CPUs have
2104 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2105 * Since clusters are allocated sequentially, count zeros only if
2106 * they are bounded by ones.
2110 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2111 if (test_bit(i
, clustermap
)) {
2112 clusters
+= 1 + zeros
;
2118 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2119 * not guaranteed to be synced between boards
2121 if (is_vsmp_box() && clusters
> 1)
2125 * If clusters > 2, then should be multi-chassis.
2126 * May have to revisit this when multi-core + hyperthreaded CPUs come
2127 * out, but AFAIK this will work even for them.
2129 return (clusters
> 2);
2134 * APIC command line parameters
2136 static int __init
setup_disableapic(char *arg
)
2139 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2142 early_param("disableapic", setup_disableapic
);
2144 /* same as disableapic, for compatibility */
2145 static int __init
setup_nolapic(char *arg
)
2147 return setup_disableapic(arg
);
2149 early_param("nolapic", setup_nolapic
);
2151 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2153 local_apic_timer_c2_ok
= 1;
2156 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2158 static int __init
parse_disable_apic_timer(char *arg
)
2160 disable_apic_timer
= 1;
2163 early_param("noapictimer", parse_disable_apic_timer
);
2165 static int __init
parse_nolapic_timer(char *arg
)
2167 disable_apic_timer
= 1;
2170 early_param("nolapic_timer", parse_nolapic_timer
);
2172 static int __init
apic_set_verbosity(char *arg
)
2175 #ifdef CONFIG_X86_64
2176 skip_ioapic_setup
= 0;
2182 if (strcmp("debug", arg
) == 0)
2183 apic_verbosity
= APIC_DEBUG
;
2184 else if (strcmp("verbose", arg
) == 0)
2185 apic_verbosity
= APIC_VERBOSE
;
2187 pr_warning("APIC Verbosity level %s not recognised"
2188 " use apic=verbose or apic=debug\n", arg
);
2194 early_param("apic", apic_set_verbosity
);
2196 static int __init
lapic_insert_resource(void)
2201 /* Put local APIC into the resource map. */
2202 lapic_resource
.start
= apic_phys
;
2203 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2204 insert_resource(&iomem_resource
, &lapic_resource
);
2210 * need call insert after e820_reserve_resources()
2211 * that is using request_resource
2213 late_initcall(lapic_insert_resource
);