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[MIPS] Momentum: Resurrect after things were moved around a while ago.
[linux-2.6/mini2440.git] / arch / mips / momentum / ocelot_c / setup.c
blobbd02e60d037a94ad0768d33077751168d2a593ff
1 /*
2 * BRIEF MODULE DESCRIPTION
3 * Momentum Computer Ocelot-C and -CS board dependent boot routines
4 *
5 * Copyright (C) 1996, 1997, 2001 Ralf Baechle
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Copyright (C) 2001 Red Hat, Inc.
8 * Copyright (C) 2002 Momentum Computer
9 *
10 * Author: Matthew Dharm, Momentum Computer
11 * mdharm@momenco.com
12 *
13 * Louis Hamilton, Red Hat, Inc.
14 * hamilton@redhat.com [MIPS64 modifications]
15 *
16 * Author: RidgeRun, Inc.
17 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
18 *
19 * Copyright 2001 MontaVista Software Inc.
20 * Author: jsun@mvista.com or jsun@junsun.net
21 *
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License as published by the
24 * Free Software Foundation; either version 2 of the License, or (at your
25 * option) any later version.
26 *
27 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
30 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
33 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
34 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * You should have received a copy of the GNU General Public License along
39 * with this program; if not, write to the Free Software Foundation, Inc.,
40 * 675 Mass Ave, Cambridge, MA 02139, USA.
41 *
42 */
43 #include <linux/config.h>
44 #include <linux/bcd.h>
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/mm.h>
49 #include <linux/swap.h>
50 #include <linux/ioport.h>
51 #include <linux/sched.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/pm.h>
55 #include <linux/timex.h>
56 #include <linux/vmalloc.h>
57 #include <linux/mv643xx.h>
58
59 #include <asm/time.h>
60 #include <asm/bootinfo.h>
61 #include <asm/page.h>
62 #include <asm/io.h>
63 #include <asm/irq.h>
64 #include <asm/pci.h>
65 #include <asm/processor.h>
66 #include <asm/ptrace.h>
67 #include <asm/reboot.h>
68 #include <asm/marvell.h>
69 #include <linux/bootmem.h>
70 #include <linux/blkdev.h>
71 #include "ocelot_c_fpga.h"
72
73 unsigned long marvell_base;
74 extern unsigned long mv64340_sram_base;
75 unsigned long cpu_clock;
76
77 /* These functions are used for rebooting or halting the machine*/
78 extern void momenco_ocelot_restart(char *command);
79 extern void momenco_ocelot_halt(void);
80 extern void momenco_ocelot_power_off(void);
81
82 void momenco_time_init(void);
83
84 static char reset_reason;
85
86 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask);
87
88 static unsigned long ENTRYLO(unsigned long paddr)
89 {
90 return ((paddr & PAGE_MASK) |
91 (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
92 _CACHE_UNCACHED)) >> 6;
93 }
94
95 /* setup code for a handoff from a version 2 PMON 2000 PROM */
96 void PMON_v2_setup(void)
97 {
98 /* Some wired TLB entries for the MV64340 and perhiperals. The
99 MV64340 is going to be hit on every IRQ anyway - there's
100 absolutely no point in letting it be a random TLB entry, as
101 it'll just cause needless churning of the TLB. And we use
102 the other half for the serial port, which is just a PITA
103 otherwise :)
104
105 Device Physical Virtual
106 MV64340 Internal Regs 0xf4000000 0xf4000000
107 Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
108 NVRAM (CS1) 0xfc800000 0xfc800000
109 UARTs (CS2) 0xfd000000 0xfd000000
110 Internal SRAM 0xfe000000 0xfe000000
111 M-Systems DOC (CS3) 0xff000000 0xff000000
112 */
113 printk("PMON_v2_setup\n");
114
115 #ifdef CONFIG_64BIT
116 /* marvell and extra space */
117 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
118 /* fpga, rtc, and uart */
119 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfffffffffc000000, PM_16M);
120 /* m-sys and internal SRAM */
121 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
122
123 marvell_base = 0xfffffffff4000000;
124 mv64340_sram_base = 0xfffffffffe000000;
125 #else
126 /* marvell and extra space */
127 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
128 /* fpga, rtc, and uart */
129 add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), 0xfc000000, PM_16M);
130 /* m-sys and internal SRAM */
131 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
132
133 marvell_base = 0xf4000000;
134 mv64340_sram_base = 0xfe000000;
135 #endif
136 }
137
138 unsigned long m48t37y_get_time(void)
139 {
140 #ifdef CONFIG_64BIT
141 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
142 #else
143 unsigned char* rtc_base = (unsigned char*)0xfc800000;
144 #endif
145 unsigned int year, month, day, hour, min, sec;
146 unsigned long flags;
147
148 spin_lock_irqsave(&rtc_lock, flags);
149 /* stop the update */
150 rtc_base[0x7ff8] = 0x40;
151
152 year = BCD2BIN(rtc_base[0x7fff]);
153 year += BCD2BIN(rtc_base[0x7ff1]) * 100;
154
155 month = BCD2BIN(rtc_base[0x7ffe]);
156
157 day = BCD2BIN(rtc_base[0x7ffd]);
158
159 hour = BCD2BIN(rtc_base[0x7ffb]);
160 min = BCD2BIN(rtc_base[0x7ffa]);
161 sec = BCD2BIN(rtc_base[0x7ff9]);
162
163 /* start the update */
164 rtc_base[0x7ff8] = 0x00;
165 spin_unlock_irqrestore(&rtc_lock, flags);
166
167 return mktime(year, month, day, hour, min, sec);
168 }
169
170 int m48t37y_set_time(unsigned long sec)
171 {
172 #ifdef CONFIG_64BIT
173 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
174 #else
175 unsigned char* rtc_base = (unsigned char*)0xfc800000;
176 #endif
177 struct rtc_time tm;
178 unsigned long flags;
179
180 /* convert to a more useful format -- note months count from 0 */
181 to_tm(sec, &tm);
182 tm.tm_mon += 1;
183
184 spin_lock_irqsave(&rtc_lock, flags);
185 /* enable writing */
186 rtc_base[0x7ff8] = 0x80;
187
188 /* year */
189 rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
190 rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
191
192 /* month */
193 rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
194
195 /* day */
196 rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
197
198 /* hour/min/sec */
199 rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
200 rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
201 rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
202
203 /* day of week -- not really used, but let's keep it up-to-date */
204 rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
205
206 /* disable writing */
207 rtc_base[0x7ff8] = 0x00;
208 spin_unlock_irqrestore(&rtc_lock, flags);
209
210 return 0;
211 }
212
213 void momenco_timer_setup(struct irqaction *irq)
214 {
215 setup_irq(7, irq);
216 }
217
218 void momenco_time_init(void)
219 {
220 #ifdef CONFIG_CPU_SR71000
221 mips_hpt_frequency = cpu_clock;
222 #elif defined(CONFIG_CPU_RM7000)
223 mips_hpt_frequency = cpu_clock / 2;
224 #else
225 #error Unknown CPU for this board
226 #endif
227 printk("momenco_time_init cpu_clock=%d\n", cpu_clock);
228 board_timer_setup = momenco_timer_setup;
229
230 rtc_get_time = m48t37y_get_time;
231 rtc_set_time = m48t37y_set_time;
232 }
233
234 void __init plat_setup(void)
235 {
236 unsigned int tmpword;
237
238 board_time_init = momenco_time_init;
239
240 _machine_restart = momenco_ocelot_restart;
241 _machine_halt = momenco_ocelot_halt;
242 pm_power_off = momenco_ocelot_power_off;
243
244 /*
245 * initrd_start = (ulong)ocelot_initrd_start;
246 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
247 * initrd_below_start_ok = 1;
248 */
249
250 /* do handoff reconfiguration */
251 PMON_v2_setup();
252
253 /* shut down ethernet ports, just to be sure our memory doesn't get
254 * corrupted by random ethernet traffic.
255 */
256 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
257 MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
258 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
259 MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
260 do {}
261 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
262 do {}
263 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
264 do {}
265 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
266 do {}
267 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
268 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
269 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
270 MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
271 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
272
273 /* Turn off the Bit-Error LED */
274 OCELOT_FPGA_WRITE(0x80, CLR);
275
276 tmpword = OCELOT_FPGA_READ(BOARDREV);
277 #ifdef CONFIG_CPU_SR71000
278 if (tmpword < 26)
279 printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
280 'A'+tmpword);
281 else
282 printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
283 tmpword);
284 #else
285 if (tmpword < 26)
286 printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
287 'A'+tmpword);
288 else
289 printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
290 tmpword);
291 #endif
292
293 tmpword = OCELOT_FPGA_READ(FPGA_REV);
294 printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
295 tmpword = OCELOT_FPGA_READ(RESET_STATUS);
296 printk("Reset reason: 0x%x\n", tmpword);
297 switch (tmpword) {
298 case 0x1:
299 printk(" - Power-up reset\n");
300 break;
301 case 0x2:
302 printk(" - Push-button reset\n");
303 break;
304 case 0x4:
305 printk(" - cPCI bus reset\n");
306 break;
307 case 0x8:
308 printk(" - Watchdog reset\n");
309 break;
310 case 0x10:
311 printk(" - Software reset\n");
312 break;
313 default:
314 printk(" - Unknown reset cause\n");
315 }
316 reset_reason = tmpword;
317 OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
318
319 tmpword = OCELOT_FPGA_READ(CPCI_ID);
320 printk("cPCI ID register: 0x%02x\n", tmpword);
321 printk(" - Slot number: %d\n", tmpword & 0x1f);
322 printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
323 printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
324
325 tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
326 printk("Board Status register: 0x%02x\n", tmpword);
327 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
328 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
329 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
330 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
331
332 switch(tmpword &3) {
333 case 3:
334 /* 512MiB */
335 add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
336 break;
337 case 2:
338 /* 256MiB */
339 add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
340 break;
341 case 1:
342 /* 128MiB */
343 add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
344 break;
345 case 0:
346 /* 1GiB -- needs CONFIG_HIGHMEM */
347 add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
348 break;
349 }
350 }
351
352 #ifndef CONFIG_64BIT
353 /* This needs to be one of the first initcalls, because no I/O port access
354 can work before this */
355 static int io_base_ioremap(void)
356 {
357 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
358 void *io_remap_range = ioremap(0xc0000000, 0x30000000);
359
360 if (!io_remap_range) {
361 panic("Could not ioremap I/O port range");
362 }
363 printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range);
364 set_io_port_base(io_remap_range - 0xc0000000);
365
366 return 0;
367 }
368
369 module_init(io_base_ioremap);
370 #endif
Support for the Chinese Samsung S3C2440 based development boards