2 * Xilinx SystemACE device driver
4 * Copyright 2007 Secret Lab Technologies Ltd.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 * The SystemACE chip is designed to configure FPGAs by loading an FPGA
13 * bitstream from a file on a CF card and squirting it into FPGAs connected
14 * to the SystemACE JTAG chain. It also has the advantage of providing an
15 * MPU interface which can be used to control the FPGA configuration process
16 * and to use the attached CF card for general purpose storage.
18 * This driver is a block device driver for the SystemACE.
21 * The driver registers itself as a platform_device driver at module
22 * load time. The platform bus will take care of calling the
23 * ace_probe() method for all SystemACE instances in the system. Any
24 * number of SystemACE instances are supported. ace_probe() calls
25 * ace_setup() which initialized all data structures, reads the CF
26 * id structure and registers the device.
29 * Just about all of the heavy lifting in this driver is performed by
30 * a Finite State Machine (FSM). The driver needs to wait on a number
31 * of events; some raised by interrupts, some which need to be polled
32 * for. Describing all of the behaviour in a FSM seems to be the
33 * easiest way to keep the complexity low and make it easy to
34 * understand what the driver is doing. If the block ops or the
35 * request function need to interact with the hardware, then they
36 * simply need to flag the request and kick of FSM processing.
38 * The FSM itself is atomic-safe code which can be run from any
39 * context. The general process flow is:
40 * 1. obtain the ace->lock spinlock.
41 * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
43 * 3. release the lock.
45 * Individual states do not sleep in any way. If a condition needs to
46 * be waited for then the state much clear the fsm_continue flag and
47 * either schedule the FSM to be run again at a later time, or expect
48 * an interrupt to call the FSM when the desired condition is met.
50 * In normal operation, the FSM is processed at interrupt context
51 * either when the driver's tasklet is scheduled, or when an irq is
52 * raised by the hardware. The tasklet can be scheduled at any time.
53 * The request method in particular schedules the tasklet when a new
54 * request has been indicated by the block layer. Once started, the
55 * FSM proceeds as far as it can processing the request until it
56 * needs on a hardware event. At this point, it must yield execution.
58 * A state has two options when yielding execution:
60 * - Call if need to poll for event.
61 * - clears the fsm_continue flag to exit the processing loop
62 * - reschedules the tasklet to run again as soon as possible
63 * 2. ace_fsm_yieldirq()
64 * - Call if an irq is expected from the HW
65 * - clears the fsm_continue flag to exit the processing loop
66 * - does not reschedule the tasklet so the FSM will not be processed
67 * again until an irq is received.
68 * After calling a yield function, the state must return control back
69 * to the FSM main loop.
71 * Additionally, the driver maintains a kernel timer which can process
72 * the FSM. If the FSM gets stalled, typically due to a missed
73 * interrupt, then the kernel timer will expire and the driver can
74 * continue where it left off.
77 * - Add FPGA configuration control interface.
78 * - Request major number from lanana
83 #include <linux/module.h>
84 #include <linux/ctype.h>
85 #include <linux/init.h>
86 #include <linux/interrupt.h>
87 #include <linux/errno.h>
88 #include <linux/kernel.h>
89 #include <linux/delay.h>
90 #include <linux/slab.h>
91 #include <linux/blkdev.h>
92 #include <linux/hdreg.h>
93 #include <linux/platform_device.h>
95 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
96 MODULE_DESCRIPTION("Xilinx SystemACE device driver");
97 MODULE_LICENSE("GPL");
99 /* SystemACE register definitions */
100 #define ACE_BUSMODE (0x00)
102 #define ACE_STATUS (0x04)
103 #define ACE_STATUS_CFGLOCK (0x00000001)
104 #define ACE_STATUS_MPULOCK (0x00000002)
105 #define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */
106 #define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */
107 #define ACE_STATUS_CFDETECT (0x00000010)
108 #define ACE_STATUS_DATABUFRDY (0x00000020)
109 #define ACE_STATUS_DATABUFMODE (0x00000040)
110 #define ACE_STATUS_CFGDONE (0x00000080)
111 #define ACE_STATUS_RDYFORCFCMD (0x00000100)
112 #define ACE_STATUS_CFGMODEPIN (0x00000200)
113 #define ACE_STATUS_CFGADDR_MASK (0x0000e000)
114 #define ACE_STATUS_CFBSY (0x00020000)
115 #define ACE_STATUS_CFRDY (0x00040000)
116 #define ACE_STATUS_CFDWF (0x00080000)
117 #define ACE_STATUS_CFDSC (0x00100000)
118 #define ACE_STATUS_CFDRQ (0x00200000)
119 #define ACE_STATUS_CFCORR (0x00400000)
120 #define ACE_STATUS_CFERR (0x00800000)
122 #define ACE_ERROR (0x08)
123 #define ACE_CFGLBA (0x0c)
124 #define ACE_MPULBA (0x10)
126 #define ACE_SECCNTCMD (0x14)
127 #define ACE_SECCNTCMD_RESET (0x0100)
128 #define ACE_SECCNTCMD_IDENTIFY (0x0200)
129 #define ACE_SECCNTCMD_READ_DATA (0x0300)
130 #define ACE_SECCNTCMD_WRITE_DATA (0x0400)
131 #define ACE_SECCNTCMD_ABORT (0x0600)
133 #define ACE_VERSION (0x16)
134 #define ACE_VERSION_REVISION_MASK (0x00FF)
135 #define ACE_VERSION_MINOR_MASK (0x0F00)
136 #define ACE_VERSION_MAJOR_MASK (0xF000)
138 #define ACE_CTRL (0x18)
139 #define ACE_CTRL_FORCELOCKREQ (0x0001)
140 #define ACE_CTRL_LOCKREQ (0x0002)
141 #define ACE_CTRL_FORCECFGADDR (0x0004)
142 #define ACE_CTRL_FORCECFGMODE (0x0008)
143 #define ACE_CTRL_CFGMODE (0x0010)
144 #define ACE_CTRL_CFGSTART (0x0020)
145 #define ACE_CTRL_CFGSEL (0x0040)
146 #define ACE_CTRL_CFGRESET (0x0080)
147 #define ACE_CTRL_DATABUFRDYIRQ (0x0100)
148 #define ACE_CTRL_ERRORIRQ (0x0200)
149 #define ACE_CTRL_CFGDONEIRQ (0x0400)
150 #define ACE_CTRL_RESETIRQ (0x0800)
151 #define ACE_CTRL_CFGPROG (0x1000)
152 #define ACE_CTRL_CFGADDR_MASK (0xe000)
154 #define ACE_FATSTAT (0x1c)
156 #define ACE_NUM_MINORS 16
157 #define ACE_SECTOR_SIZE (512)
158 #define ACE_FIFO_SIZE (32)
159 #define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE)
161 #define ACE_BUS_WIDTH_8 0
162 #define ACE_BUS_WIDTH_16 1
167 /* driver state data */
171 struct list_head list
;
173 /* finite state machine data */
174 struct tasklet_struct fsm_tasklet
;
175 uint fsm_task
; /* Current activity (ACE_TASK_*) */
176 uint fsm_state
; /* Current state (ACE_FSM_STATE_*) */
177 uint fsm_continue_flag
; /* cleared to exit FSM mainloop */
179 struct timer_list stall_timer
;
181 /* Transfer state/result, use for both id and block request */
182 struct request
*req
; /* request being processed */
183 void *data_ptr
; /* pointer to I/O buffer */
184 int data_count
; /* number of buffers remaining */
185 int data_result
; /* Result of transfer; 0 := success */
187 int id_req_count
; /* count of id requests */
189 struct completion id_completion
; /* used when id req finishes */
192 /* Details of hardware device */
193 unsigned long physaddr
;
196 int bus_width
; /* 0 := 8 bit; 1 := 16 bit */
197 struct ace_reg_ops
*reg_ops
;
200 /* Block device data structures */
203 struct request_queue
*queue
;
206 /* Inserted CF card parameters */
207 struct hd_driveid cf_id
;
210 static int ace_major
;
212 /* ---------------------------------------------------------------------
213 * Low level register access
217 u16(*in
) (struct ace_device
* ace
, int reg
);
218 void (*out
) (struct ace_device
* ace
, int reg
, u16 val
);
219 void (*datain
) (struct ace_device
* ace
);
220 void (*dataout
) (struct ace_device
* ace
);
223 /* 8 Bit bus width */
224 static u16
ace_in_8(struct ace_device
*ace
, int reg
)
226 void *r
= ace
->baseaddr
+ reg
;
227 return in_8(r
) | (in_8(r
+ 1) << 8);
230 static void ace_out_8(struct ace_device
*ace
, int reg
, u16 val
)
232 void *r
= ace
->baseaddr
+ reg
;
234 out_8(r
+ 1, val
>> 8);
237 static void ace_datain_8(struct ace_device
*ace
)
239 void *r
= ace
->baseaddr
+ 0x40;
240 u8
*dst
= ace
->data_ptr
;
241 int i
= ACE_FIFO_SIZE
;
247 static void ace_dataout_8(struct ace_device
*ace
)
249 void *r
= ace
->baseaddr
+ 0x40;
250 u8
*src
= ace
->data_ptr
;
251 int i
= ACE_FIFO_SIZE
;
257 static struct ace_reg_ops ace_reg_8_ops
= {
260 .datain
= ace_datain_8
,
261 .dataout
= ace_dataout_8
,
264 /* 16 bit big endian bus attachment */
265 static u16
ace_in_be16(struct ace_device
*ace
, int reg
)
267 return in_be16(ace
->baseaddr
+ reg
);
270 static void ace_out_be16(struct ace_device
*ace
, int reg
, u16 val
)
272 out_be16(ace
->baseaddr
+ reg
, val
);
275 static void ace_datain_be16(struct ace_device
*ace
)
277 int i
= ACE_FIFO_SIZE
/ 2;
278 u16
*dst
= ace
->data_ptr
;
280 *dst
++ = in_le16(ace
->baseaddr
+ 0x40);
284 static void ace_dataout_be16(struct ace_device
*ace
)
286 int i
= ACE_FIFO_SIZE
/ 2;
287 u16
*src
= ace
->data_ptr
;
289 out_le16(ace
->baseaddr
+ 0x40, *src
++);
293 /* 16 bit little endian bus attachment */
294 static u16
ace_in_le16(struct ace_device
*ace
, int reg
)
296 return in_le16(ace
->baseaddr
+ reg
);
299 static void ace_out_le16(struct ace_device
*ace
, int reg
, u16 val
)
301 out_le16(ace
->baseaddr
+ reg
, val
);
304 static void ace_datain_le16(struct ace_device
*ace
)
306 int i
= ACE_FIFO_SIZE
/ 2;
307 u16
*dst
= ace
->data_ptr
;
309 *dst
++ = in_be16(ace
->baseaddr
+ 0x40);
313 static void ace_dataout_le16(struct ace_device
*ace
)
315 int i
= ACE_FIFO_SIZE
/ 2;
316 u16
*src
= ace
->data_ptr
;
318 out_be16(ace
->baseaddr
+ 0x40, *src
++);
322 static struct ace_reg_ops ace_reg_be16_ops
= {
325 .datain
= ace_datain_be16
,
326 .dataout
= ace_dataout_be16
,
329 static struct ace_reg_ops ace_reg_le16_ops
= {
332 .datain
= ace_datain_le16
,
333 .dataout
= ace_dataout_le16
,
336 static inline u16
ace_in(struct ace_device
*ace
, int reg
)
338 return ace
->reg_ops
->in(ace
, reg
);
341 static inline u32
ace_in32(struct ace_device
*ace
, int reg
)
343 return ace_in(ace
, reg
) | (ace_in(ace
, reg
+ 2) << 16);
346 static inline void ace_out(struct ace_device
*ace
, int reg
, u16 val
)
348 ace
->reg_ops
->out(ace
, reg
, val
);
351 static inline void ace_out32(struct ace_device
*ace
, int reg
, u32 val
)
353 ace_out(ace
, reg
, val
);
354 ace_out(ace
, reg
+ 2, val
>> 16);
357 /* ---------------------------------------------------------------------
358 * Debug support functions
362 static void ace_dump_mem(void *base
, int len
)
364 const char *ptr
= base
;
367 for (i
= 0; i
< len
; i
+= 16) {
368 printk(KERN_INFO
"%.8x:", i
);
369 for (j
= 0; j
< 16; j
++) {
372 printk("%.2x", ptr
[i
+ j
]);
375 for (j
= 0; j
< 16; j
++)
376 printk("%c", isprint(ptr
[i
+ j
]) ? ptr
[i
+ j
] : '.');
381 static inline void ace_dump_mem(void *base
, int len
)
386 static void ace_dump_regs(struct ace_device
*ace
)
388 dev_info(ace
->dev
, " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n"
389 " status:%.8x mpu_lba:%.8x busmode:%4x\n"
390 " error: %.8x cfg_lba:%.8x fatstat:%.4x\n",
391 ace_in32(ace
, ACE_CTRL
),
392 ace_in(ace
, ACE_SECCNTCMD
),
393 ace_in(ace
, ACE_VERSION
),
394 ace_in32(ace
, ACE_STATUS
),
395 ace_in32(ace
, ACE_MPULBA
),
396 ace_in(ace
, ACE_BUSMODE
),
397 ace_in32(ace
, ACE_ERROR
),
398 ace_in32(ace
, ACE_CFGLBA
), ace_in(ace
, ACE_FATSTAT
));
401 void ace_fix_driveid(struct hd_driveid
*id
)
403 #if defined(__BIG_ENDIAN)
404 u16
*buf
= (void *)id
;
407 /* All half words have wrong byte order; swap the bytes */
408 for (i
= 0; i
< sizeof(struct hd_driveid
); i
+= 2, buf
++)
409 *buf
= le16_to_cpu(*buf
);
411 /* Some of the data values are 32bit; swap the half words */
412 id
->lba_capacity
= ((id
->lba_capacity
>> 16) & 0x0000FFFF) |
413 ((id
->lba_capacity
<< 16) & 0xFFFF0000);
414 id
->spg
= ((id
->spg
>> 16) & 0x0000FFFF) |
415 ((id
->spg
<< 16) & 0xFFFF0000);
419 /* ---------------------------------------------------------------------
420 * Finite State Machine (FSM) implementation
423 /* FSM tasks; used to direct state transitions */
424 #define ACE_TASK_IDLE 0
425 #define ACE_TASK_IDENTIFY 1
426 #define ACE_TASK_READ 2
427 #define ACE_TASK_WRITE 3
428 #define ACE_FSM_NUM_TASKS 4
430 /* FSM state definitions */
431 #define ACE_FSM_STATE_IDLE 0
432 #define ACE_FSM_STATE_REQ_LOCK 1
433 #define ACE_FSM_STATE_WAIT_LOCK 2
434 #define ACE_FSM_STATE_WAIT_CFREADY 3
435 #define ACE_FSM_STATE_IDENTIFY_PREPARE 4
436 #define ACE_FSM_STATE_IDENTIFY_TRANSFER 5
437 #define ACE_FSM_STATE_IDENTIFY_COMPLETE 6
438 #define ACE_FSM_STATE_REQ_PREPARE 7
439 #define ACE_FSM_STATE_REQ_TRANSFER 8
440 #define ACE_FSM_STATE_REQ_COMPLETE 9
441 #define ACE_FSM_STATE_ERROR 10
442 #define ACE_FSM_NUM_STATES 11
444 /* Set flag to exit FSM loop and reschedule tasklet */
445 static inline void ace_fsm_yield(struct ace_device
*ace
)
447 dev_dbg(ace
->dev
, "ace_fsm_yield()\n");
448 tasklet_schedule(&ace
->fsm_tasklet
);
449 ace
->fsm_continue_flag
= 0;
452 /* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */
453 static inline void ace_fsm_yieldirq(struct ace_device
*ace
)
455 dev_dbg(ace
->dev
, "ace_fsm_yieldirq()\n");
457 if (ace
->irq
== NO_IRQ
)
458 /* No IRQ assigned, so need to poll */
459 tasklet_schedule(&ace
->fsm_tasklet
);
460 ace
->fsm_continue_flag
= 0;
463 /* Get the next read/write request; ending requests that we don't handle */
464 struct request
*ace_get_next_request(struct request_queue
* q
)
468 while ((req
= elv_next_request(q
)) != NULL
) {
469 if (blk_fs_request(req
))
476 static void ace_fsm_dostate(struct ace_device
*ace
)
485 dev_dbg(ace
->dev
, "fsm_state=%i, id_req_count=%i\n",
486 ace
->fsm_state
, ace
->id_req_count
);
489 switch (ace
->fsm_state
) {
490 case ACE_FSM_STATE_IDLE
:
491 /* See if there is anything to do */
492 if (ace
->id_req_count
|| ace_get_next_request(ace
->queue
)) {
494 ace
->fsm_state
= ACE_FSM_STATE_REQ_LOCK
;
495 mod_timer(&ace
->stall_timer
, jiffies
+ HZ
);
496 if (!timer_pending(&ace
->stall_timer
))
497 add_timer(&ace
->stall_timer
);
500 del_timer(&ace
->stall_timer
);
501 ace
->fsm_continue_flag
= 0;
504 case ACE_FSM_STATE_REQ_LOCK
:
505 if (ace_in(ace
, ACE_STATUS
) & ACE_STATUS_MPULOCK
) {
506 /* Already have the lock, jump to next state */
507 ace
->fsm_state
= ACE_FSM_STATE_WAIT_CFREADY
;
511 /* Request the lock */
512 val
= ace_in(ace
, ACE_CTRL
);
513 ace_out(ace
, ACE_CTRL
, val
| ACE_CTRL_LOCKREQ
);
514 ace
->fsm_state
= ACE_FSM_STATE_WAIT_LOCK
;
517 case ACE_FSM_STATE_WAIT_LOCK
:
518 if (ace_in(ace
, ACE_STATUS
) & ACE_STATUS_MPULOCK
) {
519 /* got the lock; move to next state */
520 ace
->fsm_state
= ACE_FSM_STATE_WAIT_CFREADY
;
524 /* wait a bit for the lock */
528 case ACE_FSM_STATE_WAIT_CFREADY
:
529 status
= ace_in32(ace
, ACE_STATUS
);
530 if (!(status
& ACE_STATUS_RDYFORCFCMD
) ||
531 (status
& ACE_STATUS_CFBSY
)) {
532 /* CF card isn't ready; it needs to be polled */
537 /* Device is ready for command; determine what to do next */
538 if (ace
->id_req_count
)
539 ace
->fsm_state
= ACE_FSM_STATE_IDENTIFY_PREPARE
;
541 ace
->fsm_state
= ACE_FSM_STATE_REQ_PREPARE
;
544 case ACE_FSM_STATE_IDENTIFY_PREPARE
:
545 /* Send identify command */
546 ace
->fsm_task
= ACE_TASK_IDENTIFY
;
547 ace
->data_ptr
= &ace
->cf_id
;
548 ace
->data_count
= ACE_BUF_PER_SECTOR
;
549 ace_out(ace
, ACE_SECCNTCMD
, ACE_SECCNTCMD_IDENTIFY
);
551 /* As per datasheet, put config controller in reset */
552 val
= ace_in(ace
, ACE_CTRL
);
553 ace_out(ace
, ACE_CTRL
, val
| ACE_CTRL_CFGRESET
);
555 /* irq handler takes over from this point; wait for the
556 * transfer to complete */
557 ace
->fsm_state
= ACE_FSM_STATE_IDENTIFY_TRANSFER
;
558 ace_fsm_yieldirq(ace
);
561 case ACE_FSM_STATE_IDENTIFY_TRANSFER
:
562 /* Check that the sysace is ready to receive data */
563 status
= ace_in32(ace
, ACE_STATUS
);
564 if (status
& ACE_STATUS_CFBSY
) {
565 dev_dbg(ace
->dev
, "CFBSY set; t=%i iter=%i dc=%i\n",
566 ace
->fsm_task
, ace
->fsm_iter_num
,
571 if (!(status
& ACE_STATUS_DATABUFRDY
)) {
576 /* Transfer the next buffer */
577 ace
->reg_ops
->datain(ace
);
580 /* If there are still buffers to be transfers; jump out here */
581 if (ace
->data_count
!= 0) {
582 ace_fsm_yieldirq(ace
);
586 /* transfer finished; kick state machine */
587 dev_dbg(ace
->dev
, "identify finished\n");
588 ace
->fsm_state
= ACE_FSM_STATE_IDENTIFY_COMPLETE
;
591 case ACE_FSM_STATE_IDENTIFY_COMPLETE
:
592 ace_fix_driveid(&ace
->cf_id
);
593 ace_dump_mem(&ace
->cf_id
, 512); /* Debug: Dump out disk ID */
595 if (ace
->data_result
) {
596 /* Error occured, disable the disk */
597 ace
->media_change
= 1;
598 set_capacity(ace
->gd
, 0);
599 dev_err(ace
->dev
, "error fetching CF id (%i)\n",
602 ace
->media_change
= 0;
604 /* Record disk parameters */
605 set_capacity(ace
->gd
, ace
->cf_id
.lba_capacity
);
606 dev_info(ace
->dev
, "capacity: %i sectors\n",
607 ace
->cf_id
.lba_capacity
);
610 /* We're done, drop to IDLE state and notify waiters */
611 ace
->fsm_state
= ACE_FSM_STATE_IDLE
;
612 ace
->id_result
= ace
->data_result
;
613 while (ace
->id_req_count
) {
614 complete(&ace
->id_completion
);
619 case ACE_FSM_STATE_REQ_PREPARE
:
620 req
= ace_get_next_request(ace
->queue
);
622 ace
->fsm_state
= ACE_FSM_STATE_IDLE
;
626 /* Okay, it's a data request, set it up for transfer */
628 "request: sec=%lx hcnt=%lx, ccnt=%x, dir=%i\n",
629 req
->sector
, req
->hard_nr_sectors
,
630 req
->current_nr_sectors
, rq_data_dir(req
));
633 ace
->data_ptr
= req
->buffer
;
634 ace
->data_count
= req
->current_nr_sectors
* ACE_BUF_PER_SECTOR
;
635 ace_out32(ace
, ACE_MPULBA
, req
->sector
& 0x0FFFFFFF);
637 count
= req
->hard_nr_sectors
;
638 if (rq_data_dir(req
)) {
639 /* Kick off write request */
640 dev_dbg(ace
->dev
, "write data\n");
641 ace
->fsm_task
= ACE_TASK_WRITE
;
642 ace_out(ace
, ACE_SECCNTCMD
,
643 count
| ACE_SECCNTCMD_WRITE_DATA
);
645 /* Kick off read request */
646 dev_dbg(ace
->dev
, "read data\n");
647 ace
->fsm_task
= ACE_TASK_READ
;
648 ace_out(ace
, ACE_SECCNTCMD
,
649 count
| ACE_SECCNTCMD_READ_DATA
);
652 /* As per datasheet, put config controller in reset */
653 val
= ace_in(ace
, ACE_CTRL
);
654 ace_out(ace
, ACE_CTRL
, val
| ACE_CTRL_CFGRESET
);
656 /* Move to the transfer state. The systemace will raise
657 * an interrupt once there is something to do
659 ace
->fsm_state
= ACE_FSM_STATE_REQ_TRANSFER
;
660 if (ace
->fsm_task
== ACE_TASK_READ
)
661 ace_fsm_yieldirq(ace
); /* wait for data ready */
664 case ACE_FSM_STATE_REQ_TRANSFER
:
665 /* Check that the sysace is ready to receive data */
666 status
= ace_in32(ace
, ACE_STATUS
);
667 if (status
& ACE_STATUS_CFBSY
) {
669 "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n",
670 ace
->fsm_task
, ace
->fsm_iter_num
,
671 ace
->req
->current_nr_sectors
* 16,
672 ace
->data_count
, ace
->in_irq
);
673 ace_fsm_yield(ace
); /* need to poll CFBSY bit */
676 if (!(status
& ACE_STATUS_DATABUFRDY
)) {
678 "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n",
679 ace
->fsm_task
, ace
->fsm_iter_num
,
680 ace
->req
->current_nr_sectors
* 16,
681 ace
->data_count
, ace
->in_irq
);
682 ace_fsm_yieldirq(ace
);
686 /* Transfer the next buffer */
688 if (ace
->fsm_task
== ACE_TASK_WRITE
)
689 ace
->reg_ops
->dataout(ace
);
691 ace
->reg_ops
->datain(ace
);
694 /* If there are still buffers to be transfers; jump out here */
695 if (ace
->data_count
!= 0) {
696 ace_fsm_yieldirq(ace
);
700 /* bio finished; is there another one? */
701 i
= ace
->req
->current_nr_sectors
;
702 if (end_that_request_first(ace
->req
, 1, i
)) {
703 /* dev_dbg(ace->dev, "next block; h=%li c=%i\n",
704 * ace->req->hard_nr_sectors,
705 * ace->req->current_nr_sectors);
707 ace
->data_ptr
= ace
->req
->buffer
;
708 ace
->data_count
= ace
->req
->current_nr_sectors
* 16;
709 ace_fsm_yieldirq(ace
);
713 ace
->fsm_state
= ACE_FSM_STATE_REQ_COMPLETE
;
716 case ACE_FSM_STATE_REQ_COMPLETE
:
717 /* Complete the block request */
718 blkdev_dequeue_request(ace
->req
);
719 end_that_request_last(ace
->req
, 1);
722 /* Finished request; go to idle state */
723 ace
->fsm_state
= ACE_FSM_STATE_IDLE
;
727 ace
->fsm_state
= ACE_FSM_STATE_IDLE
;
732 static void ace_fsm_tasklet(unsigned long data
)
734 struct ace_device
*ace
= (void *)data
;
737 spin_lock_irqsave(&ace
->lock
, flags
);
739 /* Loop over state machine until told to stop */
740 ace
->fsm_continue_flag
= 1;
741 while (ace
->fsm_continue_flag
)
742 ace_fsm_dostate(ace
);
744 spin_unlock_irqrestore(&ace
->lock
, flags
);
747 static void ace_stall_timer(unsigned long data
)
749 struct ace_device
*ace
= (void *)data
;
753 "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n",
754 ace
->fsm_state
, ace
->fsm_task
, ace
->fsm_iter_num
,
756 spin_lock_irqsave(&ace
->lock
, flags
);
758 /* Rearm the stall timer *before* entering FSM (which may then
759 * delete the timer) */
760 mod_timer(&ace
->stall_timer
, jiffies
+ HZ
);
762 /* Loop over state machine until told to stop */
763 ace
->fsm_continue_flag
= 1;
764 while (ace
->fsm_continue_flag
)
765 ace_fsm_dostate(ace
);
767 spin_unlock_irqrestore(&ace
->lock
, flags
);
770 /* ---------------------------------------------------------------------
771 * Interrupt handling routines
773 static int ace_interrupt_checkstate(struct ace_device
*ace
)
775 u32 sreg
= ace_in32(ace
, ACE_STATUS
);
776 u16 creg
= ace_in(ace
, ACE_CTRL
);
778 /* Check for error occurance */
779 if ((sreg
& (ACE_STATUS_CFGERROR
| ACE_STATUS_CFCERROR
)) &&
780 (creg
& ACE_CTRL_ERRORIRQ
)) {
781 dev_err(ace
->dev
, "transfer failure\n");
789 static irqreturn_t
ace_interrupt(int irq
, void *dev_id
)
792 struct ace_device
*ace
= dev_id
;
794 /* be safe and get the lock */
795 spin_lock(&ace
->lock
);
798 /* clear the interrupt */
799 creg
= ace_in(ace
, ACE_CTRL
);
800 ace_out(ace
, ACE_CTRL
, creg
| ACE_CTRL_RESETIRQ
);
801 ace_out(ace
, ACE_CTRL
, creg
);
803 /* check for IO failures */
804 if (ace_interrupt_checkstate(ace
))
805 ace
->data_result
= -EIO
;
807 if (ace
->fsm_task
== 0) {
809 "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n",
810 ace_in32(ace
, ACE_STATUS
), ace_in32(ace
, ACE_CTRL
),
811 ace_in(ace
, ACE_SECCNTCMD
));
812 dev_err(ace
->dev
, "fsm_task=%i fsm_state=%i data_count=%i\n",
813 ace
->fsm_task
, ace
->fsm_state
, ace
->data_count
);
816 /* Loop over state machine until told to stop */
817 ace
->fsm_continue_flag
= 1;
818 while (ace
->fsm_continue_flag
)
819 ace_fsm_dostate(ace
);
821 /* done with interrupt; drop the lock */
823 spin_unlock(&ace
->lock
);
828 /* ---------------------------------------------------------------------
831 static void ace_request(struct request_queue
* q
)
834 struct ace_device
*ace
;
836 req
= ace_get_next_request(q
);
839 ace
= req
->rq_disk
->private_data
;
840 tasklet_schedule(&ace
->fsm_tasklet
);
844 static int ace_media_changed(struct gendisk
*gd
)
846 struct ace_device
*ace
= gd
->private_data
;
847 dev_dbg(ace
->dev
, "ace_media_changed(): %i\n", ace
->media_change
);
849 return ace
->media_change
;
852 static int ace_revalidate_disk(struct gendisk
*gd
)
854 struct ace_device
*ace
= gd
->private_data
;
857 dev_dbg(ace
->dev
, "ace_revalidate_disk()\n");
859 if (ace
->media_change
) {
860 dev_dbg(ace
->dev
, "requesting cf id and scheduling tasklet\n");
862 spin_lock_irqsave(&ace
->lock
, flags
);
864 spin_unlock_irqrestore(&ace
->lock
, flags
);
866 tasklet_schedule(&ace
->fsm_tasklet
);
867 wait_for_completion(&ace
->id_completion
);
870 dev_dbg(ace
->dev
, "revalidate complete\n");
871 return ace
->id_result
;
874 static int ace_open(struct inode
*inode
, struct file
*filp
)
876 struct ace_device
*ace
= inode
->i_bdev
->bd_disk
->private_data
;
879 dev_dbg(ace
->dev
, "ace_open() users=%i\n", ace
->users
+ 1);
881 filp
->private_data
= ace
;
882 spin_lock_irqsave(&ace
->lock
, flags
);
884 spin_unlock_irqrestore(&ace
->lock
, flags
);
886 check_disk_change(inode
->i_bdev
);
890 static int ace_release(struct inode
*inode
, struct file
*filp
)
892 struct ace_device
*ace
= inode
->i_bdev
->bd_disk
->private_data
;
896 dev_dbg(ace
->dev
, "ace_release() users=%i\n", ace
->users
- 1);
898 spin_lock_irqsave(&ace
->lock
, flags
);
900 if (ace
->users
== 0) {
901 val
= ace_in(ace
, ACE_CTRL
);
902 ace_out(ace
, ACE_CTRL
, val
& ~ACE_CTRL_LOCKREQ
);
904 spin_unlock_irqrestore(&ace
->lock
, flags
);
908 static int ace_getgeo(struct block_device
*bdev
, struct hd_geometry
*geo
)
910 struct ace_device
*ace
= bdev
->bd_disk
->private_data
;
912 dev_dbg(ace
->dev
, "ace_getgeo()\n");
914 geo
->heads
= ace
->cf_id
.heads
;
915 geo
->sectors
= ace
->cf_id
.sectors
;
916 geo
->cylinders
= ace
->cf_id
.cyls
;
921 static struct block_device_operations ace_fops
= {
922 .owner
= THIS_MODULE
,
924 .release
= ace_release
,
925 .media_changed
= ace_media_changed
,
926 .revalidate_disk
= ace_revalidate_disk
,
927 .getgeo
= ace_getgeo
,
930 /* --------------------------------------------------------------------
931 * SystemACE device setup/teardown code
933 static int __devinit
ace_setup(struct ace_device
*ace
)
939 dev_dbg(ace
->dev
, "ace_setup(ace=0x%p)\n", ace
);
940 dev_dbg(ace
->dev
, "physaddr=0x%lx irq=%i\n", ace
->physaddr
, ace
->irq
);
942 spin_lock_init(&ace
->lock
);
943 init_completion(&ace
->id_completion
);
948 ace
->baseaddr
= ioremap(ace
->physaddr
, 0x80);
953 * Initialize the state machine tasklet and stall timer
955 tasklet_init(&ace
->fsm_tasklet
, ace_fsm_tasklet
, (unsigned long)ace
);
956 setup_timer(&ace
->stall_timer
, ace_stall_timer
, (unsigned long)ace
);
959 * Initialize the request queue
961 ace
->queue
= blk_init_queue(ace_request
, &ace
->lock
);
962 if (ace
->queue
== NULL
)
964 blk_queue_hardsect_size(ace
->queue
, 512);
967 * Allocate and initialize GD structure
969 ace
->gd
= alloc_disk(ACE_NUM_MINORS
);
973 ace
->gd
->major
= ace_major
;
974 ace
->gd
->first_minor
= ace
->id
* ACE_NUM_MINORS
;
975 ace
->gd
->fops
= &ace_fops
;
976 ace
->gd
->queue
= ace
->queue
;
977 ace
->gd
->private_data
= ace
;
978 snprintf(ace
->gd
->disk_name
, 32, "xs%c", ace
->id
+ 'a');
981 if (ace
->bus_width
== ACE_BUS_WIDTH_16
) {
982 /* 0x0101 should work regardless of endianess */
983 ace_out_le16(ace
, ACE_BUSMODE
, 0x0101);
985 /* read it back to determine endianess */
986 if (ace_in_le16(ace
, ACE_BUSMODE
) == 0x0001)
987 ace
->reg_ops
= &ace_reg_le16_ops
;
989 ace
->reg_ops
= &ace_reg_be16_ops
;
991 ace_out_8(ace
, ACE_BUSMODE
, 0x00);
992 ace
->reg_ops
= &ace_reg_8_ops
;
995 /* Make sure version register is sane */
996 version
= ace_in(ace
, ACE_VERSION
);
997 if ((version
== 0) || (version
== 0xFFFF))
1000 /* Put sysace in a sane state by clearing most control reg bits */
1001 ace_out(ace
, ACE_CTRL
, ACE_CTRL_FORCECFGMODE
|
1002 ACE_CTRL_DATABUFRDYIRQ
| ACE_CTRL_ERRORIRQ
);
1004 /* Enable interrupts */
1005 val
= ace_in(ace
, ACE_CTRL
);
1006 val
|= ACE_CTRL_DATABUFRDYIRQ
| ACE_CTRL_ERRORIRQ
;
1007 ace_out(ace
, ACE_CTRL
, val
);
1009 /* Now we can hook up the irq handler */
1010 if (ace
->irq
!= NO_IRQ
) {
1011 rc
= request_irq(ace
->irq
, ace_interrupt
, 0, "systemace", ace
);
1013 /* Failure - fall back to polled mode */
1014 dev_err(ace
->dev
, "request_irq failed\n");
1019 /* Print the identification */
1020 dev_info(ace
->dev
, "Xilinx SystemACE revision %i.%i.%i\n",
1021 (version
>> 12) & 0xf, (version
>> 8) & 0x0f, version
& 0xff);
1022 dev_dbg(ace
->dev
, "physaddr 0x%lx, mapped to 0x%p, irq=%i\n",
1023 ace
->physaddr
, ace
->baseaddr
, ace
->irq
);
1025 ace
->media_change
= 1;
1026 ace_revalidate_disk(ace
->gd
);
1028 /* Make the sysace device 'live' */
1036 blk_cleanup_queue(ace
->queue
);
1038 iounmap(ace
->baseaddr
);
1040 dev_info(ace
->dev
, "xsysace: error initializing device at 0x%lx\n",
1045 static void __devexit
ace_teardown(struct ace_device
*ace
)
1048 del_gendisk(ace
->gd
);
1053 blk_cleanup_queue(ace
->queue
);
1055 tasklet_kill(&ace
->fsm_tasklet
);
1057 if (ace
->irq
!= NO_IRQ
)
1058 free_irq(ace
->irq
, ace
);
1060 iounmap(ace
->baseaddr
);
1063 static int __devinit
1064 ace_alloc(struct device
*dev
, int id
, unsigned long physaddr
,
1065 int irq
, int bus_width
)
1067 struct ace_device
*ace
;
1069 dev_dbg(dev
, "ace_alloc(%p)\n", dev
);
1076 /* Allocate and initialize the ace device structure */
1077 ace
= kzalloc(sizeof(struct ace_device
), GFP_KERNEL
);
1085 ace
->physaddr
= physaddr
;
1087 ace
->bus_width
= bus_width
;
1089 /* Call the setup code */
1090 if ((rc
= ace_setup(ace
)) != 0)
1093 dev_set_drvdata(dev
, ace
);
1097 dev_set_drvdata(dev
, NULL
);
1101 dev_err(dev
, "could not initialize device, err=%i\n", rc
);
1105 static void __devexit
ace_free(struct device
*dev
)
1107 struct ace_device
*ace
= dev_get_drvdata(dev
);
1108 dev_dbg(dev
, "ace_free(%p)\n", dev
);
1112 dev_set_drvdata(dev
, NULL
);
1117 /* ---------------------------------------------------------------------
1118 * Platform Bus Support
1121 static int __devinit
ace_probe(struct platform_device
*dev
)
1123 unsigned long physaddr
= 0;
1124 int bus_width
= ACE_BUS_WIDTH_16
; /* FIXME: should not be hard coded */
1129 dev_dbg(&dev
->dev
, "ace_probe(%p)\n", dev
);
1131 for (i
= 0; i
< dev
->num_resources
; i
++) {
1132 if (dev
->resource
[i
].flags
& IORESOURCE_MEM
)
1133 physaddr
= dev
->resource
[i
].start
;
1134 if (dev
->resource
[i
].flags
& IORESOURCE_IRQ
)
1135 irq
= dev
->resource
[i
].start
;
1138 /* Call the bus-independant setup code */
1139 return ace_alloc(&dev
->dev
, id
, physaddr
, irq
, bus_width
);
1143 * Platform bus remove() method
1145 static int __devexit
ace_remove(struct platform_device
*dev
)
1147 ace_free(&dev
->dev
);
1151 static struct platform_driver ace_platform_driver
= {
1153 .remove
= __devexit_p(ace_remove
),
1155 .owner
= THIS_MODULE
,
1160 /* ---------------------------------------------------------------------
1161 * Module init/exit routines
1163 static int __init
ace_init(void)
1167 ace_major
= register_blkdev(ace_major
, "xsysace");
1168 if (ace_major
<= 0) {
1173 pr_debug("xsysace: registering platform binding\n");
1174 if ((rc
= platform_driver_register(&ace_platform_driver
)) != 0)
1177 pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major
);
1181 unregister_blkdev(ace_major
, "xsysace");
1183 printk(KERN_ERR
"xsysace: registration failed; err=%i\n", rc
);
1187 static void __exit
ace_exit(void)
1189 pr_debug("Unregistering Xilinx SystemACE driver\n");
1190 platform_driver_unregister(&ace_platform_driver
);
1191 unregister_blkdev(ace_major
, "xsysace");
1194 module_init(ace_init
);
1195 module_exit(ace_exit
);