drivers/video/geode/lxfb.h

   1 #ifndef _LXFB_H_
   2 #define _LXFB_H_
   3
   4 #include <linux/fb.h>
   5
   6 #define GP_REG_COUNT    (0x7c / 4)
   7 #define DC_REG_COUNT    (0xf0 / 4)
   8 #define VP_REG_COUNT    (0x158 / 8)
   9 #define FP_REG_COUNT    (0x60 / 8)
  10
  11 #define DC_PAL_COUNT    0x104
  12 #define DC_HFILT_COUNT  0x100
  13 #define DC_VFILT_COUNT  0x100
  14 #define VP_COEFF_SIZE   0x1000
  15
  16 #define OUTPUT_CRT   0x01
  17 #define OUTPUT_PANEL 0x02
  18
  19 struct lxfb_par {
  20         int output;
  21
  22         void __iomem *gp_regs;
  23         void __iomem *dc_regs;
  24         void __iomem *vp_regs;
  25 #ifdef CONFIG_PM
  26         int powered_down;
  27
  28         /* register state, for power mgmt functionality */
  29         struct {
  30                 uint64_t padsel;
  31                 uint64_t dotpll;
  32                 uint64_t dfglcfg;
  33                 uint64_t dcspare;
  34         } msr;
  35
  36         uint32_t gp[GP_REG_COUNT];
  37         uint32_t dc[DC_REG_COUNT];
  38         uint64_t vp[VP_REG_COUNT];
  39         uint64_t fp[FP_REG_COUNT];
  40
  41         uint32_t pal[DC_PAL_COUNT];
  42         uint32_t hcoeff[DC_HFILT_COUNT * 2];
  43         uint32_t vcoeff[DC_VFILT_COUNT];
  44         uint32_t vp_coeff[VP_COEFF_SIZE / 4];
  45 #endif
  46 };
  47
  48 static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
  49 {
  50         return (((xres * (bpp >> 3)) + 7) & ~7);
  51 }
  52
  53 void lx_set_mode(struct fb_info *);
  54 void lx_get_gamma(struct fb_info *, unsigned int *, int);
  55 void lx_set_gamma(struct fb_info *, unsigned int *, int);
  56 unsigned int lx_framebuffer_size(void);
  57 int lx_blank_display(struct fb_info *, int);
  58 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
  59                         unsigned int, unsigned int);
  60
  61 #ifdef CONFIG_PM
  62 int lx_powerdown(struct fb_info *info);
  63 int lx_powerup(struct fb_info *info);
  64 #endif
  65
  66
  67 /* Graphics Processor registers (table 6-29 from the data book) */
  68 enum gp_registers {
  69         GP_DST_OFFSET = 0,
  70         GP_SRC_OFFSET,
  71         GP_STRIDE,
  72         GP_WID_HEIGHT,
  73
  74         GP_SRC_COLOR_FG,
  75         GP_SRC_COLOR_BG,
  76         GP_PAT_COLOR_0,
  77         GP_PAT_COLOR_1,
  78
  79         GP_PAT_COLOR_2,
  80         GP_PAT_COLOR_3,
  81         GP_PAT_COLOR_4,
  82         GP_PAT_COLOR_5,
  83
  84         GP_PAT_DATA_0,
  85         GP_PAT_DATA_1,
  86         GP_RASTER_MODE,
  87         GP_VECTOR_MODE,
  88
  89         GP_BLT_MODE,
  90         GP_BLT_STATUS,
  91         GP_HST_SRC,
  92         GP_BASE_OFFSET,
  93
  94         GP_CMD_TOP,
  95         GP_CMD_BOT,
  96         GP_CMD_READ,
  97         GP_CMD_WRITE,
  98
  99         GP_CH3_OFFSET,
 100         GP_CH3_MODE_STR,
 101         GP_CH3_WIDHI,
 102         GP_CH3_HSRC,
 103
 104         GP_LUT_INDEX,
 105         GP_LUT_DATA,
 106         GP_INT_CNTRL, /* 0x78 */
 107 };
 108
 109 #define GP_BLT_STATUS_CE                (1 << 4)        /* cmd buf empty */
 110 #define GP_BLT_STATUS_PB                (1 << 0)        /* primative busy */
 111
 112
 113 /* Display Controller registers (table 6-47 from the data book) */
 114 enum dc_registers {
 115         DC_UNLOCK = 0,
 116         DC_GENERAL_CFG,
 117         DC_DISPLAY_CFG,
 118         DC_ARB_CFG,
 119
 120         DC_FB_ST_OFFSET,
 121         DC_CB_ST_OFFSET,
 122         DC_CURS_ST_OFFSET,
 123         DC_RSVD_0,
 124
 125         DC_VID_Y_ST_OFFSET,
 126         DC_VID_U_ST_OFFSET,
 127         DC_VID_V_ST_OFFSET,
 128         DC_DV_TOP,
 129
 130         DC_LINE_SIZE,
 131         DC_GFX_PITCH,
 132         DC_VID_YUV_PITCH,
 133         DC_RSVD_1,
 134
 135         DC_H_ACTIVE_TIMING,
 136         DC_H_BLANK_TIMING,
 137         DC_H_SYNC_TIMING,
 138         DC_RSVD_2,
 139
 140         DC_V_ACTIVE_TIMING,
 141         DC_V_BLANK_TIMING,
 142         DC_V_SYNC_TIMING,
 143         DC_FB_ACTIVE,
 144
 145         DC_CURSOR_X,
 146         DC_CURSOR_Y,
 147         DC_RSVD_3,
 148         DC_LINE_CNT,
 149
 150         DC_PAL_ADDRESS,
 151         DC_PAL_DATA,
 152         DC_DFIFO_DIAG,
 153         DC_CFIFO_DIAG,
 154
 155         DC_VID_DS_DELTA,
 156         DC_GLIU0_MEM_OFFSET,
 157         DC_DV_CTL,
 158         DC_DV_ACCESS,
 159
 160         DC_GFX_SCALE,
 161         DC_IRQ_FILT_CTL,
 162         DC_FILT_COEFF1,
 163         DC_FILT_COEFF2,
 164
 165         DC_VBI_EVEN_CTL,
 166         DC_VBI_ODD_CTL,
 167         DC_VBI_HOR,
 168         DC_VBI_LN_ODD,
 169
 170         DC_VBI_LN_EVEN,
 171         DC_VBI_PITCH,
 172         DC_CLR_KEY,
 173         DC_CLR_KEY_MASK,
 174
 175         DC_CLR_KEY_X,
 176         DC_CLR_KEY_Y,
 177         DC_IRQ,
 178         DC_RSVD_4,
 179
 180         DC_RSVD_5,
 181         DC_GENLK_CTL,
 182         DC_VID_EVEN_Y_ST_OFFSET,
 183         DC_VID_EVEN_U_ST_OFFSET,
 184
 185         DC_VID_EVEN_V_ST_OFFSET,
 186         DC_V_ACTIVE_EVEN_TIMING,
 187         DC_V_BLANK_EVEN_TIMING,
 188         DC_V_SYNC_EVEN_TIMING,  /* 0xec */
 189 };
 190
 191 #define DC_UNLOCK_LOCK                  0x00000000
 192 #define DC_UNLOCK_UNLOCK                0x00004758      /* magic value */
 193
 194 #define DC_GENERAL_CFG_FDTY             (1 << 17)
 195 #define DC_GENERAL_CFG_DFHPEL_SHIFT     (12)
 196 #define DC_GENERAL_CFG_DFHPSL_SHIFT     (8)
 197 #define DC_GENERAL_CFG_VGAE             (1 << 7)
 198 #define DC_GENERAL_CFG_DECE             (1 << 6)
 199 #define DC_GENERAL_CFG_CMPE             (1 << 5)
 200 #define DC_GENERAL_CFG_VIDE             (1 << 3)
 201 #define DC_GENERAL_CFG_DFLE             (1 << 0)
 202
 203 #define DC_DISPLAY_CFG_VISL             (1 << 27)
 204 #define DC_DISPLAY_CFG_PALB             (1 << 25)
 205 #define DC_DISPLAY_CFG_DCEN             (1 << 24)
 206 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
 207 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
 208 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
 209 #define DC_DISPLAY_CFG_TRUP             (1 << 6)
 210 #define DC_DISPLAY_CFG_VDEN             (1 << 4)
 211 #define DC_DISPLAY_CFG_GDEN             (1 << 3)
 212 #define DC_DISPLAY_CFG_TGEN             (1 << 0)
 213
 214 #define DC_DV_TOP_DV_TOP_EN             (1 << 0)
 215
 216 #define DC_DV_CTL_DV_LINE_SIZE          ((1 << 10) | (1 << 11))
 217 #define DC_DV_CTL_DV_LINE_SIZE_1K       (0)
 218 #define DC_DV_CTL_DV_LINE_SIZE_2K       (1 << 10)
 219 #define DC_DV_CTL_DV_LINE_SIZE_4K       (1 << 11)
 220 #define DC_DV_CTL_DV_LINE_SIZE_8K       ((1 << 10) | (1 << 11))
 221 #define DC_DV_CTL_CLEAR_DV_RAM          (1 << 0)
 222
 223 #define DC_IRQ_FILT_CTL_H_FILT_SEL      (1 << 10)
 224
 225 #define DC_CLR_KEY_CLR_KEY_EN           (1 << 24)
 226
 227 #define DC_IRQ_VIP_VSYNC_IRQ_STATUS     (1 << 21)       /* undocumented? */
 228 #define DC_IRQ_STATUS                   (1 << 20)       /* undocumented? */
 229 #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK  (1 << 1)
 230 #define DC_IRQ_MASK                     (1 << 0)
 231
 232 #define DC_GENLK_CTL_FLICK_SEL_MASK     (0x0F << 28)
 233 #define DC_GENLK_CTL_ALPHA_FLICK_EN     (1 << 25)
 234 #define DC_GENLK_CTL_FLICK_EN           (1 << 24)
 235 #define DC_GENLK_CTL_GENLK_EN           (1 << 18)
 236
 237
 238 /*
 239  * Video Processor registers (table 6-71).
 240  * There is space for 64 bit values, but we never use more than the
 241  * lower 32 bits.  The actual register save/restore code only bothers
 242  * to restore those 32 bits.
 243  */
 244 enum vp_registers {
 245         VP_VCFG = 0,
 246         VP_DCFG,
 247
 248         VP_VX,
 249         VP_VY,
 250
 251         VP_SCL,
 252         VP_VCK,
 253
 254         VP_VCM,
 255         VP_PAR,
 256
 257         VP_PDR,
 258         VP_SLR,
 259
 260         VP_MISC,
 261         VP_CCS,
 262
 263         VP_VYS,
 264         VP_VXS,
 265
 266         VP_RSVD_0,
 267         VP_VDC,
 268
 269         VP_RSVD_1,
 270         VP_CRC,
 271
 272         VP_CRC32,
 273         VP_VDE,
 274
 275         VP_CCK,
 276         VP_CCM,
 277
 278         VP_CC1,
 279         VP_CC2,
 280
 281         VP_A1X,
 282         VP_A1Y,
 283
 284         VP_A1C,
 285         VP_A1T,
 286
 287         VP_A2X,
 288         VP_A2Y,
 289
 290         VP_A2C,
 291         VP_A2T,
 292
 293         VP_A3X,
 294         VP_A3Y,
 295
 296         VP_A3C,
 297         VP_A3T,
 298
 299         VP_VRR,
 300         VP_AWT,
 301
 302         VP_VTM,
 303         VP_VYE,
 304
 305         VP_A1YE,
 306         VP_A2YE,
 307
 308         VP_A3YE,        /* 0x150 */
 309
 310         VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
 311 };
 312
 313 #define VP_VCFG_VID_EN                  (1 << 0)
 314
 315 #define VP_DCFG_GV_GAM                  (1 << 21)
 316 #define VP_DCFG_PWR_SEQ_DELAY           ((1 << 17) | (1 << 18) | (1 << 19))
 317 #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT   (1 << 19)       /* undocumented */
 318 #define VP_DCFG_CRT_SYNC_SKW            ((1 << 14) | (1 << 15) | (1 << 16))
 319 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
 320 #define VP_DCFG_CRT_VSYNC_POL           (1 << 9)
 321 #define VP_DCFG_CRT_HSYNC_POL           (1 << 8)
 322 #define VP_DCFG_DAC_BL_EN               (1 << 3)
 323 #define VP_DCFG_VSYNC_EN                (1 << 2)
 324 #define VP_DCFG_HSYNC_EN                (1 << 1)
 325 #define VP_DCFG_CRT_EN                  (1 << 0)
 326
 327 #define VP_MISC_APWRDN                  (1 << 11)
 328 #define VP_MISC_DACPWRDN                (1 << 10)
 329 #define VP_MISC_BYP_BOTH                (1 << 0)
 330
 331
 332 /*
 333  * Flat Panel registers (table 6-71).
 334  * Also 64 bit registers; see above note about 32-bit handling.
 335  */
 336
 337 /* we're actually in the VP register space, starting at address 0x400 */
 338 #define VP_FP_START     0x400
 339
 340 enum fp_registers {
 341         FP_PT1 = 0,
 342         FP_PT2,
 343
 344         FP_PM,
 345         FP_DFC,
 346
 347         FP_RSVD_0,
 348         FP_RSVD_1,
 349
 350         FP_RSVD_2,
 351         FP_RSVD_3,
 352
 353         FP_RSVD_4,
 354         FP_DCA,
 355
 356         FP_DMD,
 357         FP_CRC, /* 0x458 */
 358 };
 359
 360 #define FP_PT2_SCRC                     (1 << 27)       /* shfclk free */
 361
 362 #define FP_PM_P                         (1 << 24)       /* panel power ctl */
 363 #define FP_PM_PANEL_PWR_UP              (1 << 3)        /* r/o */
 364 #define FP_PM_PANEL_PWR_DOWN            (1 << 2)        /* r/o */
 365 #define FP_PM_PANEL_OFF                 (1 << 1)        /* r/o */
 366 #define FP_PM_PANEL_ON                  (1 << 0)        /* r/o */
 367
 368 #define FP_DFC_BC                       ((1 << 4) | (1 << 5) | (1 << 6))
 369
 370
 371 /* register access functions */
 372
 373 static inline uint32_t read_gp(struct lxfb_par *par, int reg)
 374 {
 375         return readl(par->gp_regs + 4*reg);
 376 }
 377
 378 static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
 379 {
 380         writel(val, par->gp_regs + 4*reg);
 381 }
 382
 383 static inline uint32_t read_dc(struct lxfb_par *par, int reg)
 384 {
 385         return readl(par->dc_regs + 4*reg);
 386 }
 387
 388 static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
 389 {
 390         writel(val, par->dc_regs + 4*reg);
 391 }
 392
 393 static inline uint32_t read_vp(struct lxfb_par *par, int reg)
 394 {
 395         return readl(par->vp_regs + 8*reg);
 396 }
 397
 398 static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
 399 {
 400         writel(val, par->vp_regs + 8*reg);
 401 }
 402
 403 static inline uint32_t read_fp(struct lxfb_par *par, int reg)
 404 {
 405         return readl(par->vp_regs + 8*reg + VP_FP_START);
 406 }
 407
 408 static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
 409 {
 410         writel(val, par->vp_regs + 8*reg + VP_FP_START);
 411 }
 412
 413
 414 /* MSRs are defined in asm/geode.h; their bitfields are here */
 415
 416 #define MSR_GLCP_DOTPLL_LOCK            (1 << 25)       /* r/o */
 417 #define MSR_GLCP_DOTPLL_HALFPIX         (1 << 24)
 418 #define MSR_GLCP_DOTPLL_BYPASS          (1 << 15)
 419 #define MSR_GLCP_DOTPLL_DOTRESET        (1 << 0)
 420
 421 /* note: this is actually the VP's GLD_MSR_CONFIG */
 422 #define MSR_LX_GLD_MSR_CONFIG_FMT       ((1 << 3) | (1 << 4) | (1 << 5))
 423 #define MSR_LX_GLD_MSR_CONFIG_FMT_FP    (1 << 3)
 424 #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT   (0)
 425 #define MSR_LX_GLD_MSR_CONFIG_FPC       (1 << 15)       /* FP *and* CRT */
 426
 427 #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW   0xDFFFFFFF      /* ??? */
 428 #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH  0x0000003F      /* ??? */
 429
 430 #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO  (1 << 11)       /* undocumented */
 431 #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL  (1 << 10)       /* undocumented */
 432 #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD   (1 << 9)        /* undocumented */
 433 #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8)        /* undocumented */
 434 #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7)        /* undocumented */
 435 #define MSR_LX_SPARE_MSR_DIS_VIFO_WM    (1 << 6)
 436 #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK  (1 << 5)        /* undocumented */
 437 #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX   (1 << 4)        /* undocumented */
 438 #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1)        /* undocumented */
 439
 440 #endif