6 #define GP_REG_COUNT (0x7c / 4)
7 #define DC_REG_COUNT (0xf0 / 4)
8 #define VP_REG_COUNT (0x158 / 8)
9 #define FP_REG_COUNT (0x60 / 8)
11 #define DC_PAL_COUNT 0x104
12 #define DC_HFILT_COUNT 0x100
13 #define DC_VFILT_COUNT 0x100
14 #define VP_COEFF_SIZE 0x1000
16 #define OUTPUT_CRT 0x01
17 #define OUTPUT_PANEL 0x02
22 void __iomem
*gp_regs
;
23 void __iomem
*dc_regs
;
24 void __iomem
*vp_regs
;
28 /* register state, for power mgmt functionality */
36 uint32_t gp
[GP_REG_COUNT
];
37 uint32_t dc
[DC_REG_COUNT
];
38 uint64_t vp
[VP_REG_COUNT
];
39 uint64_t fp
[FP_REG_COUNT
];
41 uint32_t pal
[DC_PAL_COUNT
];
42 uint32_t hcoeff
[DC_HFILT_COUNT
* 2];
43 uint32_t vcoeff
[DC_VFILT_COUNT
];
44 uint32_t vp_coeff
[VP_COEFF_SIZE
/ 4];
48 static inline unsigned int lx_get_pitch(unsigned int xres
, int bpp
)
50 return (((xres
* (bpp
>> 3)) + 7) & ~7);
53 void lx_set_mode(struct fb_info
*);
54 void lx_get_gamma(struct fb_info
*, unsigned int *, int);
55 void lx_set_gamma(struct fb_info
*, unsigned int *, int);
56 unsigned int lx_framebuffer_size(void);
57 int lx_blank_display(struct fb_info
*, int);
58 void lx_set_palette_reg(struct fb_info
*, unsigned int, unsigned int,
59 unsigned int, unsigned int);
62 int lx_powerdown(struct fb_info
*info
);
63 int lx_powerup(struct fb_info
*info
);
67 /* Graphics Processor registers (table 6-29 from the data book) */
106 GP_INT_CNTRL
, /* 0x78 */
109 #define GP_BLT_STATUS_CE (1 << 4) /* cmd buf empty */
110 #define GP_BLT_STATUS_PB (1 << 0) /* primative busy */
113 /* Display Controller registers (table 6-47 from the data book) */
182 DC_VID_EVEN_Y_ST_OFFSET
,
183 DC_VID_EVEN_U_ST_OFFSET
,
185 DC_VID_EVEN_V_ST_OFFSET
,
186 DC_V_ACTIVE_EVEN_TIMING
,
187 DC_V_BLANK_EVEN_TIMING
,
188 DC_V_SYNC_EVEN_TIMING
, /* 0xec */
191 #define DC_UNLOCK_LOCK 0x00000000
192 #define DC_UNLOCK_UNLOCK 0x00004758 /* magic value */
194 #define DC_GENERAL_CFG_FDTY (1 << 17)
195 #define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
196 #define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
197 #define DC_GENERAL_CFG_VGAE (1 << 7)
198 #define DC_GENERAL_CFG_DECE (1 << 6)
199 #define DC_GENERAL_CFG_CMPE (1 << 5)
200 #define DC_GENERAL_CFG_VIDE (1 << 3)
201 #define DC_GENERAL_CFG_DFLE (1 << 0)
203 #define DC_DISPLAY_CFG_VISL (1 << 27)
204 #define DC_DISPLAY_CFG_PALB (1 << 25)
205 #define DC_DISPLAY_CFG_DCEN (1 << 24)
206 #define DC_DISPLAY_CFG_DISP_MODE_24BPP (1 << 9)
207 #define DC_DISPLAY_CFG_DISP_MODE_16BPP (1 << 8)
208 #define DC_DISPLAY_CFG_DISP_MODE_8BPP (0)
209 #define DC_DISPLAY_CFG_TRUP (1 << 6)
210 #define DC_DISPLAY_CFG_VDEN (1 << 4)
211 #define DC_DISPLAY_CFG_GDEN (1 << 3)
212 #define DC_DISPLAY_CFG_TGEN (1 << 0)
214 #define DC_DV_TOP_DV_TOP_EN (1 << 0)
216 #define DC_DV_CTL_DV_LINE_SIZE ((1 << 10) | (1 << 11))
217 #define DC_DV_CTL_DV_LINE_SIZE_1K (0)
218 #define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
219 #define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
220 #define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
221 #define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
223 #define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
225 #define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
227 #define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21) /* undocumented? */
228 #define DC_IRQ_STATUS (1 << 20) /* undocumented? */
229 #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK (1 << 1)
230 #define DC_IRQ_MASK (1 << 0)
232 #define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
233 #define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
234 #define DC_GENLK_CTL_FLICK_EN (1 << 24)
235 #define DC_GENLK_CTL_GENLK_EN (1 << 18)
239 * Video Processor registers (table 6-71).
240 * There is space for 64 bit values, but we never use more than the
241 * lower 32 bits. The actual register save/restore code only bothers
242 * to restore those 32 bits.
310 VP_VCR
= 0x1000, /* 0x1000 - 0x1fff */
313 #define VP_VCFG_VID_EN (1 << 0)
315 #define VP_DCFG_GV_GAM (1 << 21)
316 #define VP_DCFG_PWR_SEQ_DELAY ((1 << 17) | (1 << 18) | (1 << 19))
317 #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT (1 << 19) /* undocumented */
318 #define VP_DCFG_CRT_SYNC_SKW ((1 << 14) | (1 << 15) | (1 << 16))
319 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT (1 << 16)
320 #define VP_DCFG_CRT_VSYNC_POL (1 << 9)
321 #define VP_DCFG_CRT_HSYNC_POL (1 << 8)
322 #define VP_DCFG_DAC_BL_EN (1 << 3)
323 #define VP_DCFG_VSYNC_EN (1 << 2)
324 #define VP_DCFG_HSYNC_EN (1 << 1)
325 #define VP_DCFG_CRT_EN (1 << 0)
327 #define VP_MISC_APWRDN (1 << 11)
328 #define VP_MISC_DACPWRDN (1 << 10)
329 #define VP_MISC_BYP_BOTH (1 << 0)
333 * Flat Panel registers (table 6-71).
334 * Also 64 bit registers; see above note about 32-bit handling.
337 /* we're actually in the VP register space, starting at address 0x400 */
338 #define VP_FP_START 0x400
360 #define FP_PT2_SCRC (1 << 27) /* shfclk free */
362 #define FP_PM_P (1 << 24) /* panel power ctl */
363 #define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
364 #define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
365 #define FP_PM_PANEL_OFF (1 << 1) /* r/o */
366 #define FP_PM_PANEL_ON (1 << 0) /* r/o */
368 #define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
371 /* register access functions */
373 static inline uint32_t read_gp(struct lxfb_par
*par
, int reg
)
375 return readl(par
->gp_regs
+ 4*reg
);
378 static inline void write_gp(struct lxfb_par
*par
, int reg
, uint32_t val
)
380 writel(val
, par
->gp_regs
+ 4*reg
);
383 static inline uint32_t read_dc(struct lxfb_par
*par
, int reg
)
385 return readl(par
->dc_regs
+ 4*reg
);
388 static inline void write_dc(struct lxfb_par
*par
, int reg
, uint32_t val
)
390 writel(val
, par
->dc_regs
+ 4*reg
);
393 static inline uint32_t read_vp(struct lxfb_par
*par
, int reg
)
395 return readl(par
->vp_regs
+ 8*reg
);
398 static inline void write_vp(struct lxfb_par
*par
, int reg
, uint32_t val
)
400 writel(val
, par
->vp_regs
+ 8*reg
);
403 static inline uint32_t read_fp(struct lxfb_par
*par
, int reg
)
405 return readl(par
->vp_regs
+ 8*reg
+ VP_FP_START
);
408 static inline void write_fp(struct lxfb_par
*par
, int reg
, uint32_t val
)
410 writel(val
, par
->vp_regs
+ 8*reg
+ VP_FP_START
);
414 /* MSRs are defined in asm/geode.h; their bitfields are here */
416 #define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
417 #define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
418 #define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
419 #define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
421 /* note: this is actually the VP's GLD_MSR_CONFIG */
422 #define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
423 #define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
424 #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
425 #define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
427 #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
428 #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
430 #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
431 #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
432 #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
433 #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
434 #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
435 #define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
436 #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
437 #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
438 #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */