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ALSA: hda - Remove duplicated strings from codec name
[linux-2.6/mini2440.git] / drivers / scsi / lpfc / lpfc_hw.h
blob7773b949aa7c8b8f320fefc83ba5a767f3cf3d34
1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2008 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
30
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
33
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
48
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
66
67
68 /* Common Transport structures and definitions */
69
70 union CtRevisionId {
71 /* Structure is in Big Endian format */
72 struct {
73 uint32_t Revision:8;
74 uint32_t InId:24;
75 } bits;
76 uint32_t word;
77 };
78
79 union CtCommandResponse {
80 /* Structure is in Big Endian format */
81 struct {
82 uint32_t CmdRsp:16;
83 uint32_t Size:16;
84 } bits;
85 uint32_t word;
86 };
87
88 #define FC4_FEATURE_INIT 0x2
89 #define FC4_FEATURE_TARGET 0x1
90
91 struct lpfc_sli_ct_request {
92 /* Structure is in Big Endian format */
93 union CtRevisionId RevisionId;
94 uint8_t FsType;
95 uint8_t FsSubType;
96 uint8_t Options;
97 uint8_t Rsrvd1;
98 union CtCommandResponse CommandResponse;
99 uint8_t Rsrvd2;
100 uint8_t ReasonCode;
101 uint8_t Explanation;
102 uint8_t VendorUnique;
103
104 union {
105 uint32_t PortID;
106 struct gid {
107 uint8_t PortType; /* for GID_PT requests */
108 uint8_t DomainScope;
109 uint8_t AreaScope;
110 uint8_t Fc4Type; /* for GID_FT requests */
111 } gid;
112 struct rft {
113 uint32_t PortId; /* For RFT_ID requests */
114
115 #ifdef __BIG_ENDIAN_BITFIELD
116 uint32_t rsvd0:16;
117 uint32_t rsvd1:7;
118 uint32_t fcpReg:1; /* Type 8 */
119 uint32_t rsvd2:2;
120 uint32_t ipReg:1; /* Type 5 */
121 uint32_t rsvd3:5;
122 #else /* __LITTLE_ENDIAN_BITFIELD */
123 uint32_t rsvd0:16;
124 uint32_t fcpReg:1; /* Type 8 */
125 uint32_t rsvd1:7;
126 uint32_t rsvd3:5;
127 uint32_t ipReg:1; /* Type 5 */
128 uint32_t rsvd2:2;
129 #endif
130
131 uint32_t rsvd[7];
132 } rft;
133 struct rnn {
134 uint32_t PortId; /* For RNN_ID requests */
135 uint8_t wwnn[8];
136 } rnn;
137 struct rsnn { /* For RSNN_ID requests */
138 uint8_t wwnn[8];
139 uint8_t len;
140 uint8_t symbname[255];
141 } rsnn;
142 struct da_id { /* For DA_ID requests */
143 uint32_t port_id;
144 } da_id;
145 struct rspn { /* For RSPN_ID requests */
146 uint32_t PortId;
147 uint8_t len;
148 uint8_t symbname[255];
149 } rspn;
150 struct gff {
151 uint32_t PortId;
152 } gff;
153 struct gff_acc {
154 uint8_t fbits[128];
155 } gff_acc;
156 #define FCP_TYPE_FEATURE_OFFSET 7
157 struct rff {
158 uint32_t PortId;
159 uint8_t reserved[2];
160 uint8_t fbits;
161 uint8_t type_code; /* type=8 for FCP */
162 } rff;
163 } un;
164 };
165
166 #define SLI_CT_REVISION 1
167 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
168 sizeof(struct gid))
169 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
170 sizeof(struct gff))
171 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
172 sizeof(struct rft))
173 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
174 sizeof(struct rff))
175 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
176 sizeof(struct rnn))
177 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
178 sizeof(struct rsnn))
179 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180 sizeof(struct da_id))
181 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
182 sizeof(struct rspn))
183
184 /*
185 * FsType Definitions
186 */
187
188 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
189 #define SLI_CT_TIME_SERVICE 0xFB
190 #define SLI_CT_DIRECTORY_SERVICE 0xFC
191 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
192
193 /*
194 * Directory Service Subtypes
195 */
196
197 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
198
199 /*
200 * Response Codes
201 */
202
203 #define SLI_CT_RESPONSE_FS_RJT 0x8001
204 #define SLI_CT_RESPONSE_FS_ACC 0x8002
205
206 /*
207 * Reason Codes
208 */
209
210 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
211 #define SLI_CT_INVALID_COMMAND 0x01
212 #define SLI_CT_INVALID_VERSION 0x02
213 #define SLI_CT_LOGICAL_ERROR 0x03
214 #define SLI_CT_INVALID_IU_SIZE 0x04
215 #define SLI_CT_LOGICAL_BUSY 0x05
216 #define SLI_CT_PROTOCOL_ERROR 0x07
217 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
218 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
219 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
220 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
221 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
222 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
223 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
224 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
225 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
226 #define SLI_CT_VENDOR_UNIQUE 0xff
227
228 /*
229 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
230 */
231
232 #define SLI_CT_NO_PORT_ID 0x01
233 #define SLI_CT_NO_PORT_NAME 0x02
234 #define SLI_CT_NO_NODE_NAME 0x03
235 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
236 #define SLI_CT_NO_IP_ADDRESS 0x05
237 #define SLI_CT_NO_IPA 0x06
238 #define SLI_CT_NO_FC4_TYPES 0x07
239 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
240 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
241 #define SLI_CT_NO_PORT_TYPE 0x0A
242 #define SLI_CT_ACCESS_DENIED 0x10
243 #define SLI_CT_INVALID_PORT_ID 0x11
244 #define SLI_CT_DATABASE_EMPTY 0x12
245
246 /*
247 * Name Server Command Codes
248 */
249
250 #define SLI_CTNS_GA_NXT 0x0100
251 #define SLI_CTNS_GPN_ID 0x0112
252 #define SLI_CTNS_GNN_ID 0x0113
253 #define SLI_CTNS_GCS_ID 0x0114
254 #define SLI_CTNS_GFT_ID 0x0117
255 #define SLI_CTNS_GSPN_ID 0x0118
256 #define SLI_CTNS_GPT_ID 0x011A
257 #define SLI_CTNS_GFF_ID 0x011F
258 #define SLI_CTNS_GID_PN 0x0121
259 #define SLI_CTNS_GID_NN 0x0131
260 #define SLI_CTNS_GIP_NN 0x0135
261 #define SLI_CTNS_GIPA_NN 0x0136
262 #define SLI_CTNS_GSNN_NN 0x0139
263 #define SLI_CTNS_GNN_IP 0x0153
264 #define SLI_CTNS_GIPA_IP 0x0156
265 #define SLI_CTNS_GID_FT 0x0171
266 #define SLI_CTNS_GID_PT 0x01A1
267 #define SLI_CTNS_RPN_ID 0x0212
268 #define SLI_CTNS_RNN_ID 0x0213
269 #define SLI_CTNS_RCS_ID 0x0214
270 #define SLI_CTNS_RFT_ID 0x0217
271 #define SLI_CTNS_RSPN_ID 0x0218
272 #define SLI_CTNS_RPT_ID 0x021A
273 #define SLI_CTNS_RFF_ID 0x021F
274 #define SLI_CTNS_RIP_NN 0x0235
275 #define SLI_CTNS_RIPA_NN 0x0236
276 #define SLI_CTNS_RSNN_NN 0x0239
277 #define SLI_CTNS_DA_ID 0x0300
278
279 /*
280 * Port Types
281 */
282
283 #define SLI_CTPT_N_PORT 0x01
284 #define SLI_CTPT_NL_PORT 0x02
285 #define SLI_CTPT_FNL_PORT 0x03
286 #define SLI_CTPT_IP 0x04
287 #define SLI_CTPT_FCP 0x08
288 #define SLI_CTPT_NX_PORT 0x7F
289 #define SLI_CTPT_F_PORT 0x81
290 #define SLI_CTPT_FL_PORT 0x82
291 #define SLI_CTPT_E_PORT 0x84
292
293 #define SLI_CT_LAST_ENTRY 0x80000000
294
295 /* Fibre Channel Service Parameter definitions */
296
297 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
298 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
299 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
300 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
301
302 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
303 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
304 #define FC_PH3 0x20 /* FC-PH-3 version */
305
306 #define FF_FRAME_SIZE 2048
307
308 struct lpfc_name {
309 union {
310 struct {
311 #ifdef __BIG_ENDIAN_BITFIELD
312 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
313 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
314 8:11 of IEEE ext */
315 #else /* __LITTLE_ENDIAN_BITFIELD */
316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
317 8:11 of IEEE ext */
318 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
319 #endif
320
321 #define NAME_IEEE 0x1 /* IEEE name - nameType */
322 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
323 #define NAME_FC_TYPE 0x3 /* FC native name type */
324 #define NAME_IP_TYPE 0x4 /* IP address */
325 #define NAME_CCITT_TYPE 0xC
326 #define NAME_CCITT_GR_TYPE 0xE
327 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
328 extended Lsb */
329 uint8_t IEEE[6]; /* FC IEEE address */
330 } s;
331 uint8_t wwn[8];
332 } u;
333 };
334
335 struct csp {
336 uint8_t fcphHigh; /* FC Word 0, byte 0 */
337 uint8_t fcphLow;
338 uint8_t bbCreditMsb;
339 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
340
341 #ifdef __BIG_ENDIAN_BITFIELD
342 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
343 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
344 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
345 uint16_t fPort:1; /* FC Word 1, bit 28 */
346 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
347 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
348 uint16_t multicast:1; /* FC Word 1, bit 25 */
349 uint16_t broadcast:1; /* FC Word 1, bit 24 */
350
351 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
352 uint16_t simplex:1; /* FC Word 1, bit 22 */
353 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
354 uint16_t dhd:1; /* FC Word 1, bit 18 */
355 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
356 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
357 #else /* __LITTLE_ENDIAN_BITFIELD */
358 uint16_t broadcast:1; /* FC Word 1, bit 24 */
359 uint16_t multicast:1; /* FC Word 1, bit 25 */
360 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
361 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
362 uint16_t fPort:1; /* FC Word 1, bit 28 */
363 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
364 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
365 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
366
367 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
368 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
369 uint16_t dhd:1; /* FC Word 1, bit 18 */
370 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
371 uint16_t simplex:1; /* FC Word 1, bit 22 */
372 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
373 #endif
374
375 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
376 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
377 union {
378 struct {
379 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
380
381 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
382 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
383
384 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
385 } nPort;
386 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
387 } w2;
388
389 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
390 };
391
392 struct class_parms {
393 #ifdef __BIG_ENDIAN_BITFIELD
394 uint8_t classValid:1; /* FC Word 0, bit 31 */
395 uint8_t intermix:1; /* FC Word 0, bit 30 */
396 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
397 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
398 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
399 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
400 #else /* __LITTLE_ENDIAN_BITFIELD */
401 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
402 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
403 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
404 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
405 uint8_t intermix:1; /* FC Word 0, bit 30 */
406 uint8_t classValid:1; /* FC Word 0, bit 31 */
407
408 #endif
409
410 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
411
412 #ifdef __BIG_ENDIAN_BITFIELD
413 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
414 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
415 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
416 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
417 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
418 #else /* __LITTLE_ENDIAN_BITFIELD */
419 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
420 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
421 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
422 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
423 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
424 #endif
425
426 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
427
428 #ifdef __BIG_ENDIAN_BITFIELD
429 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
430 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
431 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
432 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
433 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
434 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
435 #else /* __LITTLE_ENDIAN_BITFIELD */
436 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
437 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
438 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
439 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
440 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
441 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
442 #endif
443
444 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
445 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
446 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
447
448 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
449 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
450 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
451 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
452
453 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
454 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
455 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
456 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
457 };
458
459 struct serv_parm { /* Structure is in Big Endian format */
460 struct csp cmn;
461 struct lpfc_name portName;
462 struct lpfc_name nodeName;
463 struct class_parms cls1;
464 struct class_parms cls2;
465 struct class_parms cls3;
466 struct class_parms cls4;
467 uint8_t vendorVersion[16];
468 };
469
470 /*
471 * Extended Link Service LS_COMMAND codes (Payload Word 0)
472 */
473 #ifdef __BIG_ENDIAN_BITFIELD
474 #define ELS_CMD_MASK 0xffff0000
475 #define ELS_RSP_MASK 0xff000000
476 #define ELS_CMD_LS_RJT 0x01000000
477 #define ELS_CMD_ACC 0x02000000
478 #define ELS_CMD_PLOGI 0x03000000
479 #define ELS_CMD_FLOGI 0x04000000
480 #define ELS_CMD_LOGO 0x05000000
481 #define ELS_CMD_ABTX 0x06000000
482 #define ELS_CMD_RCS 0x07000000
483 #define ELS_CMD_RES 0x08000000
484 #define ELS_CMD_RSS 0x09000000
485 #define ELS_CMD_RSI 0x0A000000
486 #define ELS_CMD_ESTS 0x0B000000
487 #define ELS_CMD_ESTC 0x0C000000
488 #define ELS_CMD_ADVC 0x0D000000
489 #define ELS_CMD_RTV 0x0E000000
490 #define ELS_CMD_RLS 0x0F000000
491 #define ELS_CMD_ECHO 0x10000000
492 #define ELS_CMD_TEST 0x11000000
493 #define ELS_CMD_RRQ 0x12000000
494 #define ELS_CMD_PRLI 0x20100014
495 #define ELS_CMD_PRLO 0x21100014
496 #define ELS_CMD_PRLO_ACC 0x02100014
497 #define ELS_CMD_PDISC 0x50000000
498 #define ELS_CMD_FDISC 0x51000000
499 #define ELS_CMD_ADISC 0x52000000
500 #define ELS_CMD_FARP 0x54000000
501 #define ELS_CMD_FARPR 0x55000000
502 #define ELS_CMD_RPS 0x56000000
503 #define ELS_CMD_RPL 0x57000000
504 #define ELS_CMD_FAN 0x60000000
505 #define ELS_CMD_RSCN 0x61040000
506 #define ELS_CMD_SCR 0x62000000
507 #define ELS_CMD_RNID 0x78000000
508 #define ELS_CMD_LIRR 0x7A000000
509 #else /* __LITTLE_ENDIAN_BITFIELD */
510 #define ELS_CMD_MASK 0xffff
511 #define ELS_RSP_MASK 0xff
512 #define ELS_CMD_LS_RJT 0x01
513 #define ELS_CMD_ACC 0x02
514 #define ELS_CMD_PLOGI 0x03
515 #define ELS_CMD_FLOGI 0x04
516 #define ELS_CMD_LOGO 0x05
517 #define ELS_CMD_ABTX 0x06
518 #define ELS_CMD_RCS 0x07
519 #define ELS_CMD_RES 0x08
520 #define ELS_CMD_RSS 0x09
521 #define ELS_CMD_RSI 0x0A
522 #define ELS_CMD_ESTS 0x0B
523 #define ELS_CMD_ESTC 0x0C
524 #define ELS_CMD_ADVC 0x0D
525 #define ELS_CMD_RTV 0x0E
526 #define ELS_CMD_RLS 0x0F
527 #define ELS_CMD_ECHO 0x10
528 #define ELS_CMD_TEST 0x11
529 #define ELS_CMD_RRQ 0x12
530 #define ELS_CMD_PRLI 0x14001020
531 #define ELS_CMD_PRLO 0x14001021
532 #define ELS_CMD_PRLO_ACC 0x14001002
533 #define ELS_CMD_PDISC 0x50
534 #define ELS_CMD_FDISC 0x51
535 #define ELS_CMD_ADISC 0x52
536 #define ELS_CMD_FARP 0x54
537 #define ELS_CMD_FARPR 0x55
538 #define ELS_CMD_RPS 0x56
539 #define ELS_CMD_RPL 0x57
540 #define ELS_CMD_FAN 0x60
541 #define ELS_CMD_RSCN 0x0461
542 #define ELS_CMD_SCR 0x62
543 #define ELS_CMD_RNID 0x78
544 #define ELS_CMD_LIRR 0x7A
545 #endif
546
547 /*
548 * LS_RJT Payload Definition
549 */
550
551 struct ls_rjt { /* Structure is in Big Endian format */
552 union {
553 uint32_t lsRjtError;
554 struct {
555 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
556
557 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
558 /* LS_RJT reason codes */
559 #define LSRJT_INVALID_CMD 0x01
560 #define LSRJT_LOGICAL_ERR 0x03
561 #define LSRJT_LOGICAL_BSY 0x05
562 #define LSRJT_PROTOCOL_ERR 0x07
563 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
564 #define LSRJT_CMD_UNSUPPORTED 0x0B
565 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
566
567 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
568 /* LS_RJT reason explanation */
569 #define LSEXP_NOTHING_MORE 0x00
570 #define LSEXP_SPARM_OPTIONS 0x01
571 #define LSEXP_SPARM_ICTL 0x03
572 #define LSEXP_SPARM_RCTL 0x05
573 #define LSEXP_SPARM_RCV_SIZE 0x07
574 #define LSEXP_SPARM_CONCUR_SEQ 0x09
575 #define LSEXP_SPARM_CREDIT 0x0B
576 #define LSEXP_INVALID_PNAME 0x0D
577 #define LSEXP_INVALID_NNAME 0x0E
578 #define LSEXP_INVALID_CSP 0x0F
579 #define LSEXP_INVALID_ASSOC_HDR 0x11
580 #define LSEXP_ASSOC_HDR_REQ 0x13
581 #define LSEXP_INVALID_O_SID 0x15
582 #define LSEXP_INVALID_OX_RX 0x17
583 #define LSEXP_CMD_IN_PROGRESS 0x19
584 #define LSEXP_PORT_LOGIN_REQ 0x1E
585 #define LSEXP_INVALID_NPORT_ID 0x1F
586 #define LSEXP_INVALID_SEQ_ID 0x21
587 #define LSEXP_INVALID_XCHG 0x23
588 #define LSEXP_INACTIVE_XCHG 0x25
589 #define LSEXP_RQ_REQUIRED 0x27
590 #define LSEXP_OUT_OF_RESOURCE 0x29
591 #define LSEXP_CANT_GIVE_DATA 0x2A
592 #define LSEXP_REQ_UNSUPPORTED 0x2C
593 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
594 } b;
595 } un;
596 };
597
598 /*
599 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
600 */
601
602 typedef struct _LOGO { /* Structure is in Big Endian format */
603 union {
604 uint32_t nPortId32; /* Access nPortId as a word */
605 struct {
606 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
607 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
608 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
609 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
610 } b;
611 } un;
612 struct lpfc_name portName; /* N_port name field */
613 } LOGO;
614
615 /*
616 * FCP Login (PRLI Request / ACC) Payload Definition
617 */
618
619 #define PRLX_PAGE_LEN 0x10
620 #define TPRLO_PAGE_LEN 0x14
621
622 typedef struct _PRLI { /* Structure is in Big Endian format */
623 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
624
625 #define PRLI_FCP_TYPE 0x08
626 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
627
628 #ifdef __BIG_ENDIAN_BITFIELD
629 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
630 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
631 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
632
633 /* ACC = imagePairEstablished */
634 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
635 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
636 #else /* __LITTLE_ENDIAN_BITFIELD */
637 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
638 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
639 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
640 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
641 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
642 /* ACC = imagePairEstablished */
643 #endif
644
645 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
646 #define PRLI_NO_RESOURCES 0x2
647 #define PRLI_INIT_INCOMPLETE 0x3
648 #define PRLI_NO_SUCH_PA 0x4
649 #define PRLI_PREDEF_CONFIG 0x5
650 #define PRLI_PARTIAL_SUCCESS 0x6
651 #define PRLI_INVALID_PAGE_CNT 0x7
652 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
653
654 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
655
656 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
657
658 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
659 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
660
661 #ifdef __BIG_ENDIAN_BITFIELD
662 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
663 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
664 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
665 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
666 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
667 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
668 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
669 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
670 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
671 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
672 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
673 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
674 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
675 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
676 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
677 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
678 #else /* __LITTLE_ENDIAN_BITFIELD */
679 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
680 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
681 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
682 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
683 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
684 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
685 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
686 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
687 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
688 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
689 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
690 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
691 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
692 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
693 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
694 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
695 #endif
696 } PRLI;
697
698 /*
699 * FCP Logout (PRLO Request / ACC) Payload Definition
700 */
701
702 typedef struct _PRLO { /* Structure is in Big Endian format */
703 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
704
705 #define PRLO_FCP_TYPE 0x08
706 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
707
708 #ifdef __BIG_ENDIAN_BITFIELD
709 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
710 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
711 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
712 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
713 #else /* __LITTLE_ENDIAN_BITFIELD */
714 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
715 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
716 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
717 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
718 #endif
719
720 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
721 #define PRLO_NO_SUCH_IMAGE 0x4
722 #define PRLO_INVALID_PAGE_CNT 0x7
723
724 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
725
726 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
727
728 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
729
730 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
731 } PRLO;
732
733 typedef struct _ADISC { /* Structure is in Big Endian format */
734 uint32_t hardAL_PA;
735 struct lpfc_name portName;
736 struct lpfc_name nodeName;
737 uint32_t DID;
738 } ADISC;
739
740 typedef struct _FARP { /* Structure is in Big Endian format */
741 uint32_t Mflags:8;
742 uint32_t Odid:24;
743 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
744 action */
745 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
746 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
747 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
748 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
749 supported */
750 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
751 supported */
752 uint32_t Rflags:8;
753 uint32_t Rdid:24;
754 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
755 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
756 struct lpfc_name OportName;
757 struct lpfc_name OnodeName;
758 struct lpfc_name RportName;
759 struct lpfc_name RnodeName;
760 uint8_t Oipaddr[16];
761 uint8_t Ripaddr[16];
762 } FARP;
763
764 typedef struct _FAN { /* Structure is in Big Endian format */
765 uint32_t Fdid;
766 struct lpfc_name FportName;
767 struct lpfc_name FnodeName;
768 } FAN;
769
770 typedef struct _SCR { /* Structure is in Big Endian format */
771 uint8_t resvd1;
772 uint8_t resvd2;
773 uint8_t resvd3;
774 uint8_t Function;
775 #define SCR_FUNC_FABRIC 0x01
776 #define SCR_FUNC_NPORT 0x02
777 #define SCR_FUNC_FULL 0x03
778 #define SCR_CLEAR 0xff
779 } SCR;
780
781 typedef struct _RNID_TOP_DISC {
782 struct lpfc_name portName;
783 uint8_t resvd[8];
784 uint32_t unitType;
785 #define RNID_HBA 0x7
786 #define RNID_HOST 0xa
787 #define RNID_DRIVER 0xd
788 uint32_t physPort;
789 uint32_t attachedNodes;
790 uint16_t ipVersion;
791 #define RNID_IPV4 0x1
792 #define RNID_IPV6 0x2
793 uint16_t UDPport;
794 uint8_t ipAddr[16];
795 uint16_t resvd1;
796 uint16_t flags;
797 #define RNID_TD_SUPPORT 0x1
798 #define RNID_LP_VALID 0x2
799 } RNID_TOP_DISC;
800
801 typedef struct _RNID { /* Structure is in Big Endian format */
802 uint8_t Format;
803 #define RNID_TOPOLOGY_DISC 0xdf
804 uint8_t CommonLen;
805 uint8_t resvd1;
806 uint8_t SpecificLen;
807 struct lpfc_name portName;
808 struct lpfc_name nodeName;
809 union {
810 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
811 } un;
812 } RNID;
813
814 typedef struct _RPS { /* Structure is in Big Endian format */
815 union {
816 uint32_t portNum;
817 struct lpfc_name portName;
818 } un;
819 } RPS;
820
821 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
822 uint16_t rsvd1;
823 uint16_t portStatus;
824 uint32_t linkFailureCnt;
825 uint32_t lossSyncCnt;
826 uint32_t lossSignalCnt;
827 uint32_t primSeqErrCnt;
828 uint32_t invalidXmitWord;
829 uint32_t crcCnt;
830 } RPS_RSP;
831
832 typedef struct _RPL { /* Structure is in Big Endian format */
833 uint32_t maxsize;
834 uint32_t index;
835 } RPL;
836
837 typedef struct _PORT_NUM_BLK {
838 uint32_t portNum;
839 uint32_t portID;
840 struct lpfc_name portName;
841 } PORT_NUM_BLK;
842
843 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
844 uint32_t listLen;
845 uint32_t index;
846 PORT_NUM_BLK port_num_blk;
847 } RPL_RSP;
848
849 /* This is used for RSCN command */
850 typedef struct _D_ID { /* Structure is in Big Endian format */
851 union {
852 uint32_t word;
853 struct {
854 #ifdef __BIG_ENDIAN_BITFIELD
855 uint8_t resv;
856 uint8_t domain;
857 uint8_t area;
858 uint8_t id;
859 #else /* __LITTLE_ENDIAN_BITFIELD */
860 uint8_t id;
861 uint8_t area;
862 uint8_t domain;
863 uint8_t resv;
864 #endif
865 } b;
866 } un;
867 } D_ID;
868
869 /*
870 * Structure to define all ELS Payload types
871 */
872
873 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
874 uint8_t elsCode; /* FC Word 0, bit 24:31 */
875 uint8_t elsByte1;
876 uint8_t elsByte2;
877 uint8_t elsByte3;
878 union {
879 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
880 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
881 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
882 PRLI prli; /* Payload for PRLI/ACC */
883 PRLO prlo; /* Payload for PRLO/ACC */
884 ADISC adisc; /* Payload for ADISC/ACC */
885 FARP farp; /* Payload for FARP/ACC */
886 FAN fan; /* Payload for FAN */
887 SCR scr; /* Payload for SCR/ACC */
888 RNID rnid; /* Payload for RNID */
889 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
890 } un;
891 } ELS_PKT;
892
893 /*
894 * FDMI
895 * HBA MAnagement Operations Command Codes
896 */
897 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
898 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
899 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
900 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
901 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
902 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
903 #define SLI_MGMT_RPRT 0x210 /* Register Port */
904 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
905 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
906 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
907
908 /*
909 * Management Service Subtypes
910 */
911 #define SLI_CT_FDMI_Subtypes 0x10
912
913 /*
914 * HBA Management Service Reject Code
915 */
916 #define REJECT_CODE 0x9 /* Unable to perform command request */
917
918 /*
919 * HBA Management Service Reject Reason Code
920 * Please refer to the Reason Codes above
921 */
922
923 /*
924 * HBA Attribute Types
925 */
926 #define NODE_NAME 0x1
927 #define MANUFACTURER 0x2
928 #define SERIAL_NUMBER 0x3
929 #define MODEL 0x4
930 #define MODEL_DESCRIPTION 0x5
931 #define HARDWARE_VERSION 0x6
932 #define DRIVER_VERSION 0x7
933 #define OPTION_ROM_VERSION 0x8
934 #define FIRMWARE_VERSION 0x9
935 #define OS_NAME_VERSION 0xa
936 #define MAX_CT_PAYLOAD_LEN 0xb
937
938 /*
939 * Port Attrubute Types
940 */
941 #define SUPPORTED_FC4_TYPES 0x1
942 #define SUPPORTED_SPEED 0x2
943 #define PORT_SPEED 0x3
944 #define MAX_FRAME_SIZE 0x4
945 #define OS_DEVICE_NAME 0x5
946 #define HOST_NAME 0x6
947
948 union AttributesDef {
949 /* Structure is in Big Endian format */
950 struct {
951 uint32_t AttrType:16;
952 uint32_t AttrLen:16;
953 } bits;
954 uint32_t word;
955 };
956
957
958 /*
959 * HBA Attribute Entry (8 - 260 bytes)
960 */
961 typedef struct {
962 union AttributesDef ad;
963 union {
964 uint32_t VendorSpecific;
965 uint8_t Manufacturer[64];
966 uint8_t SerialNumber[64];
967 uint8_t Model[256];
968 uint8_t ModelDescription[256];
969 uint8_t HardwareVersion[256];
970 uint8_t DriverVersion[256];
971 uint8_t OptionROMVersion[256];
972 uint8_t FirmwareVersion[256];
973 struct lpfc_name NodeName;
974 uint8_t SupportFC4Types[32];
975 uint32_t SupportSpeed;
976 uint32_t PortSpeed;
977 uint32_t MaxFrameSize;
978 uint8_t OsDeviceName[256];
979 uint8_t OsNameVersion[256];
980 uint32_t MaxCTPayloadLen;
981 uint8_t HostName[256];
982 } un;
983 } ATTRIBUTE_ENTRY;
984
985 /*
986 * HBA Attribute Block
987 */
988 typedef struct {
989 uint32_t EntryCnt; /* Number of HBA attribute entries */
990 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
991 } ATTRIBUTE_BLOCK;
992
993 /*
994 * Port Entry
995 */
996 typedef struct {
997 struct lpfc_name PortName;
998 } PORT_ENTRY;
999
1000 /*
1001 * HBA Identifier
1002 */
1003 typedef struct {
1004 struct lpfc_name PortName;
1005 } HBA_IDENTIFIER;
1006
1007 /*
1008 * Registered Port List Format
1009 */
1010 typedef struct {
1011 uint32_t EntryCnt;
1012 PORT_ENTRY pe; /* Variable-length array */
1013 } REG_PORT_LIST;
1014
1015 /*
1016 * Register HBA(RHBA)
1017 */
1018 typedef struct {
1019 HBA_IDENTIFIER hi;
1020 REG_PORT_LIST rpl; /* variable-length array */
1021 /* ATTRIBUTE_BLOCK ab; */
1022 } REG_HBA;
1023
1024 /*
1025 * Register HBA Attributes (RHAT)
1026 */
1027 typedef struct {
1028 struct lpfc_name HBA_PortName;
1029 ATTRIBUTE_BLOCK ab;
1030 } REG_HBA_ATTRIBUTE;
1031
1032 /*
1033 * Register Port Attributes (RPA)
1034 */
1035 typedef struct {
1036 struct lpfc_name PortName;
1037 ATTRIBUTE_BLOCK ab;
1038 } REG_PORT_ATTRIBUTE;
1039
1040 /*
1041 * Get Registered HBA List (GRHL) Accept Payload Format
1042 */
1043 typedef struct {
1044 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1045 struct lpfc_name HBA_PortName; /* Variable-length array */
1046 } GRHL_ACC_PAYLOAD;
1047
1048 /*
1049 * Get Registered Port List (GRPL) Accept Payload Format
1050 */
1051 typedef struct {
1052 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1053 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1054 } GRPL_ACC_PAYLOAD;
1055
1056 /*
1057 * Get Port Attributes (GPAT) Accept Payload Format
1058 */
1059
1060 typedef struct {
1061 ATTRIBUTE_BLOCK pab;
1062 } GPAT_ACC_PAYLOAD;
1063
1064
1065 /*
1066 * Begin HBA configuration parameters.
1067 * The PCI configuration register BAR assignments are:
1068 * BAR0, offset 0x10 - SLIM base memory address
1069 * BAR1, offset 0x14 - SLIM base memory high address
1070 * BAR2, offset 0x18 - REGISTER base memory address
1071 * BAR3, offset 0x1c - REGISTER base memory high address
1072 * BAR4, offset 0x20 - BIU I/O registers
1073 * BAR5, offset 0x24 - REGISTER base io high address
1074 */
1075
1076 /* Number of rings currently used and available. */
1077 #define MAX_CONFIGURED_RINGS 3
1078 #define MAX_RINGS 4
1079
1080 /* IOCB / Mailbox is owned by FireFly */
1081 #define OWN_CHIP 1
1082
1083 /* IOCB / Mailbox is owned by Host */
1084 #define OWN_HOST 0
1085
1086 /* Number of 4-byte words in an IOCB. */
1087 #define IOCB_WORD_SZ 8
1088
1089 /* defines for type field in fc header */
1090 #define FC_ELS_DATA 0x1
1091 #define FC_LLC_SNAP 0x5
1092 #define FC_FCP_DATA 0x8
1093 #define FC_COMMON_TRANSPORT_ULP 0x20
1094
1095 /* defines for rctl field in fc header */
1096 #define FC_DEV_DATA 0x0
1097 #define FC_UNSOL_CTL 0x2
1098 #define FC_SOL_CTL 0x3
1099 #define FC_UNSOL_DATA 0x4
1100 #define FC_FCP_CMND 0x6
1101 #define FC_ELS_REQ 0x22
1102 #define FC_ELS_RSP 0x23
1103
1104 /* network headers for Dfctl field */
1105 #define FC_NET_HDR 0x20
1106
1107 /* Start FireFly Register definitions */
1108 #define PCI_VENDOR_ID_EMULEX 0x10df
1109 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1110 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1111 #define PCI_DEVICE_ID_SAT_MID 0xf015
1112 #define PCI_DEVICE_ID_RFLY 0xf095
1113 #define PCI_DEVICE_ID_PFLY 0xf098
1114 #define PCI_DEVICE_ID_LP101 0xf0a1
1115 #define PCI_DEVICE_ID_TFLY 0xf0a5
1116 #define PCI_DEVICE_ID_BSMB 0xf0d1
1117 #define PCI_DEVICE_ID_BMID 0xf0d5
1118 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1119 #define PCI_DEVICE_ID_ZMID 0xf0e5
1120 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1121 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1122 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1123 #define PCI_DEVICE_ID_SAT 0xf100
1124 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1125 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1126 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1127 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1128 #define PCI_DEVICE_ID_CENTAUR 0xf900
1129 #define PCI_DEVICE_ID_PEGASUS 0xf980
1130 #define PCI_DEVICE_ID_THOR 0xfa00
1131 #define PCI_DEVICE_ID_VIPER 0xfb00
1132 #define PCI_DEVICE_ID_LP10000S 0xfc00
1133 #define PCI_DEVICE_ID_LP11000S 0xfc10
1134 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1135 #define PCI_DEVICE_ID_SAT_S 0xfc40
1136 #define PCI_DEVICE_ID_HELIOS 0xfd00
1137 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1138 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1139 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1140 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1141 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1142
1143 #define JEDEC_ID_ADDRESS 0x0080001c
1144 #define FIREFLY_JEDEC_ID 0x1ACC
1145 #define SUPERFLY_JEDEC_ID 0x0020
1146 #define DRAGONFLY_JEDEC_ID 0x0021
1147 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1148 #define CENTAUR_2G_JEDEC_ID 0x0026
1149 #define CENTAUR_1G_JEDEC_ID 0x0028
1150 #define PEGASUS_ORION_JEDEC_ID 0x0036
1151 #define PEGASUS_JEDEC_ID 0x0038
1152 #define THOR_JEDEC_ID 0x0012
1153 #define HELIOS_JEDEC_ID 0x0364
1154 #define ZEPHYR_JEDEC_ID 0x0577
1155 #define VIPER_JEDEC_ID 0x4838
1156 #define SATURN_JEDEC_ID 0x1004
1157
1158 #define JEDEC_ID_MASK 0x0FFFF000
1159 #define JEDEC_ID_SHIFT 12
1160 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1161
1162 typedef struct { /* FireFly BIU registers */
1163 uint32_t hostAtt; /* See definitions for Host Attention
1164 register */
1165 uint32_t chipAtt; /* See definitions for Chip Attention
1166 register */
1167 uint32_t hostStatus; /* See definitions for Host Status register */
1168 uint32_t hostControl; /* See definitions for Host Control register */
1169 uint32_t buiConfig; /* See definitions for BIU configuration
1170 register */
1171 } FF_REGS;
1172
1173 /* IO Register size in bytes */
1174 #define FF_REG_AREA_SIZE 256
1175
1176 /* Host Attention Register */
1177
1178 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1179
1180 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1181 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1182 #define HA_R0ATT 0x00000008 /* Bit 3 */
1183 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1184 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1185 #define HA_R1ATT 0x00000080 /* Bit 7 */
1186 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1187 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1188 #define HA_R2ATT 0x00000800 /* Bit 11 */
1189 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1190 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1191 #define HA_R3ATT 0x00008000 /* Bit 15 */
1192 #define HA_LATT 0x20000000 /* Bit 29 */
1193 #define HA_MBATT 0x40000000 /* Bit 30 */
1194 #define HA_ERATT 0x80000000 /* Bit 31 */
1195
1196 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1197 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1198 #define HA_RXATT 0x00000008 /* Bit 3 */
1199 #define HA_RXMASK 0x0000000f
1200
1201 /* Chip Attention Register */
1202
1203 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1204
1205 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1206 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1207 #define CA_R0ATT 0x00000008 /* Bit 3 */
1208 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1209 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1210 #define CA_R1ATT 0x00000080 /* Bit 7 */
1211 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1212 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1213 #define CA_R2ATT 0x00000800 /* Bit 11 */
1214 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1215 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1216 #define CA_R3ATT 0x00008000 /* Bit 15 */
1217 #define CA_MBATT 0x40000000 /* Bit 30 */
1218
1219 /* Host Status Register */
1220
1221 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1222
1223 #define HS_MBRDY 0x00400000 /* Bit 22 */
1224 #define HS_FFRDY 0x00800000 /* Bit 23 */
1225 #define HS_FFER8 0x01000000 /* Bit 24 */
1226 #define HS_FFER7 0x02000000 /* Bit 25 */
1227 #define HS_FFER6 0x04000000 /* Bit 26 */
1228 #define HS_FFER5 0x08000000 /* Bit 27 */
1229 #define HS_FFER4 0x10000000 /* Bit 28 */
1230 #define HS_FFER3 0x20000000 /* Bit 29 */
1231 #define HS_FFER2 0x40000000 /* Bit 30 */
1232 #define HS_FFER1 0x80000000 /* Bit 31 */
1233 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1234 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1235
1236 /* Host Control Register */
1237
1238 #define HC_REG_OFFSET 12 /* Word offset from register base address */
1239
1240 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1241 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1242 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1243 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1244 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1245 #define HC_INITHBI 0x02000000 /* Bit 25 */
1246 #define HC_INITMB 0x04000000 /* Bit 26 */
1247 #define HC_INITFF 0x08000000 /* Bit 27 */
1248 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1249 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1250
1251 /* Mailbox Commands */
1252 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1253 #define MBX_LOAD_SM 0x01
1254 #define MBX_READ_NV 0x02
1255 #define MBX_WRITE_NV 0x03
1256 #define MBX_RUN_BIU_DIAG 0x04
1257 #define MBX_INIT_LINK 0x05
1258 #define MBX_DOWN_LINK 0x06
1259 #define MBX_CONFIG_LINK 0x07
1260 #define MBX_CONFIG_RING 0x09
1261 #define MBX_RESET_RING 0x0A
1262 #define MBX_READ_CONFIG 0x0B
1263 #define MBX_READ_RCONFIG 0x0C
1264 #define MBX_READ_SPARM 0x0D
1265 #define MBX_READ_STATUS 0x0E
1266 #define MBX_READ_RPI 0x0F
1267 #define MBX_READ_XRI 0x10
1268 #define MBX_READ_REV 0x11
1269 #define MBX_READ_LNK_STAT 0x12
1270 #define MBX_REG_LOGIN 0x13
1271 #define MBX_UNREG_LOGIN 0x14
1272 #define MBX_READ_LA 0x15
1273 #define MBX_CLEAR_LA 0x16
1274 #define MBX_DUMP_MEMORY 0x17
1275 #define MBX_DUMP_CONTEXT 0x18
1276 #define MBX_RUN_DIAGS 0x19
1277 #define MBX_RESTART 0x1A
1278 #define MBX_UPDATE_CFG 0x1B
1279 #define MBX_DOWN_LOAD 0x1C
1280 #define MBX_DEL_LD_ENTRY 0x1D
1281 #define MBX_RUN_PROGRAM 0x1E
1282 #define MBX_SET_MASK 0x20
1283 #define MBX_SET_VARIABLE 0x21
1284 #define MBX_UNREG_D_ID 0x23
1285 #define MBX_KILL_BOARD 0x24
1286 #define MBX_CONFIG_FARP 0x25
1287 #define MBX_BEACON 0x2A
1288 #define MBX_HEARTBEAT 0x31
1289 #define MBX_WRITE_VPARMS 0x32
1290 #define MBX_ASYNCEVT_ENABLE 0x33
1291
1292 #define MBX_CONFIG_HBQ 0x7C
1293 #define MBX_LOAD_AREA 0x81
1294 #define MBX_RUN_BIU_DIAG64 0x84
1295 #define MBX_CONFIG_PORT 0x88
1296 #define MBX_READ_SPARM64 0x8D
1297 #define MBX_READ_RPI64 0x8F
1298 #define MBX_REG_LOGIN64 0x93
1299 #define MBX_READ_LA64 0x95
1300 #define MBX_REG_VPI 0x96
1301 #define MBX_UNREG_VPI 0x97
1302 #define MBX_REG_VNPID 0x96
1303 #define MBX_UNREG_VNPID 0x97
1304
1305 #define MBX_WRITE_WWN 0x98
1306 #define MBX_SET_DEBUG 0x99
1307 #define MBX_LOAD_EXP_ROM 0x9C
1308
1309 #define MBX_MAX_CMDS 0x9D
1310 #define MBX_SLI2_CMD_MASK 0x80
1311
1312 /* IOCB Commands */
1313
1314 #define CMD_RCV_SEQUENCE_CX 0x01
1315 #define CMD_XMIT_SEQUENCE_CR 0x02
1316 #define CMD_XMIT_SEQUENCE_CX 0x03
1317 #define CMD_XMIT_BCAST_CN 0x04
1318 #define CMD_XMIT_BCAST_CX 0x05
1319 #define CMD_QUE_RING_BUF_CN 0x06
1320 #define CMD_QUE_XRI_BUF_CX 0x07
1321 #define CMD_IOCB_CONTINUE_CN 0x08
1322 #define CMD_RET_XRI_BUF_CX 0x09
1323 #define CMD_ELS_REQUEST_CR 0x0A
1324 #define CMD_ELS_REQUEST_CX 0x0B
1325 #define CMD_RCV_ELS_REQ_CX 0x0D
1326 #define CMD_ABORT_XRI_CN 0x0E
1327 #define CMD_ABORT_XRI_CX 0x0F
1328 #define CMD_CLOSE_XRI_CN 0x10
1329 #define CMD_CLOSE_XRI_CX 0x11
1330 #define CMD_CREATE_XRI_CR 0x12
1331 #define CMD_CREATE_XRI_CX 0x13
1332 #define CMD_GET_RPI_CN 0x14
1333 #define CMD_XMIT_ELS_RSP_CX 0x15
1334 #define CMD_GET_RPI_CR 0x16
1335 #define CMD_XRI_ABORTED_CX 0x17
1336 #define CMD_FCP_IWRITE_CR 0x18
1337 #define CMD_FCP_IWRITE_CX 0x19
1338 #define CMD_FCP_IREAD_CR 0x1A
1339 #define CMD_FCP_IREAD_CX 0x1B
1340 #define CMD_FCP_ICMND_CR 0x1C
1341 #define CMD_FCP_ICMND_CX 0x1D
1342 #define CMD_FCP_TSEND_CX 0x1F
1343 #define CMD_FCP_TRECEIVE_CX 0x21
1344 #define CMD_FCP_TRSP_CX 0x23
1345 #define CMD_FCP_AUTO_TRSP_CX 0x29
1346
1347 #define CMD_ADAPTER_MSG 0x20
1348 #define CMD_ADAPTER_DUMP 0x22
1349
1350 /* SLI_2 IOCB Command Set */
1351
1352 #define CMD_ASYNC_STATUS 0x7C
1353 #define CMD_RCV_SEQUENCE64_CX 0x81
1354 #define CMD_XMIT_SEQUENCE64_CR 0x82
1355 #define CMD_XMIT_SEQUENCE64_CX 0x83
1356 #define CMD_XMIT_BCAST64_CN 0x84
1357 #define CMD_XMIT_BCAST64_CX 0x85
1358 #define CMD_QUE_RING_BUF64_CN 0x86
1359 #define CMD_QUE_XRI_BUF64_CX 0x87
1360 #define CMD_IOCB_CONTINUE64_CN 0x88
1361 #define CMD_RET_XRI_BUF64_CX 0x89
1362 #define CMD_ELS_REQUEST64_CR 0x8A
1363 #define CMD_ELS_REQUEST64_CX 0x8B
1364 #define CMD_ABORT_MXRI64_CN 0x8C
1365 #define CMD_RCV_ELS_REQ64_CX 0x8D
1366 #define CMD_XMIT_ELS_RSP64_CX 0x95
1367 #define CMD_FCP_IWRITE64_CR 0x98
1368 #define CMD_FCP_IWRITE64_CX 0x99
1369 #define CMD_FCP_IREAD64_CR 0x9A
1370 #define CMD_FCP_IREAD64_CX 0x9B
1371 #define CMD_FCP_ICMND64_CR 0x9C
1372 #define CMD_FCP_ICMND64_CX 0x9D
1373 #define CMD_FCP_TSEND64_CX 0x9F
1374 #define CMD_FCP_TRECEIVE64_CX 0xA1
1375 #define CMD_FCP_TRSP64_CX 0xA3
1376
1377 #define CMD_QUE_XRI64_CX 0xB3
1378 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1379 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1380 #define CMD_IOCB_RET_XRI64_CX 0xB9
1381 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1382
1383 #define CMD_GEN_REQUEST64_CR 0xC2
1384 #define CMD_GEN_REQUEST64_CX 0xC3
1385
1386 /* Unhandled SLI-3 Commands */
1387 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1388 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1389 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1390 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1391 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1392 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1393 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1394 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1395 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1396 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1397 #define CMD_IOCB_LOGENTRY_CN 0x94
1398 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1399
1400 #define CMD_MAX_IOCB_CMD 0xE6
1401 #define CMD_IOCB_MASK 0xff
1402
1403 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1404 iocb */
1405 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1406 /*
1407 * Define Status
1408 */
1409 #define MBX_SUCCESS 0
1410 #define MBXERR_NUM_RINGS 1
1411 #define MBXERR_NUM_IOCBS 2
1412 #define MBXERR_IOCBS_EXCEEDED 3
1413 #define MBXERR_BAD_RING_NUMBER 4
1414 #define MBXERR_MASK_ENTRIES_RANGE 5
1415 #define MBXERR_MASKS_EXCEEDED 6
1416 #define MBXERR_BAD_PROFILE 7
1417 #define MBXERR_BAD_DEF_CLASS 8
1418 #define MBXERR_BAD_MAX_RESPONDER 9
1419 #define MBXERR_BAD_MAX_ORIGINATOR 10
1420 #define MBXERR_RPI_REGISTERED 11
1421 #define MBXERR_RPI_FULL 12
1422 #define MBXERR_NO_RESOURCES 13
1423 #define MBXERR_BAD_RCV_LENGTH 14
1424 #define MBXERR_DMA_ERROR 15
1425 #define MBXERR_ERROR 16
1426 #define MBX_NOT_FINISHED 255
1427
1428 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1429 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1430
1431 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1432
1433 /*
1434 * Begin Structure Definitions for Mailbox Commands
1435 */
1436
1437 typedef struct {
1438 #ifdef __BIG_ENDIAN_BITFIELD
1439 uint8_t tval;
1440 uint8_t tmask;
1441 uint8_t rval;
1442 uint8_t rmask;
1443 #else /* __LITTLE_ENDIAN_BITFIELD */
1444 uint8_t rmask;
1445 uint8_t rval;
1446 uint8_t tmask;
1447 uint8_t tval;
1448 #endif
1449 } RR_REG;
1450
1451 struct ulp_bde {
1452 uint32_t bdeAddress;
1453 #ifdef __BIG_ENDIAN_BITFIELD
1454 uint32_t bdeReserved:4;
1455 uint32_t bdeAddrHigh:4;
1456 uint32_t bdeSize:24;
1457 #else /* __LITTLE_ENDIAN_BITFIELD */
1458 uint32_t bdeSize:24;
1459 uint32_t bdeAddrHigh:4;
1460 uint32_t bdeReserved:4;
1461 #endif
1462 };
1463
1464 struct ulp_bde64 { /* SLI-2 */
1465 union ULP_BDE_TUS {
1466 uint32_t w;
1467 struct {
1468 #ifdef __BIG_ENDIAN_BITFIELD
1469 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1470 VALUE !! */
1471 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1472 #else /* __LITTLE_ENDIAN_BITFIELD */
1473 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1474 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1475 VALUE !! */
1476 #endif
1477
1478 #define BUFF_USE_RSVD 0x01 /* bdeFlags */
1479 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1480 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1481 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1482 buffer */
1483 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1484 addr */
1485 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1486 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1487 #define BUFF_TYPE_INVALID 0x80 /* "" "" */
1488 } f;
1489 } tus;
1490 uint32_t addrLow;
1491 uint32_t addrHigh;
1492 };
1493 #define BDE64_SIZE_WORD 0
1494 #define BPL64_SIZE_WORD 0x40
1495
1496 typedef struct ULP_BDL { /* SLI-2 */
1497 #ifdef __BIG_ENDIAN_BITFIELD
1498 uint32_t bdeFlags:8; /* BDL Flags */
1499 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1500 #else /* __LITTLE_ENDIAN_BITFIELD */
1501 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1502 uint32_t bdeFlags:8; /* BDL Flags */
1503 #endif
1504
1505 uint32_t addrLow; /* Address 0:31 */
1506 uint32_t addrHigh; /* Address 32:63 */
1507 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1508 } ULP_BDL;
1509
1510 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1511
1512 typedef struct {
1513 #ifdef __BIG_ENDIAN_BITFIELD
1514 uint32_t rsvd2:25;
1515 uint32_t acknowledgment:1;
1516 uint32_t version:1;
1517 uint32_t erase_or_prog:1;
1518 uint32_t update_flash:1;
1519 uint32_t update_ram:1;
1520 uint32_t method:1;
1521 uint32_t load_cmplt:1;
1522 #else /* __LITTLE_ENDIAN_BITFIELD */
1523 uint32_t load_cmplt:1;
1524 uint32_t method:1;
1525 uint32_t update_ram:1;
1526 uint32_t update_flash:1;
1527 uint32_t erase_or_prog:1;
1528 uint32_t version:1;
1529 uint32_t acknowledgment:1;
1530 uint32_t rsvd2:25;
1531 #endif
1532
1533 uint32_t dl_to_adr_low;
1534 uint32_t dl_to_adr_high;
1535 uint32_t dl_len;
1536 union {
1537 uint32_t dl_from_mbx_offset;
1538 struct ulp_bde dl_from_bde;
1539 struct ulp_bde64 dl_from_bde64;
1540 } un;
1541
1542 } LOAD_SM_VAR;
1543
1544 /* Structure for MB Command READ_NVPARM (02) */
1545
1546 typedef struct {
1547 uint32_t rsvd1[3]; /* Read as all one's */
1548 uint32_t rsvd2; /* Read as all zero's */
1549 uint32_t portname[2]; /* N_PORT name */
1550 uint32_t nodename[2]; /* NODE name */
1551
1552 #ifdef __BIG_ENDIAN_BITFIELD
1553 uint32_t pref_DID:24;
1554 uint32_t hardAL_PA:8;
1555 #else /* __LITTLE_ENDIAN_BITFIELD */
1556 uint32_t hardAL_PA:8;
1557 uint32_t pref_DID:24;
1558 #endif
1559
1560 uint32_t rsvd3[21]; /* Read as all one's */
1561 } READ_NV_VAR;
1562
1563 /* Structure for MB Command WRITE_NVPARMS (03) */
1564
1565 typedef struct {
1566 uint32_t rsvd1[3]; /* Must be all one's */
1567 uint32_t rsvd2; /* Must be all zero's */
1568 uint32_t portname[2]; /* N_PORT name */
1569 uint32_t nodename[2]; /* NODE name */
1570
1571 #ifdef __BIG_ENDIAN_BITFIELD
1572 uint32_t pref_DID:24;
1573 uint32_t hardAL_PA:8;
1574 #else /* __LITTLE_ENDIAN_BITFIELD */
1575 uint32_t hardAL_PA:8;
1576 uint32_t pref_DID:24;
1577 #endif
1578
1579 uint32_t rsvd3[21]; /* Must be all one's */
1580 } WRITE_NV_VAR;
1581
1582 /* Structure for MB Command RUN_BIU_DIAG (04) */
1583 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1584
1585 typedef struct {
1586 uint32_t rsvd1;
1587 union {
1588 struct {
1589 struct ulp_bde xmit_bde;
1590 struct ulp_bde rcv_bde;
1591 } s1;
1592 struct {
1593 struct ulp_bde64 xmit_bde64;
1594 struct ulp_bde64 rcv_bde64;
1595 } s2;
1596 } un;
1597 } BIU_DIAG_VAR;
1598
1599 /* Structure for MB Command INIT_LINK (05) */
1600
1601 typedef struct {
1602 #ifdef __BIG_ENDIAN_BITFIELD
1603 uint32_t rsvd1:24;
1604 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1605 #else /* __LITTLE_ENDIAN_BITFIELD */
1606 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1607 uint32_t rsvd1:24;
1608 #endif
1609
1610 #ifdef __BIG_ENDIAN_BITFIELD
1611 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1612 uint8_t rsvd2;
1613 uint16_t link_flags;
1614 #else /* __LITTLE_ENDIAN_BITFIELD */
1615 uint16_t link_flags;
1616 uint8_t rsvd2;
1617 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1618 #endif
1619
1620 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1621 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1622 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1623 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1624 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1625 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1626 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1627
1628 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1629 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1630 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1631
1632 uint32_t link_speed;
1633 #define LINK_SPEED_AUTO 0 /* Auto selection */
1634 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1635 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1636 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1637 #define LINK_SPEED_8G 8 /* 8 Gigabaud */
1638 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1639
1640 } INIT_LINK_VAR;
1641
1642 /* Structure for MB Command DOWN_LINK (06) */
1643
1644 typedef struct {
1645 uint32_t rsvd1;
1646 } DOWN_LINK_VAR;
1647
1648 /* Structure for MB Command CONFIG_LINK (07) */
1649
1650 typedef struct {
1651 #ifdef __BIG_ENDIAN_BITFIELD
1652 uint32_t cr:1;
1653 uint32_t ci:1;
1654 uint32_t cr_delay:6;
1655 uint32_t cr_count:8;
1656 uint32_t rsvd1:8;
1657 uint32_t MaxBBC:8;
1658 #else /* __LITTLE_ENDIAN_BITFIELD */
1659 uint32_t MaxBBC:8;
1660 uint32_t rsvd1:8;
1661 uint32_t cr_count:8;
1662 uint32_t cr_delay:6;
1663 uint32_t ci:1;
1664 uint32_t cr:1;
1665 #endif
1666
1667 uint32_t myId;
1668 uint32_t rsvd2;
1669 uint32_t edtov;
1670 uint32_t arbtov;
1671 uint32_t ratov;
1672 uint32_t rttov;
1673 uint32_t altov;
1674 uint32_t crtov;
1675 uint32_t citov;
1676 #ifdef __BIG_ENDIAN_BITFIELD
1677 uint32_t rrq_enable:1;
1678 uint32_t rrq_immed:1;
1679 uint32_t rsvd4:29;
1680 uint32_t ack0_enable:1;
1681 #else /* __LITTLE_ENDIAN_BITFIELD */
1682 uint32_t ack0_enable:1;
1683 uint32_t rsvd4:29;
1684 uint32_t rrq_immed:1;
1685 uint32_t rrq_enable:1;
1686 #endif
1687 } CONFIG_LINK;
1688
1689 /* Structure for MB Command PART_SLIM (08)
1690 * will be removed since SLI1 is no longer supported!
1691 */
1692 typedef struct {
1693 #ifdef __BIG_ENDIAN_BITFIELD
1694 uint16_t offCiocb;
1695 uint16_t numCiocb;
1696 uint16_t offRiocb;
1697 uint16_t numRiocb;
1698 #else /* __LITTLE_ENDIAN_BITFIELD */
1699 uint16_t numCiocb;
1700 uint16_t offCiocb;
1701 uint16_t numRiocb;
1702 uint16_t offRiocb;
1703 #endif
1704 } RING_DEF;
1705
1706 typedef struct {
1707 #ifdef __BIG_ENDIAN_BITFIELD
1708 uint32_t unused1:24;
1709 uint32_t numRing:8;
1710 #else /* __LITTLE_ENDIAN_BITFIELD */
1711 uint32_t numRing:8;
1712 uint32_t unused1:24;
1713 #endif
1714
1715 RING_DEF ringdef[4];
1716 uint32_t hbainit;
1717 } PART_SLIM_VAR;
1718
1719 /* Structure for MB Command CONFIG_RING (09) */
1720
1721 typedef struct {
1722 #ifdef __BIG_ENDIAN_BITFIELD
1723 uint32_t unused2:6;
1724 uint32_t recvSeq:1;
1725 uint32_t recvNotify:1;
1726 uint32_t numMask:8;
1727 uint32_t profile:8;
1728 uint32_t unused1:4;
1729 uint32_t ring:4;
1730 #else /* __LITTLE_ENDIAN_BITFIELD */
1731 uint32_t ring:4;
1732 uint32_t unused1:4;
1733 uint32_t profile:8;
1734 uint32_t numMask:8;
1735 uint32_t recvNotify:1;
1736 uint32_t recvSeq:1;
1737 uint32_t unused2:6;
1738 #endif
1739
1740 #ifdef __BIG_ENDIAN_BITFIELD
1741 uint16_t maxRespXchg;
1742 uint16_t maxOrigXchg;
1743 #else /* __LITTLE_ENDIAN_BITFIELD */
1744 uint16_t maxOrigXchg;
1745 uint16_t maxRespXchg;
1746 #endif
1747
1748 RR_REG rrRegs[6];
1749 } CONFIG_RING_VAR;
1750
1751 /* Structure for MB Command RESET_RING (10) */
1752
1753 typedef struct {
1754 uint32_t ring_no;
1755 } RESET_RING_VAR;
1756
1757 /* Structure for MB Command READ_CONFIG (11) */
1758
1759 typedef struct {
1760 #ifdef __BIG_ENDIAN_BITFIELD
1761 uint32_t cr:1;
1762 uint32_t ci:1;
1763 uint32_t cr_delay:6;
1764 uint32_t cr_count:8;
1765 uint32_t InitBBC:8;
1766 uint32_t MaxBBC:8;
1767 #else /* __LITTLE_ENDIAN_BITFIELD */
1768 uint32_t MaxBBC:8;
1769 uint32_t InitBBC:8;
1770 uint32_t cr_count:8;
1771 uint32_t cr_delay:6;
1772 uint32_t ci:1;
1773 uint32_t cr:1;
1774 #endif
1775
1776 #ifdef __BIG_ENDIAN_BITFIELD
1777 uint32_t topology:8;
1778 uint32_t myDid:24;
1779 #else /* __LITTLE_ENDIAN_BITFIELD */
1780 uint32_t myDid:24;
1781 uint32_t topology:8;
1782 #endif
1783
1784 /* Defines for topology (defined previously) */
1785 #ifdef __BIG_ENDIAN_BITFIELD
1786 uint32_t AR:1;
1787 uint32_t IR:1;
1788 uint32_t rsvd1:29;
1789 uint32_t ack0:1;
1790 #else /* __LITTLE_ENDIAN_BITFIELD */
1791 uint32_t ack0:1;
1792 uint32_t rsvd1:29;
1793 uint32_t IR:1;
1794 uint32_t AR:1;
1795 #endif
1796
1797 uint32_t edtov;
1798 uint32_t arbtov;
1799 uint32_t ratov;
1800 uint32_t rttov;
1801 uint32_t altov;
1802 uint32_t lmt;
1803 #define LMT_RESERVED 0x000 /* Not used */
1804 #define LMT_1Gb 0x004
1805 #define LMT_2Gb 0x008
1806 #define LMT_4Gb 0x040
1807 #define LMT_8Gb 0x080
1808 #define LMT_10Gb 0x100
1809 uint32_t rsvd2;
1810 uint32_t rsvd3;
1811 uint32_t max_xri;
1812 uint32_t max_iocb;
1813 uint32_t max_rpi;
1814 uint32_t avail_xri;
1815 uint32_t avail_iocb;
1816 uint32_t avail_rpi;
1817 uint32_t max_vpi;
1818 uint32_t rsvd4;
1819 uint32_t rsvd5;
1820 uint32_t avail_vpi;
1821 } READ_CONFIG_VAR;
1822
1823 /* Structure for MB Command READ_RCONFIG (12) */
1824
1825 typedef struct {
1826 #ifdef __BIG_ENDIAN_BITFIELD
1827 uint32_t rsvd2:7;
1828 uint32_t recvNotify:1;
1829 uint32_t numMask:8;
1830 uint32_t profile:8;
1831 uint32_t rsvd1:4;
1832 uint32_t ring:4;
1833 #else /* __LITTLE_ENDIAN_BITFIELD */
1834 uint32_t ring:4;
1835 uint32_t rsvd1:4;
1836 uint32_t profile:8;
1837 uint32_t numMask:8;
1838 uint32_t recvNotify:1;
1839 uint32_t rsvd2:7;
1840 #endif
1841
1842 #ifdef __BIG_ENDIAN_BITFIELD
1843 uint16_t maxResp;
1844 uint16_t maxOrig;
1845 #else /* __LITTLE_ENDIAN_BITFIELD */
1846 uint16_t maxOrig;
1847 uint16_t maxResp;
1848 #endif
1849
1850 RR_REG rrRegs[6];
1851
1852 #ifdef __BIG_ENDIAN_BITFIELD
1853 uint16_t cmdRingOffset;
1854 uint16_t cmdEntryCnt;
1855 uint16_t rspRingOffset;
1856 uint16_t rspEntryCnt;
1857 uint16_t nextCmdOffset;
1858 uint16_t rsvd3;
1859 uint16_t nextRspOffset;
1860 uint16_t rsvd4;
1861 #else /* __LITTLE_ENDIAN_BITFIELD */
1862 uint16_t cmdEntryCnt;
1863 uint16_t cmdRingOffset;
1864 uint16_t rspEntryCnt;
1865 uint16_t rspRingOffset;
1866 uint16_t rsvd3;
1867 uint16_t nextCmdOffset;
1868 uint16_t rsvd4;
1869 uint16_t nextRspOffset;
1870 #endif
1871 } READ_RCONF_VAR;
1872
1873 /* Structure for MB Command READ_SPARM (13) */
1874 /* Structure for MB Command READ_SPARM64 (0x8D) */
1875
1876 typedef struct {
1877 uint32_t rsvd1;
1878 uint32_t rsvd2;
1879 union {
1880 struct ulp_bde sp; /* This BDE points to struct serv_parm
1881 structure */
1882 struct ulp_bde64 sp64;
1883 } un;
1884 #ifdef __BIG_ENDIAN_BITFIELD
1885 uint16_t rsvd3;
1886 uint16_t vpi;
1887 #else /* __LITTLE_ENDIAN_BITFIELD */
1888 uint16_t vpi;
1889 uint16_t rsvd3;
1890 #endif
1891 } READ_SPARM_VAR;
1892
1893 /* Structure for MB Command READ_STATUS (14) */
1894
1895 typedef struct {
1896 #ifdef __BIG_ENDIAN_BITFIELD
1897 uint32_t rsvd1:31;
1898 uint32_t clrCounters:1;
1899 uint16_t activeXriCnt;
1900 uint16_t activeRpiCnt;
1901 #else /* __LITTLE_ENDIAN_BITFIELD */
1902 uint32_t clrCounters:1;
1903 uint32_t rsvd1:31;
1904 uint16_t activeRpiCnt;
1905 uint16_t activeXriCnt;
1906 #endif
1907
1908 uint32_t xmitByteCnt;
1909 uint32_t rcvByteCnt;
1910 uint32_t xmitFrameCnt;
1911 uint32_t rcvFrameCnt;
1912 uint32_t xmitSeqCnt;
1913 uint32_t rcvSeqCnt;
1914 uint32_t totalOrigExchanges;
1915 uint32_t totalRespExchanges;
1916 uint32_t rcvPbsyCnt;
1917 uint32_t rcvFbsyCnt;
1918 } READ_STATUS_VAR;
1919
1920 /* Structure for MB Command READ_RPI (15) */
1921 /* Structure for MB Command READ_RPI64 (0x8F) */
1922
1923 typedef struct {
1924 #ifdef __BIG_ENDIAN_BITFIELD
1925 uint16_t nextRpi;
1926 uint16_t reqRpi;
1927 uint32_t rsvd2:8;
1928 uint32_t DID:24;
1929 #else /* __LITTLE_ENDIAN_BITFIELD */
1930 uint16_t reqRpi;
1931 uint16_t nextRpi;
1932 uint32_t DID:24;
1933 uint32_t rsvd2:8;
1934 #endif
1935
1936 union {
1937 struct ulp_bde sp;
1938 struct ulp_bde64 sp64;
1939 } un;
1940
1941 } READ_RPI_VAR;
1942
1943 /* Structure for MB Command READ_XRI (16) */
1944
1945 typedef struct {
1946 #ifdef __BIG_ENDIAN_BITFIELD
1947 uint16_t nextXri;
1948 uint16_t reqXri;
1949 uint16_t rsvd1;
1950 uint16_t rpi;
1951 uint32_t rsvd2:8;
1952 uint32_t DID:24;
1953 uint32_t rsvd3:8;
1954 uint32_t SID:24;
1955 uint32_t rsvd4;
1956 uint8_t seqId;
1957 uint8_t rsvd5;
1958 uint16_t seqCount;
1959 uint16_t oxId;
1960 uint16_t rxId;
1961 uint32_t rsvd6:30;
1962 uint32_t si:1;
1963 uint32_t exchOrig:1;
1964 #else /* __LITTLE_ENDIAN_BITFIELD */
1965 uint16_t reqXri;
1966 uint16_t nextXri;
1967 uint16_t rpi;
1968 uint16_t rsvd1;
1969 uint32_t DID:24;
1970 uint32_t rsvd2:8;
1971 uint32_t SID:24;
1972 uint32_t rsvd3:8;
1973 uint32_t rsvd4;
1974 uint16_t seqCount;
1975 uint8_t rsvd5;
1976 uint8_t seqId;
1977 uint16_t rxId;
1978 uint16_t oxId;
1979 uint32_t exchOrig:1;
1980 uint32_t si:1;
1981 uint32_t rsvd6:30;
1982 #endif
1983 } READ_XRI_VAR;
1984
1985 /* Structure for MB Command READ_REV (17) */
1986
1987 typedef struct {
1988 #ifdef __BIG_ENDIAN_BITFIELD
1989 uint32_t cv:1;
1990 uint32_t rr:1;
1991 uint32_t rsvd2:2;
1992 uint32_t v3req:1;
1993 uint32_t v3rsp:1;
1994 uint32_t rsvd1:25;
1995 uint32_t rv:1;
1996 #else /* __LITTLE_ENDIAN_BITFIELD */
1997 uint32_t rv:1;
1998 uint32_t rsvd1:25;
1999 uint32_t v3rsp:1;
2000 uint32_t v3req:1;
2001 uint32_t rsvd2:2;
2002 uint32_t rr:1;
2003 uint32_t cv:1;
2004 #endif
2005
2006 uint32_t biuRev;
2007 uint32_t smRev;
2008 union {
2009 uint32_t smFwRev;
2010 struct {
2011 #ifdef __BIG_ENDIAN_BITFIELD
2012 uint8_t ProgType;
2013 uint8_t ProgId;
2014 uint16_t ProgVer:4;
2015 uint16_t ProgRev:4;
2016 uint16_t ProgFixLvl:2;
2017 uint16_t ProgDistType:2;
2018 uint16_t DistCnt:4;
2019 #else /* __LITTLE_ENDIAN_BITFIELD */
2020 uint16_t DistCnt:4;
2021 uint16_t ProgDistType:2;
2022 uint16_t ProgFixLvl:2;
2023 uint16_t ProgRev:4;
2024 uint16_t ProgVer:4;
2025 uint8_t ProgId;
2026 uint8_t ProgType;
2027 #endif
2028
2029 } b;
2030 } un;
2031 uint32_t endecRev;
2032 #ifdef __BIG_ENDIAN_BITFIELD
2033 uint8_t feaLevelHigh;
2034 uint8_t feaLevelLow;
2035 uint8_t fcphHigh;
2036 uint8_t fcphLow;
2037 #else /* __LITTLE_ENDIAN_BITFIELD */
2038 uint8_t fcphLow;
2039 uint8_t fcphHigh;
2040 uint8_t feaLevelLow;
2041 uint8_t feaLevelHigh;
2042 #endif
2043
2044 uint32_t postKernRev;
2045 uint32_t opFwRev;
2046 uint8_t opFwName[16];
2047 uint32_t sli1FwRev;
2048 uint8_t sli1FwName[16];
2049 uint32_t sli2FwRev;
2050 uint8_t sli2FwName[16];
2051 uint32_t sli3Feat;
2052 uint32_t RandomData[6];
2053 } READ_REV_VAR;
2054
2055 /* Structure for MB Command READ_LINK_STAT (18) */
2056
2057 typedef struct {
2058 uint32_t rsvd1;
2059 uint32_t linkFailureCnt;
2060 uint32_t lossSyncCnt;
2061
2062 uint32_t lossSignalCnt;
2063 uint32_t primSeqErrCnt;
2064 uint32_t invalidXmitWord;
2065 uint32_t crcCnt;
2066 uint32_t primSeqTimeout;
2067 uint32_t elasticOverrun;
2068 uint32_t arbTimeout;
2069 } READ_LNK_VAR;
2070
2071 /* Structure for MB Command REG_LOGIN (19) */
2072 /* Structure for MB Command REG_LOGIN64 (0x93) */
2073
2074 typedef struct {
2075 #ifdef __BIG_ENDIAN_BITFIELD
2076 uint16_t rsvd1;
2077 uint16_t rpi;
2078 uint32_t rsvd2:8;
2079 uint32_t did:24;
2080 #else /* __LITTLE_ENDIAN_BITFIELD */
2081 uint16_t rpi;
2082 uint16_t rsvd1;
2083 uint32_t did:24;
2084 uint32_t rsvd2:8;
2085 #endif
2086
2087 union {
2088 struct ulp_bde sp;
2089 struct ulp_bde64 sp64;
2090 } un;
2091
2092 #ifdef __BIG_ENDIAN_BITFIELD
2093 uint16_t rsvd6;
2094 uint16_t vpi;
2095 #else /* __LITTLE_ENDIAN_BITFIELD */
2096 uint16_t vpi;
2097 uint16_t rsvd6;
2098 #endif
2099
2100 } REG_LOGIN_VAR;
2101
2102 /* Word 30 contents for REG_LOGIN */
2103 typedef union {
2104 struct {
2105 #ifdef __BIG_ENDIAN_BITFIELD
2106 uint16_t rsvd1:12;
2107 uint16_t wd30_class:4;
2108 uint16_t xri;
2109 #else /* __LITTLE_ENDIAN_BITFIELD */
2110 uint16_t xri;
2111 uint16_t wd30_class:4;
2112 uint16_t rsvd1:12;
2113 #endif
2114 } f;
2115 uint32_t word;
2116 } REG_WD30;
2117
2118 /* Structure for MB Command UNREG_LOGIN (20) */
2119
2120 typedef struct {
2121 #ifdef __BIG_ENDIAN_BITFIELD
2122 uint16_t rsvd1;
2123 uint16_t rpi;
2124 uint32_t rsvd2;
2125 uint32_t rsvd3;
2126 uint32_t rsvd4;
2127 uint32_t rsvd5;
2128 uint16_t rsvd6;
2129 uint16_t vpi;
2130 #else /* __LITTLE_ENDIAN_BITFIELD */
2131 uint16_t rpi;
2132 uint16_t rsvd1;
2133 uint32_t rsvd2;
2134 uint32_t rsvd3;
2135 uint32_t rsvd4;
2136 uint32_t rsvd5;
2137 uint16_t vpi;
2138 uint16_t rsvd6;
2139 #endif
2140 } UNREG_LOGIN_VAR;
2141
2142 /* Structure for MB Command REG_VPI (0x96) */
2143 typedef struct {
2144 #ifdef __BIG_ENDIAN_BITFIELD
2145 uint32_t rsvd1;
2146 uint32_t rsvd2:8;
2147 uint32_t sid:24;
2148 uint32_t rsvd3;
2149 uint32_t rsvd4;
2150 uint32_t rsvd5;
2151 uint16_t rsvd6;
2152 uint16_t vpi;
2153 #else /* __LITTLE_ENDIAN */
2154 uint32_t rsvd1;
2155 uint32_t sid:24;
2156 uint32_t rsvd2:8;
2157 uint32_t rsvd3;
2158 uint32_t rsvd4;
2159 uint32_t rsvd5;
2160 uint16_t vpi;
2161 uint16_t rsvd6;
2162 #endif
2163 } REG_VPI_VAR;
2164
2165 /* Structure for MB Command UNREG_VPI (0x97) */
2166 typedef struct {
2167 uint32_t rsvd1;
2168 uint32_t rsvd2;
2169 uint32_t rsvd3;
2170 uint32_t rsvd4;
2171 uint32_t rsvd5;
2172 #ifdef __BIG_ENDIAN_BITFIELD
2173 uint16_t rsvd6;
2174 uint16_t vpi;
2175 #else /* __LITTLE_ENDIAN */
2176 uint16_t vpi;
2177 uint16_t rsvd6;
2178 #endif
2179 } UNREG_VPI_VAR;
2180
2181 /* Structure for MB Command UNREG_D_ID (0x23) */
2182
2183 typedef struct {
2184 uint32_t did;
2185 uint32_t rsvd2;
2186 uint32_t rsvd3;
2187 uint32_t rsvd4;
2188 uint32_t rsvd5;
2189 #ifdef __BIG_ENDIAN_BITFIELD
2190 uint16_t rsvd6;
2191 uint16_t vpi;
2192 #else
2193 uint16_t vpi;
2194 uint16_t rsvd6;
2195 #endif
2196 } UNREG_D_ID_VAR;
2197
2198 /* Structure for MB Command READ_LA (21) */
2199 /* Structure for MB Command READ_LA64 (0x95) */
2200
2201 typedef struct {
2202 uint32_t eventTag; /* Event tag */
2203 #ifdef __BIG_ENDIAN_BITFIELD
2204 uint32_t rsvd1:22;
2205 uint32_t pb:1;
2206 uint32_t il:1;
2207 uint32_t attType:8;
2208 #else /* __LITTLE_ENDIAN_BITFIELD */
2209 uint32_t attType:8;
2210 uint32_t il:1;
2211 uint32_t pb:1;
2212 uint32_t rsvd1:22;
2213 #endif
2214
2215 #define AT_RESERVED 0x00 /* Reserved - attType */
2216 #define AT_LINK_UP 0x01 /* Link is up */
2217 #define AT_LINK_DOWN 0x02 /* Link is down */
2218
2219 #ifdef __BIG_ENDIAN_BITFIELD
2220 uint8_t granted_AL_PA;
2221 uint8_t lipAlPs;
2222 uint8_t lipType;
2223 uint8_t topology;
2224 #else /* __LITTLE_ENDIAN_BITFIELD */
2225 uint8_t topology;
2226 uint8_t lipType;
2227 uint8_t lipAlPs;
2228 uint8_t granted_AL_PA;
2229 #endif
2230
2231 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2232 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2233
2234 union {
2235 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2236 to */
2237 /* store the LILP AL_PA position map into */
2238 struct ulp_bde64 lilpBde64;
2239 } un;
2240
2241 #ifdef __BIG_ENDIAN_BITFIELD
2242 uint32_t Dlu:1;
2243 uint32_t Dtf:1;
2244 uint32_t Drsvd2:14;
2245 uint32_t DlnkSpeed:8;
2246 uint32_t DnlPort:4;
2247 uint32_t Dtx:2;
2248 uint32_t Drx:2;
2249 #else /* __LITTLE_ENDIAN_BITFIELD */
2250 uint32_t Drx:2;
2251 uint32_t Dtx:2;
2252 uint32_t DnlPort:4;
2253 uint32_t DlnkSpeed:8;
2254 uint32_t Drsvd2:14;
2255 uint32_t Dtf:1;
2256 uint32_t Dlu:1;
2257 #endif
2258
2259 #ifdef __BIG_ENDIAN_BITFIELD
2260 uint32_t Ulu:1;
2261 uint32_t Utf:1;
2262 uint32_t Ursvd2:14;
2263 uint32_t UlnkSpeed:8;
2264 uint32_t UnlPort:4;
2265 uint32_t Utx:2;
2266 uint32_t Urx:2;
2267 #else /* __LITTLE_ENDIAN_BITFIELD */
2268 uint32_t Urx:2;
2269 uint32_t Utx:2;
2270 uint32_t UnlPort:4;
2271 uint32_t UlnkSpeed:8;
2272 uint32_t Ursvd2:14;
2273 uint32_t Utf:1;
2274 uint32_t Ulu:1;
2275 #endif
2276
2277 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2278 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2279 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2280 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2281 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2282 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2283
2284 } READ_LA_VAR;
2285
2286 /* Structure for MB Command CLEAR_LA (22) */
2287
2288 typedef struct {
2289 uint32_t eventTag; /* Event tag */
2290 uint32_t rsvd1;
2291 } CLEAR_LA_VAR;
2292
2293 /* Structure for MB Command DUMP */
2294
2295 typedef struct {
2296 #ifdef __BIG_ENDIAN_BITFIELD
2297 uint32_t rsvd:25;
2298 uint32_t ra:1;
2299 uint32_t co:1;
2300 uint32_t cv:1;
2301 uint32_t type:4;
2302 uint32_t entry_index:16;
2303 uint32_t region_id:16;
2304 #else /* __LITTLE_ENDIAN_BITFIELD */
2305 uint32_t type:4;
2306 uint32_t cv:1;
2307 uint32_t co:1;
2308 uint32_t ra:1;
2309 uint32_t rsvd:25;
2310 uint32_t region_id:16;
2311 uint32_t entry_index:16;
2312 #endif
2313
2314 uint32_t rsvd1;
2315 uint32_t word_cnt;
2316 uint32_t resp_offset;
2317 } DUMP_VAR;
2318
2319 #define DMP_MEM_REG 0x1
2320 #define DMP_NV_PARAMS 0x2
2321
2322 #define DMP_REGION_VPD 0xe
2323 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2324 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2325 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2326
2327 struct hbq_mask {
2328 #ifdef __BIG_ENDIAN_BITFIELD
2329 uint8_t tmatch;
2330 uint8_t tmask;
2331 uint8_t rctlmatch;
2332 uint8_t rctlmask;
2333 #else /* __LITTLE_ENDIAN */
2334 uint8_t rctlmask;
2335 uint8_t rctlmatch;
2336 uint8_t tmask;
2337 uint8_t tmatch;
2338 #endif
2339 };
2340
2341
2342 /* Structure for MB Command CONFIG_HBQ (7c) */
2343
2344 struct config_hbq_var {
2345 #ifdef __BIG_ENDIAN_BITFIELD
2346 uint32_t rsvd1 :7;
2347 uint32_t recvNotify :1; /* Receive Notification */
2348 uint32_t numMask :8; /* # Mask Entries */
2349 uint32_t profile :8; /* Selection Profile */
2350 uint32_t rsvd2 :8;
2351 #else /* __LITTLE_ENDIAN */
2352 uint32_t rsvd2 :8;
2353 uint32_t profile :8; /* Selection Profile */
2354 uint32_t numMask :8; /* # Mask Entries */
2355 uint32_t recvNotify :1; /* Receive Notification */
2356 uint32_t rsvd1 :7;
2357 #endif
2358
2359 #ifdef __BIG_ENDIAN_BITFIELD
2360 uint32_t hbqId :16;
2361 uint32_t rsvd3 :12;
2362 uint32_t ringMask :4;
2363 #else /* __LITTLE_ENDIAN */
2364 uint32_t ringMask :4;
2365 uint32_t rsvd3 :12;
2366 uint32_t hbqId :16;
2367 #endif
2368
2369 #ifdef __BIG_ENDIAN_BITFIELD
2370 uint32_t entry_count :16;
2371 uint32_t rsvd4 :8;
2372 uint32_t headerLen :8;
2373 #else /* __LITTLE_ENDIAN */
2374 uint32_t headerLen :8;
2375 uint32_t rsvd4 :8;
2376 uint32_t entry_count :16;
2377 #endif
2378
2379 uint32_t hbqaddrLow;
2380 uint32_t hbqaddrHigh;
2381
2382 #ifdef __BIG_ENDIAN_BITFIELD
2383 uint32_t rsvd5 :31;
2384 uint32_t logEntry :1;
2385 #else /* __LITTLE_ENDIAN */
2386 uint32_t logEntry :1;
2387 uint32_t rsvd5 :31;
2388 #endif
2389
2390 uint32_t rsvd6; /* w7 */
2391 uint32_t rsvd7; /* w8 */
2392 uint32_t rsvd8; /* w9 */
2393
2394 struct hbq_mask hbqMasks[6];
2395
2396
2397 union {
2398 uint32_t allprofiles[12];
2399
2400 struct {
2401 #ifdef __BIG_ENDIAN_BITFIELD
2402 uint32_t seqlenoff :16;
2403 uint32_t maxlen :16;
2404 #else /* __LITTLE_ENDIAN */
2405 uint32_t maxlen :16;
2406 uint32_t seqlenoff :16;
2407 #endif
2408 #ifdef __BIG_ENDIAN_BITFIELD
2409 uint32_t rsvd1 :28;
2410 uint32_t seqlenbcnt :4;
2411 #else /* __LITTLE_ENDIAN */
2412 uint32_t seqlenbcnt :4;
2413 uint32_t rsvd1 :28;
2414 #endif
2415 uint32_t rsvd[10];
2416 } profile2;
2417
2418 struct {
2419 #ifdef __BIG_ENDIAN_BITFIELD
2420 uint32_t seqlenoff :16;
2421 uint32_t maxlen :16;
2422 #else /* __LITTLE_ENDIAN */
2423 uint32_t maxlen :16;
2424 uint32_t seqlenoff :16;
2425 #endif
2426 #ifdef __BIG_ENDIAN_BITFIELD
2427 uint32_t cmdcodeoff :28;
2428 uint32_t rsvd1 :12;
2429 uint32_t seqlenbcnt :4;
2430 #else /* __LITTLE_ENDIAN */
2431 uint32_t seqlenbcnt :4;
2432 uint32_t rsvd1 :12;
2433 uint32_t cmdcodeoff :28;
2434 #endif
2435 uint32_t cmdmatch[8];
2436
2437 uint32_t rsvd[2];
2438 } profile3;
2439
2440 struct {
2441 #ifdef __BIG_ENDIAN_BITFIELD
2442 uint32_t seqlenoff :16;
2443 uint32_t maxlen :16;
2444 #else /* __LITTLE_ENDIAN */
2445 uint32_t maxlen :16;
2446 uint32_t seqlenoff :16;
2447 #endif
2448 #ifdef __BIG_ENDIAN_BITFIELD
2449 uint32_t cmdcodeoff :28;
2450 uint32_t rsvd1 :12;
2451 uint32_t seqlenbcnt :4;
2452 #else /* __LITTLE_ENDIAN */
2453 uint32_t seqlenbcnt :4;
2454 uint32_t rsvd1 :12;
2455 uint32_t cmdcodeoff :28;
2456 #endif
2457 uint32_t cmdmatch[8];
2458
2459 uint32_t rsvd[2];
2460 } profile5;
2461
2462 } profiles;
2463
2464 };
2465
2466
2467
2468 /* Structure for MB Command CONFIG_PORT (0x88) */
2469 typedef struct {
2470 #ifdef __BIG_ENDIAN_BITFIELD
2471 uint32_t cBE : 1;
2472 uint32_t cET : 1;
2473 uint32_t cHpcb : 1;
2474 uint32_t cMA : 1;
2475 uint32_t sli_mode : 4;
2476 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2477 * config block */
2478 #else /* __LITTLE_ENDIAN */
2479 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2480 * config block */
2481 uint32_t sli_mode : 4;
2482 uint32_t cMA : 1;
2483 uint32_t cHpcb : 1;
2484 uint32_t cET : 1;
2485 uint32_t cBE : 1;
2486 #endif
2487
2488 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2489 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2490 uint32_t hbainit[6];
2491
2492 #ifdef __BIG_ENDIAN_BITFIELD
2493 uint32_t rsvd : 24; /* Reserved */
2494 uint32_t cmv : 1; /* Configure Max VPIs */
2495 uint32_t ccrp : 1; /* Config Command Ring Polling */
2496 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2497 uint32_t chbs : 1; /* Cofigure Host Backing store */
2498 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2499 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2500 uint32_t cmx : 1; /* Configure Max XRIs */
2501 uint32_t cmr : 1; /* Configure Max RPIs */
2502 #else /* __LITTLE_ENDIAN */
2503 uint32_t cmr : 1; /* Configure Max RPIs */
2504 uint32_t cmx : 1; /* Configure Max XRIs */
2505 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2506 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2507 uint32_t chbs : 1; /* Cofigure Host Backing store */
2508 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2509 uint32_t ccrp : 1; /* Config Command Ring Polling */
2510 uint32_t cmv : 1; /* Configure Max VPIs */
2511 uint32_t rsvd : 24; /* Reserved */
2512 #endif
2513 #ifdef __BIG_ENDIAN_BITFIELD
2514 uint32_t rsvd2 : 24; /* Reserved */
2515 uint32_t gmv : 1; /* Grant Max VPIs */
2516 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2517 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2518 uint32_t ghbs : 1; /* Grant Host Backing Store */
2519 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2520 uint32_t gerbm : 1; /* Grant ERBM Request */
2521 uint32_t gmx : 1; /* Grant Max XRIs */
2522 uint32_t gmr : 1; /* Grant Max RPIs */
2523 #else /* __LITTLE_ENDIAN */
2524 uint32_t gmr : 1; /* Grant Max RPIs */
2525 uint32_t gmx : 1; /* Grant Max XRIs */
2526 uint32_t gerbm : 1; /* Grant ERBM Request */
2527 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2528 uint32_t ghbs : 1; /* Grant Host Backing Store */
2529 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2530 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2531 uint32_t gmv : 1; /* Grant Max VPIs */
2532 uint32_t rsvd2 : 24; /* Reserved */
2533 #endif
2534
2535 #ifdef __BIG_ENDIAN_BITFIELD
2536 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2537 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2538 #else /* __LITTLE_ENDIAN */
2539 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2540 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2541 #endif
2542
2543 #ifdef __BIG_ENDIAN_BITFIELD
2544 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2545 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2546 #else /* __LITTLE_ENDIAN */
2547 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2548 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2549 #endif
2550
2551 uint32_t rsvd4; /* Reserved */
2552
2553 #ifdef __BIG_ENDIAN_BITFIELD
2554 uint32_t rsvd5 : 16; /* Reserved */
2555 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2556 #else /* __LITTLE_ENDIAN */
2557 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2558 uint32_t rsvd5 : 16; /* Reserved */
2559 #endif
2560
2561 } CONFIG_PORT_VAR;
2562
2563 /* SLI-2 Port Control Block */
2564
2565 /* SLIM POINTER */
2566 #define SLIMOFF 0x30 /* WORD */
2567
2568 typedef struct _SLI2_RDSC {
2569 uint32_t cmdEntries;
2570 uint32_t cmdAddrLow;
2571 uint32_t cmdAddrHigh;
2572
2573 uint32_t rspEntries;
2574 uint32_t rspAddrLow;
2575 uint32_t rspAddrHigh;
2576 } SLI2_RDSC;
2577
2578 typedef struct _PCB {
2579 #ifdef __BIG_ENDIAN_BITFIELD
2580 uint32_t type:8;
2581 #define TYPE_NATIVE_SLI2 0x01;
2582 uint32_t feature:8;
2583 #define FEATURE_INITIAL_SLI2 0x01;
2584 uint32_t rsvd:12;
2585 uint32_t maxRing:4;
2586 #else /* __LITTLE_ENDIAN_BITFIELD */
2587 uint32_t maxRing:4;
2588 uint32_t rsvd:12;
2589 uint32_t feature:8;
2590 #define FEATURE_INITIAL_SLI2 0x01;
2591 uint32_t type:8;
2592 #define TYPE_NATIVE_SLI2 0x01;
2593 #endif
2594
2595 uint32_t mailBoxSize;
2596 uint32_t mbAddrLow;
2597 uint32_t mbAddrHigh;
2598
2599 uint32_t hgpAddrLow;
2600 uint32_t hgpAddrHigh;
2601
2602 uint32_t pgpAddrLow;
2603 uint32_t pgpAddrHigh;
2604 SLI2_RDSC rdsc[MAX_RINGS];
2605 } PCB_t;
2606
2607 /* NEW_FEATURE */
2608 typedef struct {
2609 #ifdef __BIG_ENDIAN_BITFIELD
2610 uint32_t rsvd0:27;
2611 uint32_t discardFarp:1;
2612 uint32_t IPEnable:1;
2613 uint32_t nodeName:1;
2614 uint32_t portName:1;
2615 uint32_t filterEnable:1;
2616 #else /* __LITTLE_ENDIAN_BITFIELD */
2617 uint32_t filterEnable:1;
2618 uint32_t portName:1;
2619 uint32_t nodeName:1;
2620 uint32_t IPEnable:1;
2621 uint32_t discardFarp:1;
2622 uint32_t rsvd:27;
2623 #endif
2624
2625 uint8_t portname[8]; /* Used to be struct lpfc_name */
2626 uint8_t nodename[8];
2627 uint32_t rsvd1;
2628 uint32_t rsvd2;
2629 uint32_t rsvd3;
2630 uint32_t IPAddress;
2631 } CONFIG_FARP_VAR;
2632
2633 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
2634
2635 typedef struct {
2636 #ifdef __BIG_ENDIAN_BITFIELD
2637 uint32_t rsvd:30;
2638 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2639 #else /* __LITTLE_ENDIAN */
2640 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2641 uint32_t rsvd:30;
2642 #endif
2643 } ASYNCEVT_ENABLE_VAR;
2644
2645 /* Union of all Mailbox Command types */
2646 #define MAILBOX_CMD_WSIZE 32
2647 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2648
2649 typedef union {
2650 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2651 * feature/max ring number
2652 */
2653 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2654 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2655 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2656 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2657 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2658 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2659 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2660 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2661 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2662 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2663 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2664 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2665 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2666 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2667 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2668 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2669 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2670 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2671 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2672 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2673 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2674 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2675 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2676 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2677 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2678 * NEW_FEATURE
2679 */
2680 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2681 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2682 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2683 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2684 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
2685 } MAILVARIANTS;
2686
2687 /*
2688 * SLI-2 specific structures
2689 */
2690
2691 struct lpfc_hgp {
2692 __le32 cmdPutInx;
2693 __le32 rspGetInx;
2694 };
2695
2696 struct lpfc_pgp {
2697 __le32 cmdGetInx;
2698 __le32 rspPutInx;
2699 };
2700
2701 struct sli2_desc {
2702 uint32_t unused1[16];
2703 struct lpfc_hgp host[MAX_RINGS];
2704 struct lpfc_pgp port[MAX_RINGS];
2705 };
2706
2707 struct sli3_desc {
2708 struct lpfc_hgp host[MAX_RINGS];
2709 uint32_t reserved[8];
2710 uint32_t hbq_put[16];
2711 };
2712
2713 struct sli3_pgp {
2714 struct lpfc_pgp port[MAX_RINGS];
2715 uint32_t hbq_get[16];
2716 };
2717
2718 typedef union {
2719 struct sli2_desc s2;
2720 struct sli3_desc s3;
2721 struct sli3_pgp s3_pgp;
2722 } SLI_VAR;
2723
2724 typedef struct {
2725 #ifdef __BIG_ENDIAN_BITFIELD
2726 uint16_t mbxStatus;
2727 uint8_t mbxCommand;
2728 uint8_t mbxReserved:6;
2729 uint8_t mbxHc:1;
2730 uint8_t mbxOwner:1; /* Low order bit first word */
2731 #else /* __LITTLE_ENDIAN_BITFIELD */
2732 uint8_t mbxOwner:1; /* Low order bit first word */
2733 uint8_t mbxHc:1;
2734 uint8_t mbxReserved:6;
2735 uint8_t mbxCommand;
2736 uint16_t mbxStatus;
2737 #endif
2738
2739 MAILVARIANTS un;
2740 SLI_VAR us;
2741 } MAILBOX_t;
2742
2743 /*
2744 * Begin Structure Definitions for IOCB Commands
2745 */
2746
2747 typedef struct {
2748 #ifdef __BIG_ENDIAN_BITFIELD
2749 uint8_t statAction;
2750 uint8_t statRsn;
2751 uint8_t statBaExp;
2752 uint8_t statLocalError;
2753 #else /* __LITTLE_ENDIAN_BITFIELD */
2754 uint8_t statLocalError;
2755 uint8_t statBaExp;
2756 uint8_t statRsn;
2757 uint8_t statAction;
2758 #endif
2759 /* statRsn P/F_RJT reason codes */
2760 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2761 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2762 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2763 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2764 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2765 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2766 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2767 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2768 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2769 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2770 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2771 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2772 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2773 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2774 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2775 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
2776 #define RJT_XCHG_ERR 0x11 /* Exchange error */
2777 #define RJT_PROT_ERR 0x12 /* Protocol error */
2778 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2779 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2780 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2781 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2782 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2783 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2784 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2785 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2786
2787 #define IOERR_SUCCESS 0x00 /* statLocalError */
2788 #define IOERR_MISSING_CONTINUE 0x01
2789 #define IOERR_SEQUENCE_TIMEOUT 0x02
2790 #define IOERR_INTERNAL_ERROR 0x03
2791 #define IOERR_INVALID_RPI 0x04
2792 #define IOERR_NO_XRI 0x05
2793 #define IOERR_ILLEGAL_COMMAND 0x06
2794 #define IOERR_XCHG_DROPPED 0x07
2795 #define IOERR_ILLEGAL_FIELD 0x08
2796 #define IOERR_BAD_CONTINUE 0x09
2797 #define IOERR_TOO_MANY_BUFFERS 0x0A
2798 #define IOERR_RCV_BUFFER_WAITING 0x0B
2799 #define IOERR_NO_CONNECTION 0x0C
2800 #define IOERR_TX_DMA_FAILED 0x0D
2801 #define IOERR_RX_DMA_FAILED 0x0E
2802 #define IOERR_ILLEGAL_FRAME 0x0F
2803 #define IOERR_EXTRA_DATA 0x10
2804 #define IOERR_NO_RESOURCES 0x11
2805 #define IOERR_RESERVED 0x12
2806 #define IOERR_ILLEGAL_LENGTH 0x13
2807 #define IOERR_UNSUPPORTED_FEATURE 0x14
2808 #define IOERR_ABORT_IN_PROGRESS 0x15
2809 #define IOERR_ABORT_REQUESTED 0x16
2810 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2811 #define IOERR_LOOP_OPEN_FAILURE 0x18
2812 #define IOERR_RING_RESET 0x19
2813 #define IOERR_LINK_DOWN 0x1A
2814 #define IOERR_CORRUPTED_DATA 0x1B
2815 #define IOERR_CORRUPTED_RPI 0x1C
2816 #define IOERR_OUT_OF_ORDER_DATA 0x1D
2817 #define IOERR_OUT_OF_ORDER_ACK 0x1E
2818 #define IOERR_DUP_FRAME 0x1F
2819 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2820 #define IOERR_BAD_HOST_ADDRESS 0x21
2821 #define IOERR_RCV_HDRBUF_WAITING 0x22
2822 #define IOERR_MISSING_HDR_BUFFER 0x23
2823 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2824 #define IOERR_ABORTMULT_REQUESTED 0x25
2825 #define IOERR_BUFFER_SHORTAGE 0x28
2826 #define IOERR_DEFAULT 0x29
2827 #define IOERR_CNT 0x2A
2828
2829 #define IOERR_DRVR_MASK 0x100
2830 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2831 #define IOERR_SLI_BRESET 0x102
2832 #define IOERR_SLI_ABORTED 0x103
2833 } PARM_ERR;
2834
2835 typedef union {
2836 struct {
2837 #ifdef __BIG_ENDIAN_BITFIELD
2838 uint8_t Rctl; /* R_CTL field */
2839 uint8_t Type; /* TYPE field */
2840 uint8_t Dfctl; /* DF_CTL field */
2841 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2842 #else /* __LITTLE_ENDIAN_BITFIELD */
2843 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2844 uint8_t Dfctl; /* DF_CTL field */
2845 uint8_t Type; /* TYPE field */
2846 uint8_t Rctl; /* R_CTL field */
2847 #endif
2848
2849 #define BC 0x02 /* Broadcast Received - Fctl */
2850 #define SI 0x04 /* Sequence Initiative */
2851 #define LA 0x08 /* Ignore Link Attention state */
2852 #define LS 0x80 /* Last Sequence */
2853 } hcsw;
2854 uint32_t reserved;
2855 } WORD5;
2856
2857 /* IOCB Command template for a generic response */
2858 typedef struct {
2859 uint32_t reserved[4];
2860 PARM_ERR perr;
2861 } GENERIC_RSP;
2862
2863 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2864 typedef struct {
2865 struct ulp_bde xrsqbde[2];
2866 uint32_t xrsqRo; /* Starting Relative Offset */
2867 WORD5 w5; /* Header control/status word */
2868 } XR_SEQ_FIELDS;
2869
2870 /* IOCB Command template for ELS_REQUEST */
2871 typedef struct {
2872 struct ulp_bde elsReq;
2873 struct ulp_bde elsRsp;
2874
2875 #ifdef __BIG_ENDIAN_BITFIELD
2876 uint32_t word4Rsvd:7;
2877 uint32_t fl:1;
2878 uint32_t myID:24;
2879 uint32_t word5Rsvd:8;
2880 uint32_t remoteID:24;
2881 #else /* __LITTLE_ENDIAN_BITFIELD */
2882 uint32_t myID:24;
2883 uint32_t fl:1;
2884 uint32_t word4Rsvd:7;
2885 uint32_t remoteID:24;
2886 uint32_t word5Rsvd:8;
2887 #endif
2888 } ELS_REQUEST;
2889
2890 /* IOCB Command template for RCV_ELS_REQ */
2891 typedef struct {
2892 struct ulp_bde elsReq[2];
2893 uint32_t parmRo;
2894
2895 #ifdef __BIG_ENDIAN_BITFIELD
2896 uint32_t word5Rsvd:8;
2897 uint32_t remoteID:24;
2898 #else /* __LITTLE_ENDIAN_BITFIELD */
2899 uint32_t remoteID:24;
2900 uint32_t word5Rsvd:8;
2901 #endif
2902 } RCV_ELS_REQ;
2903
2904 /* IOCB Command template for ABORT / CLOSE_XRI */
2905 typedef struct {
2906 uint32_t rsvd[3];
2907 uint32_t abortType;
2908 #define ABORT_TYPE_ABTX 0x00000000
2909 #define ABORT_TYPE_ABTS 0x00000001
2910 uint32_t parm;
2911 #ifdef __BIG_ENDIAN_BITFIELD
2912 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2913 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2914 #else /* __LITTLE_ENDIAN_BITFIELD */
2915 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2916 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2917 #endif
2918 } AC_XRI;
2919
2920 /* IOCB Command template for ABORT_MXRI64 */
2921 typedef struct {
2922 uint32_t rsvd[3];
2923 uint32_t abortType;
2924 uint32_t parm;
2925 uint32_t iotag32;
2926 } A_MXRI64;
2927
2928 /* IOCB Command template for GET_RPI */
2929 typedef struct {
2930 uint32_t rsvd[4];
2931 uint32_t parmRo;
2932 #ifdef __BIG_ENDIAN_BITFIELD
2933 uint32_t word5Rsvd:8;
2934 uint32_t remoteID:24;
2935 #else /* __LITTLE_ENDIAN_BITFIELD */
2936 uint32_t remoteID:24;
2937 uint32_t word5Rsvd:8;
2938 #endif
2939 } GET_RPI;
2940
2941 /* IOCB Command template for all FCP Initiator commands */
2942 typedef struct {
2943 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2944 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2945 uint32_t fcpi_parm;
2946 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2947 } FCPI_FIELDS;
2948
2949 /* IOCB Command template for all FCP Target commands */
2950 typedef struct {
2951 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2952 uint32_t fcpt_Offset;
2953 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2954 } FCPT_FIELDS;
2955
2956 /* SLI-2 IOCB structure definitions */
2957
2958 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2959 typedef struct {
2960 ULP_BDL bdl;
2961 uint32_t xrsqRo; /* Starting Relative Offset */
2962 WORD5 w5; /* Header control/status word */
2963 } XMT_SEQ_FIELDS64;
2964
2965 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2966 typedef struct {
2967 struct ulp_bde64 rcvBde;
2968 uint32_t rsvd1;
2969 uint32_t xrsqRo; /* Starting Relative Offset */
2970 WORD5 w5; /* Header control/status word */
2971 } RCV_SEQ_FIELDS64;
2972
2973 /* IOCB Command template for ELS_REQUEST64 */
2974 typedef struct {
2975 ULP_BDL bdl;
2976 #ifdef __BIG_ENDIAN_BITFIELD
2977 uint32_t word4Rsvd:7;
2978 uint32_t fl:1;
2979 uint32_t myID:24;
2980 uint32_t word5Rsvd:8;
2981 uint32_t remoteID:24;
2982 #else /* __LITTLE_ENDIAN_BITFIELD */
2983 uint32_t myID:24;
2984 uint32_t fl:1;
2985 uint32_t word4Rsvd:7;
2986 uint32_t remoteID:24;
2987 uint32_t word5Rsvd:8;
2988 #endif
2989 } ELS_REQUEST64;
2990
2991 /* IOCB Command template for GEN_REQUEST64 */
2992 typedef struct {
2993 ULP_BDL bdl;
2994 uint32_t xrsqRo; /* Starting Relative Offset */
2995 WORD5 w5; /* Header control/status word */
2996 } GEN_REQUEST64;
2997
2998 /* IOCB Command template for RCV_ELS_REQ64 */
2999 typedef struct {
3000 struct ulp_bde64 elsReq;
3001 uint32_t rcvd1;
3002 uint32_t parmRo;
3003
3004 #ifdef __BIG_ENDIAN_BITFIELD
3005 uint32_t word5Rsvd:8;
3006 uint32_t remoteID:24;
3007 #else /* __LITTLE_ENDIAN_BITFIELD */
3008 uint32_t remoteID:24;
3009 uint32_t word5Rsvd:8;
3010 #endif
3011 } RCV_ELS_REQ64;
3012
3013 /* IOCB Command template for RCV_SEQ64 */
3014 struct rcv_seq64 {
3015 struct ulp_bde64 elsReq;
3016 uint32_t hbq_1;
3017 uint32_t parmRo;
3018 #ifdef __BIG_ENDIAN_BITFIELD
3019 uint32_t rctl:8;
3020 uint32_t type:8;
3021 uint32_t dfctl:8;
3022 uint32_t ls:1;
3023 uint32_t fs:1;
3024 uint32_t rsvd2:3;
3025 uint32_t si:1;
3026 uint32_t bc:1;
3027 uint32_t rsvd3:1;
3028 #else /* __LITTLE_ENDIAN_BITFIELD */
3029 uint32_t rsvd3:1;
3030 uint32_t bc:1;
3031 uint32_t si:1;
3032 uint32_t rsvd2:3;
3033 uint32_t fs:1;
3034 uint32_t ls:1;
3035 uint32_t dfctl:8;
3036 uint32_t type:8;
3037 uint32_t rctl:8;
3038 #endif
3039 };
3040
3041 /* IOCB Command template for all 64 bit FCP Initiator commands */
3042 typedef struct {
3043 ULP_BDL bdl;
3044 uint32_t fcpi_parm;
3045 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3046 } FCPI_FIELDS64;
3047
3048 /* IOCB Command template for all 64 bit FCP Target commands */
3049 typedef struct {
3050 ULP_BDL bdl;
3051 uint32_t fcpt_Offset;
3052 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3053 } FCPT_FIELDS64;
3054
3055 /* IOCB Command template for Async Status iocb commands */
3056 typedef struct {
3057 uint32_t rsvd[4];
3058 uint32_t param;
3059 #ifdef __BIG_ENDIAN_BITFIELD
3060 uint16_t evt_code; /* High order bits word 5 */
3061 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3062 #else /* __LITTLE_ENDIAN_BITFIELD */
3063 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3064 uint16_t evt_code; /* Low order bits word 5 */
3065 #endif
3066 } ASYNCSTAT_FIELDS;
3067 #define ASYNC_TEMP_WARN 0x100
3068 #define ASYNC_TEMP_SAFE 0x101
3069
3070 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3071 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3072
3073 struct rcv_sli3 {
3074 uint32_t word8Rsvd;
3075 #ifdef __BIG_ENDIAN_BITFIELD
3076 uint16_t vpi;
3077 uint16_t word9Rsvd;
3078 #else /* __LITTLE_ENDIAN */
3079 uint16_t word9Rsvd;
3080 uint16_t vpi;
3081 #endif
3082 uint32_t word10Rsvd;
3083 uint32_t acc_len; /* accumulated length */
3084 struct ulp_bde64 bde2;
3085 };
3086
3087 /* Structure used for a single HBQ entry */
3088 struct lpfc_hbq_entry {
3089 struct ulp_bde64 bde;
3090 uint32_t buffer_tag;
3091 };
3092
3093 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3094 typedef struct {
3095 struct lpfc_hbq_entry buff;
3096 uint32_t rsvd;
3097 uint32_t rsvd1;
3098 } QUE_XRI64_CX_FIELDS;
3099
3100 struct que_xri64cx_ext_fields {
3101 uint32_t iotag64_low;
3102 uint32_t iotag64_high;
3103 uint32_t ebde_count;
3104 uint32_t rsvd;
3105 struct lpfc_hbq_entry buff[5];
3106 };
3107
3108 typedef struct _IOCB { /* IOCB structure */
3109 union {
3110 GENERIC_RSP grsp; /* Generic response */
3111 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3112 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3113 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3114 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3115 A_MXRI64 amxri; /* abort multiple xri command overlay */
3116 GET_RPI getrpi; /* GET_RPI template */
3117 FCPI_FIELDS fcpi; /* FCP Initiator template */
3118 FCPT_FIELDS fcpt; /* FCP target template */
3119
3120 /* SLI-2 structures */
3121
3122 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3123 * bde_64s */
3124 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3125 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3126 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3127 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3128 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3129 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3130 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3131 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3132 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3133
3134 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3135 } un;
3136 union {
3137 struct {
3138 #ifdef __BIG_ENDIAN_BITFIELD
3139 uint16_t ulpContext; /* High order bits word 6 */
3140 uint16_t ulpIoTag; /* Low order bits word 6 */
3141 #else /* __LITTLE_ENDIAN_BITFIELD */
3142 uint16_t ulpIoTag; /* Low order bits word 6 */
3143 uint16_t ulpContext; /* High order bits word 6 */
3144 #endif
3145 } t1;
3146 struct {
3147 #ifdef __BIG_ENDIAN_BITFIELD
3148 uint16_t ulpContext; /* High order bits word 6 */
3149 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3150 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3151 #else /* __LITTLE_ENDIAN_BITFIELD */
3152 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3153 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3154 uint16_t ulpContext; /* High order bits word 6 */
3155 #endif
3156 } t2;
3157 } un1;
3158 #define ulpContext un1.t1.ulpContext
3159 #define ulpIoTag un1.t1.ulpIoTag
3160 #define ulpIoTag0 un1.t2.ulpIoTag0
3161
3162 #ifdef __BIG_ENDIAN_BITFIELD
3163 uint32_t ulpTimeout:8;
3164 uint32_t ulpXS:1;
3165 uint32_t ulpFCP2Rcvy:1;
3166 uint32_t ulpPU:2;
3167 uint32_t ulpIr:1;
3168 uint32_t ulpClass:3;
3169 uint32_t ulpCommand:8;
3170 uint32_t ulpStatus:4;
3171 uint32_t ulpBdeCount:2;
3172 uint32_t ulpLe:1;
3173 uint32_t ulpOwner:1; /* Low order bit word 7 */
3174 #else /* __LITTLE_ENDIAN_BITFIELD */
3175 uint32_t ulpOwner:1; /* Low order bit word 7 */
3176 uint32_t ulpLe:1;
3177 uint32_t ulpBdeCount:2;
3178 uint32_t ulpStatus:4;
3179 uint32_t ulpCommand:8;
3180 uint32_t ulpClass:3;
3181 uint32_t ulpIr:1;
3182 uint32_t ulpPU:2;
3183 uint32_t ulpFCP2Rcvy:1;
3184 uint32_t ulpXS:1;
3185 uint32_t ulpTimeout:8;
3186 #endif
3187
3188 union {
3189 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3190
3191 /* words 8-31 used for que_xri_cx iocb */
3192 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3193
3194 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3195 } unsli3;
3196
3197 #define ulpCt_h ulpXS
3198 #define ulpCt_l ulpFCP2Rcvy
3199
3200 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3201 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3202 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3203 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3204 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3205 #define PARM_NPIV_DID 3
3206 #define CLASS1 0 /* Class 1 */
3207 #define CLASS2 1 /* Class 2 */
3208 #define CLASS3 2 /* Class 3 */
3209 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3210
3211 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3212 #define IOSTAT_FCP_RSP_ERROR 0x1
3213 #define IOSTAT_REMOTE_STOP 0x2
3214 #define IOSTAT_LOCAL_REJECT 0x3
3215 #define IOSTAT_NPORT_RJT 0x4
3216 #define IOSTAT_FABRIC_RJT 0x5
3217 #define IOSTAT_NPORT_BSY 0x6
3218 #define IOSTAT_FABRIC_BSY 0x7
3219 #define IOSTAT_INTERMED_RSP 0x8
3220 #define IOSTAT_LS_RJT 0x9
3221 #define IOSTAT_BA_RJT 0xA
3222 #define IOSTAT_RSVD1 0xB
3223 #define IOSTAT_RSVD2 0xC
3224 #define IOSTAT_RSVD3 0xD
3225 #define IOSTAT_RSVD4 0xE
3226 #define IOSTAT_NEED_BUFFER 0xF
3227 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3228 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3229 #define IOSTAT_CNT 0x11
3230
3231 } IOCB_t;
3232
3233
3234 #define SLI1_SLIM_SIZE (4 * 1024)
3235
3236 /* Up to 498 IOCBs will fit into 16k
3237 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3238 */
3239 #define SLI2_SLIM_SIZE (64 * 1024)
3240
3241 /* Maximum IOCBs that will fit in SLI2 slim */
3242 #define MAX_SLI2_IOCB 498
3243 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3244 (sizeof(MAILBOX_t) + sizeof(PCB_t)))
3245
3246 /* HBQ entries are 4 words each = 4k */
3247 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3248 lpfc_sli_hbq_count())
3249
3250 struct lpfc_sli2_slim {
3251 MAILBOX_t mbx;
3252 PCB_t pcb;
3253 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3254 };
3255
3256 /*
3257 * This function checks PCI device to allow special handling for LC HBAs.
3258 *
3259 * Parameters:
3260 * device : struct pci_dev 's device field
3261 *
3262 * return 1 => TRUE
3263 * 0 => FALSE
3264 */
3265 static inline int
3266 lpfc_is_LC_HBA(unsigned short device)
3267 {
3268 if ((device == PCI_DEVICE_ID_TFLY) ||
3269 (device == PCI_DEVICE_ID_PFLY) ||
3270 (device == PCI_DEVICE_ID_LP101) ||
3271 (device == PCI_DEVICE_ID_BMID) ||
3272 (device == PCI_DEVICE_ID_BSMB) ||
3273 (device == PCI_DEVICE_ID_ZMID) ||
3274 (device == PCI_DEVICE_ID_ZSMB) ||
3275 (device == PCI_DEVICE_ID_SAT_MID) ||
3276 (device == PCI_DEVICE_ID_SAT_SMB) ||
3277 (device == PCI_DEVICE_ID_RFLY))
3278 return 1;
3279 else
3280 return 0;
3281 }
3282
3283 /*
3284 * Determine if an IOCB failed because of a link event or firmware reset.
3285 */
3286
3287 static inline int
3288 lpfc_error_lost_link(IOCB_t *iocbp)
3289 {
3290 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3291 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3292 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3293 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3294 }
Support for the Chinese Samsung S3C2440 based development boards