arch/x86/kernel/irqinit_64.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel_stat.h>
  12 #include <linux/sysdev.h>
  13 #include <linux/bitops.h>
  14 #include <linux/acpi.h>
  15 #include <linux/io.h>
  16 #include <linux/delay.h>
  17
  18 #include <asm/atomic.h>
  19 #include <asm/system.h>
  20 #include <asm/hw_irq.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/desc.h>
  23 #include <asm/apic.h>
  24 #include <asm/i8259.h>
  25
  26 /*
  27  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  28  * (these are usually mapped to vectors 0x30-0x3f)
  29  */
  30
  31 /*
  32  * The IO-APIC gives us many more interrupt sources. Most of these
  33  * are unused but an SMP system is supposed to have enough memory ...
  34  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  35  * across the spectrum, so we really want to be prepared to get all
  36  * of these. Plus, more powerful systems might have more than 64
  37  * IO-APIC registers.
  38  *
  39  * (these are usually mapped into the 0x30-0xff vector range)
  40  */
  41
  42 #ifdef CONFIG_X86_32
  43 /*
  44  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  45  * as the irq is unreliable, and exception 16 works correctly
  46  * (ie as explained in the intel literature). On a 386, you
  47  * can't use exception 16 due to bad IBM design, so we have to
  48  * rely on the less exact irq13.
  49  *
  50  * Careful.. Not only is IRQ13 unreliable, but it is also
  51  * leads to races. IBM designers who came up with it should
  52  * be shot.
  53  */
  54
  55 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  56 {
  57         outb(0, 0xF0);
  58         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  59                 return IRQ_NONE;
  60         math_error((void __user *)get_irq_regs()->ip);
  61         return IRQ_HANDLED;
  62 }
  63
  64 /*
  65  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  66  * so allow interrupt sharing.
  67  */
  68 static struct irqaction fpu_irq = {
  69         .handler = math_error_irq,
  70         .name = "fpu",
  71 };
  72 #endif
  73
  74 /*
  75  * IRQ2 is cascade interrupt to second interrupt controller
  76  */
  77 static struct irqaction irq2 = {
  78         .handler = no_action,
  79         .name = "cascade",
  80 };
  81
  82 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  83         [0 ... IRQ0_VECTOR - 1] = -1,
  84         [IRQ0_VECTOR] = 0,
  85         [IRQ1_VECTOR] = 1,
  86         [IRQ2_VECTOR] = 2,
  87         [IRQ3_VECTOR] = 3,
  88         [IRQ4_VECTOR] = 4,
  89         [IRQ5_VECTOR] = 5,
  90         [IRQ6_VECTOR] = 6,
  91         [IRQ7_VECTOR] = 7,
  92         [IRQ8_VECTOR] = 8,
  93         [IRQ9_VECTOR] = 9,
  94         [IRQ10_VECTOR] = 10,
  95         [IRQ11_VECTOR] = 11,
  96         [IRQ12_VECTOR] = 12,
  97         [IRQ13_VECTOR] = 13,
  98         [IRQ14_VECTOR] = 14,
  99         [IRQ15_VECTOR] = 15,
 100         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 101 };
 102
 103 int vector_used_by_percpu_irq(unsigned int vector)
 104 {
 105         int cpu;
 106
 107         for_each_online_cpu(cpu) {
 108                 if (per_cpu(vector_irq, cpu)[vector] != -1)
 109                         return 1;
 110         }
 111
 112         return 0;
 113 }
 114
 115 static void __init init_ISA_irqs(void)
 116 {
 117         int i;
 118
 119 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 120         init_bsp_APIC();
 121 #endif
 122         init_8259A(0);
 123
 124         /*
 125          * 16 old-style INTA-cycle interrupts:
 126          */
 127         for (i = 0; i < NR_IRQS_LEGACY; i++) {
 128                 struct irq_desc *desc = irq_to_desc(i);
 129
 130                 desc->status = IRQ_DISABLED;
 131                 desc->action = NULL;
 132                 desc->depth = 1;
 133
 134                 set_irq_chip_and_handler_name(i, &i8259A_chip,
 135                                               handle_level_irq, "XT");
 136         }
 137 }
 138
 139 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 140
 141 static void __init smp_intr_init(void)
 142 {
 143 #ifdef CONFIG_SMP
 144 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 145         /*
 146          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 147          * IPI, driven by wakeup.
 148          */
 149         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 150
 151         /* IPIs for invalidation */
 152         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 153         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 154         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 155         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 156         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 157         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 158         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 159         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 160
 161         /* IPI for generic function call */
 162         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 163
 164         /* IPI for generic single function call */
 165         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 166                         call_function_single_interrupt);
 167
 168         /* Low priority IPI to cleanup after moving an irq */
 169         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 170         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 171 #endif
 172 #endif /* CONFIG_SMP */
 173 }
 174
 175 static void __init apic_intr_init(void)
 176 {
 177         smp_intr_init();
 178
 179         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 180         alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 181
 182         /* self generated IPI for local APIC timer */
 183         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 184
 185         /* generic IPI for platform specific use */
 186         alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
 187
 188         /* IPI vectors for APIC spurious and error interrupts */
 189         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 190         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 191 }
 192
 193 #ifdef CONFIG_X86_32
 194 /**
 195  * x86_quirk_pre_intr_init - initialisation prior to setting up interrupt vectors
 196  *
 197  * Description:
 198  *      Perform any necessary interrupt initialisation prior to setting up
 199  *      the "ordinary" interrupt call gates.  For legacy reasons, the ISA
 200  *      interrupts should be initialised here if the machine emulates a PC
 201  *      in any way.
 202  **/
 203 static void __init x86_quirk_pre_intr_init(void)
 204 {
 205         if (x86_quirks->arch_pre_intr_init) {
 206                 if (x86_quirks->arch_pre_intr_init())
 207                         return;
 208         }
 209         init_ISA_irqs();
 210 }
 211 #endif
 212
 213 void __init native_init_IRQ(void)
 214 {
 215         int i;
 216
 217 #ifdef CONFIG_X86_32
 218         /* Execute any quirks before the call gates are initialised: */
 219         x86_quirk_pre_intr_init();
 220 #else
 221         init_ISA_irqs();
 222 #endif
 223
 224         /*
 225          * Cover the whole vector space, no vector can escape
 226          * us. (some of these will be overridden and become
 227          * 'special' SMP interrupts)
 228          */
 229         for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 230 #ifdef CONFIG_X86_32
 231                 /* SYSCALL_VECTOR was reserved in trap_init. */
 232                 if (i != SYSCALL_VECTOR)
 233                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 234 #else
 235                 /* IA32_SYSCALL_VECTOR was reserved in trap_init. */
 236                 if (i != IA32_SYSCALL_VECTOR)
 237                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 238 #endif
 239         }
 240
 241         apic_intr_init();
 242
 243         if (!acpi_ioapic)
 244                 setup_irq(2, &irq2);
 245
 246 #ifdef CONFIG_X86_32
 247         /*
 248          * Call quirks after call gates are initialised (usually add in
 249          * the architecture specific gates):
 250          */
 251         x86_quirk_intr_init();
 252
 253         /*
 254          * External FPU? Set up irq13 if so, for
 255          * original braindamaged IBM FERR coupling.
 256          */
 257         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 258                 setup_irq(FPU_IRQ, &fpu_irq);
 259
 260         irq_ctx_init(smp_processor_id());
 261 #endif
 262 }