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udf: support files larger than 1G
[linux-2.6/mini2440.git] / drivers / net / smc91x.h
blob7053026d6c765aa0fecfcecaaf995e7409b9d2ee
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_BFIN)
59
60 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
61
62 # if defined (CONFIG_BFIN561_EZKIT)
63 #define SMC_CAN_USE_8BIT 0
64 #define SMC_CAN_USE_16BIT 1
65 #define SMC_CAN_USE_32BIT 1
66 #define SMC_IO_SHIFT 0
67 #define SMC_NOWAIT 1
68 #define SMC_USE_BFIN_DMA 0
69
70
71 #define SMC_inw(a, r) readw((a) + (r))
72 #define SMC_outw(v, a, r) writew(v, (a) + (r))
73 #define SMC_inl(a, r) readl((a) + (r))
74 #define SMC_outl(v, a, r) writel(v, (a) + (r))
75 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
76 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
77 # else
78 #define SMC_CAN_USE_8BIT 0
79 #define SMC_CAN_USE_16BIT 1
80 #define SMC_CAN_USE_32BIT 0
81 #define SMC_IO_SHIFT 0
82 #define SMC_NOWAIT 1
83 #define SMC_USE_BFIN_DMA 0
84
85
86 #define SMC_inw(a, r) readw((a) + (r))
87 #define SMC_outw(v, a, r) writew(v, (a) + (r))
88 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
89 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
90 # endif
91 /* check if the mac in reg is valid */
92 #define SMC_GET_MAC_ADDR(addr) \
93 do { \
94 unsigned int __v; \
95 __v = SMC_inw(ioaddr, ADDR0_REG); \
96 addr[0] = __v; addr[1] = __v >> 8; \
97 __v = SMC_inw(ioaddr, ADDR1_REG); \
98 addr[2] = __v; addr[3] = __v >> 8; \
99 __v = SMC_inw(ioaddr, ADDR2_REG); \
100 addr[4] = __v; addr[5] = __v >> 8; \
101 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
102 random_ether_addr(addr); \
103 } \
104 } while (0)
105 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
106
107 /* We can only do 16-bit reads and writes in the static memory space. */
108 #define SMC_CAN_USE_8BIT 0
109 #define SMC_CAN_USE_16BIT 1
110 #define SMC_CAN_USE_32BIT 0
111 #define SMC_NOWAIT 1
112
113 #define SMC_IO_SHIFT 0
114
115 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
116 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
117 #define SMC_insw(a, r, p, l) \
118 do { \
119 unsigned long __port = (a) + (r); \
120 u16 *__p = (u16 *)(p); \
121 int __l = (l); \
122 insw(__port, __p, __l); \
123 while (__l > 0) { \
124 *__p = swab16(*__p); \
125 __p++; \
126 __l--; \
127 } \
128 } while (0)
129 #define SMC_outsw(a, r, p, l) \
130 do { \
131 unsigned long __port = (a) + (r); \
132 u16 *__p = (u16 *)(p); \
133 int __l = (l); \
134 while (__l > 0) { \
135 /* Believe it or not, the swab isn't needed. */ \
136 outw( /* swab16 */ (*__p++), __port); \
137 __l--; \
138 } \
139 } while (0)
140 #define SMC_IRQ_FLAGS (0)
141
142 #elif defined(CONFIG_SA1100_PLEB)
143 /* We can only do 16-bit reads and writes in the static memory space. */
144 #define SMC_CAN_USE_8BIT 1
145 #define SMC_CAN_USE_16BIT 1
146 #define SMC_CAN_USE_32BIT 0
147 #define SMC_IO_SHIFT 0
148 #define SMC_NOWAIT 1
149
150 #define SMC_inb(a, r) readb((a) + (r))
151 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
152 #define SMC_inw(a, r) readw((a) + (r))
153 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
154 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
155 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
156 #define SMC_outw(v, a, r) writew(v, (a) + (r))
157 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
158
159 #define SMC_IRQ_FLAGS (0)
160
161 #elif defined(CONFIG_SA1100_ASSABET)
162
163 #include <asm/arch/neponset.h>
164
165 /* We can only do 8-bit reads and writes in the static memory space. */
166 #define SMC_CAN_USE_8BIT 1
167 #define SMC_CAN_USE_16BIT 0
168 #define SMC_CAN_USE_32BIT 0
169 #define SMC_NOWAIT 1
170
171 /* The first two address lines aren't connected... */
172 #define SMC_IO_SHIFT 2
173
174 #define SMC_inb(a, r) readb((a) + (r))
175 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
176 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
177 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
178
179 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
180
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
185 #define SMC_NOWAIT 1
186
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
191
192 #elif defined(CONFIG_ARCH_INNOKOM) || \
193 defined(CONFIG_MACH_MAINSTONE) || \
194 defined(CONFIG_ARCH_PXA_IDP) || \
195 defined(CONFIG_ARCH_RAMSES)
196
197 #define SMC_CAN_USE_8BIT 1
198 #define SMC_CAN_USE_16BIT 1
199 #define SMC_CAN_USE_32BIT 1
200 #define SMC_IO_SHIFT 0
201 #define SMC_NOWAIT 1
202 #define SMC_USE_PXA_DMA 1
203
204 #define SMC_inb(a, r) readb((a) + (r))
205 #define SMC_inw(a, r) readw((a) + (r))
206 #define SMC_inl(a, r) readl((a) + (r))
207 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
208 #define SMC_outl(v, a, r) writel(v, (a) + (r))
209 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
210 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
211
212 /* We actually can't write halfwords properly if not word aligned */
213 static inline void
214 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
215 {
216 if (reg & 2) {
217 unsigned int v = val << 16;
218 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
219 writel(v, ioaddr + (reg & ~2));
220 } else {
221 writew(val, ioaddr + reg);
222 }
223 }
224
225 #elif defined(CONFIG_ARCH_OMAP)
226
227 /* We can only do 16-bit reads and writes in the static memory space. */
228 #define SMC_CAN_USE_8BIT 0
229 #define SMC_CAN_USE_16BIT 1
230 #define SMC_CAN_USE_32BIT 0
231 #define SMC_IO_SHIFT 0
232 #define SMC_NOWAIT 1
233
234 #define SMC_inw(a, r) readw((a) + (r))
235 #define SMC_outw(v, a, r) writew(v, (a) + (r))
236 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
237 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
238
239 #include <asm/mach-types.h>
240 #include <asm/arch/cpu.h>
241
242 #define SMC_IRQ_FLAGS (( \
243 machine_is_omap_h2() \
244 || machine_is_omap_h3() \
245 || machine_is_omap_h4() \
246 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
247 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
248
249
250 #elif defined(CONFIG_SH_SH4202_MICRODEV)
251
252 #define SMC_CAN_USE_8BIT 0
253 #define SMC_CAN_USE_16BIT 1
254 #define SMC_CAN_USE_32BIT 0
255
256 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
257 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
258 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
259 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
260 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
261 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
262 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
263 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
264 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
265 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
266
267 #define SMC_IRQ_FLAGS (0)
268
269 #elif defined(CONFIG_ISA)
270
271 #define SMC_CAN_USE_8BIT 1
272 #define SMC_CAN_USE_16BIT 1
273 #define SMC_CAN_USE_32BIT 0
274
275 #define SMC_inb(a, r) inb((a) + (r))
276 #define SMC_inw(a, r) inw((a) + (r))
277 #define SMC_outb(v, a, r) outb(v, (a) + (r))
278 #define SMC_outw(v, a, r) outw(v, (a) + (r))
279 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
280 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
281
282 #elif defined(CONFIG_M32R)
283
284 #define SMC_CAN_USE_8BIT 0
285 #define SMC_CAN_USE_16BIT 1
286 #define SMC_CAN_USE_32BIT 0
287
288 #define SMC_inb(a, r) inb(((u32)a) + (r))
289 #define SMC_inw(a, r) inw(((u32)a) + (r))
290 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
291 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
292 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
293 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
294
295 #define SMC_IRQ_FLAGS (0)
296
297 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
298 #define RPC_LSB_DEFAULT RPC_LED_100_10
299
300 #elif defined(CONFIG_MACH_LPD79520) \
301 || defined(CONFIG_MACH_LPD7A400) \
302 || defined(CONFIG_MACH_LPD7A404)
303
304 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
305 * way that the CPU handles chip selects and the way that the SMC chip
306 * expects the chip select to operate. Refer to
307 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
308 * IOBARRIER is a byte, in order that we read the least-common
309 * denominator. It would be wasteful to read 32 bits from an 8-bit
310 * accessible region.
311 *
312 * There is no explicit protection against interrupts intervening
313 * between the writew and the IOBARRIER. In SMC ISR there is a
314 * preamble that performs an IOBARRIER in the extremely unlikely event
315 * that the driver interrupts itself between a writew to the chip an
316 * the IOBARRIER that follows *and* the cache is large enough that the
317 * first off-chip access while handing the interrupt is to the SMC
318 * chip. Other devices in the same address space as the SMC chip must
319 * be aware of the potential for trouble and perform a similar
320 * IOBARRIER on entry to their ISR.
321 */
322
323 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
324
325 #define SMC_CAN_USE_8BIT 0
326 #define SMC_CAN_USE_16BIT 1
327 #define SMC_CAN_USE_32BIT 0
328 #define SMC_NOWAIT 0
329 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
330
331 #define SMC_inw(a,r)\
332 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
333 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
334
335 #define SMC_insw LPD7_SMC_insw
336 static inline void LPD7_SMC_insw (unsigned char* a, int r,
337 unsigned char* p, int l)
338 {
339 unsigned short* ps = (unsigned short*) p;
340 while (l-- > 0) {
341 *ps++ = readw (a + r);
342 LPD7X_IOBARRIER;
343 }
344 }
345
346 #define SMC_outsw LPD7_SMC_outsw
347 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
348 unsigned char* p, int l)
349 {
350 unsigned short* ps = (unsigned short*) p;
351 while (l-- > 0) {
352 writew (*ps++, a + r);
353 LPD7X_IOBARRIER;
354 }
355 }
356
357 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
358
359 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
360 #define RPC_LSB_DEFAULT RPC_LED_100_10
361
362 #elif defined(CONFIG_SOC_AU1X00)
363
364 #include <au1xxx.h>
365
366 /* We can only do 16-bit reads and writes in the static memory space. */
367 #define SMC_CAN_USE_8BIT 0
368 #define SMC_CAN_USE_16BIT 1
369 #define SMC_CAN_USE_32BIT 0
370 #define SMC_IO_SHIFT 0
371 #define SMC_NOWAIT 1
372
373 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
374 #define SMC_insw(a, r, p, l) \
375 do { \
376 unsigned long _a = (unsigned long)((a) + (r)); \
377 int _l = (l); \
378 u16 *_p = (u16 *)(p); \
379 while (_l-- > 0) \
380 *_p++ = au_readw(_a); \
381 } while(0)
382 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
383 #define SMC_outsw(a, r, p, l) \
384 do { \
385 unsigned long _a = (unsigned long)((a) + (r)); \
386 int _l = (l); \
387 const u16 *_p = (const u16 *)(p); \
388 while (_l-- > 0) \
389 au_writew(*_p++ , _a); \
390 } while(0)
391
392 #define SMC_IRQ_FLAGS (0)
393
394 #elif defined(CONFIG_ARCH_VERSATILE)
395
396 #define SMC_CAN_USE_8BIT 1
397 #define SMC_CAN_USE_16BIT 1
398 #define SMC_CAN_USE_32BIT 1
399 #define SMC_NOWAIT 1
400
401 #define SMC_inb(a, r) readb((a) + (r))
402 #define SMC_inw(a, r) readw((a) + (r))
403 #define SMC_inl(a, r) readl((a) + (r))
404 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
405 #define SMC_outw(v, a, r) writew(v, (a) + (r))
406 #define SMC_outl(v, a, r) writel(v, (a) + (r))
407 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
408 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
409
410 #define SMC_IRQ_FLAGS (0)
411
412 #else
413
414 #define SMC_CAN_USE_8BIT 1
415 #define SMC_CAN_USE_16BIT 1
416 #define SMC_CAN_USE_32BIT 1
417 #define SMC_NOWAIT 1
418
419 #define SMC_inb(a, r) readb((a) + (r))
420 #define SMC_inw(a, r) readw((a) + (r))
421 #define SMC_inl(a, r) readl((a) + (r))
422 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
423 #define SMC_outw(v, a, r) writew(v, (a) + (r))
424 #define SMC_outl(v, a, r) writel(v, (a) + (r))
425 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
426 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
427
428 #define RPC_LSA_DEFAULT RPC_LED_100_10
429 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
430
431 #endif
432
433 #ifdef SMC_USE_PXA_DMA
434 /*
435 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
436 * always happening in irq context so no need to worry about races. TX is
437 * different and probably not worth it for that reason, and not as critical
438 * as RX which can overrun memory and lose packets.
439 */
440 #include <linux/dma-mapping.h>
441 #include <asm/dma.h>
442 #include <asm/arch/pxa-regs.h>
443
444 #ifdef SMC_insl
445 #undef SMC_insl
446 #define SMC_insl(a, r, p, l) \
447 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
448 static inline void
449 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
450 u_char *buf, int len)
451 {
452 dma_addr_t dmabuf;
453
454 /* fallback if no DMA available */
455 if (dma == (unsigned char)-1) {
456 readsl(ioaddr + reg, buf, len);
457 return;
458 }
459
460 /* 64 bit alignment is required for memory to memory DMA */
461 if ((long)buf & 4) {
462 *((u32 *)buf) = SMC_inl(ioaddr, reg);
463 buf += 4;
464 len--;
465 }
466
467 len *= 4;
468 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
469 DCSR(dma) = DCSR_NODESC;
470 DTADR(dma) = dmabuf;
471 DSADR(dma) = physaddr + reg;
472 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
473 DCMD_WIDTH4 | (DCMD_LENGTH & len));
474 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
475 while (!(DCSR(dma) & DCSR_STOPSTATE))
476 cpu_relax();
477 DCSR(dma) = 0;
478 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
479 }
480 #endif
481
482 #ifdef SMC_insw
483 #undef SMC_insw
484 #define SMC_insw(a, r, p, l) \
485 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
486 static inline void
487 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
488 u_char *buf, int len)
489 {
490 dma_addr_t dmabuf;
491
492 /* fallback if no DMA available */
493 if (dma == (unsigned char)-1) {
494 readsw(ioaddr + reg, buf, len);
495 return;
496 }
497
498 /* 64 bit alignment is required for memory to memory DMA */
499 while ((long)buf & 6) {
500 *((u16 *)buf) = SMC_inw(ioaddr, reg);
501 buf += 2;
502 len--;
503 }
504
505 len *= 2;
506 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
507 DCSR(dma) = DCSR_NODESC;
508 DTADR(dma) = dmabuf;
509 DSADR(dma) = physaddr + reg;
510 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
511 DCMD_WIDTH2 | (DCMD_LENGTH & len));
512 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
513 while (!(DCSR(dma) & DCSR_STOPSTATE))
514 cpu_relax();
515 DCSR(dma) = 0;
516 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
517 }
518 #endif
519
520 static void
521 smc_pxa_dma_irq(int dma, void *dummy)
522 {
523 DCSR(dma) = 0;
524 }
525 #endif /* SMC_USE_PXA_DMA */
526
527
528 /*
529 * Everything a particular hardware setup needs should have been defined
530 * at this point. Add stubs for the undefined cases, mainly to avoid
531 * compilation warnings since they'll be optimized away, or to prevent buggy
532 * use of them.
533 */
534
535 #if ! SMC_CAN_USE_32BIT
536 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
537 #define SMC_outl(x, ioaddr, reg) BUG()
538 #define SMC_insl(a, r, p, l) BUG()
539 #define SMC_outsl(a, r, p, l) BUG()
540 #endif
541
542 #if !defined(SMC_insl) || !defined(SMC_outsl)
543 #define SMC_insl(a, r, p, l) BUG()
544 #define SMC_outsl(a, r, p, l) BUG()
545 #endif
546
547 #if ! SMC_CAN_USE_16BIT
548
549 /*
550 * Any 16-bit access is performed with two 8-bit accesses if the hardware
551 * can't do it directly. Most registers are 16-bit so those are mandatory.
552 */
553 #define SMC_outw(x, ioaddr, reg) \
554 do { \
555 unsigned int __val16 = (x); \
556 SMC_outb( __val16, ioaddr, reg ); \
557 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
558 } while (0)
559 #define SMC_inw(ioaddr, reg) \
560 ({ \
561 unsigned int __val16; \
562 __val16 = SMC_inb( ioaddr, reg ); \
563 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
564 __val16; \
565 })
566
567 #define SMC_insw(a, r, p, l) BUG()
568 #define SMC_outsw(a, r, p, l) BUG()
569
570 #endif
571
572 #if !defined(SMC_insw) || !defined(SMC_outsw)
573 #define SMC_insw(a, r, p, l) BUG()
574 #define SMC_outsw(a, r, p, l) BUG()
575 #endif
576
577 #if ! SMC_CAN_USE_8BIT
578 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
579 #define SMC_outb(x, ioaddr, reg) BUG()
580 #define SMC_insb(a, r, p, l) BUG()
581 #define SMC_outsb(a, r, p, l) BUG()
582 #endif
583
584 #if !defined(SMC_insb) || !defined(SMC_outsb)
585 #define SMC_insb(a, r, p, l) BUG()
586 #define SMC_outsb(a, r, p, l) BUG()
587 #endif
588
589 #ifndef SMC_CAN_USE_DATACS
590 #define SMC_CAN_USE_DATACS 0
591 #endif
592
593 #ifndef SMC_IO_SHIFT
594 #define SMC_IO_SHIFT 0
595 #endif
596
597 #ifndef SMC_IRQ_FLAGS
598 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
599 #endif
600
601 #ifndef SMC_INTERRUPT_PREAMBLE
602 #define SMC_INTERRUPT_PREAMBLE
603 #endif
604
605
606 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
607 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
608 #define SMC_DATA_EXTENT (4)
609
610 /*
611 . Bank Select Register:
612 .
613 . yyyy yyyy 0000 00xx
614 . xx = bank number
615 . yyyy yyyy = 0x33, for identification purposes.
616 */
617 #define BANK_SELECT (14 << SMC_IO_SHIFT)
618
619
620 // Transmit Control Register
621 /* BANK 0 */
622 #define TCR_REG SMC_REG(0x0000, 0)
623 #define TCR_ENABLE 0x0001 // When 1 we can transmit
624 #define TCR_LOOP 0x0002 // Controls output pin LBK
625 #define TCR_FORCOL 0x0004 // When 1 will force a collision
626 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
627 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
628 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
629 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
630 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
631 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
632 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
633
634 #define TCR_CLEAR 0 /* do NOTHING */
635 /* the default settings for the TCR register : */
636 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
637
638
639 // EPH Status Register
640 /* BANK 0 */
641 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
642 #define ES_TX_SUC 0x0001 // Last TX was successful
643 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
644 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
645 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
646 #define ES_16COL 0x0010 // 16 Collisions Reached
647 #define ES_SQET 0x0020 // Signal Quality Error Test
648 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
649 #define ES_TXDEFR 0x0080 // Transmit Deferred
650 #define ES_LATCOL 0x0200 // Late collision detected on last tx
651 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
652 #define ES_EXC_DEF 0x0800 // Excessive Deferral
653 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
654 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
655 #define ES_TXUNRN 0x8000 // Tx Underrun
656
657
658 // Receive Control Register
659 /* BANK 0 */
660 #define RCR_REG SMC_REG(0x0004, 0)
661 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
662 #define RCR_PRMS 0x0002 // Enable promiscuous mode
663 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
664 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
665 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
666 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
667 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
668 #define RCR_SOFTRST 0x8000 // resets the chip
669
670 /* the normal settings for the RCR register : */
671 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
672 #define RCR_CLEAR 0x0 // set it to a base state
673
674
675 // Counter Register
676 /* BANK 0 */
677 #define COUNTER_REG SMC_REG(0x0006, 0)
678
679
680 // Memory Information Register
681 /* BANK 0 */
682 #define MIR_REG SMC_REG(0x0008, 0)
683
684
685 // Receive/Phy Control Register
686 /* BANK 0 */
687 #define RPC_REG SMC_REG(0x000A, 0)
688 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
689 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
690 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
691 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
692 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
693 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
694 #define RPC_LED_RES (0x01) // LED = Reserved
695 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
696 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
697 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
698 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
699 #define RPC_LED_TX (0x06) // LED = TX packet occurred
700 #define RPC_LED_RX (0x07) // LED = RX packet occurred
701
702 #ifndef RPC_LSA_DEFAULT
703 #define RPC_LSA_DEFAULT RPC_LED_100
704 #endif
705 #ifndef RPC_LSB_DEFAULT
706 #define RPC_LSB_DEFAULT RPC_LED_FD
707 #endif
708
709 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
710
711
712 /* Bank 0 0x0C is reserved */
713
714 // Bank Select Register
715 /* All Banks */
716 #define BSR_REG 0x000E
717
718
719 // Configuration Reg
720 /* BANK 1 */
721 #define CONFIG_REG SMC_REG(0x0000, 1)
722 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
723 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
724 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
725 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
726
727 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
728 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
729
730
731 // Base Address Register
732 /* BANK 1 */
733 #define BASE_REG SMC_REG(0x0002, 1)
734
735
736 // Individual Address Registers
737 /* BANK 1 */
738 #define ADDR0_REG SMC_REG(0x0004, 1)
739 #define ADDR1_REG SMC_REG(0x0006, 1)
740 #define ADDR2_REG SMC_REG(0x0008, 1)
741
742
743 // General Purpose Register
744 /* BANK 1 */
745 #define GP_REG SMC_REG(0x000A, 1)
746
747
748 // Control Register
749 /* BANK 1 */
750 #define CTL_REG SMC_REG(0x000C, 1)
751 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
752 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
753 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
754 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
755 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
756 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
757 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
758 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
759
760
761 // MMU Command Register
762 /* BANK 2 */
763 #define MMU_CMD_REG SMC_REG(0x0000, 2)
764 #define MC_BUSY 1 // When 1 the last release has not completed
765 #define MC_NOP (0<<5) // No Op
766 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
767 #define MC_RESET (2<<5) // Reset MMU to initial state
768 #define MC_REMOVE (3<<5) // Remove the current rx packet
769 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
770 #define MC_FREEPKT (5<<5) // Release packet in PNR register
771 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
772 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
773
774
775 // Packet Number Register
776 /* BANK 2 */
777 #define PN_REG SMC_REG(0x0002, 2)
778
779
780 // Allocation Result Register
781 /* BANK 2 */
782 #define AR_REG SMC_REG(0x0003, 2)
783 #define AR_FAILED 0x80 // Alocation Failed
784
785
786 // TX FIFO Ports Register
787 /* BANK 2 */
788 #define TXFIFO_REG SMC_REG(0x0004, 2)
789 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
790
791 // RX FIFO Ports Register
792 /* BANK 2 */
793 #define RXFIFO_REG SMC_REG(0x0005, 2)
794 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
795
796 #define FIFO_REG SMC_REG(0x0004, 2)
797
798 // Pointer Register
799 /* BANK 2 */
800 #define PTR_REG SMC_REG(0x0006, 2)
801 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
802 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
803 #define PTR_READ 0x2000 // When 1 the operation is a read
804
805
806 // Data Register
807 /* BANK 2 */
808 #define DATA_REG SMC_REG(0x0008, 2)
809
810
811 // Interrupt Status/Acknowledge Register
812 /* BANK 2 */
813 #define INT_REG SMC_REG(0x000C, 2)
814
815
816 // Interrupt Mask Register
817 /* BANK 2 */
818 #define IM_REG SMC_REG(0x000D, 2)
819 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
820 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
821 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
822 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
823 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
824 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
825 #define IM_TX_INT 0x02 // Transmit Interrupt
826 #define IM_RCV_INT 0x01 // Receive Interrupt
827
828
829 // Multicast Table Registers
830 /* BANK 3 */
831 #define MCAST_REG1 SMC_REG(0x0000, 3)
832 #define MCAST_REG2 SMC_REG(0x0002, 3)
833 #define MCAST_REG3 SMC_REG(0x0004, 3)
834 #define MCAST_REG4 SMC_REG(0x0006, 3)
835
836
837 // Management Interface Register (MII)
838 /* BANK 3 */
839 #define MII_REG SMC_REG(0x0008, 3)
840 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
841 #define MII_MDOE 0x0008 // MII Output Enable
842 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
843 #define MII_MDI 0x0002 // MII Input, pin MDI
844 #define MII_MDO 0x0001 // MII Output, pin MDO
845
846
847 // Revision Register
848 /* BANK 3 */
849 /* ( hi: chip id low: rev # ) */
850 #define REV_REG SMC_REG(0x000A, 3)
851
852
853 // Early RCV Register
854 /* BANK 3 */
855 /* this is NOT on SMC9192 */
856 #define ERCV_REG SMC_REG(0x000C, 3)
857 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
858 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
859
860
861 // External Register
862 /* BANK 7 */
863 #define EXT_REG SMC_REG(0x0000, 7)
864
865
866 #define CHIP_9192 3
867 #define CHIP_9194 4
868 #define CHIP_9195 5
869 #define CHIP_9196 6
870 #define CHIP_91100 7
871 #define CHIP_91100FD 8
872 #define CHIP_91111FD 9
873
874 static const char * chip_ids[ 16 ] = {
875 NULL, NULL, NULL,
876 /* 3 */ "SMC91C90/91C92",
877 /* 4 */ "SMC91C94",
878 /* 5 */ "SMC91C95",
879 /* 6 */ "SMC91C96",
880 /* 7 */ "SMC91C100",
881 /* 8 */ "SMC91C100FD",
882 /* 9 */ "SMC91C11xFD",
883 NULL, NULL, NULL,
884 NULL, NULL, NULL};
885
886
887 /*
888 . Receive status bits
889 */
890 #define RS_ALGNERR 0x8000
891 #define RS_BRODCAST 0x4000
892 #define RS_BADCRC 0x2000
893 #define RS_ODDFRAME 0x1000
894 #define RS_TOOLONG 0x0800
895 #define RS_TOOSHORT 0x0400
896 #define RS_MULTICAST 0x0001
897 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
898
899
900 /*
901 * PHY IDs
902 * LAN83C183 == LAN91C111 Internal PHY
903 */
904 #define PHY_LAN83C183 0x0016f840
905 #define PHY_LAN83C180 0x02821c50
906
907 /*
908 * PHY Register Addresses (LAN91C111 Internal PHY)
909 *
910 * Generic PHY registers can be found in <linux/mii.h>
911 *
912 * These phy registers are specific to our on-board phy.
913 */
914
915 // PHY Configuration Register 1
916 #define PHY_CFG1_REG 0x10
917 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
918 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
919 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
920 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
921 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
922 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
923 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
924 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
925 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
926 #define PHY_CFG1_TLVL_MASK 0x003C
927 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
928
929
930 // PHY Configuration Register 2
931 #define PHY_CFG2_REG 0x11
932 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
933 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
934 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
935 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
936
937 // PHY Status Output (and Interrupt status) Register
938 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
939 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
940 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
941 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
942 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
943 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
944 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
945 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
946 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
947 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
948 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
949
950 // PHY Interrupt/Status Mask Register
951 #define PHY_MASK_REG 0x13 // Interrupt Mask
952 // Uses the same bit definitions as PHY_INT_REG
953
954
955 /*
956 * SMC91C96 ethernet config and status registers.
957 * These are in the "attribute" space.
958 */
959 #define ECOR 0x8000
960 #define ECOR_RESET 0x80
961 #define ECOR_LEVEL_IRQ 0x40
962 #define ECOR_WR_ATTRIB 0x04
963 #define ECOR_ENABLE 0x01
964
965 #define ECSR 0x8002
966 #define ECSR_IOIS8 0x20
967 #define ECSR_PWRDWN 0x04
968 #define ECSR_INT 0x02
969
970 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
971
972
973 /*
974 * Macros to abstract register access according to the data bus
975 * capabilities. Please use those and not the in/out primitives.
976 * Note: the following macros do *not* select the bank -- this must
977 * be done separately as needed in the main code. The SMC_REG() macro
978 * only uses the bank argument for debugging purposes (when enabled).
979 *
980 * Note: despite inline functions being safer, everything leading to this
981 * should preferably be macros to let BUG() display the line number in
982 * the core source code since we're interested in the top call site
983 * not in any inline function location.
984 */
985
986 #if SMC_DEBUG > 0
987 #define SMC_REG(reg, bank) \
988 ({ \
989 int __b = SMC_CURRENT_BANK(); \
990 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
991 printk( "%s: bank reg screwed (0x%04x)\n", \
992 CARDNAME, __b ); \
993 BUG(); \
994 } \
995 reg<<SMC_IO_SHIFT; \
996 })
997 #else
998 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
999 #endif
1000
1001 /*
1002 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1003 * aligned to a 32 bit boundary. I tell you that does exist!
1004 * Fortunately the affected register accesses can be easily worked around
1005 * since we can write zeroes to the preceeding 16 bits without adverse
1006 * effects and use a 32-bit access.
1007 *
1008 * Enforce it on any 32-bit capable setup for now.
1009 */
1010 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1011
1012 #define SMC_GET_PN() \
1013 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1014 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1015
1016 #define SMC_SET_PN(x) \
1017 do { \
1018 if (SMC_MUST_ALIGN_WRITE) \
1019 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1020 else if (SMC_CAN_USE_8BIT) \
1021 SMC_outb(x, ioaddr, PN_REG); \
1022 else \
1023 SMC_outw(x, ioaddr, PN_REG); \
1024 } while (0)
1025
1026 #define SMC_GET_AR() \
1027 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1028 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1029
1030 #define SMC_GET_TXFIFO() \
1031 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1032 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1033
1034 #define SMC_GET_RXFIFO() \
1035 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1036 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1037
1038 #define SMC_GET_INT() \
1039 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1040 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1041
1042 #define SMC_ACK_INT(x) \
1043 do { \
1044 if (SMC_CAN_USE_8BIT) \
1045 SMC_outb(x, ioaddr, INT_REG); \
1046 else { \
1047 unsigned long __flags; \
1048 int __mask; \
1049 local_irq_save(__flags); \
1050 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1051 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1052 local_irq_restore(__flags); \
1053 } \
1054 } while (0)
1055
1056 #define SMC_GET_INT_MASK() \
1057 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1058 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1059
1060 #define SMC_SET_INT_MASK(x) \
1061 do { \
1062 if (SMC_CAN_USE_8BIT) \
1063 SMC_outb(x, ioaddr, IM_REG); \
1064 else \
1065 SMC_outw((x) << 8, ioaddr, INT_REG); \
1066 } while (0)
1067
1068 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1069
1070 #define SMC_SELECT_BANK(x) \
1071 do { \
1072 if (SMC_MUST_ALIGN_WRITE) \
1073 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1074 else \
1075 SMC_outw(x, ioaddr, BANK_SELECT); \
1076 } while (0)
1077
1078 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1079
1080 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1081
1082 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1083
1084 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1085
1086 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1087
1088 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1089
1090 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1091
1092 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1093
1094 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1095
1096 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1097
1098 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1099
1100 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1101
1102 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1103
1104 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1105
1106 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1107
1108 #define SMC_SET_PTR(x) \
1109 do { \
1110 if (SMC_MUST_ALIGN_WRITE) \
1111 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1112 else \
1113 SMC_outw(x, ioaddr, PTR_REG); \
1114 } while (0)
1115
1116 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1117
1118 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1119
1120 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1121
1122 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1123
1124 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1125
1126 #define SMC_SET_RPC(x) \
1127 do { \
1128 if (SMC_MUST_ALIGN_WRITE) \
1129 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1130 else \
1131 SMC_outw(x, ioaddr, RPC_REG); \
1132 } while (0)
1133
1134 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1135
1136 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1137
1138 #ifndef SMC_GET_MAC_ADDR
1139 #define SMC_GET_MAC_ADDR(addr) \
1140 do { \
1141 unsigned int __v; \
1142 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1143 addr[0] = __v; addr[1] = __v >> 8; \
1144 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1145 addr[2] = __v; addr[3] = __v >> 8; \
1146 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1147 addr[4] = __v; addr[5] = __v >> 8; \
1148 } while (0)
1149 #endif
1150
1151 #define SMC_SET_MAC_ADDR(addr) \
1152 do { \
1153 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1154 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1155 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1156 } while (0)
1157
1158 #define SMC_SET_MCAST(x) \
1159 do { \
1160 const unsigned char *mt = (x); \
1161 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1162 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1163 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1164 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1165 } while (0)
1166
1167 #define SMC_PUT_PKT_HDR(status, length) \
1168 do { \
1169 if (SMC_CAN_USE_32BIT) \
1170 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1171 else { \
1172 SMC_outw(status, ioaddr, DATA_REG); \
1173 SMC_outw(length, ioaddr, DATA_REG); \
1174 } \
1175 } while (0)
1176
1177 #define SMC_GET_PKT_HDR(status, length) \
1178 do { \
1179 if (SMC_CAN_USE_32BIT) { \
1180 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1181 (status) = __val & 0xffff; \
1182 (length) = __val >> 16; \
1183 } else { \
1184 (status) = SMC_inw(ioaddr, DATA_REG); \
1185 (length) = SMC_inw(ioaddr, DATA_REG); \
1186 } \
1187 } while (0)
1188
1189 #define SMC_PUSH_DATA(p, l) \
1190 do { \
1191 if (SMC_CAN_USE_32BIT) { \
1192 void *__ptr = (p); \
1193 int __len = (l); \
1194 void __iomem *__ioaddr = ioaddr; \
1195 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1196 __len -= 2; \
1197 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1198 __ptr += 2; \
1199 } \
1200 if (SMC_CAN_USE_DATACS && lp->datacs) \
1201 __ioaddr = lp->datacs; \
1202 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1203 if (__len & 2) { \
1204 __ptr += (__len & ~3); \
1205 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1206 } \
1207 } else if (SMC_CAN_USE_16BIT) \
1208 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1209 else if (SMC_CAN_USE_8BIT) \
1210 SMC_outsb(ioaddr, DATA_REG, p, l); \
1211 } while (0)
1212
1213 #define SMC_PULL_DATA(p, l) \
1214 do { \
1215 if (SMC_CAN_USE_32BIT) { \
1216 void *__ptr = (p); \
1217 int __len = (l); \
1218 void __iomem *__ioaddr = ioaddr; \
1219 if ((unsigned long)__ptr & 2) { \
1220 /* \
1221 * We want 32bit alignment here. \
1222 * Since some buses perform a full \
1223 * 32bit fetch even for 16bit data \
1224 * we can't use SMC_inw() here. \
1225 * Back both source (on-chip) and \
1226 * destination pointers of 2 bytes. \
1227 * This is possible since the call to \
1228 * SMC_GET_PKT_HDR() already advanced \
1229 * the source pointer of 4 bytes, and \
1230 * the skb_reserve(skb, 2) advanced \
1231 * the destination pointer of 2 bytes. \
1232 */ \
1233 __ptr -= 2; \
1234 __len += 2; \
1235 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1236 } \
1237 if (SMC_CAN_USE_DATACS && lp->datacs) \
1238 __ioaddr = lp->datacs; \
1239 __len += 2; \
1240 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1241 } else if (SMC_CAN_USE_16BIT) \
1242 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1243 else if (SMC_CAN_USE_8BIT) \
1244 SMC_insb(ioaddr, DATA_REG, p, l); \
1245 } while (0)
1246
1247 #endif /* _SMC91X_H_ */
Support for the Chinese Samsung S3C2440 based development boards