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ALSA: hda - allow probing of 4 codecs
[linux-2.6/mini2440.git] / sound / pci / hda / hda_intel.c
blob60cc44abf58f2e915444e07ae6029297d622c9e9
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
51
52
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
55 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
56 static char *model[SNDRV_CARDS];
57 static int position_fix[SNDRV_CARDS];
58 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
59 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int single_cmd;
61 static int enable_msi;
62
63 module_param_array(index, int, NULL, 0444);
64 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
65 module_param_array(id, charp, NULL, 0444);
66 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
67 module_param_array(enable, bool, NULL, 0444);
68 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
69 module_param_array(model, charp, NULL, 0444);
70 MODULE_PARM_DESC(model, "Use the given board model.");
71 module_param_array(position_fix, int, NULL, 0444);
72 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
73 "(0 = auto, 1 = none, 2 = POSBUF).");
74 module_param_array(bdl_pos_adj, int, NULL, 0644);
75 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
76 module_param_array(probe_mask, int, NULL, 0444);
77 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
78 module_param(single_cmd, bool, 0444);
79 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
80 "(for debugging only).");
81 module_param(enable_msi, int, 0444);
82 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
83
84 #ifdef CONFIG_SND_HDA_POWER_SAVE
85 /* power_save option is defined in hda_codec.c */
86
87 /* reset the HD-audio controller in power save mode.
88 * this may give more power-saving, but will take longer time to
89 * wake up.
90 */
91 static int power_save_controller = 1;
92 module_param(power_save_controller, bool, 0644);
93 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
94 #endif
95
96 MODULE_LICENSE("GPL");
97 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
98 "{Intel, ICH6M},"
99 "{Intel, ICH7},"
100 "{Intel, ESB2},"
101 "{Intel, ICH8},"
102 "{Intel, ICH9},"
103 "{Intel, ICH10},"
104 "{Intel, PCH},"
105 "{Intel, SCH},"
106 "{ATI, SB450},"
107 "{ATI, SB600},"
108 "{ATI, RS600},"
109 "{ATI, RS690},"
110 "{ATI, RS780},"
111 "{ATI, R600},"
112 "{ATI, RV630},"
113 "{ATI, RV610},"
114 "{ATI, RV670},"
115 "{ATI, RV635},"
116 "{ATI, RV620},"
117 "{ATI, RV770},"
118 "{VIA, VT8251},"
119 "{VIA, VT8237A},"
120 "{SiS, SIS966},"
121 "{ULI, M5461}}");
122 MODULE_DESCRIPTION("Intel HDA driver");
123
124 #define SFX "hda-intel: "
125
126
127 /*
128 * registers
129 */
130 #define ICH6_REG_GCAP 0x00
131 #define ICH6_REG_VMIN 0x02
132 #define ICH6_REG_VMAJ 0x03
133 #define ICH6_REG_OUTPAY 0x04
134 #define ICH6_REG_INPAY 0x06
135 #define ICH6_REG_GCTL 0x08
136 #define ICH6_REG_WAKEEN 0x0c
137 #define ICH6_REG_STATESTS 0x0e
138 #define ICH6_REG_GSTS 0x10
139 #define ICH6_REG_INTCTL 0x20
140 #define ICH6_REG_INTSTS 0x24
141 #define ICH6_REG_WALCLK 0x30
142 #define ICH6_REG_SYNC 0x34
143 #define ICH6_REG_CORBLBASE 0x40
144 #define ICH6_REG_CORBUBASE 0x44
145 #define ICH6_REG_CORBWP 0x48
146 #define ICH6_REG_CORBRP 0x4A
147 #define ICH6_REG_CORBCTL 0x4c
148 #define ICH6_REG_CORBSTS 0x4d
149 #define ICH6_REG_CORBSIZE 0x4e
150
151 #define ICH6_REG_RIRBLBASE 0x50
152 #define ICH6_REG_RIRBUBASE 0x54
153 #define ICH6_REG_RIRBWP 0x58
154 #define ICH6_REG_RINTCNT 0x5a
155 #define ICH6_REG_RIRBCTL 0x5c
156 #define ICH6_REG_RIRBSTS 0x5d
157 #define ICH6_REG_RIRBSIZE 0x5e
158
159 #define ICH6_REG_IC 0x60
160 #define ICH6_REG_IR 0x64
161 #define ICH6_REG_IRS 0x68
162 #define ICH6_IRS_VALID (1<<1)
163 #define ICH6_IRS_BUSY (1<<0)
164
165 #define ICH6_REG_DPLBASE 0x70
166 #define ICH6_REG_DPUBASE 0x74
167 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
168
169 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
170 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
171
172 /* stream register offsets from stream base */
173 #define ICH6_REG_SD_CTL 0x00
174 #define ICH6_REG_SD_STS 0x03
175 #define ICH6_REG_SD_LPIB 0x04
176 #define ICH6_REG_SD_CBL 0x08
177 #define ICH6_REG_SD_LVI 0x0c
178 #define ICH6_REG_SD_FIFOW 0x0e
179 #define ICH6_REG_SD_FIFOSIZE 0x10
180 #define ICH6_REG_SD_FORMAT 0x12
181 #define ICH6_REG_SD_BDLPL 0x18
182 #define ICH6_REG_SD_BDLPU 0x1c
183
184 /* PCI space */
185 #define ICH6_PCIREG_TCSEL 0x44
186
187 /*
188 * other constants
189 */
190
191 /* max number of SDs */
192 /* ICH, ATI and VIA have 4 playback and 4 capture */
193 #define ICH6_NUM_CAPTURE 4
194 #define ICH6_NUM_PLAYBACK 4
195
196 /* ULI has 6 playback and 5 capture */
197 #define ULI_NUM_CAPTURE 5
198 #define ULI_NUM_PLAYBACK 6
199
200 /* ATI HDMI has 1 playback and 0 capture */
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_NUM_PLAYBACK 1
203
204 /* TERA has 4 playback and 3 capture */
205 #define TERA_NUM_CAPTURE 3
206 #define TERA_NUM_PLAYBACK 4
207
208 /* this number is statically defined for simplicity */
209 #define MAX_AZX_DEV 16
210
211 /* max number of fragments - we may use more if allocating more pages for BDL */
212 #define BDL_SIZE 4096
213 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
214 #define AZX_MAX_FRAG 32
215 /* max buffer size - no h/w limit, you can increase as you like */
216 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
217 /* max number of PCM devics per card */
218 #define AZX_MAX_PCMS 8
219
220 /* RIRB int mask: overrun[2], response[0] */
221 #define RIRB_INT_RESPONSE 0x01
222 #define RIRB_INT_OVERRUN 0x04
223 #define RIRB_INT_MASK 0x05
224
225 /* STATESTS int mask: S3,SD2,SD1,SD0 */
226 #define AZX_MAX_CODECS 4
227 #define STATESTS_INT_MASK 0x0f
228
229 /* SD_CTL bits */
230 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
231 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
232 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
233 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
234 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
235 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
236 #define SD_CTL_STREAM_TAG_SHIFT 20
237
238 /* SD_CTL and SD_STS */
239 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
240 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
241 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
242 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
243 SD_INT_COMPLETE)
244
245 /* SD_STS */
246 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
247
248 /* INTCTL and INTSTS */
249 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
250 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
251 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
252
253 /* GCTL unsolicited response enable bit */
254 #define ICH6_GCTL_UREN (1<<8)
255
256 /* GCTL reset bit */
257 #define ICH6_GCTL_RESET (1<<0)
258
259 /* CORB/RIRB control, read/write pointer */
260 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
261 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
262 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
263 /* below are so far hardcoded - should read registers in future */
264 #define ICH6_MAX_CORB_ENTRIES 256
265 #define ICH6_MAX_RIRB_ENTRIES 256
266
267 /* position fix mode */
268 enum {
269 POS_FIX_AUTO,
270 POS_FIX_LPIB,
271 POS_FIX_POSBUF,
272 };
273
274 /* Defines for ATI HD Audio support in SB450 south bridge */
275 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
276 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
277
278 /* Defines for Nvidia HDA support */
279 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
280 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
281 #define NVIDIA_HDA_ISTRM_COH 0x4d
282 #define NVIDIA_HDA_OSTRM_COH 0x4c
283 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
284
285 /* Defines for Intel SCH HDA snoop control */
286 #define INTEL_SCH_HDA_DEVC 0x78
287 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
288
289 /* Define IN stream 0 FIFO size offset in VIA controller */
290 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
291 /* Define VIA HD Audio Device ID*/
292 #define VIA_HDAC_DEVICE_ID 0x3288
293
294
295 /*
296 */
297
298 struct azx_dev {
299 struct snd_dma_buffer bdl; /* BDL buffer */
300 u32 *posbuf; /* position buffer pointer */
301
302 unsigned int bufsize; /* size of the play buffer in bytes */
303 unsigned int period_bytes; /* size of the period in bytes */
304 unsigned int frags; /* number for period in the play buffer */
305 unsigned int fifo_size; /* FIFO size */
306
307 void __iomem *sd_addr; /* stream descriptor pointer */
308
309 u32 sd_int_sta_mask; /* stream int status mask */
310
311 /* pcm support */
312 struct snd_pcm_substream *substream; /* assigned substream,
313 * set in PCM open
314 */
315 unsigned int format_val; /* format value to be set in the
316 * controller and the codec
317 */
318 unsigned char stream_tag; /* assigned stream */
319 unsigned char index; /* stream index */
320
321 unsigned int opened :1;
322 unsigned int running :1;
323 unsigned int irq_pending :1;
324 unsigned int irq_ignore :1;
325 /*
326 * For VIA:
327 * A flag to ensure DMA position is 0
328 * when link position is not greater than FIFO size
329 */
330 unsigned int insufficient :1;
331 };
332
333 /* CORB/RIRB */
334 struct azx_rb {
335 u32 *buf; /* CORB/RIRB buffer
336 * Each CORB entry is 4byte, RIRB is 8byte
337 */
338 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
339 /* for RIRB */
340 unsigned short rp, wp; /* read/write pointers */
341 int cmds; /* number of pending requests */
342 u32 res; /* last read value */
343 };
344
345 struct azx {
346 struct snd_card *card;
347 struct pci_dev *pci;
348 int dev_index;
349
350 /* chip type specific */
351 int driver_type;
352 int playback_streams;
353 int playback_index_offset;
354 int capture_streams;
355 int capture_index_offset;
356 int num_streams;
357
358 /* pci resources */
359 unsigned long addr;
360 void __iomem *remap_addr;
361 int irq;
362
363 /* locks */
364 spinlock_t reg_lock;
365 struct mutex open_mutex;
366
367 /* streams (x num_streams) */
368 struct azx_dev *azx_dev;
369
370 /* PCM */
371 struct snd_pcm *pcm[AZX_MAX_PCMS];
372
373 /* HD codec */
374 unsigned short codec_mask;
375 struct hda_bus *bus;
376
377 /* CORB/RIRB */
378 struct azx_rb corb;
379 struct azx_rb rirb;
380
381 /* CORB/RIRB and position buffers */
382 struct snd_dma_buffer rb;
383 struct snd_dma_buffer posbuf;
384
385 /* flags */
386 int position_fix;
387 unsigned int running :1;
388 unsigned int initialized :1;
389 unsigned int single_cmd :1;
390 unsigned int polling_mode :1;
391 unsigned int msi :1;
392 unsigned int irq_pending_warned :1;
393 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
394
395 /* for debugging */
396 unsigned int last_cmd; /* last issued command (to sync) */
397
398 /* for pending irqs */
399 struct work_struct irq_pending_work;
400 };
401
402 /* driver types */
403 enum {
404 AZX_DRIVER_ICH,
405 AZX_DRIVER_SCH,
406 AZX_DRIVER_ATI,
407 AZX_DRIVER_ATIHDMI,
408 AZX_DRIVER_VIA,
409 AZX_DRIVER_SIS,
410 AZX_DRIVER_ULI,
411 AZX_DRIVER_NVIDIA,
412 AZX_DRIVER_TERA,
413 AZX_NUM_DRIVERS, /* keep this as last entry */
414 };
415
416 static char *driver_short_names[] __devinitdata = {
417 [AZX_DRIVER_ICH] = "HDA Intel",
418 [AZX_DRIVER_SCH] = "HDA Intel MID",
419 [AZX_DRIVER_ATI] = "HDA ATI SB",
420 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
421 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
422 [AZX_DRIVER_SIS] = "HDA SIS966",
423 [AZX_DRIVER_ULI] = "HDA ULI M5461",
424 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
425 [AZX_DRIVER_TERA] = "HDA Teradici",
426 };
427
428 /*
429 * macros for easy use
430 */
431 #define azx_writel(chip,reg,value) \
432 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
433 #define azx_readl(chip,reg) \
434 readl((chip)->remap_addr + ICH6_REG_##reg)
435 #define azx_writew(chip,reg,value) \
436 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
437 #define azx_readw(chip,reg) \
438 readw((chip)->remap_addr + ICH6_REG_##reg)
439 #define azx_writeb(chip,reg,value) \
440 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
441 #define azx_readb(chip,reg) \
442 readb((chip)->remap_addr + ICH6_REG_##reg)
443
444 #define azx_sd_writel(dev,reg,value) \
445 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
446 #define azx_sd_readl(dev,reg) \
447 readl((dev)->sd_addr + ICH6_REG_##reg)
448 #define azx_sd_writew(dev,reg,value) \
449 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
450 #define azx_sd_readw(dev,reg) \
451 readw((dev)->sd_addr + ICH6_REG_##reg)
452 #define azx_sd_writeb(dev,reg,value) \
453 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
454 #define azx_sd_readb(dev,reg) \
455 readb((dev)->sd_addr + ICH6_REG_##reg)
456
457 /* for pcm support */
458 #define get_azx_dev(substream) (substream->runtime->private_data)
459
460 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
461
462 /*
463 * Interface for HD codec
464 */
465
466 /*
467 * CORB / RIRB interface
468 */
469 static int azx_alloc_cmd_io(struct azx *chip)
470 {
471 int err;
472
473 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
474 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
475 snd_dma_pci_data(chip->pci),
476 PAGE_SIZE, &chip->rb);
477 if (err < 0) {
478 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
479 return err;
480 }
481 return 0;
482 }
483
484 static void azx_init_cmd_io(struct azx *chip)
485 {
486 /* CORB set up */
487 chip->corb.addr = chip->rb.addr;
488 chip->corb.buf = (u32 *)chip->rb.area;
489 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
490 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
491
492 /* set the corb size to 256 entries (ULI requires explicitly) */
493 azx_writeb(chip, CORBSIZE, 0x02);
494 /* set the corb write pointer to 0 */
495 azx_writew(chip, CORBWP, 0);
496 /* reset the corb hw read pointer */
497 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
498 /* enable corb dma */
499 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
500
501 /* RIRB set up */
502 chip->rirb.addr = chip->rb.addr + 2048;
503 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
504 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
505 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
506
507 /* set the rirb size to 256 entries (ULI requires explicitly) */
508 azx_writeb(chip, RIRBSIZE, 0x02);
509 /* reset the rirb hw write pointer */
510 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
511 /* set N=1, get RIRB response interrupt for new entry */
512 azx_writew(chip, RINTCNT, 1);
513 /* enable rirb dma and response irq */
514 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
515 chip->rirb.rp = chip->rirb.cmds = 0;
516 }
517
518 static void azx_free_cmd_io(struct azx *chip)
519 {
520 /* disable ringbuffer DMAs */
521 azx_writeb(chip, RIRBCTL, 0);
522 azx_writeb(chip, CORBCTL, 0);
523 }
524
525 /* send a command */
526 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
527 {
528 struct azx *chip = codec->bus->private_data;
529 unsigned int wp;
530
531 /* add command to corb */
532 wp = azx_readb(chip, CORBWP);
533 wp++;
534 wp %= ICH6_MAX_CORB_ENTRIES;
535
536 spin_lock_irq(&chip->reg_lock);
537 chip->rirb.cmds++;
538 chip->corb.buf[wp] = cpu_to_le32(val);
539 azx_writel(chip, CORBWP, wp);
540 spin_unlock_irq(&chip->reg_lock);
541
542 return 0;
543 }
544
545 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
546
547 /* retrieve RIRB entry - called from interrupt handler */
548 static void azx_update_rirb(struct azx *chip)
549 {
550 unsigned int rp, wp;
551 u32 res, res_ex;
552
553 wp = azx_readb(chip, RIRBWP);
554 if (wp == chip->rirb.wp)
555 return;
556 chip->rirb.wp = wp;
557
558 while (chip->rirb.rp != wp) {
559 chip->rirb.rp++;
560 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
561
562 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
563 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
564 res = le32_to_cpu(chip->rirb.buf[rp]);
565 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
566 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
567 else if (chip->rirb.cmds) {
568 chip->rirb.res = res;
569 smp_wmb();
570 chip->rirb.cmds--;
571 }
572 }
573 }
574
575 /* receive a response */
576 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
577 {
578 struct azx *chip = codec->bus->private_data;
579 unsigned long timeout;
580
581 again:
582 timeout = jiffies + msecs_to_jiffies(1000);
583 for (;;) {
584 if (chip->polling_mode) {
585 spin_lock_irq(&chip->reg_lock);
586 azx_update_rirb(chip);
587 spin_unlock_irq(&chip->reg_lock);
588 }
589 if (!chip->rirb.cmds) {
590 smp_rmb();
591 return chip->rirb.res; /* the last value */
592 }
593 if (time_after(jiffies, timeout))
594 break;
595 if (codec->bus->needs_damn_long_delay)
596 msleep(2); /* temporary workaround */
597 else {
598 udelay(10);
599 cond_resched();
600 }
601 }
602
603 if (chip->msi) {
604 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
605 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
606 free_irq(chip->irq, chip);
607 chip->irq = -1;
608 pci_disable_msi(chip->pci);
609 chip->msi = 0;
610 if (azx_acquire_irq(chip, 1) < 0)
611 return -1;
612 goto again;
613 }
614
615 if (!chip->polling_mode) {
616 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
617 "switching to polling mode: last cmd=0x%08x\n",
618 chip->last_cmd);
619 chip->polling_mode = 1;
620 goto again;
621 }
622
623 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
624 "switching to single_cmd mode: last cmd=0x%08x\n",
625 chip->last_cmd);
626 chip->rirb.rp = azx_readb(chip, RIRBWP);
627 chip->rirb.cmds = 0;
628 /* switch to single_cmd mode */
629 chip->single_cmd = 1;
630 azx_free_cmd_io(chip);
631 return -1;
632 }
633
634 /*
635 * Use the single immediate command instead of CORB/RIRB for simplicity
636 *
637 * Note: according to Intel, this is not preferred use. The command was
638 * intended for the BIOS only, and may get confused with unsolicited
639 * responses. So, we shouldn't use it for normal operation from the
640 * driver.
641 * I left the codes, however, for debugging/testing purposes.
642 */
643
644 /* send a command */
645 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
646 {
647 struct azx *chip = codec->bus->private_data;
648 int timeout = 50;
649
650 while (timeout--) {
651 /* check ICB busy bit */
652 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
653 /* Clear IRV valid bit */
654 azx_writew(chip, IRS, azx_readw(chip, IRS) |
655 ICH6_IRS_VALID);
656 azx_writel(chip, IC, val);
657 azx_writew(chip, IRS, azx_readw(chip, IRS) |
658 ICH6_IRS_BUSY);
659 return 0;
660 }
661 udelay(1);
662 }
663 if (printk_ratelimit())
664 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
665 azx_readw(chip, IRS), val);
666 return -EIO;
667 }
668
669 /* receive a response */
670 static unsigned int azx_single_get_response(struct hda_codec *codec)
671 {
672 struct azx *chip = codec->bus->private_data;
673 int timeout = 50;
674
675 while (timeout--) {
676 /* check IRV busy bit */
677 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
678 return azx_readl(chip, IR);
679 udelay(1);
680 }
681 if (printk_ratelimit())
682 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
683 azx_readw(chip, IRS));
684 return (unsigned int)-1;
685 }
686
687 /*
688 * The below are the main callbacks from hda_codec.
689 *
690 * They are just the skeleton to call sub-callbacks according to the
691 * current setting of chip->single_cmd.
692 */
693
694 /* send a command */
695 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
696 int direct, unsigned int verb,
697 unsigned int para)
698 {
699 struct azx *chip = codec->bus->private_data;
700 u32 val;
701
702 val = (u32)(codec->addr & 0x0f) << 28;
703 val |= (u32)direct << 27;
704 val |= (u32)nid << 20;
705 val |= verb << 8;
706 val |= para;
707 chip->last_cmd = val;
708
709 if (chip->single_cmd)
710 return azx_single_send_cmd(codec, val);
711 else
712 return azx_corb_send_cmd(codec, val);
713 }
714
715 /* get a response */
716 static unsigned int azx_get_response(struct hda_codec *codec)
717 {
718 struct azx *chip = codec->bus->private_data;
719 if (chip->single_cmd)
720 return azx_single_get_response(codec);
721 else
722 return azx_rirb_get_response(codec);
723 }
724
725 #ifdef CONFIG_SND_HDA_POWER_SAVE
726 static void azx_power_notify(struct hda_codec *codec);
727 #endif
728
729 /* reset codec link */
730 static int azx_reset(struct azx *chip)
731 {
732 int count;
733
734 /* clear STATESTS */
735 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
736
737 /* reset controller */
738 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
739
740 count = 50;
741 while (azx_readb(chip, GCTL) && --count)
742 msleep(1);
743
744 /* delay for >= 100us for codec PLL to settle per spec
745 * Rev 0.9 section 5.5.1
746 */
747 msleep(1);
748
749 /* Bring controller out of reset */
750 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
751
752 count = 50;
753 while (!azx_readb(chip, GCTL) && --count)
754 msleep(1);
755
756 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
757 msleep(1);
758
759 /* check to see if controller is ready */
760 if (!azx_readb(chip, GCTL)) {
761 snd_printd("azx_reset: controller not ready!\n");
762 return -EBUSY;
763 }
764
765 /* Accept unsolicited responses */
766 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
767
768 /* detect codecs */
769 if (!chip->codec_mask) {
770 chip->codec_mask = azx_readw(chip, STATESTS);
771 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
772 }
773
774 return 0;
775 }
776
777
778 /*
779 * Lowlevel interface
780 */
781
782 /* enable interrupts */
783 static void azx_int_enable(struct azx *chip)
784 {
785 /* enable controller CIE and GIE */
786 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
787 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
788 }
789
790 /* disable interrupts */
791 static void azx_int_disable(struct azx *chip)
792 {
793 int i;
794
795 /* disable interrupts in stream descriptor */
796 for (i = 0; i < chip->num_streams; i++) {
797 struct azx_dev *azx_dev = &chip->azx_dev[i];
798 azx_sd_writeb(azx_dev, SD_CTL,
799 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
800 }
801
802 /* disable SIE for all streams */
803 azx_writeb(chip, INTCTL, 0);
804
805 /* disable controller CIE and GIE */
806 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
807 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
808 }
809
810 /* clear interrupts */
811 static void azx_int_clear(struct azx *chip)
812 {
813 int i;
814
815 /* clear stream status */
816 for (i = 0; i < chip->num_streams; i++) {
817 struct azx_dev *azx_dev = &chip->azx_dev[i];
818 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
819 }
820
821 /* clear STATESTS */
822 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
823
824 /* clear rirb status */
825 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
826
827 /* clear int status */
828 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
829 }
830
831 /* start a stream */
832 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
833 {
834 /*
835 * Before stream start, initialize parameter
836 */
837 azx_dev->insufficient = 1;
838
839 /* enable SIE */
840 azx_writeb(chip, INTCTL,
841 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
842 /* set DMA start and interrupt mask */
843 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
844 SD_CTL_DMA_START | SD_INT_MASK);
845 }
846
847 /* stop a stream */
848 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
849 {
850 /* stop DMA */
851 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
852 ~(SD_CTL_DMA_START | SD_INT_MASK));
853 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
854 /* disable SIE */
855 azx_writeb(chip, INTCTL,
856 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
857 }
858
859
860 /*
861 * reset and start the controller registers
862 */
863 static void azx_init_chip(struct azx *chip)
864 {
865 if (chip->initialized)
866 return;
867
868 /* reset controller */
869 azx_reset(chip);
870
871 /* initialize interrupts */
872 azx_int_clear(chip);
873 azx_int_enable(chip);
874
875 /* initialize the codec command I/O */
876 if (!chip->single_cmd)
877 azx_init_cmd_io(chip);
878
879 /* program the position buffer */
880 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
881 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
882
883 chip->initialized = 1;
884 }
885
886 /*
887 * initialize the PCI registers
888 */
889 /* update bits in a PCI register byte */
890 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
891 unsigned char mask, unsigned char val)
892 {
893 unsigned char data;
894
895 pci_read_config_byte(pci, reg, &data);
896 data &= ~mask;
897 data |= (val & mask);
898 pci_write_config_byte(pci, reg, data);
899 }
900
901 static void azx_init_pci(struct azx *chip)
902 {
903 unsigned short snoop;
904
905 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
906 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
907 * Ensuring these bits are 0 clears playback static on some HD Audio
908 * codecs
909 */
910 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
911
912 switch (chip->driver_type) {
913 case AZX_DRIVER_ATI:
914 /* For ATI SB450 azalia HD audio, we need to enable snoop */
915 update_pci_byte(chip->pci,
916 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
917 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
918 break;
919 case AZX_DRIVER_NVIDIA:
920 /* For NVIDIA HDA, enable snoop */
921 update_pci_byte(chip->pci,
922 NVIDIA_HDA_TRANSREG_ADDR,
923 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
924 update_pci_byte(chip->pci,
925 NVIDIA_HDA_ISTRM_COH,
926 0x01, NVIDIA_HDA_ENABLE_COHBIT);
927 update_pci_byte(chip->pci,
928 NVIDIA_HDA_OSTRM_COH,
929 0x01, NVIDIA_HDA_ENABLE_COHBIT);
930 break;
931 case AZX_DRIVER_SCH:
932 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
933 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
934 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
935 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
936 pci_read_config_word(chip->pci,
937 INTEL_SCH_HDA_DEVC, &snoop);
938 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
939 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
940 ? "Failed" : "OK");
941 }
942 break;
943
944 }
945 }
946
947
948 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
949
950 /*
951 * interrupt handler
952 */
953 static irqreturn_t azx_interrupt(int irq, void *dev_id)
954 {
955 struct azx *chip = dev_id;
956 struct azx_dev *azx_dev;
957 u32 status;
958 int i;
959
960 spin_lock(&chip->reg_lock);
961
962 status = azx_readl(chip, INTSTS);
963 if (status == 0) {
964 spin_unlock(&chip->reg_lock);
965 return IRQ_NONE;
966 }
967
968 for (i = 0; i < chip->num_streams; i++) {
969 azx_dev = &chip->azx_dev[i];
970 if (status & azx_dev->sd_int_sta_mask) {
971 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
972 if (!azx_dev->substream || !azx_dev->running)
973 continue;
974 /* ignore the first dummy IRQ (due to pos_adj) */
975 if (azx_dev->irq_ignore) {
976 azx_dev->irq_ignore = 0;
977 continue;
978 }
979 /* check whether this IRQ is really acceptable */
980 if (azx_position_ok(chip, azx_dev)) {
981 azx_dev->irq_pending = 0;
982 spin_unlock(&chip->reg_lock);
983 snd_pcm_period_elapsed(azx_dev->substream);
984 spin_lock(&chip->reg_lock);
985 } else {
986 /* bogus IRQ, process it later */
987 azx_dev->irq_pending = 1;
988 schedule_work(&chip->irq_pending_work);
989 }
990 }
991 }
992
993 /* clear rirb int */
994 status = azx_readb(chip, RIRBSTS);
995 if (status & RIRB_INT_MASK) {
996 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
997 azx_update_rirb(chip);
998 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
999 }
1000
1001 #if 0
1002 /* clear state status int */
1003 if (azx_readb(chip, STATESTS) & 0x04)
1004 azx_writeb(chip, STATESTS, 0x04);
1005 #endif
1006 spin_unlock(&chip->reg_lock);
1007
1008 return IRQ_HANDLED;
1009 }
1010
1011
1012 /*
1013 * set up a BDL entry
1014 */
1015 static int setup_bdle(struct snd_pcm_substream *substream,
1016 struct azx_dev *azx_dev, u32 **bdlp,
1017 int ofs, int size, int with_ioc)
1018 {
1019 u32 *bdl = *bdlp;
1020
1021 while (size > 0) {
1022 dma_addr_t addr;
1023 int chunk;
1024
1025 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1026 return -EINVAL;
1027
1028 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1029 /* program the address field of the BDL entry */
1030 bdl[0] = cpu_to_le32((u32)addr);
1031 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1032 /* program the size field of the BDL entry */
1033 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1034 bdl[2] = cpu_to_le32(chunk);
1035 /* program the IOC to enable interrupt
1036 * only when the whole fragment is processed
1037 */
1038 size -= chunk;
1039 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1040 bdl += 4;
1041 azx_dev->frags++;
1042 ofs += chunk;
1043 }
1044 *bdlp = bdl;
1045 return ofs;
1046 }
1047
1048 /*
1049 * set up BDL entries
1050 */
1051 static int azx_setup_periods(struct azx *chip,
1052 struct snd_pcm_substream *substream,
1053 struct azx_dev *azx_dev)
1054 {
1055 u32 *bdl;
1056 int i, ofs, periods, period_bytes;
1057 int pos_adj;
1058
1059 /* reset BDL address */
1060 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1061 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1062
1063 period_bytes = snd_pcm_lib_period_bytes(substream);
1064 azx_dev->period_bytes = period_bytes;
1065 periods = azx_dev->bufsize / period_bytes;
1066
1067 /* program the initial BDL entries */
1068 bdl = (u32 *)azx_dev->bdl.area;
1069 ofs = 0;
1070 azx_dev->frags = 0;
1071 azx_dev->irq_ignore = 0;
1072 pos_adj = bdl_pos_adj[chip->dev_index];
1073 if (pos_adj > 0) {
1074 struct snd_pcm_runtime *runtime = substream->runtime;
1075 int pos_align = pos_adj;
1076 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1077 if (!pos_adj)
1078 pos_adj = pos_align;
1079 else
1080 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1081 pos_align;
1082 pos_adj = frames_to_bytes(runtime, pos_adj);
1083 if (pos_adj >= period_bytes) {
1084 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1085 bdl_pos_adj[chip->dev_index]);
1086 pos_adj = 0;
1087 } else {
1088 ofs = setup_bdle(substream, azx_dev,
1089 &bdl, ofs, pos_adj, 1);
1090 if (ofs < 0)
1091 goto error;
1092 azx_dev->irq_ignore = 1;
1093 }
1094 } else
1095 pos_adj = 0;
1096 for (i = 0; i < periods; i++) {
1097 if (i == periods - 1 && pos_adj)
1098 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1099 period_bytes - pos_adj, 0);
1100 else
1101 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1102 period_bytes, 1);
1103 if (ofs < 0)
1104 goto error;
1105 }
1106 return 0;
1107
1108 error:
1109 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1110 azx_dev->bufsize, period_bytes);
1111 /* reset */
1112 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1113 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1114 return -EINVAL;
1115 }
1116
1117 /*
1118 * set up the SD for streaming
1119 */
1120 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1121 {
1122 unsigned char val;
1123 int timeout;
1124
1125 /* make sure the run bit is zero for SD */
1126 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1127 ~SD_CTL_DMA_START);
1128 /* reset stream */
1129 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1130 SD_CTL_STREAM_RESET);
1131 udelay(3);
1132 timeout = 300;
1133 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1134 --timeout)
1135 ;
1136 val &= ~SD_CTL_STREAM_RESET;
1137 azx_sd_writeb(azx_dev, SD_CTL, val);
1138 udelay(3);
1139
1140 timeout = 300;
1141 /* waiting for hardware to report that the stream is out of reset */
1142 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1143 --timeout)
1144 ;
1145
1146 /* program the stream_tag */
1147 azx_sd_writel(azx_dev, SD_CTL,
1148 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1149 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1150
1151 /* program the length of samples in cyclic buffer */
1152 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1153
1154 /* program the stream format */
1155 /* this value needs to be the same as the one programmed */
1156 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1157
1158 /* program the stream LVI (last valid index) of the BDL */
1159 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1160
1161 /* program the BDL address */
1162 /* lower BDL address */
1163 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1164 /* upper BDL address */
1165 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1166
1167 /* enable the position buffer */
1168 if (chip->position_fix == POS_FIX_POSBUF ||
1169 chip->position_fix == POS_FIX_AUTO ||
1170 chip->via_dmapos_patch) {
1171 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1172 azx_writel(chip, DPLBASE,
1173 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1174 }
1175
1176 /* set the interrupt enable bits in the descriptor control register */
1177 azx_sd_writel(azx_dev, SD_CTL,
1178 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1179
1180 return 0;
1181 }
1182
1183
1184 /*
1185 * Codec initialization
1186 */
1187
1188 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1189 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1190 [AZX_DRIVER_TERA] = 1,
1191 };
1192
1193 /* number of slots to probe as default
1194 * this can be different from azx_max_codecs[] -- e.g. some boards
1195 * report wrongly the non-existing 4th slot availability
1196 */
1197 static unsigned int azx_default_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1198 [AZX_DRIVER_ICH] = 3,
1199 [AZX_DRIVER_ATI] = 3,
1200 };
1201
1202 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1203 unsigned int codec_probe_mask)
1204 {
1205 struct hda_bus_template bus_temp;
1206 int c, codecs, audio_codecs, err;
1207 int def_slots, max_slots;
1208
1209 memset(&bus_temp, 0, sizeof(bus_temp));
1210 bus_temp.private_data = chip;
1211 bus_temp.modelname = model;
1212 bus_temp.pci = chip->pci;
1213 bus_temp.ops.command = azx_send_cmd;
1214 bus_temp.ops.get_response = azx_get_response;
1215 #ifdef CONFIG_SND_HDA_POWER_SAVE
1216 bus_temp.ops.pm_notify = azx_power_notify;
1217 #endif
1218
1219 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1220 if (err < 0)
1221 return err;
1222
1223 codecs = audio_codecs = 0;
1224 max_slots = azx_max_codecs[chip->driver_type];
1225 if (!max_slots)
1226 max_slots = AZX_MAX_CODECS;
1227 def_slots = azx_default_codecs[chip->driver_type];
1228 if (!def_slots)
1229 def_slots = max_slots;
1230 for (c = 0; c < def_slots; c++) {
1231 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1232 struct hda_codec *codec;
1233 err = snd_hda_codec_new(chip->bus, c, &codec);
1234 if (err < 0)
1235 continue;
1236 codecs++;
1237 if (codec->afg)
1238 audio_codecs++;
1239 }
1240 }
1241 if (!audio_codecs) {
1242 /* probe additional slots if no codec is found */
1243 for (; c < max_slots; c++) {
1244 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1245 err = snd_hda_codec_new(chip->bus, c, NULL);
1246 if (err < 0)
1247 continue;
1248 codecs++;
1249 }
1250 }
1251 }
1252 if (!codecs) {
1253 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1254 return -ENXIO;
1255 }
1256
1257 return 0;
1258 }
1259
1260
1261 /*
1262 * PCM support
1263 */
1264
1265 /* assign a stream for the PCM */
1266 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1267 {
1268 int dev, i, nums;
1269 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1270 dev = chip->playback_index_offset;
1271 nums = chip->playback_streams;
1272 } else {
1273 dev = chip->capture_index_offset;
1274 nums = chip->capture_streams;
1275 }
1276 for (i = 0; i < nums; i++, dev++)
1277 if (!chip->azx_dev[dev].opened) {
1278 chip->azx_dev[dev].opened = 1;
1279 return &chip->azx_dev[dev];
1280 }
1281 return NULL;
1282 }
1283
1284 /* release the assigned stream */
1285 static inline void azx_release_device(struct azx_dev *azx_dev)
1286 {
1287 azx_dev->opened = 0;
1288 }
1289
1290 static struct snd_pcm_hardware azx_pcm_hw = {
1291 .info = (SNDRV_PCM_INFO_MMAP |
1292 SNDRV_PCM_INFO_INTERLEAVED |
1293 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1294 SNDRV_PCM_INFO_MMAP_VALID |
1295 /* No full-resume yet implemented */
1296 /* SNDRV_PCM_INFO_RESUME |*/
1297 SNDRV_PCM_INFO_PAUSE |
1298 SNDRV_PCM_INFO_SYNC_START),
1299 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1300 .rates = SNDRV_PCM_RATE_48000,
1301 .rate_min = 48000,
1302 .rate_max = 48000,
1303 .channels_min = 2,
1304 .channels_max = 2,
1305 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1306 .period_bytes_min = 128,
1307 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1308 .periods_min = 2,
1309 .periods_max = AZX_MAX_FRAG,
1310 .fifo_size = 0,
1311 };
1312
1313 struct azx_pcm {
1314 struct azx *chip;
1315 struct hda_codec *codec;
1316 struct hda_pcm_stream *hinfo[2];
1317 };
1318
1319 static int azx_pcm_open(struct snd_pcm_substream *substream)
1320 {
1321 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1322 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1323 struct azx *chip = apcm->chip;
1324 struct azx_dev *azx_dev;
1325 struct snd_pcm_runtime *runtime = substream->runtime;
1326 unsigned long flags;
1327 int err;
1328
1329 mutex_lock(&chip->open_mutex);
1330 azx_dev = azx_assign_device(chip, substream->stream);
1331 if (azx_dev == NULL) {
1332 mutex_unlock(&chip->open_mutex);
1333 return -EBUSY;
1334 }
1335 runtime->hw = azx_pcm_hw;
1336 runtime->hw.channels_min = hinfo->channels_min;
1337 runtime->hw.channels_max = hinfo->channels_max;
1338 runtime->hw.formats = hinfo->formats;
1339 runtime->hw.rates = hinfo->rates;
1340 snd_pcm_limit_hw_rates(runtime);
1341 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1342 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1343 128);
1344 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1345 128);
1346 snd_hda_power_up(apcm->codec);
1347 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1348 if (err < 0) {
1349 azx_release_device(azx_dev);
1350 snd_hda_power_down(apcm->codec);
1351 mutex_unlock(&chip->open_mutex);
1352 return err;
1353 }
1354 spin_lock_irqsave(&chip->reg_lock, flags);
1355 azx_dev->substream = substream;
1356 azx_dev->running = 0;
1357 spin_unlock_irqrestore(&chip->reg_lock, flags);
1358
1359 runtime->private_data = azx_dev;
1360 snd_pcm_set_sync(substream);
1361 mutex_unlock(&chip->open_mutex);
1362 return 0;
1363 }
1364
1365 static int azx_pcm_close(struct snd_pcm_substream *substream)
1366 {
1367 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1368 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1369 struct azx *chip = apcm->chip;
1370 struct azx_dev *azx_dev = get_azx_dev(substream);
1371 unsigned long flags;
1372
1373 mutex_lock(&chip->open_mutex);
1374 spin_lock_irqsave(&chip->reg_lock, flags);
1375 azx_dev->substream = NULL;
1376 azx_dev->running = 0;
1377 spin_unlock_irqrestore(&chip->reg_lock, flags);
1378 azx_release_device(azx_dev);
1379 hinfo->ops.close(hinfo, apcm->codec, substream);
1380 snd_hda_power_down(apcm->codec);
1381 mutex_unlock(&chip->open_mutex);
1382 return 0;
1383 }
1384
1385 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1386 struct snd_pcm_hw_params *hw_params)
1387 {
1388 return snd_pcm_lib_malloc_pages(substream,
1389 params_buffer_bytes(hw_params));
1390 }
1391
1392 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1393 {
1394 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1395 struct azx_dev *azx_dev = get_azx_dev(substream);
1396 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1397
1398 /* reset BDL address */
1399 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1400 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1401 azx_sd_writel(azx_dev, SD_CTL, 0);
1402
1403 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1404
1405 return snd_pcm_lib_free_pages(substream);
1406 }
1407
1408 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1409 {
1410 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1411 struct azx *chip = apcm->chip;
1412 struct azx_dev *azx_dev = get_azx_dev(substream);
1413 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1414 struct snd_pcm_runtime *runtime = substream->runtime;
1415
1416 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1417 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1418 runtime->channels,
1419 runtime->format,
1420 hinfo->maxbps);
1421 if (!azx_dev->format_val) {
1422 snd_printk(KERN_ERR SFX
1423 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1424 runtime->rate, runtime->channels, runtime->format);
1425 return -EINVAL;
1426 }
1427
1428 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1429 azx_dev->bufsize, azx_dev->format_val);
1430 if (azx_setup_periods(chip, substream, azx_dev) < 0)
1431 return -EINVAL;
1432 azx_setup_controller(chip, azx_dev);
1433 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1434 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1435 else
1436 azx_dev->fifo_size = 0;
1437
1438 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1439 azx_dev->format_val, substream);
1440 }
1441
1442 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1443 {
1444 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1445 struct azx *chip = apcm->chip;
1446 struct azx_dev *azx_dev;
1447 struct snd_pcm_substream *s;
1448 int start, nsync = 0, sbits = 0;
1449 int nwait, timeout;
1450
1451 switch (cmd) {
1452 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1453 case SNDRV_PCM_TRIGGER_RESUME:
1454 case SNDRV_PCM_TRIGGER_START:
1455 start = 1;
1456 break;
1457 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1458 case SNDRV_PCM_TRIGGER_SUSPEND:
1459 case SNDRV_PCM_TRIGGER_STOP:
1460 start = 0;
1461 break;
1462 default:
1463 return -EINVAL;
1464 }
1465
1466 snd_pcm_group_for_each_entry(s, substream) {
1467 if (s->pcm->card != substream->pcm->card)
1468 continue;
1469 azx_dev = get_azx_dev(s);
1470 sbits |= 1 << azx_dev->index;
1471 nsync++;
1472 snd_pcm_trigger_done(s, substream);
1473 }
1474
1475 spin_lock(&chip->reg_lock);
1476 if (nsync > 1) {
1477 /* first, set SYNC bits of corresponding streams */
1478 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1479 }
1480 snd_pcm_group_for_each_entry(s, substream) {
1481 if (s->pcm->card != substream->pcm->card)
1482 continue;
1483 azx_dev = get_azx_dev(s);
1484 if (start)
1485 azx_stream_start(chip, azx_dev);
1486 else
1487 azx_stream_stop(chip, azx_dev);
1488 azx_dev->running = start;
1489 }
1490 spin_unlock(&chip->reg_lock);
1491 if (start) {
1492 if (nsync == 1)
1493 return 0;
1494 /* wait until all FIFOs get ready */
1495 for (timeout = 5000; timeout; timeout--) {
1496 nwait = 0;
1497 snd_pcm_group_for_each_entry(s, substream) {
1498 if (s->pcm->card != substream->pcm->card)
1499 continue;
1500 azx_dev = get_azx_dev(s);
1501 if (!(azx_sd_readb(azx_dev, SD_STS) &
1502 SD_STS_FIFO_READY))
1503 nwait++;
1504 }
1505 if (!nwait)
1506 break;
1507 cpu_relax();
1508 }
1509 } else {
1510 /* wait until all RUN bits are cleared */
1511 for (timeout = 5000; timeout; timeout--) {
1512 nwait = 0;
1513 snd_pcm_group_for_each_entry(s, substream) {
1514 if (s->pcm->card != substream->pcm->card)
1515 continue;
1516 azx_dev = get_azx_dev(s);
1517 if (azx_sd_readb(azx_dev, SD_CTL) &
1518 SD_CTL_DMA_START)
1519 nwait++;
1520 }
1521 if (!nwait)
1522 break;
1523 cpu_relax();
1524 }
1525 }
1526 if (nsync > 1) {
1527 spin_lock(&chip->reg_lock);
1528 /* reset SYNC bits */
1529 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1530 spin_unlock(&chip->reg_lock);
1531 }
1532 return 0;
1533 }
1534
1535 /* get the current DMA position with correction on VIA chips */
1536 static unsigned int azx_via_get_position(struct azx *chip,
1537 struct azx_dev *azx_dev)
1538 {
1539 unsigned int link_pos, mini_pos, bound_pos;
1540 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1541 unsigned int fifo_size;
1542
1543 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1544 if (azx_dev->index >= 4) {
1545 /* Playback, no problem using link position */
1546 return link_pos;
1547 }
1548
1549 /* Capture */
1550 /* For new chipset,
1551 * use mod to get the DMA position just like old chipset
1552 */
1553 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1554 mod_dma_pos %= azx_dev->period_bytes;
1555
1556 /* azx_dev->fifo_size can't get FIFO size of in stream.
1557 * Get from base address + offset.
1558 */
1559 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1560
1561 if (azx_dev->insufficient) {
1562 /* Link position never gather than FIFO size */
1563 if (link_pos <= fifo_size)
1564 return 0;
1565
1566 azx_dev->insufficient = 0;
1567 }
1568
1569 if (link_pos <= fifo_size)
1570 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1571 else
1572 mini_pos = link_pos - fifo_size;
1573
1574 /* Find nearest previous boudary */
1575 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1576 mod_link_pos = link_pos % azx_dev->period_bytes;
1577 if (mod_link_pos >= fifo_size)
1578 bound_pos = link_pos - mod_link_pos;
1579 else if (mod_dma_pos >= mod_mini_pos)
1580 bound_pos = mini_pos - mod_mini_pos;
1581 else {
1582 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1583 if (bound_pos >= azx_dev->bufsize)
1584 bound_pos = 0;
1585 }
1586
1587 /* Calculate real DMA position we want */
1588 return bound_pos + mod_dma_pos;
1589 }
1590
1591 static unsigned int azx_get_position(struct azx *chip,
1592 struct azx_dev *azx_dev)
1593 {
1594 unsigned int pos;
1595
1596 if (chip->via_dmapos_patch)
1597 pos = azx_via_get_position(chip, azx_dev);
1598 else if (chip->position_fix == POS_FIX_POSBUF ||
1599 chip->position_fix == POS_FIX_AUTO) {
1600 /* use the position buffer */
1601 pos = le32_to_cpu(*azx_dev->posbuf);
1602 } else {
1603 /* read LPIB */
1604 pos = azx_sd_readl(azx_dev, SD_LPIB);
1605 }
1606 if (pos >= azx_dev->bufsize)
1607 pos = 0;
1608 return pos;
1609 }
1610
1611 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1612 {
1613 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1614 struct azx *chip = apcm->chip;
1615 struct azx_dev *azx_dev = get_azx_dev(substream);
1616 return bytes_to_frames(substream->runtime,
1617 azx_get_position(chip, azx_dev));
1618 }
1619
1620 /*
1621 * Check whether the current DMA position is acceptable for updating
1622 * periods. Returns non-zero if it's OK.
1623 *
1624 * Many HD-audio controllers appear pretty inaccurate about
1625 * the update-IRQ timing. The IRQ is issued before actually the
1626 * data is processed. So, we need to process it afterwords in a
1627 * workqueue.
1628 */
1629 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1630 {
1631 unsigned int pos;
1632
1633 pos = azx_get_position(chip, azx_dev);
1634 if (chip->position_fix == POS_FIX_AUTO) {
1635 if (!pos) {
1636 printk(KERN_WARNING
1637 "hda-intel: Invalid position buffer, "
1638 "using LPIB read method instead.\n");
1639 chip->position_fix = POS_FIX_LPIB;
1640 pos = azx_get_position(chip, azx_dev);
1641 } else
1642 chip->position_fix = POS_FIX_POSBUF;
1643 }
1644
1645 if (!bdl_pos_adj[chip->dev_index])
1646 return 1; /* no delayed ack */
1647 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1648 return 0; /* NG - it's below the period boundary */
1649 return 1; /* OK, it's fine */
1650 }
1651
1652 /*
1653 * The work for pending PCM period updates.
1654 */
1655 static void azx_irq_pending_work(struct work_struct *work)
1656 {
1657 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1658 int i, pending;
1659
1660 if (!chip->irq_pending_warned) {
1661 printk(KERN_WARNING
1662 "hda-intel: IRQ timing workaround is activated "
1663 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1664 chip->card->number);
1665 chip->irq_pending_warned = 1;
1666 }
1667
1668 for (;;) {
1669 pending = 0;
1670 spin_lock_irq(&chip->reg_lock);
1671 for (i = 0; i < chip->num_streams; i++) {
1672 struct azx_dev *azx_dev = &chip->azx_dev[i];
1673 if (!azx_dev->irq_pending ||
1674 !azx_dev->substream ||
1675 !azx_dev->running)
1676 continue;
1677 if (azx_position_ok(chip, azx_dev)) {
1678 azx_dev->irq_pending = 0;
1679 spin_unlock(&chip->reg_lock);
1680 snd_pcm_period_elapsed(azx_dev->substream);
1681 spin_lock(&chip->reg_lock);
1682 } else
1683 pending++;
1684 }
1685 spin_unlock_irq(&chip->reg_lock);
1686 if (!pending)
1687 return;
1688 cond_resched();
1689 }
1690 }
1691
1692 /* clear irq_pending flags and assure no on-going workq */
1693 static void azx_clear_irq_pending(struct azx *chip)
1694 {
1695 int i;
1696
1697 spin_lock_irq(&chip->reg_lock);
1698 for (i = 0; i < chip->num_streams; i++)
1699 chip->azx_dev[i].irq_pending = 0;
1700 spin_unlock_irq(&chip->reg_lock);
1701 flush_scheduled_work();
1702 }
1703
1704 static struct snd_pcm_ops azx_pcm_ops = {
1705 .open = azx_pcm_open,
1706 .close = azx_pcm_close,
1707 .ioctl = snd_pcm_lib_ioctl,
1708 .hw_params = azx_pcm_hw_params,
1709 .hw_free = azx_pcm_hw_free,
1710 .prepare = azx_pcm_prepare,
1711 .trigger = azx_pcm_trigger,
1712 .pointer = azx_pcm_pointer,
1713 .page = snd_pcm_sgbuf_ops_page,
1714 };
1715
1716 static void azx_pcm_free(struct snd_pcm *pcm)
1717 {
1718 kfree(pcm->private_data);
1719 }
1720
1721 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1722 struct hda_pcm *cpcm)
1723 {
1724 int err;
1725 struct snd_pcm *pcm;
1726 struct azx_pcm *apcm;
1727
1728 /* if no substreams are defined for both playback and capture,
1729 * it's just a placeholder. ignore it.
1730 */
1731 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1732 return 0;
1733
1734 if (snd_BUG_ON(!cpcm->name))
1735 return -EINVAL;
1736
1737 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1738 cpcm->stream[0].substreams,
1739 cpcm->stream[1].substreams,
1740 &pcm);
1741 if (err < 0)
1742 return err;
1743 strcpy(pcm->name, cpcm->name);
1744 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1745 if (apcm == NULL)
1746 return -ENOMEM;
1747 apcm->chip = chip;
1748 apcm->codec = codec;
1749 apcm->hinfo[0] = &cpcm->stream[0];
1750 apcm->hinfo[1] = &cpcm->stream[1];
1751 pcm->private_data = apcm;
1752 pcm->private_free = azx_pcm_free;
1753 if (cpcm->stream[0].substreams)
1754 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1755 if (cpcm->stream[1].substreams)
1756 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1757 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1758 snd_dma_pci_data(chip->pci),
1759 1024 * 64, 32 * 1024 * 1024);
1760 chip->pcm[cpcm->device] = pcm;
1761 return 0;
1762 }
1763
1764 static int __devinit azx_pcm_create(struct azx *chip)
1765 {
1766 static const char *dev_name[HDA_PCM_NTYPES] = {
1767 "Audio", "SPDIF", "HDMI", "Modem"
1768 };
1769 /* starting device index for each PCM type */
1770 static int dev_idx[HDA_PCM_NTYPES] = {
1771 [HDA_PCM_TYPE_AUDIO] = 0,
1772 [HDA_PCM_TYPE_SPDIF] = 1,
1773 [HDA_PCM_TYPE_HDMI] = 3,
1774 [HDA_PCM_TYPE_MODEM] = 6
1775 };
1776 /* normal audio device indices; not linear to keep compatibility */
1777 static int audio_idx[4] = { 0, 2, 4, 5 };
1778 struct hda_codec *codec;
1779 int c, err;
1780 int num_devs[HDA_PCM_NTYPES];
1781
1782 err = snd_hda_build_pcms(chip->bus);
1783 if (err < 0)
1784 return err;
1785
1786 /* create audio PCMs */
1787 memset(num_devs, 0, sizeof(num_devs));
1788 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1789 for (c = 0; c < codec->num_pcms; c++) {
1790 struct hda_pcm *cpcm = &codec->pcm_info[c];
1791 int type = cpcm->pcm_type;
1792 switch (type) {
1793 case HDA_PCM_TYPE_AUDIO:
1794 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1795 snd_printk(KERN_WARNING
1796 "Too many audio devices\n");
1797 continue;
1798 }
1799 cpcm->device = audio_idx[num_devs[type]];
1800 break;
1801 case HDA_PCM_TYPE_SPDIF:
1802 case HDA_PCM_TYPE_HDMI:
1803 case HDA_PCM_TYPE_MODEM:
1804 if (num_devs[type]) {
1805 snd_printk(KERN_WARNING
1806 "%s already defined\n",
1807 dev_name[type]);
1808 continue;
1809 }
1810 cpcm->device = dev_idx[type];
1811 break;
1812 default:
1813 snd_printk(KERN_WARNING
1814 "Invalid PCM type %d\n", type);
1815 continue;
1816 }
1817 num_devs[type]++;
1818 err = create_codec_pcm(chip, codec, cpcm);
1819 if (err < 0)
1820 return err;
1821 }
1822 }
1823 return 0;
1824 }
1825
1826 /*
1827 * mixer creation - all stuff is implemented in hda module
1828 */
1829 static int __devinit azx_mixer_create(struct azx *chip)
1830 {
1831 return snd_hda_build_controls(chip->bus);
1832 }
1833
1834
1835 /*
1836 * initialize SD streams
1837 */
1838 static int __devinit azx_init_stream(struct azx *chip)
1839 {
1840 int i;
1841
1842 /* initialize each stream (aka device)
1843 * assign the starting bdl address to each stream (device)
1844 * and initialize
1845 */
1846 for (i = 0; i < chip->num_streams; i++) {
1847 struct azx_dev *azx_dev = &chip->azx_dev[i];
1848 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1849 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1850 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1851 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1852 azx_dev->sd_int_sta_mask = 1 << i;
1853 /* stream tag: must be non-zero and unique */
1854 azx_dev->index = i;
1855 azx_dev->stream_tag = i + 1;
1856 }
1857
1858 return 0;
1859 }
1860
1861 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1862 {
1863 if (request_irq(chip->pci->irq, azx_interrupt,
1864 chip->msi ? 0 : IRQF_SHARED,
1865 "HDA Intel", chip)) {
1866 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1867 "disabling device\n", chip->pci->irq);
1868 if (do_disconnect)
1869 snd_card_disconnect(chip->card);
1870 return -1;
1871 }
1872 chip->irq = chip->pci->irq;
1873 pci_intx(chip->pci, !chip->msi);
1874 return 0;
1875 }
1876
1877
1878 static void azx_stop_chip(struct azx *chip)
1879 {
1880 if (!chip->initialized)
1881 return;
1882
1883 /* disable interrupts */
1884 azx_int_disable(chip);
1885 azx_int_clear(chip);
1886
1887 /* disable CORB/RIRB */
1888 azx_free_cmd_io(chip);
1889
1890 /* disable position buffer */
1891 azx_writel(chip, DPLBASE, 0);
1892 azx_writel(chip, DPUBASE, 0);
1893
1894 chip->initialized = 0;
1895 }
1896
1897 #ifdef CONFIG_SND_HDA_POWER_SAVE
1898 /* power-up/down the controller */
1899 static void azx_power_notify(struct hda_codec *codec)
1900 {
1901 struct azx *chip = codec->bus->private_data;
1902 struct hda_codec *c;
1903 int power_on = 0;
1904
1905 list_for_each_entry(c, &codec->bus->codec_list, list) {
1906 if (c->power_on) {
1907 power_on = 1;
1908 break;
1909 }
1910 }
1911 if (power_on)
1912 azx_init_chip(chip);
1913 else if (chip->running && power_save_controller)
1914 azx_stop_chip(chip);
1915 }
1916 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1917
1918 #ifdef CONFIG_PM
1919 /*
1920 * power management
1921 */
1922 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1923 {
1924 struct snd_card *card = pci_get_drvdata(pci);
1925 struct azx *chip = card->private_data;
1926 int i;
1927
1928 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1929 azx_clear_irq_pending(chip);
1930 for (i = 0; i < AZX_MAX_PCMS; i++)
1931 snd_pcm_suspend_all(chip->pcm[i]);
1932 if (chip->initialized)
1933 snd_hda_suspend(chip->bus, state);
1934 azx_stop_chip(chip);
1935 if (chip->irq >= 0) {
1936 free_irq(chip->irq, chip);
1937 chip->irq = -1;
1938 }
1939 if (chip->msi)
1940 pci_disable_msi(chip->pci);
1941 pci_disable_device(pci);
1942 pci_save_state(pci);
1943 pci_set_power_state(pci, pci_choose_state(pci, state));
1944 return 0;
1945 }
1946
1947 static int azx_resume(struct pci_dev *pci)
1948 {
1949 struct snd_card *card = pci_get_drvdata(pci);
1950 struct azx *chip = card->private_data;
1951
1952 pci_set_power_state(pci, PCI_D0);
1953 pci_restore_state(pci);
1954 if (pci_enable_device(pci) < 0) {
1955 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1956 "disabling device\n");
1957 snd_card_disconnect(card);
1958 return -EIO;
1959 }
1960 pci_set_master(pci);
1961 if (chip->msi)
1962 if (pci_enable_msi(pci) < 0)
1963 chip->msi = 0;
1964 if (azx_acquire_irq(chip, 1) < 0)
1965 return -EIO;
1966 azx_init_pci(chip);
1967
1968 if (snd_hda_codecs_inuse(chip->bus))
1969 azx_init_chip(chip);
1970
1971 snd_hda_resume(chip->bus);
1972 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1973 return 0;
1974 }
1975 #endif /* CONFIG_PM */
1976
1977
1978 /*
1979 * destructor
1980 */
1981 static int azx_free(struct azx *chip)
1982 {
1983 int i;
1984
1985 if (chip->initialized) {
1986 azx_clear_irq_pending(chip);
1987 for (i = 0; i < chip->num_streams; i++)
1988 azx_stream_stop(chip, &chip->azx_dev[i]);
1989 azx_stop_chip(chip);
1990 }
1991
1992 if (chip->irq >= 0)
1993 free_irq(chip->irq, (void*)chip);
1994 if (chip->msi)
1995 pci_disable_msi(chip->pci);
1996 if (chip->remap_addr)
1997 iounmap(chip->remap_addr);
1998
1999 if (chip->azx_dev) {
2000 for (i = 0; i < chip->num_streams; i++)
2001 if (chip->azx_dev[i].bdl.area)
2002 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2003 }
2004 if (chip->rb.area)
2005 snd_dma_free_pages(&chip->rb);
2006 if (chip->posbuf.area)
2007 snd_dma_free_pages(&chip->posbuf);
2008 pci_release_regions(chip->pci);
2009 pci_disable_device(chip->pci);
2010 kfree(chip->azx_dev);
2011 kfree(chip);
2012
2013 return 0;
2014 }
2015
2016 static int azx_dev_free(struct snd_device *device)
2017 {
2018 return azx_free(device->device_data);
2019 }
2020
2021 /*
2022 * white/black-listing for position_fix
2023 */
2024 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2025 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2026 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2027 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2028 {}
2029 };
2030
2031 static int __devinit check_position_fix(struct azx *chip, int fix)
2032 {
2033 const struct snd_pci_quirk *q;
2034
2035 /* Check VIA HD Audio Controller exist */
2036 if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2037 chip->pci->device == VIA_HDAC_DEVICE_ID) {
2038 chip->via_dmapos_patch = 1;
2039 /* Use link position directly, avoid any transfer problem. */
2040 return POS_FIX_LPIB;
2041 }
2042 chip->via_dmapos_patch = 0;
2043
2044 if (fix == POS_FIX_AUTO) {
2045 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2046 if (q) {
2047 printk(KERN_INFO
2048 "hda_intel: position_fix set to %d "
2049 "for device %04x:%04x\n",
2050 q->value, q->subvendor, q->subdevice);
2051 return q->value;
2052 }
2053 }
2054 return fix;
2055 }
2056
2057 /*
2058 * black-lists for probe_mask
2059 */
2060 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2061 /* Thinkpad often breaks the controller communication when accessing
2062 * to the non-working (or non-existing) modem codec slot.
2063 */
2064 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2065 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2066 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2067 {}
2068 };
2069
2070 static void __devinit check_probe_mask(struct azx *chip, int dev)
2071 {
2072 const struct snd_pci_quirk *q;
2073
2074 if (probe_mask[dev] == -1) {
2075 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2076 if (q) {
2077 printk(KERN_INFO
2078 "hda_intel: probe_mask set to 0x%x "
2079 "for device %04x:%04x\n",
2080 q->value, q->subvendor, q->subdevice);
2081 probe_mask[dev] = q->value;
2082 }
2083 }
2084 }
2085
2086
2087 /*
2088 * constructor
2089 */
2090 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2091 int dev, int driver_type,
2092 struct azx **rchip)
2093 {
2094 struct azx *chip;
2095 int i, err;
2096 unsigned short gcap;
2097 static struct snd_device_ops ops = {
2098 .dev_free = azx_dev_free,
2099 };
2100
2101 *rchip = NULL;
2102
2103 err = pci_enable_device(pci);
2104 if (err < 0)
2105 return err;
2106
2107 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2108 if (!chip) {
2109 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2110 pci_disable_device(pci);
2111 return -ENOMEM;
2112 }
2113
2114 spin_lock_init(&chip->reg_lock);
2115 mutex_init(&chip->open_mutex);
2116 chip->card = card;
2117 chip->pci = pci;
2118 chip->irq = -1;
2119 chip->driver_type = driver_type;
2120 chip->msi = enable_msi;
2121 chip->dev_index = dev;
2122 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2123
2124 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2125 check_probe_mask(chip, dev);
2126
2127 chip->single_cmd = single_cmd;
2128
2129 if (bdl_pos_adj[dev] < 0) {
2130 switch (chip->driver_type) {
2131 case AZX_DRIVER_ICH:
2132 bdl_pos_adj[dev] = 1;
2133 break;
2134 default:
2135 bdl_pos_adj[dev] = 32;
2136 break;
2137 }
2138 }
2139
2140 #if BITS_PER_LONG != 64
2141 /* Fix up base address on ULI M5461 */
2142 if (chip->driver_type == AZX_DRIVER_ULI) {
2143 u16 tmp3;
2144 pci_read_config_word(pci, 0x40, &tmp3);
2145 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2146 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2147 }
2148 #endif
2149
2150 err = pci_request_regions(pci, "ICH HD audio");
2151 if (err < 0) {
2152 kfree(chip);
2153 pci_disable_device(pci);
2154 return err;
2155 }
2156
2157 chip->addr = pci_resource_start(pci, 0);
2158 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2159 if (chip->remap_addr == NULL) {
2160 snd_printk(KERN_ERR SFX "ioremap error\n");
2161 err = -ENXIO;
2162 goto errout;
2163 }
2164
2165 if (chip->msi)
2166 if (pci_enable_msi(pci) < 0)
2167 chip->msi = 0;
2168
2169 if (azx_acquire_irq(chip, 0) < 0) {
2170 err = -EBUSY;
2171 goto errout;
2172 }
2173
2174 pci_set_master(pci);
2175 synchronize_irq(chip->irq);
2176
2177 gcap = azx_readw(chip, GCAP);
2178 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2179
2180 /* allow 64bit DMA address if supported by H/W */
2181 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2182 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2183
2184 /* read number of streams from GCAP register instead of using
2185 * hardcoded value
2186 */
2187 chip->capture_streams = (gcap >> 8) & 0x0f;
2188 chip->playback_streams = (gcap >> 12) & 0x0f;
2189 if (!chip->playback_streams && !chip->capture_streams) {
2190 /* gcap didn't give any info, switching to old method */
2191
2192 switch (chip->driver_type) {
2193 case AZX_DRIVER_ULI:
2194 chip->playback_streams = ULI_NUM_PLAYBACK;
2195 chip->capture_streams = ULI_NUM_CAPTURE;
2196 break;
2197 case AZX_DRIVER_ATIHDMI:
2198 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2199 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2200 break;
2201 default:
2202 chip->playback_streams = ICH6_NUM_PLAYBACK;
2203 chip->capture_streams = ICH6_NUM_CAPTURE;
2204 break;
2205 }
2206 }
2207 chip->capture_index_offset = 0;
2208 chip->playback_index_offset = chip->capture_streams;
2209 chip->num_streams = chip->playback_streams + chip->capture_streams;
2210 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2211 GFP_KERNEL);
2212 if (!chip->azx_dev) {
2213 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2214 goto errout;
2215 }
2216
2217 for (i = 0; i < chip->num_streams; i++) {
2218 /* allocate memory for the BDL for each stream */
2219 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2220 snd_dma_pci_data(chip->pci),
2221 BDL_SIZE, &chip->azx_dev[i].bdl);
2222 if (err < 0) {
2223 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2224 goto errout;
2225 }
2226 }
2227 /* allocate memory for the position buffer */
2228 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2229 snd_dma_pci_data(chip->pci),
2230 chip->num_streams * 8, &chip->posbuf);
2231 if (err < 0) {
2232 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2233 goto errout;
2234 }
2235 /* allocate CORB/RIRB */
2236 if (!chip->single_cmd) {
2237 err = azx_alloc_cmd_io(chip);
2238 if (err < 0)
2239 goto errout;
2240 }
2241
2242 /* initialize streams */
2243 azx_init_stream(chip);
2244
2245 /* initialize chip */
2246 azx_init_pci(chip);
2247 azx_init_chip(chip);
2248
2249 /* codec detection */
2250 if (!chip->codec_mask) {
2251 snd_printk(KERN_ERR SFX "no codecs found!\n");
2252 err = -ENODEV;
2253 goto errout;
2254 }
2255
2256 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2257 if (err <0) {
2258 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2259 goto errout;
2260 }
2261
2262 strcpy(card->driver, "HDA-Intel");
2263 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2264 sprintf(card->longname, "%s at 0x%lx irq %i",
2265 card->shortname, chip->addr, chip->irq);
2266
2267 *rchip = chip;
2268 return 0;
2269
2270 errout:
2271 azx_free(chip);
2272 return err;
2273 }
2274
2275 static void power_down_all_codecs(struct azx *chip)
2276 {
2277 #ifdef CONFIG_SND_HDA_POWER_SAVE
2278 /* The codecs were powered up in snd_hda_codec_new().
2279 * Now all initialization done, so turn them down if possible
2280 */
2281 struct hda_codec *codec;
2282 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2283 snd_hda_power_down(codec);
2284 }
2285 #endif
2286 }
2287
2288 static int __devinit azx_probe(struct pci_dev *pci,
2289 const struct pci_device_id *pci_id)
2290 {
2291 static int dev;
2292 struct snd_card *card;
2293 struct azx *chip;
2294 int err;
2295
2296 if (dev >= SNDRV_CARDS)
2297 return -ENODEV;
2298 if (!enable[dev]) {
2299 dev++;
2300 return -ENOENT;
2301 }
2302
2303 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2304 if (!card) {
2305 snd_printk(KERN_ERR SFX "Error creating card!\n");
2306 return -ENOMEM;
2307 }
2308
2309 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2310 if (err < 0) {
2311 snd_card_free(card);
2312 return err;
2313 }
2314 card->private_data = chip;
2315
2316 /* create codec instances */
2317 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2318 if (err < 0) {
2319 snd_card_free(card);
2320 return err;
2321 }
2322
2323 /* create PCM streams */
2324 err = azx_pcm_create(chip);
2325 if (err < 0) {
2326 snd_card_free(card);
2327 return err;
2328 }
2329
2330 /* create mixer controls */
2331 err = azx_mixer_create(chip);
2332 if (err < 0) {
2333 snd_card_free(card);
2334 return err;
2335 }
2336
2337 snd_card_set_dev(card, &pci->dev);
2338
2339 err = snd_card_register(card);
2340 if (err < 0) {
2341 snd_card_free(card);
2342 return err;
2343 }
2344
2345 pci_set_drvdata(pci, card);
2346 chip->running = 1;
2347 power_down_all_codecs(chip);
2348
2349 dev++;
2350 return err;
2351 }
2352
2353 static void __devexit azx_remove(struct pci_dev *pci)
2354 {
2355 snd_card_free(pci_get_drvdata(pci));
2356 pci_set_drvdata(pci, NULL);
2357 }
2358
2359 /* PCI IDs */
2360 static struct pci_device_id azx_ids[] = {
2361 /* ICH 6..10 */
2362 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2363 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2364 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2365 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2366 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2367 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2368 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2369 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2370 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2371 /* PCH */
2372 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2373 /* SCH */
2374 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2375 /* ATI SB 450/600 */
2376 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2377 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2378 /* ATI HDMI */
2379 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2380 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2381 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2382 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2383 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2384 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2385 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2386 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2387 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2388 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2389 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2390 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2391 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2392 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2393 /* VIA VT8251/VT8237A */
2394 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2395 /* SIS966 */
2396 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2397 /* ULI M5461 */
2398 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2399 /* NVIDIA MCP */
2400 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2401 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2402 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2403 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2404 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2405 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2406 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2407 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2408 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2409 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2410 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2411 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2412 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2413 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2414 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2415 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2416 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2417 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2418 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2419 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2420 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2421 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2422 /* Teradici */
2423 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2424 { 0, }
2425 };
2426 MODULE_DEVICE_TABLE(pci, azx_ids);
2427
2428 /* pci_driver definition */
2429 static struct pci_driver driver = {
2430 .name = "HDA Intel",
2431 .id_table = azx_ids,
2432 .probe = azx_probe,
2433 .remove = __devexit_p(azx_remove),
2434 #ifdef CONFIG_PM
2435 .suspend = azx_suspend,
2436 .resume = azx_resume,
2437 #endif
2438 };
2439
2440 static int __init alsa_card_azx_init(void)
2441 {
2442 return pci_register_driver(&driver);
2443 }
2444
2445 static void __exit alsa_card_azx_exit(void)
2446 {
2447 pci_unregister_driver(&driver);
2448 }
2449
2450 module_init(alsa_card_azx_init)
2451 module_exit(alsa_card_azx_exit)
Support for the Chinese Samsung S3C2440 based development boards