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PNP: convert to using pnp_dbg()
[linux-2.6/mini2440.git] / drivers / net / macmace.c
blob51ad3765e0750c2857555c437ed259631a5394b7
1 /*
2 * Driver for the Macintosh 68K onboard MACE controller with PSC
3 * driven DMA. The MACE driver code is derived from mace.c. The
4 * Mac68k theory of operation is courtesy of the MacBSD wizards.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Copyright (C) 1996 Paul Mackerras.
12 * Copyright (C) 1998 Alan Cox <alan@redhat.com>
13 *
14 * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
15 *
16 * Copyright (C) 2007 Finn Thain
17 *
18 * Converted to DMA API, converted to unified driver model,
19 * sync'd some routines with mace.c and fixed various bugs.
20 */
21
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/string.h>
29 #include <linux/crc32.h>
30 #include <linux/bitrev.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/platform_device.h>
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/macintosh.h>
36 #include <asm/macints.h>
37 #include <asm/mac_psc.h>
38 #include <asm/page.h>
39 #include "mace.h"
40
41 static char mac_mace_string[] = "macmace";
42 static struct platform_device *mac_mace_device;
43
44 #define N_TX_BUFF_ORDER 0
45 #define N_TX_RING (1 << N_TX_BUFF_ORDER)
46 #define N_RX_BUFF_ORDER 3
47 #define N_RX_RING (1 << N_RX_BUFF_ORDER)
48
49 #define TX_TIMEOUT HZ
50
51 #define MACE_BUFF_SIZE 0x800
52
53 /* Chip rev needs workaround on HW & multicast addr change */
54 #define BROKEN_ADDRCHG_REV 0x0941
55
56 /* The MACE is simply wired down on a Mac68K box */
57
58 #define MACE_BASE (void *)(0x50F1C000)
59 #define MACE_PROM (void *)(0x50F08001)
60
61 struct mace_data {
62 volatile struct mace *mace;
63 unsigned char *tx_ring;
64 dma_addr_t tx_ring_phys;
65 unsigned char *rx_ring;
66 dma_addr_t rx_ring_phys;
67 int dma_intr;
68 int rx_slot, rx_tail;
69 int tx_slot, tx_sloti, tx_count;
70 int chipid;
71 struct device *device;
72 };
73
74 struct mace_frame {
75 u8 rcvcnt;
76 u8 pad1;
77 u8 rcvsts;
78 u8 pad2;
79 u8 rntpc;
80 u8 pad3;
81 u8 rcvcc;
82 u8 pad4;
83 u32 pad5;
84 u32 pad6;
85 u8 data[1];
86 /* And frame continues.. */
87 };
88
89 #define PRIV_BYTES sizeof(struct mace_data)
90
91 static int mace_open(struct net_device *dev);
92 static int mace_close(struct net_device *dev);
93 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
94 static void mace_set_multicast(struct net_device *dev);
95 static int mace_set_address(struct net_device *dev, void *addr);
96 static void mace_reset(struct net_device *dev);
97 static irqreturn_t mace_interrupt(int irq, void *dev_id);
98 static irqreturn_t mace_dma_intr(int irq, void *dev_id);
99 static void mace_tx_timeout(struct net_device *dev);
100 static void __mace_set_address(struct net_device *dev, void *addr);
101
102 /*
103 * Load a receive DMA channel with a base address and ring length
104 */
105
106 static void mace_load_rxdma_base(struct net_device *dev, int set)
107 {
108 struct mace_data *mp = netdev_priv(dev);
109
110 psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
111 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
112 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
113 psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
114 mp->rx_tail = 0;
115 }
116
117 /*
118 * Reset the receive DMA subsystem
119 */
120
121 static void mace_rxdma_reset(struct net_device *dev)
122 {
123 struct mace_data *mp = netdev_priv(dev);
124 volatile struct mace *mace = mp->mace;
125 u8 maccc = mace->maccc;
126
127 mace->maccc = maccc & ~ENRCV;
128
129 psc_write_word(PSC_ENETRD_CTL, 0x8800);
130 mace_load_rxdma_base(dev, 0x00);
131 psc_write_word(PSC_ENETRD_CTL, 0x0400);
132
133 psc_write_word(PSC_ENETRD_CTL, 0x8800);
134 mace_load_rxdma_base(dev, 0x10);
135 psc_write_word(PSC_ENETRD_CTL, 0x0400);
136
137 mace->maccc = maccc;
138 mp->rx_slot = 0;
139
140 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
141 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
142 }
143
144 /*
145 * Reset the transmit DMA subsystem
146 */
147
148 static void mace_txdma_reset(struct net_device *dev)
149 {
150 struct mace_data *mp = netdev_priv(dev);
151 volatile struct mace *mace = mp->mace;
152 u8 maccc;
153
154 psc_write_word(PSC_ENETWR_CTL, 0x8800);
155
156 maccc = mace->maccc;
157 mace->maccc = maccc & ~ENXMT;
158
159 mp->tx_slot = mp->tx_sloti = 0;
160 mp->tx_count = N_TX_RING;
161
162 psc_write_word(PSC_ENETWR_CTL, 0x0400);
163 mace->maccc = maccc;
164 }
165
166 /*
167 * Disable DMA
168 */
169
170 static void mace_dma_off(struct net_device *dev)
171 {
172 psc_write_word(PSC_ENETRD_CTL, 0x8800);
173 psc_write_word(PSC_ENETRD_CTL, 0x1000);
174 psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
175 psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
176
177 psc_write_word(PSC_ENETWR_CTL, 0x8800);
178 psc_write_word(PSC_ENETWR_CTL, 0x1000);
179 psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
180 psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
181 }
182
183 /*
184 * Not really much of a probe. The hardware table tells us if this
185 * model of Macintrash has a MACE (AV macintoshes)
186 */
187
188 static int __devinit mace_probe(struct platform_device *pdev)
189 {
190 int j;
191 struct mace_data *mp;
192 unsigned char *addr;
193 struct net_device *dev;
194 unsigned char checksum = 0;
195 static int found = 0;
196 int err;
197 DECLARE_MAC_BUF(mac);
198
199 if (found || macintosh_config->ether_type != MAC_ETHER_MACE)
200 return -ENODEV;
201
202 found = 1; /* prevent 'finding' one on every device probe */
203
204 dev = alloc_etherdev(PRIV_BYTES);
205 if (!dev)
206 return -ENOMEM;
207
208 mp = netdev_priv(dev);
209
210 mp->device = &pdev->dev;
211 SET_NETDEV_DEV(dev, &pdev->dev);
212
213 dev->base_addr = (u32)MACE_BASE;
214 mp->mace = (volatile struct mace *) MACE_BASE;
215
216 dev->irq = IRQ_MAC_MACE;
217 mp->dma_intr = IRQ_MAC_MACE_DMA;
218
219 mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo;
220
221 /*
222 * The PROM contains 8 bytes which total 0xFF when XOR'd
223 * together. Due to the usual peculiar apple brain damage
224 * the bytes are spaced out in a strange boundary and the
225 * bits are reversed.
226 */
227
228 addr = (void *)MACE_PROM;
229
230 for (j = 0; j < 6; ++j) {
231 u8 v = bitrev8(addr[j<<4]);
232 checksum ^= v;
233 dev->dev_addr[j] = v;
234 }
235 for (; j < 8; ++j) {
236 checksum ^= bitrev8(addr[j<<4]);
237 }
238
239 if (checksum != 0xFF) {
240 free_netdev(dev);
241 return -ENODEV;
242 }
243
244 dev->open = mace_open;
245 dev->stop = mace_close;
246 dev->hard_start_xmit = mace_xmit_start;
247 dev->tx_timeout = mace_tx_timeout;
248 dev->watchdog_timeo = TX_TIMEOUT;
249 dev->set_multicast_list = mace_set_multicast;
250 dev->set_mac_address = mace_set_address;
251
252 printk(KERN_INFO "%s: 68K MACE, hardware address %s\n",
253 dev->name, print_mac(mac, dev->dev_addr));
254
255 err = register_netdev(dev);
256 if (!err)
257 return 0;
258
259 free_netdev(dev);
260 return err;
261 }
262
263 /*
264 * Reset the chip.
265 */
266
267 static void mace_reset(struct net_device *dev)
268 {
269 struct mace_data *mp = netdev_priv(dev);
270 volatile struct mace *mb = mp->mace;
271 int i;
272
273 /* soft-reset the chip */
274 i = 200;
275 while (--i) {
276 mb->biucc = SWRST;
277 if (mb->biucc & SWRST) {
278 udelay(10);
279 continue;
280 }
281 break;
282 }
283 if (!i) {
284 printk(KERN_ERR "macmace: cannot reset chip!\n");
285 return;
286 }
287
288 mb->maccc = 0; /* turn off tx, rx */
289 mb->imr = 0xFF; /* disable all intrs for now */
290 i = mb->ir;
291
292 mb->biucc = XMTSP_64;
293 mb->utr = RTRD;
294 mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU;
295
296 mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */
297 mb->rcvfc = 0;
298
299 /* load up the hardware address */
300 __mace_set_address(dev, dev->dev_addr);
301
302 /* clear the multicast filter */
303 if (mp->chipid == BROKEN_ADDRCHG_REV)
304 mb->iac = LOGADDR;
305 else {
306 mb->iac = ADDRCHG | LOGADDR;
307 while ((mb->iac & ADDRCHG) != 0)
308 ;
309 }
310 for (i = 0; i < 8; ++i)
311 mb->ladrf = 0;
312
313 /* done changing address */
314 if (mp->chipid != BROKEN_ADDRCHG_REV)
315 mb->iac = 0;
316
317 mb->plscc = PORTSEL_AUI;
318 }
319
320 /*
321 * Load the address on a mace controller.
322 */
323
324 static void __mace_set_address(struct net_device *dev, void *addr)
325 {
326 struct mace_data *mp = netdev_priv(dev);
327 volatile struct mace *mb = mp->mace;
328 unsigned char *p = addr;
329 int i;
330
331 /* load up the hardware address */
332 if (mp->chipid == BROKEN_ADDRCHG_REV)
333 mb->iac = PHYADDR;
334 else {
335 mb->iac = ADDRCHG | PHYADDR;
336 while ((mb->iac & ADDRCHG) != 0)
337 ;
338 }
339 for (i = 0; i < 6; ++i)
340 mb->padr = dev->dev_addr[i] = p[i];
341 if (mp->chipid != BROKEN_ADDRCHG_REV)
342 mb->iac = 0;
343 }
344
345 static int mace_set_address(struct net_device *dev, void *addr)
346 {
347 struct mace_data *mp = netdev_priv(dev);
348 volatile struct mace *mb = mp->mace;
349 unsigned long flags;
350 u8 maccc;
351
352 local_irq_save(flags);
353
354 maccc = mb->maccc;
355
356 __mace_set_address(dev, addr);
357
358 mb->maccc = maccc;
359
360 local_irq_restore(flags);
361
362 return 0;
363 }
364
365 /*
366 * Open the Macintosh MACE. Most of this is playing with the DMA
367 * engine. The ethernet chip is quite friendly.
368 */
369
370 static int mace_open(struct net_device *dev)
371 {
372 struct mace_data *mp = netdev_priv(dev);
373 volatile struct mace *mb = mp->mace;
374
375 /* reset the chip */
376 mace_reset(dev);
377
378 if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
379 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
380 return -EAGAIN;
381 }
382 if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
383 printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
384 free_irq(dev->irq, dev);
385 return -EAGAIN;
386 }
387
388 /* Allocate the DMA ring buffers */
389
390 mp->tx_ring = dma_alloc_coherent(mp->device,
391 N_TX_RING * MACE_BUFF_SIZE,
392 &mp->tx_ring_phys, GFP_KERNEL);
393 if (mp->tx_ring == NULL) {
394 printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name);
395 goto out1;
396 }
397
398 mp->rx_ring = dma_alloc_coherent(mp->device,
399 N_RX_RING * MACE_BUFF_SIZE,
400 &mp->rx_ring_phys, GFP_KERNEL);
401 if (mp->rx_ring == NULL) {
402 printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name);
403 goto out2;
404 }
405
406 mace_dma_off(dev);
407
408 /* Not sure what these do */
409
410 psc_write_word(PSC_ENETWR_CTL, 0x9000);
411 psc_write_word(PSC_ENETRD_CTL, 0x9000);
412 psc_write_word(PSC_ENETWR_CTL, 0x0400);
413 psc_write_word(PSC_ENETRD_CTL, 0x0400);
414
415 mace_rxdma_reset(dev);
416 mace_txdma_reset(dev);
417
418 /* turn it on! */
419 mb->maccc = ENXMT | ENRCV;
420 /* enable all interrupts except receive interrupts */
421 mb->imr = RCVINT;
422 return 0;
423
424 out2:
425 dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE,
426 mp->tx_ring, mp->tx_ring_phys);
427 out1:
428 free_irq(dev->irq, dev);
429 free_irq(mp->dma_intr, dev);
430 return -ENOMEM;
431 }
432
433 /*
434 * Shut down the mace and its interrupt channel
435 */
436
437 static int mace_close(struct net_device *dev)
438 {
439 struct mace_data *mp = netdev_priv(dev);
440 volatile struct mace *mb = mp->mace;
441
442 mb->maccc = 0; /* disable rx and tx */
443 mb->imr = 0xFF; /* disable all irqs */
444 mace_dma_off(dev); /* disable rx and tx dma */
445
446 return 0;
447 }
448
449 /*
450 * Transmit a frame
451 */
452
453 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
454 {
455 struct mace_data *mp = netdev_priv(dev);
456 unsigned long flags;
457
458 /* Stop the queue since there's only the one buffer */
459
460 local_irq_save(flags);
461 netif_stop_queue(dev);
462 if (!mp->tx_count) {
463 printk(KERN_ERR "macmace: tx queue running but no free buffers.\n");
464 local_irq_restore(flags);
465 return NETDEV_TX_BUSY;
466 }
467 mp->tx_count--;
468 local_irq_restore(flags);
469
470 dev->stats.tx_packets++;
471 dev->stats.tx_bytes += skb->len;
472
473 /* We need to copy into our xmit buffer to take care of alignment and caching issues */
474 skb_copy_from_linear_data(skb, mp->tx_ring, skb->len);
475
476 /* load the Tx DMA and fire it off */
477
478 psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
479 psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
480 psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
481
482 mp->tx_slot ^= 0x10;
483
484 dev_kfree_skb(skb);
485
486 dev->trans_start = jiffies;
487 return NETDEV_TX_OK;
488 }
489
490 static void mace_set_multicast(struct net_device *dev)
491 {
492 struct mace_data *mp = netdev_priv(dev);
493 volatile struct mace *mb = mp->mace;
494 int i, j;
495 u32 crc;
496 u8 maccc;
497 unsigned long flags;
498
499 local_irq_save(flags);
500 maccc = mb->maccc;
501 mb->maccc &= ~PROM;
502
503 if (dev->flags & IFF_PROMISC) {
504 mb->maccc |= PROM;
505 } else {
506 unsigned char multicast_filter[8];
507 struct dev_mc_list *dmi = dev->mc_list;
508
509 if (dev->flags & IFF_ALLMULTI) {
510 for (i = 0; i < 8; i++) {
511 multicast_filter[i] = 0xFF;
512 }
513 } else {
514 for (i = 0; i < 8; i++)
515 multicast_filter[i] = 0;
516 for (i = 0; i < dev->mc_count; i++) {
517 crc = ether_crc_le(6, dmi->dmi_addr);
518 j = crc >> 26; /* bit number in multicast_filter */
519 multicast_filter[j >> 3] |= 1 << (j & 7);
520 dmi = dmi->next;
521 }
522 }
523
524 if (mp->chipid == BROKEN_ADDRCHG_REV)
525 mb->iac = LOGADDR;
526 else {
527 mb->iac = ADDRCHG | LOGADDR;
528 while ((mb->iac & ADDRCHG) != 0)
529 ;
530 }
531 for (i = 0; i < 8; ++i)
532 mb->ladrf = multicast_filter[i];
533 if (mp->chipid != BROKEN_ADDRCHG_REV)
534 mb->iac = 0;
535 }
536
537 mb->maccc = maccc;
538 local_irq_restore(flags);
539 }
540
541 static void mace_handle_misc_intrs(struct net_device *dev, int intr)
542 {
543 struct mace_data *mp = netdev_priv(dev);
544 volatile struct mace *mb = mp->mace;
545 static int mace_babbles, mace_jabbers;
546
547 if (intr & MPCO)
548 dev->stats.rx_missed_errors += 256;
549 dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */
550 if (intr & RNTPCO)
551 dev->stats.rx_length_errors += 256;
552 dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */
553 if (intr & CERR)
554 ++dev->stats.tx_heartbeat_errors;
555 if (intr & BABBLE)
556 if (mace_babbles++ < 4)
557 printk(KERN_DEBUG "macmace: babbling transmitter\n");
558 if (intr & JABBER)
559 if (mace_jabbers++ < 4)
560 printk(KERN_DEBUG "macmace: jabbering transceiver\n");
561 }
562
563 static irqreturn_t mace_interrupt(int irq, void *dev_id)
564 {
565 struct net_device *dev = (struct net_device *) dev_id;
566 struct mace_data *mp = netdev_priv(dev);
567 volatile struct mace *mb = mp->mace;
568 int intr, fs;
569 unsigned long flags;
570
571 /* don't want the dma interrupt handler to fire */
572 local_irq_save(flags);
573
574 intr = mb->ir; /* read interrupt register */
575 mace_handle_misc_intrs(dev, intr);
576
577 if (intr & XMTINT) {
578 fs = mb->xmtfs;
579 if ((fs & XMTSV) == 0) {
580 printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs);
581 mace_reset(dev);
582 /*
583 * XXX mace likes to hang the machine after a xmtfs error.
584 * This is hard to reproduce, reseting *may* help
585 */
586 }
587 /* dma should have finished */
588 if (!mp->tx_count) {
589 printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs);
590 }
591 /* Update stats */
592 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
593 ++dev->stats.tx_errors;
594 if (fs & LCAR)
595 ++dev->stats.tx_carrier_errors;
596 else if (fs & (UFLO|LCOL|RTRY)) {
597 ++dev->stats.tx_aborted_errors;
598 if (mb->xmtfs & UFLO) {
599 printk(KERN_ERR "%s: DMA underrun.\n", dev->name);
600 dev->stats.tx_fifo_errors++;
601 mace_txdma_reset(dev);
602 }
603 }
604 }
605 }
606
607 if (mp->tx_count)
608 netif_wake_queue(dev);
609
610 local_irq_restore(flags);
611
612 return IRQ_HANDLED;
613 }
614
615 static void mace_tx_timeout(struct net_device *dev)
616 {
617 struct mace_data *mp = netdev_priv(dev);
618 volatile struct mace *mb = mp->mace;
619 unsigned long flags;
620
621 local_irq_save(flags);
622
623 /* turn off both tx and rx and reset the chip */
624 mb->maccc = 0;
625 printk(KERN_ERR "macmace: transmit timeout - resetting\n");
626 mace_txdma_reset(dev);
627 mace_reset(dev);
628
629 /* restart rx dma */
630 mace_rxdma_reset(dev);
631
632 mp->tx_count = N_TX_RING;
633 netif_wake_queue(dev);
634
635 /* turn it on! */
636 mb->maccc = ENXMT | ENRCV;
637 /* enable all interrupts except receive interrupts */
638 mb->imr = RCVINT;
639
640 local_irq_restore(flags);
641 }
642
643 /*
644 * Handle a newly arrived frame
645 */
646
647 static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
648 {
649 struct sk_buff *skb;
650 unsigned int frame_status = mf->rcvsts;
651
652 if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) {
653 dev->stats.rx_errors++;
654 if (frame_status & RS_OFLO) {
655 printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name);
656 dev->stats.rx_fifo_errors++;
657 }
658 if (frame_status & RS_CLSN)
659 dev->stats.collisions++;
660 if (frame_status & RS_FRAMERR)
661 dev->stats.rx_frame_errors++;
662 if (frame_status & RS_FCSERR)
663 dev->stats.rx_crc_errors++;
664 } else {
665 unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 );
666
667 skb = dev_alloc_skb(frame_length + 2);
668 if (!skb) {
669 dev->stats.rx_dropped++;
670 return;
671 }
672 skb_reserve(skb, 2);
673 memcpy(skb_put(skb, frame_length), mf->data, frame_length);
674
675 skb->protocol = eth_type_trans(skb, dev);
676 netif_rx(skb);
677 dev->last_rx = jiffies;
678 dev->stats.rx_packets++;
679 dev->stats.rx_bytes += frame_length;
680 }
681 }
682
683 /*
684 * The PSC has passed us a DMA interrupt event.
685 */
686
687 static irqreturn_t mace_dma_intr(int irq, void *dev_id)
688 {
689 struct net_device *dev = (struct net_device *) dev_id;
690 struct mace_data *mp = netdev_priv(dev);
691 int left, head;
692 u16 status;
693 u32 baka;
694
695 /* Not sure what this does */
696
697 while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
698 if (!(baka & 0x60000000)) return IRQ_NONE;
699
700 /*
701 * Process the read queue
702 */
703
704 status = psc_read_word(PSC_ENETRD_CTL);
705
706 if (status & 0x2000) {
707 mace_rxdma_reset(dev);
708 } else if (status & 0x0100) {
709 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
710
711 left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
712 head = N_RX_RING - left;
713
714 /* Loop through the ring buffer and process new packages */
715
716 while (mp->rx_tail < head) {
717 mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring
718 + (mp->rx_tail * MACE_BUFF_SIZE)));
719 mp->rx_tail++;
720 }
721
722 /* If we're out of buffers in this ring then switch to */
723 /* the other set, otherwise just reactivate this one. */
724
725 if (!left) {
726 mace_load_rxdma_base(dev, mp->rx_slot);
727 mp->rx_slot ^= 0x10;
728 } else {
729 psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
730 }
731 }
732
733 /*
734 * Process the write queue
735 */
736
737 status = psc_read_word(PSC_ENETWR_CTL);
738
739 if (status & 0x2000) {
740 mace_txdma_reset(dev);
741 } else if (status & 0x0100) {
742 psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
743 mp->tx_sloti ^= 0x10;
744 mp->tx_count++;
745 }
746 return IRQ_HANDLED;
747 }
748
749 MODULE_LICENSE("GPL");
750 MODULE_DESCRIPTION("Macintosh MACE ethernet driver");
751
752 static int __devexit mac_mace_device_remove (struct platform_device *pdev)
753 {
754 struct net_device *dev = platform_get_drvdata(pdev);
755 struct mace_data *mp = netdev_priv(dev);
756
757 unregister_netdev(dev);
758
759 free_irq(dev->irq, dev);
760 free_irq(IRQ_MAC_MACE_DMA, dev);
761
762 dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE,
763 mp->rx_ring, mp->rx_ring_phys);
764 dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE,
765 mp->tx_ring, mp->tx_ring_phys);
766
767 free_netdev(dev);
768
769 return 0;
770 }
771
772 static struct platform_driver mac_mace_driver = {
773 .probe = mace_probe,
774 .remove = __devexit_p(mac_mace_device_remove),
775 .driver = {
776 .name = mac_mace_string,
777 },
778 };
779
780 static int __init mac_mace_init_module(void)
781 {
782 int err;
783
784 if (!MACH_IS_MAC)
785 return -ENODEV;
786
787 if ((err = platform_driver_register(&mac_mace_driver))) {
788 printk(KERN_ERR "Driver registration failed\n");
789 return err;
790 }
791
792 mac_mace_device = platform_device_alloc(mac_mace_string, 0);
793 if (!mac_mace_device)
794 goto out_unregister;
795
796 if (platform_device_add(mac_mace_device)) {
797 platform_device_put(mac_mace_device);
798 mac_mace_device = NULL;
799 }
800
801 return 0;
802
803 out_unregister:
804 platform_driver_unregister(&mac_mace_driver);
805
806 return -ENOMEM;
807 }
808
809 static void __exit mac_mace_cleanup_module(void)
810 {
811 platform_driver_unregister(&mac_mace_driver);
812
813 if (mac_mace_device) {
814 platform_device_unregister(mac_mace_device);
815 mac_mace_device = NULL;
816 }
817 }
818
819 module_init(mac_mace_init_module);
820 module_exit(mac_mace_cleanup_module);
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