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ixgbe: Add 82598 support for BX mezzanine devices
[linux-2.6/mini2440.git] / drivers / net / ixgbe / ixgbe_82598.c
blobdffe7f062c8724083ab7803942a37e8fb007b95d
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
40
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data);
51
52 /**
53 */
54 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
55 {
56 struct ixgbe_mac_info *mac = &hw->mac;
57 struct ixgbe_phy_info *phy = &hw->phy;
58 s32 ret_val = 0;
59 u16 list_offset, data_offset;
60
61 /* Call PHY identify routine to get the phy type */
62 ixgbe_identify_phy_generic(hw);
63
64 /* PHY Init */
65 switch (phy->type) {
66 case ixgbe_phy_tn:
67 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
68 phy->ops.get_firmware_version =
69 &ixgbe_get_phy_firmware_version_tnx;
70 break;
71 case ixgbe_phy_nl:
72 phy->ops.reset = &ixgbe_reset_phy_nl;
73
74 /* Call SFP+ identify routine to get the SFP+ module type */
75 ret_val = phy->ops.identify_sfp(hw);
76 if (ret_val != 0)
77 goto out;
78 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
79 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
80 goto out;
81 }
82
83 /* Check to see if SFP+ module is supported */
84 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
85 &list_offset,
86 &data_offset);
87 if (ret_val != 0) {
88 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
89 goto out;
90 }
91 break;
92 default:
93 break;
94 }
95
96 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
97 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
98 mac->ops.setup_link_speed =
99 &ixgbe_setup_copper_link_speed_82598;
100 mac->ops.get_link_capabilities =
101 &ixgbe_get_copper_link_capabilities_82598;
102 }
103
104 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
105 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
106 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
107 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
108 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
109
110 out:
111 return ret_val;
112 }
113
114 /**
115 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
116 * @hw: pointer to hardware structure
117 * @speed: pointer to link speed
118 * @autoneg: boolean auto-negotiation value
119 *
120 * Determines the link capabilities by reading the AUTOC register.
121 **/
122 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
123 ixgbe_link_speed *speed,
124 bool *autoneg)
125 {
126 s32 status = 0;
127 s32 autoc_reg;
128
129 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
130
131 if (hw->mac.link_settings_loaded) {
132 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
133 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
134 autoc_reg |= hw->mac.link_attach_type;
135 autoc_reg |= hw->mac.link_mode_select;
136 }
137
138 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
139 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
140 *speed = IXGBE_LINK_SPEED_1GB_FULL;
141 *autoneg = false;
142 break;
143
144 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
145 *speed = IXGBE_LINK_SPEED_10GB_FULL;
146 *autoneg = false;
147 break;
148
149 case IXGBE_AUTOC_LMS_1G_AN:
150 *speed = IXGBE_LINK_SPEED_1GB_FULL;
151 *autoneg = true;
152 break;
153
154 case IXGBE_AUTOC_LMS_KX4_AN:
155 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
156 *speed = IXGBE_LINK_SPEED_UNKNOWN;
157 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP)
158 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
159 if (autoc_reg & IXGBE_AUTOC_KX_SUPP)
160 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
161 *autoneg = true;
162 break;
163
164 default:
165 status = IXGBE_ERR_LINK_SETUP;
166 break;
167 }
168
169 return status;
170 }
171
172 /**
173 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
174 * @hw: pointer to hardware structure
175 * @speed: pointer to link speed
176 * @autoneg: boolean auto-negotiation value
177 *
178 * Determines the link capabilities by reading the AUTOC register.
179 **/
180 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
181 ixgbe_link_speed *speed,
182 bool *autoneg)
183 {
184 s32 status = IXGBE_ERR_LINK_SETUP;
185 u16 speed_ability;
186
187 *speed = 0;
188 *autoneg = true;
189
190 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
191 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
192 &speed_ability);
193
194 if (status == 0) {
195 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
196 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
197 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
198 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
199 }
200
201 return status;
202 }
203
204 /**
205 * ixgbe_get_media_type_82598 - Determines media type
206 * @hw: pointer to hardware structure
207 *
208 * Returns the media type (fiber, copper, backplane)
209 **/
210 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
211 {
212 enum ixgbe_media_type media_type;
213
214 /* Media type for I82598 is based on device ID */
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82598:
217 case IXGBE_DEV_ID_82598_BX:
218 media_type = ixgbe_media_type_backplane;
219 break;
220 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
221 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
222 case IXGBE_DEV_ID_82598EB_CX4:
223 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
224 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
225 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
226 case IXGBE_DEV_ID_82598EB_XF_LR:
227 case IXGBE_DEV_ID_82598EB_SFP_LOM:
228 media_type = ixgbe_media_type_fiber;
229 break;
230 case IXGBE_DEV_ID_82598AT:
231 media_type = ixgbe_media_type_copper;
232 break;
233 default:
234 media_type = ixgbe_media_type_unknown;
235 break;
236 }
237
238 return media_type;
239 }
240
241 /**
242 * ixgbe_setup_fc_82598 - Configure flow control settings
243 * @hw: pointer to hardware structure
244 * @packetbuf_num: packet buffer number (0-7)
245 *
246 * Configures the flow control settings based on SW configuration. This
247 * function is used for 802.3x flow control configuration only.
248 **/
249 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
250 {
251 u32 frctl_reg;
252 u32 rmcs_reg;
253
254 if (packetbuf_num < 0 || packetbuf_num > 7) {
255 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
256 " 0-7\n", packetbuf_num);
257 }
258
259 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
260 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
261
262 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
263 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
264
265 /*
266 * 10 gig parts do not have a word in the EEPROM to determine the
267 * default flow control setting, so we explicitly set it to full.
268 */
269 if (hw->fc.type == ixgbe_fc_default)
270 hw->fc.type = ixgbe_fc_full;
271
272 /*
273 * We want to save off the original Flow Control configuration just in
274 * case we get disconnected and then reconnected into a different hub
275 * or switch with different Flow Control capabilities.
276 */
277 hw->fc.original_type = hw->fc.type;
278
279 /*
280 * The possible values of the "flow_control" parameter are:
281 * 0: Flow control is completely disabled
282 * 1: Rx flow control is enabled (we can receive pause frames but not
283 * send pause frames).
284 * 2: Tx flow control is enabled (we can send pause frames but we do not
285 * support receiving pause frames)
286 * 3: Both Rx and Tx flow control (symmetric) are enabled.
287 * other: Invalid.
288 */
289 switch (hw->fc.type) {
290 case ixgbe_fc_none:
291 break;
292 case ixgbe_fc_rx_pause:
293 /*
294 * Rx Flow control is enabled,
295 * and Tx Flow control is disabled.
296 */
297 frctl_reg |= IXGBE_FCTRL_RFCE;
298 break;
299 case ixgbe_fc_tx_pause:
300 /*
301 * Tx Flow control is enabled, and Rx Flow control is disabled,
302 * by a software over-ride.
303 */
304 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
305 break;
306 case ixgbe_fc_full:
307 /*
308 * Flow control (both Rx and Tx) is enabled by a software
309 * over-ride.
310 */
311 frctl_reg |= IXGBE_FCTRL_RFCE;
312 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
313 break;
314 default:
315 /* We should never get here. The value should be 0-3. */
316 hw_dbg(hw, "Flow control param set incorrectly\n");
317 break;
318 }
319
320 /* Enable 802.3x based flow control settings. */
321 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
322 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
323
324 /*
325 * Check for invalid software configuration, zeros are completely
326 * invalid for all parameters used past this point, and if we enable
327 * flow control with zero water marks, we blast flow control packets.
328 */
329 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
330 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
331 return IXGBE_ERR_INVALID_LINK_SETTINGS;
332 }
333
334 /*
335 * We need to set up the Receive Threshold high and low water
336 * marks as well as (optionally) enabling the transmission of
337 * XON frames.
338 */
339 if (hw->fc.type & ixgbe_fc_tx_pause) {
340 if (hw->fc.send_xon) {
341 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
342 (hw->fc.low_water | IXGBE_FCRTL_XONE));
343 } else {
344 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
345 hw->fc.low_water);
346 }
347 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
348 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
349 }
350
351 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
352 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
353
354 return 0;
355 }
356
357 /**
358 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
359 * @hw: pointer to hardware structure
360 *
361 * Configures link settings based on values in the ixgbe_hw struct.
362 * Restarts the link. Performs autonegotiation if needed.
363 **/
364 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
365 {
366 u32 autoc_reg;
367 u32 links_reg;
368 u32 i;
369 s32 status = 0;
370
371 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
372
373 if (hw->mac.link_settings_loaded) {
374 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
375 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
376 autoc_reg |= hw->mac.link_attach_type;
377 autoc_reg |= hw->mac.link_mode_select;
378
379 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
380 IXGBE_WRITE_FLUSH(hw);
381 msleep(50);
382 }
383
384 /* Restart link */
385 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
386 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
387
388 /* Only poll for autoneg to complete if specified to do so */
389 if (hw->phy.autoneg_wait_to_complete) {
390 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
391 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
392 links_reg = 0; /* Just in case Autoneg time = 0 */
393 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
394 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
395 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
396 break;
397 msleep(100);
398 }
399 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
400 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
401 hw_dbg(hw, "Autonegotiation did not complete.\n");
402 }
403 }
404 }
405
406 /*
407 * We want to save off the original Flow Control configuration just in
408 * case we get disconnected and then reconnected into a different hub
409 * or switch with different Flow Control capabilities.
410 */
411 hw->fc.original_type = hw->fc.type;
412 ixgbe_setup_fc_82598(hw, 0);
413
414 /* Add delay to filter out noises during initial link setup */
415 msleep(50);
416
417 return status;
418 }
419
420 /**
421 * ixgbe_check_mac_link_82598 - Get link/speed status
422 * @hw: pointer to hardware structure
423 * @speed: pointer to link speed
424 * @link_up: true is link is up, false otherwise
425 * @link_up_wait_to_complete: bool used to wait for link up or not
426 *
427 * Reads the links register to determine if link is up and the current speed
428 **/
429 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
430 ixgbe_link_speed *speed, bool *link_up,
431 bool link_up_wait_to_complete)
432 {
433 u32 links_reg;
434 u32 i;
435 u16 link_reg, adapt_comp_reg;
436
437 /*
438 * SERDES PHY requires us to read link status from register 0xC79F.
439 * Bit 0 set indicates link is up/ready; clear indicates link down.
440 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
441 * clear indicates active; set indicates inactive.
442 */
443 if (hw->phy.type == ixgbe_phy_nl) {
444 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
445 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
446 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
447 &adapt_comp_reg);
448 if (link_up_wait_to_complete) {
449 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
450 if ((link_reg & 1) &&
451 ((adapt_comp_reg & 1) == 0)) {
452 *link_up = true;
453 break;
454 } else {
455 *link_up = false;
456 }
457 msleep(100);
458 hw->phy.ops.read_reg(hw, 0xC79F,
459 IXGBE_TWINAX_DEV,
460 &link_reg);
461 hw->phy.ops.read_reg(hw, 0xC00C,
462 IXGBE_TWINAX_DEV,
463 &adapt_comp_reg);
464 }
465 } else {
466 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
467 *link_up = true;
468 else
469 *link_up = false;
470 }
471
472 if (*link_up == false)
473 goto out;
474 }
475
476 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
477 if (link_up_wait_to_complete) {
478 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
479 if (links_reg & IXGBE_LINKS_UP) {
480 *link_up = true;
481 break;
482 } else {
483 *link_up = false;
484 }
485 msleep(100);
486 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
487 }
488 } else {
489 if (links_reg & IXGBE_LINKS_UP)
490 *link_up = true;
491 else
492 *link_up = false;
493 }
494
495 if (links_reg & IXGBE_LINKS_SPEED)
496 *speed = IXGBE_LINK_SPEED_10GB_FULL;
497 else
498 *speed = IXGBE_LINK_SPEED_1GB_FULL;
499
500 out:
501 return 0;
502 }
503
504
505 /**
506 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
507 * @hw: pointer to hardware structure
508 * @speed: new link speed
509 * @autoneg: true if auto-negotiation enabled
510 * @autoneg_wait_to_complete: true if waiting is needed to complete
511 *
512 * Set the link speed in the AUTOC register and restarts link.
513 **/
514 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
515 ixgbe_link_speed speed, bool autoneg,
516 bool autoneg_wait_to_complete)
517 {
518 s32 status = 0;
519
520 /* If speed is 10G, then check for CX4 or XAUI. */
521 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
522 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4))) {
523 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
524 } else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg)) {
525 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
526 } else if (autoneg) {
527 /* BX mode - Autonegotiate 1G */
528 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
529 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
530 else /* KX/KX4 mode */
531 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
532 } else {
533 status = IXGBE_ERR_LINK_SETUP;
534 }
535
536 if (status == 0) {
537 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
538
539 hw->mac.link_settings_loaded = true;
540 /*
541 * Setup and restart the link based on the new values in
542 * ixgbe_hw This will write the AUTOC register based on the new
543 * stored values
544 */
545 ixgbe_setup_mac_link_82598(hw);
546 }
547
548 return status;
549 }
550
551
552 /**
553 * ixgbe_setup_copper_link_82598 - Setup copper link settings
554 * @hw: pointer to hardware structure
555 *
556 * Configures link settings based on values in the ixgbe_hw struct.
557 * Restarts the link. Performs autonegotiation if needed. Restart
558 * phy and wait for autonegotiate to finish. Then synchronize the
559 * MAC and PHY.
560 **/
561 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
562 {
563 s32 status;
564
565 /* Restart autonegotiation on PHY */
566 status = hw->phy.ops.setup_link(hw);
567
568 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
569 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
570 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
571
572 /* Set up MAC */
573 ixgbe_setup_mac_link_82598(hw);
574
575 return status;
576 }
577
578 /**
579 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
580 * @hw: pointer to hardware structure
581 * @speed: new link speed
582 * @autoneg: true if autonegotiation enabled
583 * @autoneg_wait_to_complete: true if waiting is needed to complete
584 *
585 * Sets the link speed in the AUTOC register in the MAC and restarts link.
586 **/
587 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
588 ixgbe_link_speed speed,
589 bool autoneg,
590 bool autoneg_wait_to_complete)
591 {
592 s32 status;
593
594 /* Setup the PHY according to input speed */
595 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
596 autoneg_wait_to_complete);
597
598 /* Set MAC to KX/KX4 autoneg, which defaults to Parallel detection */
599 hw->mac.link_attach_type = (IXGBE_AUTOC_10G_KX4 | IXGBE_AUTOC_1G_KX);
600 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN;
601
602 /* Set up MAC */
603 ixgbe_setup_mac_link_82598(hw);
604
605 return status;
606 }
607
608 /**
609 * ixgbe_reset_hw_82598 - Performs hardware reset
610 * @hw: pointer to hardware structure
611 *
612 * Resets the hardware by resetting the transmit and receive units, masks and
613 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
614 * reset.
615 **/
616 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
617 {
618 s32 status = 0;
619 u32 ctrl;
620 u32 gheccr;
621 u32 i;
622 u32 autoc;
623 u8 analog_val;
624
625 /* Call adapter stop to disable tx/rx and clear interrupts */
626 hw->mac.ops.stop_adapter(hw);
627
628 /*
629 * Power up the Atlas Tx lanes if they are currently powered down.
630 * Atlas Tx lanes are powered down for MAC loopback tests, but
631 * they are not automatically restored on reset.
632 */
633 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
634 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
635 /* Enable Tx Atlas so packets can be transmitted again */
636 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
637 &analog_val);
638 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
639 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
640 analog_val);
641
642 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
643 &analog_val);
644 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
645 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
646 analog_val);
647
648 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
649 &analog_val);
650 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
651 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
652 analog_val);
653
654 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
655 &analog_val);
656 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
657 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
658 analog_val);
659 }
660
661 /* Reset PHY */
662 if (hw->phy.reset_disable == false)
663 hw->phy.ops.reset(hw);
664
665 /*
666 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
667 * access and verify no pending requests before reset
668 */
669 if (ixgbe_disable_pcie_master(hw) != 0) {
670 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
671 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
672 }
673
674 /*
675 * Issue global reset to the MAC. This needs to be a SW reset.
676 * If link reset is used, it might reset the MAC when mng is using it
677 */
678 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
679 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
680 IXGBE_WRITE_FLUSH(hw);
681
682 /* Poll for reset bit to self-clear indicating reset is complete */
683 for (i = 0; i < 10; i++) {
684 udelay(1);
685 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
686 if (!(ctrl & IXGBE_CTRL_RST))
687 break;
688 }
689 if (ctrl & IXGBE_CTRL_RST) {
690 status = IXGBE_ERR_RESET_FAILED;
691 hw_dbg(hw, "Reset polling failed to complete.\n");
692 }
693
694 msleep(50);
695
696 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
697 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
698 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
699
700 /*
701 * AUTOC register which stores link settings gets cleared
702 * and reloaded from EEPROM after reset. We need to restore
703 * our stored value from init in case SW changed the attach
704 * type or speed. If this is the first time and link settings
705 * have not been stored, store default settings from AUTOC.
706 */
707 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
708 if (hw->mac.link_settings_loaded) {
709 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
710 autoc &= ~(IXGBE_AUTOC_LMS_MASK);
711 autoc |= hw->mac.link_attach_type;
712 autoc |= hw->mac.link_mode_select;
713 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
714 } else {
715 hw->mac.link_attach_type =
716 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
717 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
718 hw->mac.link_settings_loaded = true;
719 }
720
721 /* Store the permanent mac address */
722 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
723
724 return status;
725 }
726
727 /**
728 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
729 * @hw: pointer to hardware struct
730 * @rar: receive address register index to associate with a VMDq index
731 * @vmdq: VMDq set index
732 **/
733 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
734 {
735 u32 rar_high;
736
737 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
738 rar_high &= ~IXGBE_RAH_VIND_MASK;
739 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
740 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
741 return 0;
742 }
743
744 /**
745 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
746 * @hw: pointer to hardware struct
747 * @rar: receive address register index to associate with a VMDq index
748 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
749 **/
750 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
751 {
752 u32 rar_high;
753 u32 rar_entries = hw->mac.num_rar_entries;
754
755 if (rar < rar_entries) {
756 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
757 if (rar_high & IXGBE_RAH_VIND_MASK) {
758 rar_high &= ~IXGBE_RAH_VIND_MASK;
759 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
760 }
761 } else {
762 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
763 }
764
765 return 0;
766 }
767
768 /**
769 * ixgbe_set_vfta_82598 - Set VLAN filter table
770 * @hw: pointer to hardware structure
771 * @vlan: VLAN id to write to VLAN filter
772 * @vind: VMDq output index that maps queue to VLAN id in VFTA
773 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
774 *
775 * Turn on/off specified VLAN in the VLAN filter table.
776 **/
777 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
778 bool vlan_on)
779 {
780 u32 regindex;
781 u32 bitindex;
782 u32 bits;
783 u32 vftabyte;
784
785 if (vlan > 4095)
786 return IXGBE_ERR_PARAM;
787
788 /* Determine 32-bit word position in array */
789 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
790
791 /* Determine the location of the (VMD) queue index */
792 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
793 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
794
795 /* Set the nibble for VMD queue index */
796 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
797 bits &= (~(0x0F << bitindex));
798 bits |= (vind << bitindex);
799 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
800
801 /* Determine the location of the bit for this VLAN id */
802 bitindex = vlan & 0x1F; /* lower five bits */
803
804 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
805 if (vlan_on)
806 /* Turn on this VLAN id */
807 bits |= (1 << bitindex);
808 else
809 /* Turn off this VLAN id */
810 bits &= ~(1 << bitindex);
811 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
812
813 return 0;
814 }
815
816 /**
817 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
818 * @hw: pointer to hardware structure
819 *
820 * Clears the VLAN filer table, and the VMDq index associated with the filter
821 **/
822 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
823 {
824 u32 offset;
825 u32 vlanbyte;
826
827 for (offset = 0; offset < hw->mac.vft_size; offset++)
828 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
829
830 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
831 for (offset = 0; offset < hw->mac.vft_size; offset++)
832 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
833 0);
834
835 return 0;
836 }
837
838 /**
839 * ixgbe_blink_led_start_82598 - Blink LED based on index.
840 * @hw: pointer to hardware structure
841 * @index: led number to blink
842 **/
843 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
844 {
845 ixgbe_link_speed speed = 0;
846 bool link_up = 0;
847 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
848 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
849
850 /*
851 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
852 * force it if link is down.
853 */
854 hw->mac.ops.check_link(hw, &speed, &link_up, false);
855
856 if (!link_up) {
857 autoc_reg |= IXGBE_AUTOC_FLU;
858 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
859 msleep(10);
860 }
861
862 led_reg &= ~IXGBE_LED_MODE_MASK(index);
863 led_reg |= IXGBE_LED_BLINK(index);
864 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
865 IXGBE_WRITE_FLUSH(hw);
866
867 return 0;
868 }
869
870 /**
871 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
872 * @hw: pointer to hardware structure
873 * @index: led number to stop blinking
874 **/
875 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
876 {
877 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
878 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
879
880 autoc_reg &= ~IXGBE_AUTOC_FLU;
881 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
882 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
883
884 led_reg &= ~IXGBE_LED_MODE_MASK(index);
885 led_reg &= ~IXGBE_LED_BLINK(index);
886 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
887 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
888 IXGBE_WRITE_FLUSH(hw);
889
890 return 0;
891 }
892
893 /**
894 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
895 * @hw: pointer to hardware structure
896 * @reg: analog register to read
897 * @val: read value
898 *
899 * Performs read operation to Atlas analog register specified.
900 **/
901 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
902 {
903 u32 atlas_ctl;
904
905 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
906 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
907 IXGBE_WRITE_FLUSH(hw);
908 udelay(10);
909 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
910 *val = (u8)atlas_ctl;
911
912 return 0;
913 }
914
915 /**
916 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
917 * @hw: pointer to hardware structure
918 * @reg: atlas register to write
919 * @val: value to write
920 *
921 * Performs write operation to Atlas analog register specified.
922 **/
923 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
924 {
925 u32 atlas_ctl;
926
927 atlas_ctl = (reg << 8) | val;
928 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
929 IXGBE_WRITE_FLUSH(hw);
930 udelay(10);
931
932 return 0;
933 }
934
935 /**
936 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
937 * over I2C interface through an intermediate phy.
938 * @hw: pointer to hardware structure
939 * @byte_offset: EEPROM byte offset to read
940 * @eeprom_data: value read
941 *
942 * Performs byte read operation to SFP module's EEPROM over I2C interface.
943 **/
944 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
945 u8 *eeprom_data)
946 {
947 s32 status = 0;
948 u16 sfp_addr = 0;
949 u16 sfp_data = 0;
950 u16 sfp_stat = 0;
951 u32 i;
952
953 if (hw->phy.type == ixgbe_phy_nl) {
954 /*
955 * phy SDA/SCL registers are at addresses 0xC30A to
956 * 0xC30D. These registers are used to talk to the SFP+
957 * module's EEPROM through the SDA/SCL (I2C) interface.
958 */
959 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
960 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
961 hw->phy.ops.write_reg(hw,
962 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
963 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
964 sfp_addr);
965
966 /* Poll status */
967 for (i = 0; i < 100; i++) {
968 hw->phy.ops.read_reg(hw,
969 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
970 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
971 &sfp_stat);
972 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
973 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
974 break;
975 msleep(10);
976 }
977
978 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
979 hw_dbg(hw, "EEPROM read did not pass.\n");
980 status = IXGBE_ERR_SFP_NOT_PRESENT;
981 goto out;
982 }
983
984 /* Read data */
985 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
986 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
987
988 *eeprom_data = (u8)(sfp_data >> 8);
989 } else {
990 status = IXGBE_ERR_PHY;
991 goto out;
992 }
993
994 out:
995 return status;
996 }
997
998 /**
999 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1000 * @hw: pointer to hardware structure
1001 *
1002 * Determines physical layer capabilities of the current configuration.
1003 **/
1004 static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1005 {
1006 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1007
1008 switch (hw->device_id) {
1009 case IXGBE_DEV_ID_82598:
1010 /* Default device ID is mezzanine card KX/KX4 */
1011 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1012 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1013 break;
1014 case IXGBE_DEV_ID_82598_BX:
1015 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1016 case IXGBE_DEV_ID_82598EB_CX4:
1017 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1018 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1019 break;
1020 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1021 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1022 break;
1023 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1024 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1025 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1026 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1027 break;
1028 case IXGBE_DEV_ID_82598EB_XF_LR:
1029 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1030 break;
1031 case IXGBE_DEV_ID_82598AT:
1032 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1033 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1034 break;
1035 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1036 hw->phy.ops.identify_sfp(hw);
1037
1038 switch (hw->phy.sfp_type) {
1039 case ixgbe_sfp_type_da_cu:
1040 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1041 break;
1042 case ixgbe_sfp_type_sr:
1043 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1044 break;
1045 case ixgbe_sfp_type_lr:
1046 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1047 break;
1048 default:
1049 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1050 break;
1051 }
1052 break;
1053
1054 default:
1055 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1056 break;
1057 }
1058
1059 return physical_layer;
1060 }
1061
1062 static struct ixgbe_mac_operations mac_ops_82598 = {
1063 .init_hw = &ixgbe_init_hw_generic,
1064 .reset_hw = &ixgbe_reset_hw_82598,
1065 .start_hw = &ixgbe_start_hw_generic,
1066 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1067 .get_media_type = &ixgbe_get_media_type_82598,
1068 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1069 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1070 .stop_adapter = &ixgbe_stop_adapter_generic,
1071 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1072 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1073 .setup_link = &ixgbe_setup_mac_link_82598,
1074 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
1075 .check_link = &ixgbe_check_mac_link_82598,
1076 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1077 .led_on = &ixgbe_led_on_generic,
1078 .led_off = &ixgbe_led_off_generic,
1079 .blink_led_start = &ixgbe_blink_led_start_82598,
1080 .blink_led_stop = &ixgbe_blink_led_stop_82598,
1081 .set_rar = &ixgbe_set_rar_generic,
1082 .clear_rar = &ixgbe_clear_rar_generic,
1083 .set_vmdq = &ixgbe_set_vmdq_82598,
1084 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1085 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1086 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1087 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1088 .enable_mc = &ixgbe_enable_mc_generic,
1089 .disable_mc = &ixgbe_disable_mc_generic,
1090 .clear_vfta = &ixgbe_clear_vfta_82598,
1091 .set_vfta = &ixgbe_set_vfta_82598,
1092 .setup_fc = &ixgbe_setup_fc_82598,
1093 };
1094
1095 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1096 .init_params = &ixgbe_init_eeprom_params_generic,
1097 .read = &ixgbe_read_eeprom_generic,
1098 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1099 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1100 };
1101
1102 static struct ixgbe_phy_operations phy_ops_82598 = {
1103 .identify = &ixgbe_identify_phy_generic,
1104 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1105 .reset = &ixgbe_reset_phy_generic,
1106 .read_reg = &ixgbe_read_phy_reg_generic,
1107 .write_reg = &ixgbe_write_phy_reg_generic,
1108 .setup_link = &ixgbe_setup_phy_link_generic,
1109 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1110 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1111 };
1112
1113 struct ixgbe_info ixgbe_82598_info = {
1114 .mac = ixgbe_mac_82598EB,
1115 .get_invariants = &ixgbe_get_invariants_82598,
1116 .mac_ops = &mac_ops_82598,
1117 .eeprom_ops = &eeprom_ops_82598,
1118 .phy_ops = &phy_ops_82598,
1119 };
1120
Support for the Chinese Samsung S3C2440 based development boards