1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
43 * 82567LM-2 Gigabit Network Connection
44 * 82567LF-2 Gigabit Network Connection
45 * 82567V-2 Gigabit Network Connection
46 * 82562GT-3 10/100 Network Connection
47 * 82567LM-4 Gigabit Network Connection
50 #include <linux/netdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/delay.h>
53 #include <linux/pci.h>
57 #define ICH_FLASH_GFPREG 0x0000
58 #define ICH_FLASH_HSFSTS 0x0004
59 #define ICH_FLASH_HSFCTL 0x0006
60 #define ICH_FLASH_FADDR 0x0008
61 #define ICH_FLASH_FDATA0 0x0010
63 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
64 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
65 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
66 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
67 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
69 #define ICH_CYCLE_READ 0
70 #define ICH_CYCLE_WRITE 2
71 #define ICH_CYCLE_ERASE 3
73 #define FLASH_GFPREG_BASE_MASK 0x1FFF
74 #define FLASH_SECTOR_ADDR_SHIFT 12
76 #define ICH_FLASH_SEG_SIZE_256 256
77 #define ICH_FLASH_SEG_SIZE_4K 4096
78 #define ICH_FLASH_SEG_SIZE_8K 8192
79 #define ICH_FLASH_SEG_SIZE_64K 65536
82 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
84 #define E1000_ICH_MNG_IAMT_MODE 0x2
86 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
87 (ID_LED_DEF1_OFF2 << 8) | \
88 (ID_LED_DEF1_ON2 << 4) | \
91 #define E1000_ICH_NVM_SIG_WORD 0x13
92 #define E1000_ICH_NVM_SIG_MASK 0xC000
94 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
96 #define E1000_FEXTNVM_SW_CONFIG 1
97 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
99 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
101 #define E1000_ICH_RAR_ENTRIES 7
103 #define PHY_PAGE_SHIFT 5
104 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
105 ((reg) & MAX_PHY_REG_ADDRESS))
106 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
107 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
109 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
110 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
111 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
113 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
114 /* Offset 04h HSFSTS */
115 union ich8_hws_flash_status
{
117 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
118 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
119 u16 dael
:1; /* bit 2 Direct Access error Log */
120 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
121 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
122 u16 reserved1
:2; /* bit 13:6 Reserved */
123 u16 reserved2
:6; /* bit 13:6 Reserved */
124 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
125 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
130 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
131 /* Offset 06h FLCTL */
132 union ich8_hws_flash_ctrl
{
133 struct ich8_hsflctl
{
134 u16 flcgo
:1; /* 0 Flash Cycle Go */
135 u16 flcycle
:2; /* 2:1 Flash Cycle */
136 u16 reserved
:5; /* 7:3 Reserved */
137 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
138 u16 flockdn
:6; /* 15:10 Reserved */
143 /* ICH Flash Region Access Permissions */
144 union ich8_hws_flash_regacc
{
146 u32 grra
:8; /* 0:7 GbE region Read Access */
147 u32 grwa
:8; /* 8:15 GbE region Write Access */
148 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
149 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
154 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
155 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
156 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
157 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
);
158 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
159 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
160 u32 offset
, u8 byte
);
161 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
163 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
165 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
166 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
168 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
170 return readw(hw
->flash_address
+ reg
);
173 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
175 return readl(hw
->flash_address
+ reg
);
178 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
180 writew(val
, hw
->flash_address
+ reg
);
183 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
185 writel(val
, hw
->flash_address
+ reg
);
188 #define er16flash(reg) __er16flash(hw, (reg))
189 #define er32flash(reg) __er32flash(hw, (reg))
190 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
191 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
194 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
195 * @hw: pointer to the HW structure
197 * Initialize family-specific PHY parameters and function pointers.
199 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
201 struct e1000_phy_info
*phy
= &hw
->phy
;
206 phy
->reset_delay_us
= 100;
209 * We may need to do this twice - once for IGP and if that fails,
210 * we'll set BM func pointers and try again
212 ret_val
= e1000e_determine_phy_address(hw
);
214 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
215 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
216 ret_val
= e1000e_determine_phy_address(hw
);
222 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
225 ret_val
= e1000e_get_phy_id(hw
);
232 case IGP03E1000_E_PHY_ID
:
233 phy
->type
= e1000_phy_igp_3
;
234 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
237 case IFE_PLUS_E_PHY_ID
:
239 phy
->type
= e1000_phy_ife
;
240 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
242 case BME1000_E_PHY_ID
:
243 phy
->type
= e1000_phy_bm
;
244 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
245 hw
->phy
.ops
.read_phy_reg
= e1000e_read_phy_reg_bm
;
246 hw
->phy
.ops
.write_phy_reg
= e1000e_write_phy_reg_bm
;
247 hw
->phy
.ops
.commit_phy
= e1000e_phy_sw_reset
;
250 return -E1000_ERR_PHY
;
258 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
259 * @hw: pointer to the HW structure
261 * Initialize family-specific NVM parameters and function
264 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
266 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
267 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
269 u32 sector_base_addr
;
273 /* Can't read flash registers if the register set isn't mapped. */
274 if (!hw
->flash_address
) {
275 hw_dbg(hw
, "ERROR: Flash registers not mapped\n");
276 return -E1000_ERR_CONFIG
;
279 nvm
->type
= e1000_nvm_flash_sw
;
281 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
284 * sector_X_addr is a "sector"-aligned address (4096 bytes)
285 * Add 1 to sector_end_addr since this sector is included in
288 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
289 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
291 /* flash_base_addr is byte-aligned */
292 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
295 * find total size of the NVM, then cut in half since the total
296 * size represents two separate NVM banks.
298 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
299 << FLASH_SECTOR_ADDR_SHIFT
;
300 nvm
->flash_bank_size
/= 2;
301 /* Adjust to word count */
302 nvm
->flash_bank_size
/= sizeof(u16
);
304 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
306 /* Clear shadow ram */
307 for (i
= 0; i
< nvm
->word_size
; i
++) {
308 dev_spec
->shadow_ram
[i
].modified
= 0;
309 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
316 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
317 * @hw: pointer to the HW structure
319 * Initialize family-specific MAC parameters and function
322 static s32
e1000_init_mac_params_ich8lan(struct e1000_adapter
*adapter
)
324 struct e1000_hw
*hw
= &adapter
->hw
;
325 struct e1000_mac_info
*mac
= &hw
->mac
;
327 /* Set media type function pointer */
328 hw
->phy
.media_type
= e1000_media_type_copper
;
330 /* Set mta register count */
331 mac
->mta_reg_count
= 32;
332 /* Set rar entry count */
333 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
334 if (mac
->type
== e1000_ich8lan
)
335 mac
->rar_entry_count
--;
336 /* Set if manageability features are enabled. */
337 mac
->arc_subsystem_valid
= 1;
339 /* Enable PCS Lock-loss workaround for ICH8 */
340 if (mac
->type
== e1000_ich8lan
)
341 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, 1);
346 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
348 struct e1000_hw
*hw
= &adapter
->hw
;
351 rc
= e1000_init_mac_params_ich8lan(adapter
);
355 rc
= e1000_init_nvm_params_ich8lan(hw
);
359 rc
= e1000_init_phy_params_ich8lan(hw
);
363 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
364 (adapter
->hw
.phy
.type
== e1000_phy_igp_3
))
365 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
371 * e1000_acquire_swflag_ich8lan - Acquire software control flag
372 * @hw: pointer to the HW structure
374 * Acquires the software control flag for performing NVM and PHY
375 * operations. This is a function pointer entry point only called by
376 * read/write routines for the PHY and NVM parts.
378 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
381 u32 timeout
= PHY_CFG_TIMEOUT
;
384 extcnf_ctrl
= er32(EXTCNF_CTRL
);
385 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
386 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
388 extcnf_ctrl
= er32(EXTCNF_CTRL
);
389 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
396 hw_dbg(hw
, "FW or HW has locked the resource for too long.\n");
397 return -E1000_ERR_CONFIG
;
404 * e1000_release_swflag_ich8lan - Release software control flag
405 * @hw: pointer to the HW structure
407 * Releases the software control flag for performing NVM and PHY operations.
408 * This is a function pointer entry point only called by read/write
409 * routines for the PHY and NVM parts.
411 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
415 extcnf_ctrl
= er32(EXTCNF_CTRL
);
416 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
417 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
421 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
422 * @hw: pointer to the HW structure
424 * Checks if firmware is blocking the reset of the PHY.
425 * This is a function pointer entry point only called by
428 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
434 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
438 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
439 * @hw: pointer to the HW structure
441 * Forces the speed and duplex settings of the PHY.
442 * This is a function pointer entry point only called by
443 * PHY setup routines.
445 static s32
e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw
*hw
)
447 struct e1000_phy_info
*phy
= &hw
->phy
;
452 if (phy
->type
!= e1000_phy_ife
) {
453 ret_val
= e1000e_phy_force_speed_duplex_igp(hw
);
457 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
461 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
463 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
467 /* Disable MDI-X support for 10/100 */
468 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
472 data
&= ~IFE_PMC_AUTO_MDIX
;
473 data
&= ~IFE_PMC_FORCE_MDIX
;
475 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
479 hw_dbg(hw
, "IFE PMC: %X\n", data
);
483 if (phy
->autoneg_wait_to_complete
) {
484 hw_dbg(hw
, "Waiting for forced speed/duplex link on IFE phy.\n");
486 ret_val
= e1000e_phy_has_link_generic(hw
,
494 hw_dbg(hw
, "Link taking longer than expected.\n");
497 ret_val
= e1000e_phy_has_link_generic(hw
,
509 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
510 * @hw: pointer to the HW structure
513 * This is a function pointer entry point called by drivers
514 * or other shared routines.
516 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
518 struct e1000_phy_info
*phy
= &hw
->phy
;
520 u32 data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
522 u16 loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
523 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
525 ret_val
= e1000e_phy_hw_reset_generic(hw
);
530 * Initialize the PHY from the NVM on ICH platforms. This
531 * is needed due to an issue where the NVM configuration is
532 * not properly autoloaded after power transitions.
533 * Therefore, after each PHY reset, we will load the
534 * configuration data out of the NVM manually.
536 if (hw
->mac
.type
== e1000_ich8lan
&& phy
->type
== e1000_phy_igp_3
) {
537 struct e1000_adapter
*adapter
= hw
->adapter
;
539 /* Check if SW needs configure the PHY */
540 if ((adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M_AMT
) ||
541 (adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_M
))
542 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
544 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
546 data
= er32(FEXTNVM
);
547 if (!(data
& sw_cfg_mask
))
550 /* Wait for basic configuration completes before proceeding*/
553 data
&= E1000_STATUS_LAN_INIT_DONE
;
555 } while ((!data
) && --loop
);
558 * If basic configuration is incomplete before the above loop
559 * count reaches 0, loading the configuration from NVM will
560 * leave the PHY in a bad state possibly resulting in no link.
563 hw_dbg(hw
, "LAN_INIT_DONE not set, increase timeout\n");
566 /* Clear the Init Done bit for the next init event */
568 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
572 * Make sure HW does not configure LCD from PHY
573 * extended configuration before SW configuration
575 data
= er32(EXTCNF_CTRL
);
576 if (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
)
579 cnf_size
= er32(EXTCNF_SIZE
);
580 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
581 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
585 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
586 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
588 /* Configure LCD from extended configuration region. */
590 /* cnf_base_addr is in DWORD */
591 word_addr
= (u16
)(cnf_base_addr
<< 1);
593 for (i
= 0; i
< cnf_size
; i
++) {
594 ret_val
= e1000_read_nvm(hw
,
601 ret_val
= e1000_read_nvm(hw
,
602 (word_addr
+ i
* 2 + 1),
608 /* Save off the PHY page for future writes. */
609 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
614 reg_addr
|= phy_page
;
616 ret_val
= e1e_wphy(hw
, (u32
)reg_addr
, reg_data
);
626 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
627 * @hw: pointer to the HW structure
629 * Populates "phy" structure with various feature states.
630 * This function is only called by other family-specific
633 static s32
e1000_get_phy_info_ife_ich8lan(struct e1000_hw
*hw
)
635 struct e1000_phy_info
*phy
= &hw
->phy
;
640 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
645 hw_dbg(hw
, "Phy info is only valid if link is up\n");
646 return -E1000_ERR_CONFIG
;
649 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
652 phy
->polarity_correction
= (!(data
& IFE_PSC_AUTO_POLARITY_DISABLE
));
654 if (phy
->polarity_correction
) {
655 ret_val
= e1000_check_polarity_ife_ich8lan(hw
);
659 /* Polarity is forced */
660 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
661 ? e1000_rev_polarity_reversed
662 : e1000_rev_polarity_normal
;
665 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
669 phy
->is_mdix
= (data
& IFE_PMC_MDIX_STATUS
);
671 /* The following parameters are undefined for 10/100 operation. */
672 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
673 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
674 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
680 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
681 * @hw: pointer to the HW structure
683 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
684 * This is a function pointer entry point called by drivers
685 * or other shared routines.
687 static s32
e1000_get_phy_info_ich8lan(struct e1000_hw
*hw
)
689 switch (hw
->phy
.type
) {
691 return e1000_get_phy_info_ife_ich8lan(hw
);
693 case e1000_phy_igp_3
:
695 return e1000e_get_phy_info_igp(hw
);
701 return -E1000_ERR_PHY_TYPE
;
705 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
706 * @hw: pointer to the HW structure
708 * Polarity is determined on the polarity reversal feature being enabled.
709 * This function is only called by other family-specific
712 static s32
e1000_check_polarity_ife_ich8lan(struct e1000_hw
*hw
)
714 struct e1000_phy_info
*phy
= &hw
->phy
;
716 u16 phy_data
, offset
, mask
;
719 * Polarity is determined based on the reversal feature being enabled.
721 if (phy
->polarity_correction
) {
722 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
723 mask
= IFE_PESC_POLARITY_REVERSED
;
725 offset
= IFE_PHY_SPECIAL_CONTROL
;
726 mask
= IFE_PSC_FORCE_POLARITY
;
729 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
732 phy
->cable_polarity
= (phy_data
& mask
)
733 ? e1000_rev_polarity_reversed
734 : e1000_rev_polarity_normal
;
740 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
741 * @hw: pointer to the HW structure
742 * @active: TRUE to enable LPLU, FALSE to disable
744 * Sets the LPLU D0 state according to the active flag. When
745 * activating LPLU this function also disables smart speed
746 * and vice versa. LPLU will not be activated unless the
747 * device autonegotiation advertisement meets standards of
748 * either 10 or 10/100 or 10/100/1000 at all duplexes.
749 * This is a function pointer entry point only called by
750 * PHY setup routines.
752 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
754 struct e1000_phy_info
*phy
= &hw
->phy
;
759 if (phy
->type
== e1000_phy_ife
)
762 phy_ctrl
= er32(PHY_CTRL
);
765 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
766 ew32(PHY_CTRL
, phy_ctrl
);
769 * Call gig speed drop workaround on LPLU before accessing
772 if ((hw
->mac
.type
== e1000_ich8lan
) &&
773 (hw
->phy
.type
== e1000_phy_igp_3
))
774 e1000e_gig_downshift_workaround_ich8lan(hw
);
776 /* When LPLU is enabled, we should disable SmartSpeed */
777 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
778 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
779 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
783 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
784 ew32(PHY_CTRL
, phy_ctrl
);
787 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
788 * during Dx states where the power conservation is most
789 * important. During driver activity we should enable
790 * SmartSpeed, so performance is maintained.
792 if (phy
->smart_speed
== e1000_smart_speed_on
) {
793 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
798 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
799 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
803 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
804 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
809 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
810 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
821 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
822 * @hw: pointer to the HW structure
823 * @active: TRUE to enable LPLU, FALSE to disable
825 * Sets the LPLU D3 state according to the active flag. When
826 * activating LPLU this function also disables smart speed
827 * and vice versa. LPLU will not be activated unless the
828 * device autonegotiation advertisement meets standards of
829 * either 10 or 10/100 or 10/100/1000 at all duplexes.
830 * This is a function pointer entry point only called by
831 * PHY setup routines.
833 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
835 struct e1000_phy_info
*phy
= &hw
->phy
;
840 phy_ctrl
= er32(PHY_CTRL
);
843 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
844 ew32(PHY_CTRL
, phy_ctrl
);
846 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
847 * during Dx states where the power conservation is most
848 * important. During driver activity we should enable
849 * SmartSpeed, so performance is maintained.
851 if (phy
->smart_speed
== e1000_smart_speed_on
) {
852 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
857 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
858 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
862 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
863 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
868 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
869 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
874 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
875 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
876 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
877 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
878 ew32(PHY_CTRL
, phy_ctrl
);
881 * Call gig speed drop workaround on LPLU before accessing
884 if ((hw
->mac
.type
== e1000_ich8lan
) &&
885 (hw
->phy
.type
== e1000_phy_igp_3
))
886 e1000e_gig_downshift_workaround_ich8lan(hw
);
888 /* When LPLU is enabled, we should disable SmartSpeed */
889 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
893 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
894 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
901 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
902 * @hw: pointer to the HW structure
903 * @offset: The offset (in bytes) of the word(s) to read.
904 * @words: Size of data to read in words
905 * @data: Pointer to the word(s) to read at offset.
907 * Reads a word(s) from the NVM using the flash access registers.
909 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
912 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
913 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
918 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
920 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
921 return -E1000_ERR_NVM
;
924 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
928 /* Start with the bank offset, then add the relative offset. */
929 act_offset
= (er32(EECD
) & E1000_EECD_SEC1VAL
)
930 ? nvm
->flash_bank_size
932 act_offset
+= offset
;
934 for (i
= 0; i
< words
; i
++) {
935 if ((dev_spec
->shadow_ram
) &&
936 (dev_spec
->shadow_ram
[offset
+i
].modified
)) {
937 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
939 ret_val
= e1000_read_flash_word_ich8lan(hw
,
948 e1000_release_swflag_ich8lan(hw
);
954 * e1000_flash_cycle_init_ich8lan - Initialize flash
955 * @hw: pointer to the HW structure
957 * This function does initial flash setup so that a new read/write/erase cycle
960 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
962 union ich8_hws_flash_status hsfsts
;
963 s32 ret_val
= -E1000_ERR_NVM
;
966 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
968 /* Check if the flash descriptor is valid */
969 if (hsfsts
.hsf_status
.fldesvalid
== 0) {
970 hw_dbg(hw
, "Flash descriptor invalid. "
971 "SW Sequencing must be used.");
972 return -E1000_ERR_NVM
;
975 /* Clear FCERR and DAEL in hw status by writing 1 */
976 hsfsts
.hsf_status
.flcerr
= 1;
977 hsfsts
.hsf_status
.dael
= 1;
979 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
982 * Either we should have a hardware SPI cycle in progress
983 * bit to check against, in order to start a new cycle or
984 * FDONE bit should be changed in the hardware so that it
985 * is 1 after hardware reset, which can then be used as an
986 * indication whether a cycle is in progress or has been
990 if (hsfsts
.hsf_status
.flcinprog
== 0) {
992 * There is no cycle running at present,
993 * so we can start a cycle
994 * Begin by setting Flash Cycle Done.
996 hsfsts
.hsf_status
.flcdone
= 1;
997 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1001 * otherwise poll for sometime so the current
1002 * cycle has a chance to end before giving up.
1004 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
1005 hsfsts
.regval
= __er16flash(hw
, ICH_FLASH_HSFSTS
);
1006 if (hsfsts
.hsf_status
.flcinprog
== 0) {
1014 * Successful in waiting for previous cycle to timeout,
1015 * now set the Flash Cycle Done.
1017 hsfsts
.hsf_status
.flcdone
= 1;
1018 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
1020 hw_dbg(hw
, "Flash controller busy, cannot get access");
1028 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1029 * @hw: pointer to the HW structure
1030 * @timeout: maximum time to wait for completion
1032 * This function starts a flash cycle and waits for its completion.
1034 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
1036 union ich8_hws_flash_ctrl hsflctl
;
1037 union ich8_hws_flash_status hsfsts
;
1038 s32 ret_val
= -E1000_ERR_NVM
;
1041 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1042 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1043 hsflctl
.hsf_ctrl
.flcgo
= 1;
1044 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1046 /* wait till FDONE bit is set to 1 */
1048 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1049 if (hsfsts
.hsf_status
.flcdone
== 1)
1052 } while (i
++ < timeout
);
1054 if (hsfsts
.hsf_status
.flcdone
== 1 && hsfsts
.hsf_status
.flcerr
== 0)
1061 * e1000_read_flash_word_ich8lan - Read word from flash
1062 * @hw: pointer to the HW structure
1063 * @offset: offset to data location
1064 * @data: pointer to the location for storing the data
1066 * Reads the flash word at offset into data. Offset is converted
1067 * to bytes before read.
1069 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1072 /* Must convert offset into bytes. */
1075 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
1079 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1080 * @hw: pointer to the HW structure
1081 * @offset: The offset (in bytes) of the byte or word to read.
1082 * @size: Size of data to read, 1=byte 2=word
1083 * @data: Pointer to the word to store the value read.
1085 * Reads a byte or word from the NVM using the flash access registers.
1087 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1090 union ich8_hws_flash_status hsfsts
;
1091 union ich8_hws_flash_ctrl hsflctl
;
1092 u32 flash_linear_addr
;
1094 s32 ret_val
= -E1000_ERR_NVM
;
1097 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1098 return -E1000_ERR_NVM
;
1100 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1101 hw
->nvm
.flash_base_addr
;
1106 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1110 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1111 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1112 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
1113 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
1114 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1116 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1118 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1119 ICH_FLASH_READ_COMMAND_TIMEOUT
);
1122 * Check if FCERR is set to 1, if set to 1, clear it
1123 * and try the whole sequence a few more times, else
1124 * read in (shift in) the Flash Data0, the order is
1125 * least significant byte first msb to lsb
1128 flash_data
= er32flash(ICH_FLASH_FDATA0
);
1130 *data
= (u8
)(flash_data
& 0x000000FF);
1131 } else if (size
== 2) {
1132 *data
= (u16
)(flash_data
& 0x0000FFFF);
1137 * If we've gotten here, then things are probably
1138 * completely hosed, but if the error condition is
1139 * detected, it won't hurt to give it another try...
1140 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1142 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1143 if (hsfsts
.hsf_status
.flcerr
== 1) {
1144 /* Repeat for some time before giving up. */
1146 } else if (hsfsts
.hsf_status
.flcdone
== 0) {
1147 hw_dbg(hw
, "Timeout error - flash cycle "
1148 "did not complete.");
1152 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1158 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1159 * @hw: pointer to the HW structure
1160 * @offset: The offset (in bytes) of the word(s) to write.
1161 * @words: Size of data to write in words
1162 * @data: Pointer to the word(s) to write at offset.
1164 * Writes a byte or word to the NVM using the flash access registers.
1166 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
1169 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1170 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1174 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
1176 hw_dbg(hw
, "nvm parameter(s) out of bounds\n");
1177 return -E1000_ERR_NVM
;
1180 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1184 for (i
= 0; i
< words
; i
++) {
1185 dev_spec
->shadow_ram
[offset
+i
].modified
= 1;
1186 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
1189 e1000_release_swflag_ich8lan(hw
);
1195 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1196 * @hw: pointer to the HW structure
1198 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1199 * which writes the checksum to the shadow ram. The changes in the shadow
1200 * ram are then committed to the EEPROM by processing each bank at a time
1201 * checking for the modified bit and writing only the pending changes.
1202 * After a successful commit, the shadow ram is cleared and is ready for
1205 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1207 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1208 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
1209 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
;
1213 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
1217 if (nvm
->type
!= e1000_nvm_flash_sw
)
1220 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1225 * We're writing to the opposite bank so if we're on bank 1,
1226 * write to bank 0 etc. We also need to erase the segment that
1227 * is going to be written
1229 if (!(er32(EECD
) & E1000_EECD_SEC1VAL
)) {
1230 new_bank_offset
= nvm
->flash_bank_size
;
1231 old_bank_offset
= 0;
1232 e1000_erase_flash_bank_ich8lan(hw
, 1);
1234 old_bank_offset
= nvm
->flash_bank_size
;
1235 new_bank_offset
= 0;
1236 e1000_erase_flash_bank_ich8lan(hw
, 0);
1239 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1241 * Determine whether to write the value stored
1242 * in the other NVM bank or a modified value stored
1245 if (dev_spec
->shadow_ram
[i
].modified
) {
1246 data
= dev_spec
->shadow_ram
[i
].value
;
1248 e1000_read_flash_word_ich8lan(hw
,
1249 i
+ old_bank_offset
,
1254 * If the word is 0x13, then make sure the signature bits
1255 * (15:14) are 11b until the commit has completed.
1256 * This will allow us to write 10b which indicates the
1257 * signature is valid. We want to do this after the write
1258 * has completed so that we don't mark the segment valid
1259 * while the write is still in progress
1261 if (i
== E1000_ICH_NVM_SIG_WORD
)
1262 data
|= E1000_ICH_NVM_SIG_MASK
;
1264 /* Convert offset to bytes. */
1265 act_offset
= (i
+ new_bank_offset
) << 1;
1268 /* Write the bytes to the new bank. */
1269 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1276 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1284 * Don't bother writing the segment valid bits if sector
1285 * programming failed.
1288 hw_dbg(hw
, "Flash commit failed.\n");
1289 e1000_release_swflag_ich8lan(hw
);
1294 * Finally validate the new segment by setting bit 15:14
1295 * to 10b in word 0x13 , this can be done without an
1296 * erase as well since these bits are 11 to start with
1297 * and we need to change bit 14 to 0b
1299 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
1300 e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
1302 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
1306 e1000_release_swflag_ich8lan(hw
);
1311 * And invalidate the previously valid segment by setting
1312 * its signature word (0x13) high_byte to 0b. This can be
1313 * done without an erase because flash erase sets all bits
1314 * to 1's. We can write 1's to 0's without an erase
1316 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
1317 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
1319 e1000_release_swflag_ich8lan(hw
);
1323 /* Great! Everything worked, we can now clear the cached entries. */
1324 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
1325 dev_spec
->shadow_ram
[i
].modified
= 0;
1326 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
1329 e1000_release_swflag_ich8lan(hw
);
1332 * Reload the EEPROM, or else modifications will not appear
1333 * until after the next adapter reset.
1335 e1000e_reload_nvm(hw
);
1342 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1343 * @hw: pointer to the HW structure
1345 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1346 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1347 * calculated, in which case we need to calculate the checksum and set bit 6.
1349 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
1355 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1356 * needs to be fixed. This bit is an indication that the NVM
1357 * was prepared by OEM software and did not calculate the
1358 * checksum...a likely scenario.
1360 ret_val
= e1000_read_nvm(hw
, 0x19, 1, &data
);
1364 if ((data
& 0x40) == 0) {
1366 ret_val
= e1000_write_nvm(hw
, 0x19, 1, &data
);
1369 ret_val
= e1000e_update_nvm_checksum(hw
);
1374 return e1000e_validate_nvm_checksum_generic(hw
);
1378 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1379 * @hw: pointer to the HW structure
1380 * @offset: The offset (in bytes) of the byte/word to read.
1381 * @size: Size of data to read, 1=byte 2=word
1382 * @data: The byte(s) to write to the NVM.
1384 * Writes one/two bytes to the NVM using the flash access registers.
1386 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1389 union ich8_hws_flash_status hsfsts
;
1390 union ich8_hws_flash_ctrl hsflctl
;
1391 u32 flash_linear_addr
;
1396 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
1397 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
1398 return -E1000_ERR_NVM
;
1400 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
1401 hw
->nvm
.flash_base_addr
;
1406 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1410 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1411 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1412 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
1413 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
1414 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1416 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1419 flash_data
= (u32
)data
& 0x00FF;
1421 flash_data
= (u32
)data
;
1423 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
1426 * check if FCERR is set to 1 , if set to 1, clear it
1427 * and try the whole sequence a few more times else done
1429 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1430 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
1435 * If we're here, then things are most likely
1436 * completely hosed, but if the error condition
1437 * is detected, it won't hurt to give it another
1438 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1440 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1441 if (hsfsts
.hsf_status
.flcerr
== 1)
1442 /* Repeat for some time before giving up. */
1444 if (hsfsts
.hsf_status
.flcdone
== 0) {
1445 hw_dbg(hw
, "Timeout error - flash cycle "
1446 "did not complete.");
1449 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
1455 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1456 * @hw: pointer to the HW structure
1457 * @offset: The index of the byte to read.
1458 * @data: The byte to write to the NVM.
1460 * Writes a single byte to the NVM using the flash access registers.
1462 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
1465 u16 word
= (u16
)data
;
1467 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
1471 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1472 * @hw: pointer to the HW structure
1473 * @offset: The offset of the byte to write.
1474 * @byte: The byte to write to the NVM.
1476 * Writes a single byte to the NVM using the flash access registers.
1477 * Goes through a retry algorithm before giving up.
1479 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
1480 u32 offset
, u8 byte
)
1483 u16 program_retries
;
1485 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1489 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
1490 hw_dbg(hw
, "Retrying Byte %2.2X at offset %u\n", byte
, offset
);
1492 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
1496 if (program_retries
== 100)
1497 return -E1000_ERR_NVM
;
1503 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1504 * @hw: pointer to the HW structure
1505 * @bank: 0 for first bank, 1 for second bank, etc.
1507 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1508 * bank N is 4096 * N + flash_reg_addr.
1510 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
1512 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
1513 union ich8_hws_flash_status hsfsts
;
1514 union ich8_hws_flash_ctrl hsflctl
;
1515 u32 flash_linear_addr
;
1516 /* bank size is in 16bit words - adjust to bytes */
1517 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
1524 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1527 * Determine HW Sector size: Read BERASE bits of hw flash status
1529 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1530 * consecutive sectors. The start index for the nth Hw sector
1531 * can be calculated as = bank * 4096 + n * 256
1532 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1533 * The start index for the nth Hw sector can be calculated
1535 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1536 * (ich9 only, otherwise error condition)
1537 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1539 switch (hsfsts
.hsf_status
.berasesz
) {
1541 /* Hw sector size 256 */
1542 sector_size
= ICH_FLASH_SEG_SIZE_256
;
1543 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
1546 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
1547 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_4K
;
1550 if (hw
->mac
.type
== e1000_ich9lan
) {
1551 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
1552 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_8K
;
1554 return -E1000_ERR_NVM
;
1558 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
1559 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_64K
;
1562 return -E1000_ERR_NVM
;
1565 /* Start with the base address, then add the sector offset. */
1566 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
1567 flash_linear_addr
+= (bank
) ? (sector_size
* iteration
) : 0;
1569 for (j
= 0; j
< iteration
; j
++) {
1572 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
1577 * Write a value 11 (block Erase) in Flash
1578 * Cycle field in hw flash control
1580 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
1581 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
1582 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
1585 * Write the last 24 bits of an index within the
1586 * block into Flash Linear address field in Flash
1589 flash_linear_addr
+= (j
* sector_size
);
1590 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
1592 ret_val
= e1000_flash_cycle_ich8lan(hw
,
1593 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
1598 * Check if FCERR is set to 1. If 1,
1599 * clear it and try the whole sequence
1600 * a few more times else Done
1602 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
1603 if (hsfsts
.hsf_status
.flcerr
== 1)
1604 /* repeat for some time before giving up */
1606 else if (hsfsts
.hsf_status
.flcdone
== 0)
1608 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
1615 * e1000_valid_led_default_ich8lan - Set the default LED settings
1616 * @hw: pointer to the HW structure
1617 * @data: Pointer to the LED settings
1619 * Reads the LED default settings from the NVM to data. If the NVM LED
1620 * settings is all 0's or F's, set the LED default to a valid LED default
1623 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
1627 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1629 hw_dbg(hw
, "NVM Read Error\n");
1633 if (*data
== ID_LED_RESERVED_0000
||
1634 *data
== ID_LED_RESERVED_FFFF
)
1635 *data
= ID_LED_DEFAULT_ICH8LAN
;
1641 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1642 * @hw: pointer to the HW structure
1644 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1645 * register, so the the bus width is hard coded.
1647 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
1649 struct e1000_bus_info
*bus
= &hw
->bus
;
1652 ret_val
= e1000e_get_bus_info_pcie(hw
);
1655 * ICH devices are "PCI Express"-ish. They have
1656 * a configuration space, but do not contain
1657 * PCI Express Capability registers, so bus width
1658 * must be hardcoded.
1660 if (bus
->width
== e1000_bus_width_unknown
)
1661 bus
->width
= e1000_bus_width_pcie_x1
;
1667 * e1000_reset_hw_ich8lan - Reset the hardware
1668 * @hw: pointer to the HW structure
1670 * Does a full reset of the hardware which includes a reset of the PHY and
1673 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
1679 * Prevent the PCI-E bus from sticking if there is no TLP connection
1680 * on the last TLP read/write transaction when MAC is reset.
1682 ret_val
= e1000e_disable_pcie_master(hw
);
1684 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
1687 hw_dbg(hw
, "Masking off all interrupts\n");
1688 ew32(IMC
, 0xffffffff);
1691 * Disable the Transmit and Receive units. Then delay to allow
1692 * any pending transactions to complete before we hit the MAC
1693 * with the global reset.
1696 ew32(TCTL
, E1000_TCTL_PSP
);
1701 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1702 if (hw
->mac
.type
== e1000_ich8lan
) {
1703 /* Set Tx and Rx buffer allocation to 8k apiece. */
1704 ew32(PBA
, E1000_PBA_8K
);
1705 /* Set Packet Buffer Size to 16k. */
1706 ew32(PBS
, E1000_PBS_16K
);
1711 if (!e1000_check_reset_block(hw
)) {
1713 * PHY HW reset requires MAC CORE reset at the same
1714 * time to make sure the interface between MAC and the
1715 * external PHY is reset.
1717 ctrl
|= E1000_CTRL_PHY_RST
;
1719 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1720 hw_dbg(hw
, "Issuing a global reset to ich8lan");
1721 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
1724 ret_val
= e1000e_get_auto_rd_done(hw
);
1727 * When auto config read does not complete, do not
1728 * return with an error. This can happen in situations
1729 * where there is no eeprom and prevents getting link.
1731 hw_dbg(hw
, "Auto Read Done did not complete\n");
1734 ew32(IMC
, 0xffffffff);
1737 kab
= er32(KABGTXD
);
1738 kab
|= E1000_KABGTXD_BGSQLBIAS
;
1745 * e1000_init_hw_ich8lan - Initialize the hardware
1746 * @hw: pointer to the HW structure
1748 * Prepares the hardware for transmit and receive by doing the following:
1749 * - initialize hardware bits
1750 * - initialize LED identification
1751 * - setup receive address registers
1752 * - setup flow control
1753 * - setup transmit descriptors
1754 * - clear statistics
1756 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
1758 struct e1000_mac_info
*mac
= &hw
->mac
;
1759 u32 ctrl_ext
, txdctl
, snoop
;
1763 e1000_initialize_hw_bits_ich8lan(hw
);
1765 /* Initialize identification LED */
1766 ret_val
= e1000e_id_led_init(hw
);
1768 hw_dbg(hw
, "Error initializing identification LED\n");
1772 /* Setup the receive address. */
1773 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
1775 /* Zero out the Multicast HASH table */
1776 hw_dbg(hw
, "Zeroing the MTA\n");
1777 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
1778 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
1780 /* Setup link and flow control */
1781 ret_val
= e1000_setup_link_ich8lan(hw
);
1783 /* Set the transmit descriptor write-back policy for both queues */
1784 txdctl
= er32(TXDCTL(0));
1785 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
1786 E1000_TXDCTL_FULL_TX_DESC_WB
;
1787 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
1788 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
1789 ew32(TXDCTL(0), txdctl
);
1790 txdctl
= er32(TXDCTL(1));
1791 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
1792 E1000_TXDCTL_FULL_TX_DESC_WB
;
1793 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
1794 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
1795 ew32(TXDCTL(1), txdctl
);
1798 * ICH8 has opposite polarity of no_snoop bits.
1799 * By default, we should use snoop behavior.
1801 if (mac
->type
== e1000_ich8lan
)
1802 snoop
= PCIE_ICH8_SNOOP_ALL
;
1804 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
1805 e1000e_set_pcie_no_snoop(hw
, snoop
);
1807 ctrl_ext
= er32(CTRL_EXT
);
1808 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
1809 ew32(CTRL_EXT
, ctrl_ext
);
1812 * Clear all of the statistics registers (clear on read). It is
1813 * important that we do this after we have tried to establish link
1814 * because the symbol error count will increment wildly if there
1817 e1000_clear_hw_cntrs_ich8lan(hw
);
1822 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1823 * @hw: pointer to the HW structure
1825 * Sets/Clears required hardware bits necessary for correctly setting up the
1826 * hardware for transmit and receive.
1828 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
1832 /* Extended Device Control */
1833 reg
= er32(CTRL_EXT
);
1835 ew32(CTRL_EXT
, reg
);
1837 /* Transmit Descriptor Control 0 */
1838 reg
= er32(TXDCTL(0));
1840 ew32(TXDCTL(0), reg
);
1842 /* Transmit Descriptor Control 1 */
1843 reg
= er32(TXDCTL(1));
1845 ew32(TXDCTL(1), reg
);
1847 /* Transmit Arbitration Control 0 */
1848 reg
= er32(TARC(0));
1849 if (hw
->mac
.type
== e1000_ich8lan
)
1850 reg
|= (1 << 28) | (1 << 29);
1851 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
1854 /* Transmit Arbitration Control 1 */
1855 reg
= er32(TARC(1));
1856 if (er32(TCTL
) & E1000_TCTL_MULR
)
1860 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
1864 if (hw
->mac
.type
== e1000_ich8lan
) {
1872 * e1000_setup_link_ich8lan - Setup flow control and link settings
1873 * @hw: pointer to the HW structure
1875 * Determines which flow control settings to use, then configures flow
1876 * control. Calls the appropriate media-specific link configuration
1877 * function. Assuming the adapter has a valid link partner, a valid link
1878 * should be established. Assumes the hardware has previously been reset
1879 * and the transmitter and receiver are not enabled.
1881 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
1885 if (e1000_check_reset_block(hw
))
1889 * ICH parts do not have a word in the NVM to determine
1890 * the default flow control setting, so we explicitly
1893 if (hw
->fc
.type
== e1000_fc_default
)
1894 hw
->fc
.type
= e1000_fc_full
;
1896 hw
->fc
.original_type
= hw
->fc
.type
;
1898 hw_dbg(hw
, "After fix-ups FlowControl is now = %x\n", hw
->fc
.type
);
1900 /* Continue to configure the copper link. */
1901 ret_val
= e1000_setup_copper_link_ich8lan(hw
);
1905 ew32(FCTTV
, hw
->fc
.pause_time
);
1907 return e1000e_set_fc_watermarks(hw
);
1911 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
1912 * @hw: pointer to the HW structure
1914 * Configures the kumeran interface to the PHY to wait the appropriate time
1915 * when polling the PHY, then call the generic setup_copper_link to finish
1916 * configuring the copper link.
1918 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
1925 ctrl
|= E1000_CTRL_SLU
;
1926 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1930 * Set the mac to wait the maximum time between each iteration
1931 * and increase the max iterations when polling the phy;
1932 * this fixes erroneous timeouts at 10Mbps.
1934 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 4), 0xFFFF);
1937 ret_val
= e1000e_read_kmrn_reg(hw
, GG82563_REG(0x34, 9), ®_data
);
1941 ret_val
= e1000e_write_kmrn_reg(hw
, GG82563_REG(0x34, 9), reg_data
);
1945 if (hw
->phy
.type
== e1000_phy_igp_3
) {
1946 ret_val
= e1000e_copper_link_setup_igp(hw
);
1949 } else if (hw
->phy
.type
== e1000_phy_bm
) {
1950 ret_val
= e1000e_copper_link_setup_m88(hw
);
1955 if (hw
->phy
.type
== e1000_phy_ife
) {
1956 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
1960 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
1962 switch (hw
->phy
.mdix
) {
1964 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
1967 reg_data
|= IFE_PMC_FORCE_MDIX
;
1971 reg_data
|= IFE_PMC_AUTO_MDIX
;
1974 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
1978 return e1000e_setup_copper_link(hw
);
1982 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
1983 * @hw: pointer to the HW structure
1984 * @speed: pointer to store current link speed
1985 * @duplex: pointer to store the current link duplex
1987 * Calls the generic get_speed_and_duplex to retrieve the current link
1988 * information and then calls the Kumeran lock loss workaround for links at
1991 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
1996 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
2000 if ((hw
->mac
.type
== e1000_ich8lan
) &&
2001 (hw
->phy
.type
== e1000_phy_igp_3
) &&
2002 (*speed
== SPEED_1000
)) {
2003 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
2010 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2011 * @hw: pointer to the HW structure
2013 * Work-around for 82566 Kumeran PCS lock loss:
2014 * On link status change (i.e. PCI reset, speed change) and link is up and
2016 * 0) if workaround is optionally disabled do nothing
2017 * 1) wait 1ms for Kumeran link to come up
2018 * 2) check Kumeran Diagnostic register PCS lock loss bit
2019 * 3) if not set the link is locked (all is good), otherwise...
2021 * 5) repeat up to 10 times
2022 * Note: this is only called for IGP3 copper when speed is 1gb.
2024 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
2026 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2032 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
2036 * Make sure link is up before proceeding. If not just return.
2037 * Attempting this while link is negotiating fouled up link
2040 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2044 for (i
= 0; i
< 10; i
++) {
2045 /* read once to clear */
2046 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2049 /* and again to get new status */
2050 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
2054 /* check for PCS lock */
2055 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
2058 /* Issue PHY reset */
2059 e1000_phy_hw_reset(hw
);
2062 /* Disable GigE link negotiation */
2063 phy_ctrl
= er32(PHY_CTRL
);
2064 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2065 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2066 ew32(PHY_CTRL
, phy_ctrl
);
2069 * Call gig speed drop workaround on Gig disable before accessing
2072 e1000e_gig_downshift_workaround_ich8lan(hw
);
2074 /* unable to acquire PCS lock */
2075 return -E1000_ERR_PHY
;
2079 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2080 * @hw: pointer to the HW structure
2081 * @state: boolean value used to set the current Kumeran workaround state
2083 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2084 * /disabled - FALSE).
2086 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
2089 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2091 if (hw
->mac
.type
!= e1000_ich8lan
) {
2092 hw_dbg(hw
, "Workaround applies to ICH8 only.\n");
2096 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
2100 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2101 * @hw: pointer to the HW structure
2103 * Workaround for 82566 power-down on D3 entry:
2104 * 1) disable gigabit link
2105 * 2) write VR power-down enable
2107 * Continue if successful, else issue LCD reset and repeat
2109 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
2115 if (hw
->phy
.type
!= e1000_phy_igp_3
)
2118 /* Try the workaround twice (if needed) */
2121 reg
= er32(PHY_CTRL
);
2122 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
2123 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
2124 ew32(PHY_CTRL
, reg
);
2127 * Call gig speed drop workaround on Gig disable before
2128 * accessing any PHY registers
2130 if (hw
->mac
.type
== e1000_ich8lan
)
2131 e1000e_gig_downshift_workaround_ich8lan(hw
);
2133 /* Write VR power-down enable */
2134 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2135 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2136 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
2138 /* Read it back and test */
2139 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
2140 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
2141 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
2144 /* Issue PHY reset and repeat at most one more time */
2146 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
2152 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2153 * @hw: pointer to the HW structure
2155 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2156 * LPLU, Gig disable, MDIC PHY reset):
2157 * 1) Set Kumeran Near-end loopback
2158 * 2) Clear Kumeran Near-end loopback
2159 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2161 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
2166 if ((hw
->mac
.type
!= e1000_ich8lan
) ||
2167 (hw
->phy
.type
!= e1000_phy_igp_3
))
2170 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2174 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2175 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2179 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
2180 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
2185 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2186 * @hw: pointer to the HW structure
2188 * During S0 to Sx transition, it is possible the link remains at gig
2189 * instead of negotiating to a lower speed. Before going to Sx, set
2190 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2193 * Should only be called for ICH9 devices.
2195 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw
*hw
)
2199 if (hw
->mac
.type
== e1000_ich9lan
) {
2200 phy_ctrl
= er32(PHY_CTRL
);
2201 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
|
2202 E1000_PHY_CTRL_GBE_DISABLE
;
2203 ew32(PHY_CTRL
, phy_ctrl
);
2210 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2211 * @hw: pointer to the HW structure
2213 * Return the LED back to the default configuration.
2215 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
2217 if (hw
->phy
.type
== e1000_phy_ife
)
2218 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
2220 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
2225 * e1000_led_on_ich8lan - Turn LEDs on
2226 * @hw: pointer to the HW structure
2230 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
2232 if (hw
->phy
.type
== e1000_phy_ife
)
2233 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2234 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
2236 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
2241 * e1000_led_off_ich8lan - Turn LEDs off
2242 * @hw: pointer to the HW structure
2244 * Turn off the LEDs.
2246 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
2248 if (hw
->phy
.type
== e1000_phy_ife
)
2249 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
2250 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_OFF
));
2252 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
2257 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2258 * @hw: pointer to the HW structure
2260 * Clears hardware counters specific to the silicon family and calls
2261 * clear_hw_cntrs_generic to clear all general purpose counters.
2263 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
2267 e1000e_clear_hw_cntrs_base(hw
);
2269 temp
= er32(ALGNERRC
);
2270 temp
= er32(RXERRC
);
2272 temp
= er32(CEXTERR
);
2274 temp
= er32(TSCTFC
);
2276 temp
= er32(MGTPRC
);
2277 temp
= er32(MGTPDC
);
2278 temp
= er32(MGTPTC
);
2281 temp
= er32(ICRXOC
);
2285 static struct e1000_mac_operations ich8_mac_ops
= {
2286 .mng_mode_enab
= E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
,
2287 .check_for_link
= e1000e_check_for_copper_link
,
2288 .cleanup_led
= e1000_cleanup_led_ich8lan
,
2289 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
2290 .get_bus_info
= e1000_get_bus_info_ich8lan
,
2291 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
2292 .led_on
= e1000_led_on_ich8lan
,
2293 .led_off
= e1000_led_off_ich8lan
,
2294 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
2295 .reset_hw
= e1000_reset_hw_ich8lan
,
2296 .init_hw
= e1000_init_hw_ich8lan
,
2297 .setup_link
= e1000_setup_link_ich8lan
,
2298 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
2301 static struct e1000_phy_operations ich8_phy_ops
= {
2302 .acquire_phy
= e1000_acquire_swflag_ich8lan
,
2303 .check_reset_block
= e1000_check_reset_block_ich8lan
,
2305 .force_speed_duplex
= e1000_phy_force_speed_duplex_ich8lan
,
2306 .get_cfg_done
= e1000e_get_cfg_done
,
2307 .get_cable_length
= e1000e_get_cable_length_igp_2
,
2308 .get_phy_info
= e1000_get_phy_info_ich8lan
,
2309 .read_phy_reg
= e1000e_read_phy_reg_igp
,
2310 .release_phy
= e1000_release_swflag_ich8lan
,
2311 .reset_phy
= e1000_phy_hw_reset_ich8lan
,
2312 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
2313 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
2314 .write_phy_reg
= e1000e_write_phy_reg_igp
,
2317 static struct e1000_nvm_operations ich8_nvm_ops
= {
2318 .acquire_nvm
= e1000_acquire_swflag_ich8lan
,
2319 .read_nvm
= e1000_read_nvm_ich8lan
,
2320 .release_nvm
= e1000_release_swflag_ich8lan
,
2321 .update_nvm
= e1000_update_nvm_checksum_ich8lan
,
2322 .valid_led_default
= e1000_valid_led_default_ich8lan
,
2323 .validate_nvm
= e1000_validate_nvm_checksum_ich8lan
,
2324 .write_nvm
= e1000_write_nvm_ich8lan
,
2327 struct e1000_info e1000_ich8_info
= {
2328 .mac
= e1000_ich8lan
,
2329 .flags
= FLAG_HAS_WOL
2331 | FLAG_RX_CSUM_ENABLED
2332 | FLAG_HAS_CTRLEXT_ON_LOAD
2337 .get_variants
= e1000_get_variants_ich8lan
,
2338 .mac_ops
= &ich8_mac_ops
,
2339 .phy_ops
= &ich8_phy_ops
,
2340 .nvm_ops
= &ich8_nvm_ops
,
2343 struct e1000_info e1000_ich9_info
= {
2344 .mac
= e1000_ich9lan
,
2345 .flags
= FLAG_HAS_JUMBO_FRAMES
2348 | FLAG_RX_CSUM_ENABLED
2349 | FLAG_HAS_CTRLEXT_ON_LOAD
2355 .get_variants
= e1000_get_variants_ich8lan
,
2356 .mac_ops
= &ich8_mac_ops
,
2357 .phy_ops
= &ich8_phy_ops
,
2358 .nvm_ops
= &ich8_nvm_ops
,