2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
11 #ifndef _ASM_STACKFRAME_H
12 #define _ASM_STACKFRAME_H
14 #include <linux/threads.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
22 * For SMTC kernel, global IE should be left set, and interrupts
23 * controlled exclusively via IXMT.
25 #ifdef CONFIG_MIPS_MT_SMTC
27 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
33 #ifdef CONFIG_MIPS_MT_SMTC
34 #include <asm/mipsmtregs.h>
35 #endif /* CONFIG_MIPS_MT_SMTC */
45 #ifdef CONFIG_CPU_HAS_SMARTMIPS
62 LONG_S $
10, PT_R10(sp
)
63 LONG_S $
11, PT_R11(sp
)
64 LONG_S $
12, PT_R12(sp
)
65 LONG_S $
13, PT_R13(sp
)
66 LONG_S $
14, PT_R14(sp
)
67 LONG_S $
15, PT_R15(sp
)
68 LONG_S $
24, PT_R24(sp
)
72 LONG_S $
16, PT_R16(sp
)
73 LONG_S $
17, PT_R17(sp
)
74 LONG_S $
18, PT_R18(sp
)
75 LONG_S $
19, PT_R19(sp
)
76 LONG_S $
20, PT_R20(sp
)
77 LONG_S $
21, PT_R21(sp
)
78 LONG_S $
22, PT_R22(sp
)
79 LONG_S $
23, PT_R23(sp
)
80 LONG_S $
30, PT_R30(sp
)
84 #ifdef CONFIG_MIPS_MT_SMTC
85 #define PTEBASE_SHIFT 19 /* TCBIND */
87 #define PTEBASE_SHIFT 23 /* CONTEXT */
89 .macro get_saved_sp
/* SMP variation */
90 #ifdef CONFIG_MIPS_MT_SMTC
95 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
98 lui k1
, %highest(kernelsp
)
99 daddiu k1
, %higher(kernelsp
)
101 daddiu k1
, %hi(kernelsp
)
104 LONG_SRL k0
, PTEBASE_SHIFT
106 LONG_L k1
, %lo(kernelsp
)(k1
)
109 .macro set_saved_sp stackp temp temp2
110 #ifdef CONFIG_MIPS_MT_SMTC
111 mfc0
\temp
, CP0_TCBIND
113 MFC0
\temp
, CP0_CONTEXT
115 LONG_SRL
\temp
, PTEBASE_SHIFT
116 LONG_S \stackp
, kernelsp(\temp
)
119 .macro get_saved_sp
/* Uniprocessor variation */
120 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
121 lui k1
, %hi(kernelsp
)
123 lui k1
, %highest(kernelsp
)
124 daddiu k1
, %higher(kernelsp
)
126 daddiu k1
, %hi(kernelsp
)
129 LONG_L k1
, %lo(kernelsp
)(k1
)
132 .macro set_saved_sp stackp temp temp2
133 LONG_S \stackp
, kernelsp
142 sll k0
, 3 /* extract cu0 bit */
147 /* Called from user mode, new stack. */
149 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
151 PTR_SUBU sp
, k1
, PT_SIZE
154 8: PTR_SUBU k1
, PT_SIZE
159 LONG_S k0
, PT_R29(sp
)
162 * You might think that you don't need to save $0,
163 * but the FPU emulator and gdb remote debug stub
164 * need it to operate correctly
169 LONG_S v1
, PT_STATUS(sp
)
170 #ifdef CONFIG_MIPS_MT_SMTC
172 * Ideally, these instructions would be shuffled in
173 * to cover the pipeline delay.
176 mfc0 v1
, CP0_TCSTATUS
178 LONG_S v1
, PT_TCSTATUS(sp
)
179 #endif /* CONFIG_MIPS_MT_SMTC */
183 LONG_S v1
, PT_CAUSE(sp
)
191 LONG_S v1
, PT_EPC(sp
)
192 LONG_S $
25, PT_R25(sp
)
193 LONG_S $
28, PT_R28(sp
)
194 LONG_S $
31, PT_R31(sp
)
195 ori $
28, sp
, _THREAD_MASK
196 xori $
28, _THREAD_MASK
215 #ifdef CONFIG_CPU_HAS_SMARTMIPS
216 LONG_L $
24, PT_ACX(sp
)
218 LONG_L $
24, PT_HI(sp
)
220 LONG_L $
24, PT_LO(sp
)
223 LONG_L $
24, PT_LO(sp
)
225 LONG_L $
24, PT_HI(sp
)
232 LONG_L $
10, PT_R10(sp
)
233 LONG_L $
11, PT_R11(sp
)
234 LONG_L $
12, PT_R12(sp
)
235 LONG_L $
13, PT_R13(sp
)
236 LONG_L $
14, PT_R14(sp
)
237 LONG_L $
15, PT_R15(sp
)
238 LONG_L $
24, PT_R24(sp
)
241 .macro RESTORE_STATIC
242 LONG_L $
16, PT_R16(sp
)
243 LONG_L $
17, PT_R17(sp
)
244 LONG_L $
18, PT_R18(sp
)
245 LONG_L $
19, PT_R19(sp
)
246 LONG_L $
20, PT_R20(sp
)
247 LONG_L $
21, PT_R21(sp
)
248 LONG_L $
22, PT_R22(sp
)
249 LONG_L $
23, PT_R23(sp
)
250 LONG_L $
30, PT_R30(sp
)
253 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
265 LONG_L v0
, PT_STATUS(sp
)
270 LONG_L $
31, PT_R31(sp
)
271 LONG_L $
28, PT_R28(sp
)
272 LONG_L $
25, PT_R25(sp
)
282 .macro RESTORE_SP_AND_RET
285 LONG_L k0
, PT_EPC(sp
)
286 LONG_L sp
, PT_R29(sp
)
297 #ifdef CONFIG_MIPS_MT_SMTC
300 * We need to make sure the read-modify-write
301 * of Status below isn't perturbed by an interrupt
302 * or cross-TC access, so we need to do at least a DMT,
303 * protected by an interrupt-inhibit. But setting IXMT
304 * also creates a few-cycle window where an IPI could
305 * be queued and not be detected before potentially
306 * returning to a WAIT or user-mode loop. It must be
309 * We're in the middle of a context switch, and
310 * we can't dispatch it directly without trashing
311 * some registers, so we'll try to detect this unlikely
312 * case and program a software interrupt in the VPE,
313 * as would be done for a cross-VPE IPI. To accomodate
314 * the handling of that case, we're doing a DVPE instead
315 * of just a DMT here to protect against other threads.
316 * This is a lot of cruft to cover a tiny window.
317 * If you can find a better design, implement it!
320 mfc0 v0
, CP0_TCSTATUS
321 ori v0
, TCSTATUS_IXMT
322 mtc0 v0
, CP0_TCSTATUS
326 #endif /* CONFIG_MIPS_MT_SMTC */
333 LONG_L v0
, PT_STATUS(sp
)
338 #ifdef CONFIG_MIPS_MT_SMTC
340 * Only after EXL/ERL have been restored to status can we
341 * restore TCStatus.IXMT.
343 LONG_L v1
, PT_TCSTATUS(sp
)
345 mfc0 a0
, CP0_TCSTATUS
346 andi v1
, TCSTATUS_IXMT
350 * We'd like to detect any IPIs queued in the tiny window
351 * above and request an software interrupt to service them
354 * Computing the offset into the IPIQ array of the executing
355 * TC's IPI queue in-line would be tedious. We use part of
356 * the TCContext register to hold 16 bits of offset that we
357 * can add in-line to find the queue head.
359 mfc0 v0
, CP0_TCCONTEXT
366 * If we have a queue, provoke dispatch within the VPE by setting C_SW1
373 * This test should really never branch but
374 * let's be prudent here. Having atomized
375 * the shared register modifications, we can
376 * now EVPE, and must do so before interrupts
377 * are potentially re-enabled.
379 andi a1
, a1
, MVPCONTROL_EVP
383 /* We know that TCStatua.IXMT should be set from above */
384 xori a0
, a0
, TCSTATUS_IXMT
386 mtc0 a0
, CP0_TCSTATUS
390 #endif /* CONFIG_MIPS_MT_SMTC */
391 LONG_L v1
, PT_EPC(sp
)
393 LONG_L $
31, PT_R31(sp
)
394 LONG_L $
28, PT_R28(sp
)
395 LONG_L $
25, PT_R25(sp
)
409 .macro RESTORE_SP_AND_RET
410 LONG_L sp
, PT_R29(sp
)
419 LONG_L sp
, PT_R29(sp
)
430 .macro RESTORE_ALL_AND_RET
439 * Move to kernel mode and disable interrupts.
440 * Set cp0 enable bit as sign that we're running on the kernel stack
443 #if !defined(CONFIG_MIPS_MT_SMTC)
445 li t1
, ST0_CU0
| STATMASK
449 #else /* CONFIG_MIPS_MT_SMTC */
451 * For SMTC, we need to set privilege
452 * and disable interrupts only for the
453 * current TC, using the TCStatus register.
455 mfc0 t0
, CP0_TCSTATUS
456 /* Fortunately CU 0 is in the same place in both registers */
457 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
458 li t1
, ST0_CU0
| 0x08001c00
460 /* Clear TKSU, leave IXMT */
462 mtc0 t0
, CP0_TCSTATUS
464 /* We need to leave the global IE bit set, but clear EXL...*/
466 ori t0
, ST0_EXL
| ST0_ERL
467 xori t0
, ST0_EXL
| ST0_ERL
469 #endif /* CONFIG_MIPS_MT_SMTC */
474 * Move to kernel mode and enable interrupts.
475 * Set cp0 enable bit as sign that we're running on the kernel stack
478 #if !defined(CONFIG_MIPS_MT_SMTC)
480 li t1
, ST0_CU0
| STATMASK
482 xori t0
, STATMASK
& ~1
484 #else /* CONFIG_MIPS_MT_SMTC */
486 * For SMTC, we need to set privilege
487 * and enable interrupts only for the
488 * current TC, using the TCStatus register.
491 mfc0 t0
, CP0_TCSTATUS
492 /* Fortunately CU 0 is in the same place in both registers */
493 /* Set TCU0, TKSU (for later inversion) and IXMT */
494 li t1
, ST0_CU0
| 0x08001c00
496 /* Clear TKSU *and* IXMT */
498 mtc0 t0
, CP0_TCSTATUS
500 /* We need to leave the global IE bit set, but clear EXL...*/
505 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
506 #endif /* CONFIG_MIPS_MT_SMTC */
511 * Just move to kernel mode and leave interrupts as they are. Note
512 * for the R3000 this means copying the previous enable from IEp.
513 * Set cp0 enable bit as sign that we're running on the kernel stack
516 #ifdef CONFIG_MIPS_MT_SMTC
518 * This gets baroque in SMTC. We want to
519 * protect the non-atomic clearing of EXL
520 * with DMT/EMT, but we don't want to take
521 * an interrupt while DMT is still in effect.
524 /* KMODE gets invoked from both reorder and noreorder code */
528 mfc0 v0
, CP0_TCSTATUS
529 andi v1
, v0
, TCSTATUS_IXMT
530 ori v0
, TCSTATUS_IXMT
531 mtc0 v0
, CP0_TCSTATUS
535 * We don't know a priori if ra is "live"
541 #endif /* CONFIG_MIPS_MT_SMTC */
543 li t1
, ST0_CU0
| (STATMASK
& ~1)
544 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
550 xori t0
, STATMASK
& ~1
552 #ifdef CONFIG_MIPS_MT_SMTC
554 andi v0
, v0
, VPECONTROL_TE
559 mfc0 v0
, CP0_TCSTATUS
560 /* Clear IXMT, then OR in previous value */
561 ori v0
, TCSTATUS_IXMT
562 xori v0
, TCSTATUS_IXMT
564 mtc0 v0
, CP0_TCSTATUS
566 * irq_disable_hazard below should expand to EHB
570 #endif /* CONFIG_MIPS_MT_SMTC */
574 #endif /* _ASM_STACKFRAME_H */