2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
94 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20
= 0x14 // 8168C
115 #define _R(NAME,MAC,MASK) \
116 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
118 static const struct {
121 u32 RxConfigMask
; /* Clears the bits supported by this chip */
122 } rtl_chip_info
[] = {
123 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
124 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
125 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
126 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
127 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
129 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
130 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
131 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
132 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
133 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
136 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
137 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
139 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
140 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
141 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
142 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880) // PCI-E
152 static void rtl_hw_start_8169(struct net_device
*);
153 static void rtl_hw_start_8168(struct net_device
*);
154 static void rtl_hw_start_8101(struct net_device
*);
156 static struct pci_device_id rtl8169_pci_tbl
[] = {
157 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
158 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
159 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
160 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
162 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
163 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
164 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
165 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
166 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
168 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
172 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
174 static int rx_copybreak
= 200;
181 MAC0
= 0, /* Ethernet hardware address. */
183 MAR0
= 8, /* Multicast filter. */
184 CounterAddrLow
= 0x10,
185 CounterAddrHigh
= 0x14,
186 TxDescStartAddrLow
= 0x20,
187 TxDescStartAddrHigh
= 0x24,
188 TxHDescStartAddrLow
= 0x28,
189 TxHDescStartAddrHigh
= 0x2c,
212 RxDescAddrLow
= 0xe4,
213 RxDescAddrHigh
= 0xe8,
216 FuncEventMask
= 0xf4,
217 FuncPresetState
= 0xf8,
218 FuncForceEvent
= 0xfc,
221 enum rtl8110_registers
{
227 enum rtl8168_8101_registers
{
230 #define CSIAR_FLAG 0x80000000
231 #define CSIAR_WRITE_CMD 0x80000000
232 #define CSIAR_BYTE_ENABLE 0x0f
233 #define CSIAR_BYTE_ENABLE_SHIFT 12
234 #define CSIAR_ADDR_MASK 0x0fff
237 #define EPHYAR_FLAG 0x80000000
238 #define EPHYAR_WRITE_CMD 0x80000000
239 #define EPHYAR_REG_MASK 0x1f
240 #define EPHYAR_REG_SHIFT 16
241 #define EPHYAR_DATA_MASK 0xffff
243 #define FIX_NAK_1 (1 << 4)
244 #define FIX_NAK_2 (1 << 3)
247 enum rtl_register_content
{
248 /* InterruptStatusBits */
252 TxDescUnavail
= 0x0080,
274 /* TXPoll register p.5 */
275 HPQ
= 0x80, /* Poll cmd on the high prio queue */
276 NPQ
= 0x40, /* Poll cmd on the low prio queue */
277 FSWInt
= 0x01, /* Forced software interrupt */
281 Cfg9346_Unlock
= 0xc0,
286 AcceptBroadcast
= 0x08,
287 AcceptMulticast
= 0x04,
289 AcceptAllPhys
= 0x01,
296 TxInterFrameGapShift
= 24,
297 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
299 /* Config1 register p.24 */
302 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
303 Speed_down
= (1 << 4),
307 PMEnable
= (1 << 0), /* Power Management Enable */
309 /* Config2 register p. 25 */
310 PCI_Clock_66MHz
= 0x01,
311 PCI_Clock_33MHz
= 0x00,
313 /* Config3 register p.25 */
314 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
315 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
316 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
318 /* Config5 register p.27 */
319 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
320 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
321 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
322 LanWake
= (1 << 1), /* LanWake enable/disable */
323 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
326 TBIReset
= 0x80000000,
327 TBILoopback
= 0x40000000,
328 TBINwEnable
= 0x20000000,
329 TBINwRestart
= 0x10000000,
330 TBILinkOk
= 0x02000000,
331 TBINwComplete
= 0x01000000,
334 EnableBist
= (1 << 15), // 8168 8101
335 Mac_dbgo_oe
= (1 << 14), // 8168 8101
336 Normal_mode
= (1 << 13), // unused
337 Force_half_dup
= (1 << 12), // 8168 8101
338 Force_rxflow_en
= (1 << 11), // 8168 8101
339 Force_txflow_en
= (1 << 10), // 8168 8101
340 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
341 ASF
= (1 << 8), // 8168 8101
342 PktCntrDisable
= (1 << 7), // 8168 8101
343 Mac_dbgo_sel
= 0x001c, // 8168
348 INTT_0
= 0x0000, // 8168
349 INTT_1
= 0x0001, // 8168
350 INTT_2
= 0x0002, // 8168
351 INTT_3
= 0x0003, // 8168
353 /* rtl8169_PHYstatus */
364 TBILinkOK
= 0x02000000,
366 /* DumpCounterCommand */
370 enum desc_status_bit
{
371 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
372 RingEnd
= (1 << 30), /* End of descriptor ring */
373 FirstFrag
= (1 << 29), /* First segment of a packet */
374 LastFrag
= (1 << 28), /* Final segment of a packet */
377 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
378 MSSShift
= 16, /* MSS value position */
379 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
380 IPCS
= (1 << 18), /* Calculate IP checksum */
381 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
382 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
383 TxVlanTag
= (1 << 17), /* Add VLAN tag */
386 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
387 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
389 #define RxProtoUDP (PID1)
390 #define RxProtoTCP (PID0)
391 #define RxProtoIP (PID1 | PID0)
392 #define RxProtoMask RxProtoIP
394 IPFail
= (1 << 16), /* IP checksum failed */
395 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
396 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
397 RxVlanTag
= (1 << 16), /* VLAN tag available */
400 #define RsvdMask 0x3fffc000
417 u8 __pad
[sizeof(void *) - sizeof(u32
)];
421 RTL_FEATURE_WOL
= (1 << 0),
422 RTL_FEATURE_MSI
= (1 << 1),
423 RTL_FEATURE_GMII
= (1 << 2),
426 struct rtl8169_private
{
427 void __iomem
*mmio_addr
; /* memory map physical address */
428 struct pci_dev
*pci_dev
; /* Index of PCI device */
429 struct net_device
*dev
;
430 struct napi_struct napi
;
431 spinlock_t lock
; /* spin lock flag */
435 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
436 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
439 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
440 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
441 dma_addr_t TxPhyAddr
;
442 dma_addr_t RxPhyAddr
;
443 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
444 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
447 struct timer_list timer
;
452 int phy_auto_nego_reg
;
453 int phy_1000_ctrl_reg
;
454 #ifdef CONFIG_R8169_VLAN
455 struct vlan_group
*vlgrp
;
457 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
458 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
459 void (*phy_reset_enable
)(void __iomem
*);
460 void (*hw_start
)(struct net_device
*);
461 unsigned int (*phy_reset_pending
)(void __iomem
*);
462 unsigned int (*link_ok
)(void __iomem
*);
464 struct delayed_work task
;
467 struct mii_if_info mii
;
470 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
471 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
472 module_param(rx_copybreak
, int, 0);
473 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
474 module_param(use_dac
, int, 0);
475 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
476 module_param_named(debug
, debug
.msg_enable
, int, 0);
477 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
478 MODULE_LICENSE("GPL");
479 MODULE_VERSION(RTL8169_VERSION
);
481 static int rtl8169_open(struct net_device
*dev
);
482 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
483 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
484 static int rtl8169_init_ring(struct net_device
*dev
);
485 static void rtl_hw_start(struct net_device
*dev
);
486 static int rtl8169_close(struct net_device
*dev
);
487 static void rtl_set_rx_mode(struct net_device
*dev
);
488 static void rtl8169_tx_timeout(struct net_device
*dev
);
489 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
490 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
491 void __iomem
*, u32 budget
);
492 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
493 static void rtl8169_down(struct net_device
*dev
);
494 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
495 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
497 static const unsigned int rtl8169_rx_config
=
498 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
500 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
504 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
506 for (i
= 20; i
> 0; i
--) {
508 * Check if the RTL8169 has completed writing to the specified
511 if (!(RTL_R32(PHYAR
) & 0x80000000))
517 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
521 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
523 for (i
= 20; i
> 0; i
--) {
525 * Check if the RTL8169 has completed retrieving data from
526 * the specified MII register.
528 if (RTL_R32(PHYAR
) & 0x80000000) {
529 value
= RTL_R32(PHYAR
) & 0xffff;
537 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
539 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
542 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
545 struct rtl8169_private
*tp
= netdev_priv(dev
);
546 void __iomem
*ioaddr
= tp
->mmio_addr
;
548 mdio_write(ioaddr
, location
, val
);
551 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
553 struct rtl8169_private
*tp
= netdev_priv(dev
);
554 void __iomem
*ioaddr
= tp
->mmio_addr
;
556 return mdio_read(ioaddr
, location
);
559 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
563 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
564 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
566 for (i
= 0; i
< 100; i
++) {
567 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
573 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
578 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
580 for (i
= 0; i
< 100; i
++) {
581 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
582 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
591 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
595 RTL_W32(CSIDR
, value
);
596 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
597 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
599 for (i
= 0; i
< 100; i
++) {
600 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
606 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
611 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
612 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
614 for (i
= 0; i
< 100; i
++) {
615 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
616 value
= RTL_R32(CSIDR
);
625 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
627 RTL_W16(IntrMask
, 0x0000);
629 RTL_W16(IntrStatus
, 0xffff);
632 static void rtl8169_asic_down(void __iomem
*ioaddr
)
634 RTL_W8(ChipCmd
, 0x00);
635 rtl8169_irq_mask_and_ack(ioaddr
);
639 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
641 return RTL_R32(TBICSR
) & TBIReset
;
644 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
646 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
649 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
651 return RTL_R32(TBICSR
) & TBILinkOk
;
654 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
656 return RTL_R8(PHYstatus
) & LinkStatus
;
659 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
661 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
664 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
668 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
669 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
672 static void rtl8169_check_link_status(struct net_device
*dev
,
673 struct rtl8169_private
*tp
,
674 void __iomem
*ioaddr
)
678 spin_lock_irqsave(&tp
->lock
, flags
);
679 if (tp
->link_ok(ioaddr
)) {
680 netif_carrier_on(dev
);
681 if (netif_msg_ifup(tp
))
682 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
684 if (netif_msg_ifdown(tp
))
685 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
686 netif_carrier_off(dev
);
688 spin_unlock_irqrestore(&tp
->lock
, flags
);
691 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
693 struct rtl8169_private
*tp
= netdev_priv(dev
);
694 void __iomem
*ioaddr
= tp
->mmio_addr
;
699 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700 wol
->supported
= WAKE_ANY
;
702 spin_lock_irq(&tp
->lock
);
704 options
= RTL_R8(Config1
);
705 if (!(options
& PMEnable
))
708 options
= RTL_R8(Config3
);
709 if (options
& LinkUp
)
710 wol
->wolopts
|= WAKE_PHY
;
711 if (options
& MagicPacket
)
712 wol
->wolopts
|= WAKE_MAGIC
;
714 options
= RTL_R8(Config5
);
716 wol
->wolopts
|= WAKE_UCAST
;
718 wol
->wolopts
|= WAKE_BCAST
;
720 wol
->wolopts
|= WAKE_MCAST
;
723 spin_unlock_irq(&tp
->lock
);
726 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
728 struct rtl8169_private
*tp
= netdev_priv(dev
);
729 void __iomem
*ioaddr
= tp
->mmio_addr
;
736 { WAKE_ANY
, Config1
, PMEnable
},
737 { WAKE_PHY
, Config3
, LinkUp
},
738 { WAKE_MAGIC
, Config3
, MagicPacket
},
739 { WAKE_UCAST
, Config5
, UWF
},
740 { WAKE_BCAST
, Config5
, BWF
},
741 { WAKE_MCAST
, Config5
, MWF
},
742 { WAKE_ANY
, Config5
, LanWake
}
745 spin_lock_irq(&tp
->lock
);
747 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
749 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
750 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
751 if (wol
->wolopts
& cfg
[i
].opt
)
752 options
|= cfg
[i
].mask
;
753 RTL_W8(cfg
[i
].reg
, options
);
756 RTL_W8(Cfg9346
, Cfg9346_Lock
);
759 tp
->features
|= RTL_FEATURE_WOL
;
761 tp
->features
&= ~RTL_FEATURE_WOL
;
762 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
764 spin_unlock_irq(&tp
->lock
);
769 static void rtl8169_get_drvinfo(struct net_device
*dev
,
770 struct ethtool_drvinfo
*info
)
772 struct rtl8169_private
*tp
= netdev_priv(dev
);
774 strcpy(info
->driver
, MODULENAME
);
775 strcpy(info
->version
, RTL8169_VERSION
);
776 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
779 static int rtl8169_get_regs_len(struct net_device
*dev
)
781 return R8169_REGS_SIZE
;
784 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
785 u8 autoneg
, u16 speed
, u8 duplex
)
787 struct rtl8169_private
*tp
= netdev_priv(dev
);
788 void __iomem
*ioaddr
= tp
->mmio_addr
;
792 reg
= RTL_R32(TBICSR
);
793 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
794 (duplex
== DUPLEX_FULL
)) {
795 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
796 } else if (autoneg
== AUTONEG_ENABLE
)
797 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
799 if (netif_msg_link(tp
)) {
800 printk(KERN_WARNING
"%s: "
801 "incorrect speed setting refused in TBI mode\n",
810 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
811 u8 autoneg
, u16 speed
, u8 duplex
)
813 struct rtl8169_private
*tp
= netdev_priv(dev
);
814 void __iomem
*ioaddr
= tp
->mmio_addr
;
815 int auto_nego
, giga_ctrl
;
817 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
818 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
819 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
820 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
821 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
823 if (autoneg
== AUTONEG_ENABLE
) {
824 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
825 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
826 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
828 if (speed
== SPEED_10
)
829 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
830 else if (speed
== SPEED_100
)
831 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
832 else if (speed
== SPEED_1000
)
833 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
835 if (duplex
== DUPLEX_HALF
)
836 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
838 if (duplex
== DUPLEX_FULL
)
839 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
841 /* This tweak comes straight from Realtek's driver. */
842 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
843 ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
844 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
))) {
845 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
849 /* The 8100e/8101e/8102e do Fast Ethernet only. */
850 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_07
) ||
851 (tp
->mac_version
== RTL_GIGA_MAC_VER_08
) ||
852 (tp
->mac_version
== RTL_GIGA_MAC_VER_09
) ||
853 (tp
->mac_version
== RTL_GIGA_MAC_VER_10
) ||
854 (tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
855 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
856 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
) ||
857 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
858 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
859 netif_msg_link(tp
)) {
860 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
863 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
866 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
868 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
869 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
870 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
873 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
875 mdio_write(ioaddr
, 0x1f, 0x0000);
876 mdio_write(ioaddr
, 0x0e, 0x0000);
879 tp
->phy_auto_nego_reg
= auto_nego
;
880 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
882 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
883 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
884 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
888 static int rtl8169_set_speed(struct net_device
*dev
,
889 u8 autoneg
, u16 speed
, u8 duplex
)
891 struct rtl8169_private
*tp
= netdev_priv(dev
);
894 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
896 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
897 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
902 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
904 struct rtl8169_private
*tp
= netdev_priv(dev
);
908 spin_lock_irqsave(&tp
->lock
, flags
);
909 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
910 spin_unlock_irqrestore(&tp
->lock
, flags
);
915 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
917 struct rtl8169_private
*tp
= netdev_priv(dev
);
919 return tp
->cp_cmd
& RxChkSum
;
922 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
924 struct rtl8169_private
*tp
= netdev_priv(dev
);
925 void __iomem
*ioaddr
= tp
->mmio_addr
;
928 spin_lock_irqsave(&tp
->lock
, flags
);
931 tp
->cp_cmd
|= RxChkSum
;
933 tp
->cp_cmd
&= ~RxChkSum
;
935 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
938 spin_unlock_irqrestore(&tp
->lock
, flags
);
943 #ifdef CONFIG_R8169_VLAN
945 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
948 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
949 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
952 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
953 struct vlan_group
*grp
)
955 struct rtl8169_private
*tp
= netdev_priv(dev
);
956 void __iomem
*ioaddr
= tp
->mmio_addr
;
959 spin_lock_irqsave(&tp
->lock
, flags
);
962 tp
->cp_cmd
|= RxVlan
;
964 tp
->cp_cmd
&= ~RxVlan
;
965 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
967 spin_unlock_irqrestore(&tp
->lock
, flags
);
970 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
973 u32 opts2
= le32_to_cpu(desc
->opts2
);
974 struct vlan_group
*vlgrp
= tp
->vlgrp
;
977 if (vlgrp
&& (opts2
& RxVlanTag
)) {
978 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
986 #else /* !CONFIG_R8169_VLAN */
988 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
994 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1002 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1004 struct rtl8169_private
*tp
= netdev_priv(dev
);
1005 void __iomem
*ioaddr
= tp
->mmio_addr
;
1009 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1010 cmd
->port
= PORT_FIBRE
;
1011 cmd
->transceiver
= XCVR_INTERNAL
;
1013 status
= RTL_R32(TBICSR
);
1014 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1015 cmd
->autoneg
= !!(status
& TBINwEnable
);
1017 cmd
->speed
= SPEED_1000
;
1018 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1023 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1025 struct rtl8169_private
*tp
= netdev_priv(dev
);
1027 return mii_ethtool_gset(&tp
->mii
, cmd
);
1030 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1032 struct rtl8169_private
*tp
= netdev_priv(dev
);
1033 unsigned long flags
;
1036 spin_lock_irqsave(&tp
->lock
, flags
);
1038 rc
= tp
->get_settings(dev
, cmd
);
1040 spin_unlock_irqrestore(&tp
->lock
, flags
);
1044 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1047 struct rtl8169_private
*tp
= netdev_priv(dev
);
1048 unsigned long flags
;
1050 if (regs
->len
> R8169_REGS_SIZE
)
1051 regs
->len
= R8169_REGS_SIZE
;
1053 spin_lock_irqsave(&tp
->lock
, flags
);
1054 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1055 spin_unlock_irqrestore(&tp
->lock
, flags
);
1058 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1060 struct rtl8169_private
*tp
= netdev_priv(dev
);
1062 return tp
->msg_enable
;
1065 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1067 struct rtl8169_private
*tp
= netdev_priv(dev
);
1069 tp
->msg_enable
= value
;
1072 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1079 "tx_single_collisions",
1080 "tx_multi_collisions",
1088 struct rtl8169_counters
{
1094 __le16 align_errors
;
1095 __le32 tx_one_collision
;
1096 __le32 tx_multi_collision
;
1098 __le64 rx_broadcast
;
1099 __le32 rx_multicast
;
1104 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1108 return ARRAY_SIZE(rtl8169_gstrings
);
1114 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1115 struct ethtool_stats
*stats
, u64
*data
)
1117 struct rtl8169_private
*tp
= netdev_priv(dev
);
1118 void __iomem
*ioaddr
= tp
->mmio_addr
;
1119 struct rtl8169_counters
*counters
;
1125 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1129 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1130 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1131 RTL_W32(CounterAddrLow
, cmd
);
1132 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1134 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1135 if (msleep_interruptible(1))
1139 RTL_W32(CounterAddrLow
, 0);
1140 RTL_W32(CounterAddrHigh
, 0);
1142 data
[0] = le64_to_cpu(counters
->tx_packets
);
1143 data
[1] = le64_to_cpu(counters
->rx_packets
);
1144 data
[2] = le64_to_cpu(counters
->tx_errors
);
1145 data
[3] = le32_to_cpu(counters
->rx_errors
);
1146 data
[4] = le16_to_cpu(counters
->rx_missed
);
1147 data
[5] = le16_to_cpu(counters
->align_errors
);
1148 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1149 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1150 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1151 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1152 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1153 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1154 data
[12] = le16_to_cpu(counters
->tx_underun
);
1156 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1159 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1163 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1168 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1169 .get_drvinfo
= rtl8169_get_drvinfo
,
1170 .get_regs_len
= rtl8169_get_regs_len
,
1171 .get_link
= ethtool_op_get_link
,
1172 .get_settings
= rtl8169_get_settings
,
1173 .set_settings
= rtl8169_set_settings
,
1174 .get_msglevel
= rtl8169_get_msglevel
,
1175 .set_msglevel
= rtl8169_set_msglevel
,
1176 .get_rx_csum
= rtl8169_get_rx_csum
,
1177 .set_rx_csum
= rtl8169_set_rx_csum
,
1178 .set_tx_csum
= ethtool_op_set_tx_csum
,
1179 .set_sg
= ethtool_op_set_sg
,
1180 .set_tso
= ethtool_op_set_tso
,
1181 .get_regs
= rtl8169_get_regs
,
1182 .get_wol
= rtl8169_get_wol
,
1183 .set_wol
= rtl8169_set_wol
,
1184 .get_strings
= rtl8169_get_strings
,
1185 .get_sset_count
= rtl8169_get_sset_count
,
1186 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1189 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1190 int bitnum
, int bitval
)
1194 val
= mdio_read(ioaddr
, reg
);
1195 val
= (bitval
== 1) ?
1196 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1197 mdio_write(ioaddr
, reg
, val
& 0xffff);
1200 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1201 void __iomem
*ioaddr
)
1204 * The driver currently handles the 8168Bf and the 8168Be identically
1205 * but they can be identified more specifically through the test below
1208 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1210 * Same thing for the 8101Eb and the 8101Ec:
1212 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1220 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1221 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1222 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1223 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20
},
1226 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1227 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1228 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1229 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1232 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1233 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1234 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1235 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1236 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1237 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1238 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1239 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1240 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1241 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1242 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1243 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1244 /* FIXME: where did these entries come from ? -- FR */
1245 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1246 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1249 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1250 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1251 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1252 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1253 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1254 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1256 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1260 reg
= RTL_R32(TxConfig
);
1261 while ((reg
& p
->mask
) != p
->val
)
1263 tp
->mac_version
= p
->mac_version
;
1265 if (p
->mask
== 0x00000000) {
1266 struct pci_dev
*pdev
= tp
->pci_dev
;
1268 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1272 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1274 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1282 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1285 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1290 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1293 u16 regs
[5]; /* Beware of bit-sign propagation */
1294 } phy_magic
[5] = { {
1295 { 0x0000, //w 4 15 12 0
1296 0x00a1, //w 3 15 0 00a1
1297 0x0008, //w 2 15 0 0008
1298 0x1020, //w 1 15 0 1020
1299 0x1000 } },{ //w 0 15 0 1000
1300 { 0x7000, //w 4 15 12 7
1301 0xff41, //w 3 15 0 ff41
1302 0xde60, //w 2 15 0 de60
1303 0x0140, //w 1 15 0 0140
1304 0x0077 } },{ //w 0 15 0 0077
1305 { 0xa000, //w 4 15 12 a
1306 0xdf01, //w 3 15 0 df01
1307 0xdf20, //w 2 15 0 df20
1308 0xff95, //w 1 15 0 ff95
1309 0xfa00 } },{ //w 0 15 0 fa00
1310 { 0xb000, //w 4 15 12 b
1311 0xff41, //w 3 15 0 ff41
1312 0xde20, //w 2 15 0 de20
1313 0x0140, //w 1 15 0 0140
1314 0x00bb } },{ //w 0 15 0 00bb
1315 { 0xf000, //w 4 15 12 f
1316 0xdf01, //w 3 15 0 df01
1317 0xdf20, //w 2 15 0 df20
1318 0xff95, //w 1 15 0 ff95
1319 0xbf00 } //w 0 15 0 bf00
1324 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1325 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1326 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1327 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1329 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1332 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1333 mdio_write(ioaddr
, pos
, val
);
1335 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1336 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1337 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1339 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1342 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1344 struct phy_reg phy_reg_init
[] = {
1350 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1353 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1355 struct phy_reg phy_reg_init
[] = {
1360 mdio_write(ioaddr
, 0x1f, 0x0001);
1361 mdio_patch(ioaddr
, 0x16, 1 << 0);
1363 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1366 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1368 struct phy_reg phy_reg_init
[] = {
1374 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1377 static void rtl8168cp_hw_phy_config(void __iomem
*ioaddr
)
1379 struct phy_reg phy_reg_init
[] = {
1387 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1390 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1392 struct phy_reg phy_reg_init
[] = {
1412 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1414 mdio_patch(ioaddr
, 0x14, 1 << 5);
1415 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1416 mdio_write(ioaddr
, 0x1f, 0x0000);
1419 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1421 struct phy_reg phy_reg_init
[] = {
1439 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1441 mdio_patch(ioaddr
, 0x16, 1 << 0);
1442 mdio_patch(ioaddr
, 0x14, 1 << 5);
1443 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1444 mdio_write(ioaddr
, 0x1f, 0x0000);
1447 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1449 struct phy_reg phy_reg_init
[] = {
1456 mdio_write(ioaddr
, 0x1f, 0x0000);
1457 mdio_patch(ioaddr
, 0x11, 1 << 12);
1458 mdio_patch(ioaddr
, 0x19, 1 << 13);
1460 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1463 static void rtl_hw_phy_config(struct net_device
*dev
)
1465 struct rtl8169_private
*tp
= netdev_priv(dev
);
1466 void __iomem
*ioaddr
= tp
->mmio_addr
;
1468 rtl8169_print_mac_version(tp
);
1470 switch (tp
->mac_version
) {
1471 case RTL_GIGA_MAC_VER_01
:
1473 case RTL_GIGA_MAC_VER_02
:
1474 case RTL_GIGA_MAC_VER_03
:
1475 rtl8169s_hw_phy_config(ioaddr
);
1477 case RTL_GIGA_MAC_VER_04
:
1478 rtl8169sb_hw_phy_config(ioaddr
);
1480 case RTL_GIGA_MAC_VER_07
:
1481 case RTL_GIGA_MAC_VER_08
:
1482 case RTL_GIGA_MAC_VER_09
:
1483 rtl8102e_hw_phy_config(ioaddr
);
1485 case RTL_GIGA_MAC_VER_11
:
1486 rtl8168bb_hw_phy_config(ioaddr
);
1488 case RTL_GIGA_MAC_VER_12
:
1489 rtl8168bef_hw_phy_config(ioaddr
);
1491 case RTL_GIGA_MAC_VER_17
:
1492 rtl8168bef_hw_phy_config(ioaddr
);
1494 case RTL_GIGA_MAC_VER_18
:
1495 rtl8168cp_hw_phy_config(ioaddr
);
1497 case RTL_GIGA_MAC_VER_19
:
1498 rtl8168c_1_hw_phy_config(ioaddr
);
1500 case RTL_GIGA_MAC_VER_20
:
1501 rtl8168c_2_hw_phy_config(ioaddr
);
1508 static void rtl8169_phy_timer(unsigned long __opaque
)
1510 struct net_device
*dev
= (struct net_device
*)__opaque
;
1511 struct rtl8169_private
*tp
= netdev_priv(dev
);
1512 struct timer_list
*timer
= &tp
->timer
;
1513 void __iomem
*ioaddr
= tp
->mmio_addr
;
1514 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1516 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1518 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1521 spin_lock_irq(&tp
->lock
);
1523 if (tp
->phy_reset_pending(ioaddr
)) {
1525 * A busy loop could burn quite a few cycles on nowadays CPU.
1526 * Let's delay the execution of the timer for a few ticks.
1532 if (tp
->link_ok(ioaddr
))
1535 if (netif_msg_link(tp
))
1536 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1538 tp
->phy_reset_enable(ioaddr
);
1541 mod_timer(timer
, jiffies
+ timeout
);
1543 spin_unlock_irq(&tp
->lock
);
1546 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1548 struct rtl8169_private
*tp
= netdev_priv(dev
);
1549 struct timer_list
*timer
= &tp
->timer
;
1551 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1554 del_timer_sync(timer
);
1557 static inline void rtl8169_request_timer(struct net_device
*dev
)
1559 struct rtl8169_private
*tp
= netdev_priv(dev
);
1560 struct timer_list
*timer
= &tp
->timer
;
1562 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1565 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1568 #ifdef CONFIG_NET_POLL_CONTROLLER
1570 * Polling 'interrupt' - used by things like netconsole to send skbs
1571 * without having to re-enable interrupts. It's not called while
1572 * the interrupt routine is executing.
1574 static void rtl8169_netpoll(struct net_device
*dev
)
1576 struct rtl8169_private
*tp
= netdev_priv(dev
);
1577 struct pci_dev
*pdev
= tp
->pci_dev
;
1579 disable_irq(pdev
->irq
);
1580 rtl8169_interrupt(pdev
->irq
, dev
);
1581 enable_irq(pdev
->irq
);
1585 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1586 void __iomem
*ioaddr
)
1589 pci_release_regions(pdev
);
1590 pci_disable_device(pdev
);
1594 static void rtl8169_phy_reset(struct net_device
*dev
,
1595 struct rtl8169_private
*tp
)
1597 void __iomem
*ioaddr
= tp
->mmio_addr
;
1600 tp
->phy_reset_enable(ioaddr
);
1601 for (i
= 0; i
< 100; i
++) {
1602 if (!tp
->phy_reset_pending(ioaddr
))
1606 if (netif_msg_link(tp
))
1607 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1610 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1612 void __iomem
*ioaddr
= tp
->mmio_addr
;
1614 rtl_hw_phy_config(dev
);
1616 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1617 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1621 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1623 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1624 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1626 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1627 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1629 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1630 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1633 rtl8169_phy_reset(dev
, tp
);
1636 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1637 * only 8101. Don't panic.
1639 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1641 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1642 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1645 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1647 void __iomem
*ioaddr
= tp
->mmio_addr
;
1651 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1652 high
= addr
[4] | (addr
[5] << 8);
1654 spin_lock_irq(&tp
->lock
);
1656 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1658 RTL_W32(MAC4
, high
);
1659 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1661 spin_unlock_irq(&tp
->lock
);
1664 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1666 struct rtl8169_private
*tp
= netdev_priv(dev
);
1667 struct sockaddr
*addr
= p
;
1669 if (!is_valid_ether_addr(addr
->sa_data
))
1670 return -EADDRNOTAVAIL
;
1672 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1674 rtl_rar_set(tp
, dev
->dev_addr
);
1679 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1681 struct rtl8169_private
*tp
= netdev_priv(dev
);
1682 struct mii_ioctl_data
*data
= if_mii(ifr
);
1684 if (!netif_running(dev
))
1689 data
->phy_id
= 32; /* Internal PHY */
1693 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1697 if (!capable(CAP_NET_ADMIN
))
1699 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1705 static const struct rtl_cfg_info
{
1706 void (*hw_start
)(struct net_device
*);
1707 unsigned int region
;
1712 } rtl_cfg_infos
[] = {
1714 .hw_start
= rtl_hw_start_8169
,
1717 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1718 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1719 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1720 .features
= RTL_FEATURE_GMII
1723 .hw_start
= rtl_hw_start_8168
,
1726 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1727 TxErr
| TxOK
| RxOK
| RxErr
,
1728 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1729 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1732 .hw_start
= rtl_hw_start_8101
,
1735 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1736 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1737 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1738 .features
= RTL_FEATURE_MSI
1742 /* Cfg9346_Unlock assumed. */
1743 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1744 const struct rtl_cfg_info
*cfg
)
1749 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1750 if (cfg
->features
& RTL_FEATURE_MSI
) {
1751 if (pci_enable_msi(pdev
)) {
1752 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1755 msi
= RTL_FEATURE_MSI
;
1758 RTL_W8(Config2
, cfg2
);
1762 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1764 if (tp
->features
& RTL_FEATURE_MSI
) {
1765 pci_disable_msi(pdev
);
1766 tp
->features
&= ~RTL_FEATURE_MSI
;
1770 static int rtl_eeprom_read(struct pci_dev
*pdev
, int cap
, int addr
, __le32
*val
)
1772 int ret
, count
= 100;
1776 ret
= pci_write_config_word(pdev
, cap
+ PCI_VPD_ADDR
, addr
);
1782 ret
= pci_read_config_word(pdev
, cap
+ PCI_VPD_ADDR
, &status
);
1785 } while (!(status
& PCI_VPD_ADDR_F
) && --count
);
1787 if (!(status
& PCI_VPD_ADDR_F
))
1790 ret
= pci_read_config_dword(pdev
, cap
+ PCI_VPD_DATA
, &value
);
1794 *val
= cpu_to_le32(value
);
1799 static void rtl_init_mac_address(struct rtl8169_private
*tp
,
1800 void __iomem
*ioaddr
)
1802 struct pci_dev
*pdev
= tp
->pci_dev
;
1806 DECLARE_MAC_BUF(buf
);
1808 cfg1
= RTL_R8(Config1
);
1809 if (!(cfg1
& VPD
)) {
1810 dprintk("VPD access not enabled, enabling\n");
1811 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1812 RTL_W8(Config1
, cfg1
| VPD
);
1813 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1816 vpd_cap
= pci_find_capability(pdev
, PCI_CAP_ID_VPD
);
1820 /* MAC address is stored in EEPROM at offset 0x0e
1821 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1822 * address as defined in the PCI 2.2 Specifications, but the VPD data
1823 * is always consecutive 4-byte data starting from the VPD address
1826 if (rtl_eeprom_read(pdev
, vpd_cap
, 0x000e, (__le32
*)&mac
[0]) < 0 ||
1827 rtl_eeprom_read(pdev
, vpd_cap
, 0x0012, (__le32
*)&mac
[4]) < 0) {
1828 dprintk("Reading MAC address from EEPROM failed\n");
1832 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf
, mac
));
1834 /* Write MAC address */
1835 rtl_rar_set(tp
, mac
);
1838 static int __devinit
1839 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1841 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1842 const unsigned int region
= cfg
->region
;
1843 struct rtl8169_private
*tp
;
1844 struct mii_if_info
*mii
;
1845 struct net_device
*dev
;
1846 void __iomem
*ioaddr
;
1850 if (netif_msg_drv(&debug
)) {
1851 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1852 MODULENAME
, RTL8169_VERSION
);
1855 dev
= alloc_etherdev(sizeof (*tp
));
1857 if (netif_msg_drv(&debug
))
1858 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1863 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1864 tp
= netdev_priv(dev
);
1867 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
1871 mii
->mdio_read
= rtl_mdio_read
;
1872 mii
->mdio_write
= rtl_mdio_write
;
1873 mii
->phy_id_mask
= 0x1f;
1874 mii
->reg_num_mask
= 0x1f;
1875 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
1877 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1878 rc
= pci_enable_device(pdev
);
1880 if (netif_msg_probe(tp
))
1881 dev_err(&pdev
->dev
, "enable failure\n");
1882 goto err_out_free_dev_1
;
1885 rc
= pci_set_mwi(pdev
);
1887 goto err_out_disable_2
;
1889 /* make sure PCI base addr 1 is MMIO */
1890 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
1891 if (netif_msg_probe(tp
)) {
1893 "region #%d not an MMIO resource, aborting\n",
1900 /* check for weird/broken PCI region reporting */
1901 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
1902 if (netif_msg_probe(tp
)) {
1904 "Invalid PCI region size(s), aborting\n");
1910 rc
= pci_request_regions(pdev
, MODULENAME
);
1912 if (netif_msg_probe(tp
))
1913 dev_err(&pdev
->dev
, "could not request regions.\n");
1917 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
1919 if ((sizeof(dma_addr_t
) > 4) &&
1920 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
1921 tp
->cp_cmd
|= PCIDAC
;
1922 dev
->features
|= NETIF_F_HIGHDMA
;
1924 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1926 if (netif_msg_probe(tp
)) {
1928 "DMA configuration failed.\n");
1930 goto err_out_free_res_4
;
1934 pci_set_master(pdev
);
1936 /* ioremap MMIO region */
1937 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
1939 if (netif_msg_probe(tp
))
1940 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
1942 goto err_out_free_res_4
;
1945 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1946 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
1947 dev_info(&pdev
->dev
, "no PCI Express capability\n");
1949 /* Unneeded ? Don't mess with Mrs. Murphy. */
1950 rtl8169_irq_mask_and_ack(ioaddr
);
1952 /* Soft reset the chip. */
1953 RTL_W8(ChipCmd
, CmdReset
);
1955 /* Check that the chip has finished the reset. */
1956 for (i
= 0; i
< 100; i
++) {
1957 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
1959 msleep_interruptible(1);
1962 /* Identify chip attached to board */
1963 rtl8169_get_mac_version(tp
, ioaddr
);
1965 rtl8169_print_mac_version(tp
);
1967 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
1968 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
1971 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
1972 /* Unknown chip: assume array element #0, original RTL-8169 */
1973 if (netif_msg_probe(tp
)) {
1974 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1975 "unknown chip version, assuming %s\n",
1976 rtl_chip_info
[0].name
);
1982 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1983 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
1984 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
1985 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
1986 tp
->features
|= RTL_FEATURE_WOL
;
1987 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
1988 tp
->features
|= RTL_FEATURE_WOL
;
1989 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
1990 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1992 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
1993 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
1994 tp
->set_speed
= rtl8169_set_speed_tbi
;
1995 tp
->get_settings
= rtl8169_gset_tbi
;
1996 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
1997 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
1998 tp
->link_ok
= rtl8169_tbi_link_ok
;
2000 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
2002 tp
->set_speed
= rtl8169_set_speed_xmii
;
2003 tp
->get_settings
= rtl8169_gset_xmii
;
2004 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
2005 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
2006 tp
->link_ok
= rtl8169_xmii_link_ok
;
2008 dev
->do_ioctl
= rtl8169_ioctl
;
2011 spin_lock_init(&tp
->lock
);
2013 rtl_init_mac_address(tp
, ioaddr
);
2015 /* Get MAC address */
2016 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
2017 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
2018 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2020 dev
->open
= rtl8169_open
;
2021 dev
->hard_start_xmit
= rtl8169_start_xmit
;
2022 dev
->get_stats
= rtl8169_get_stats
;
2023 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
2024 dev
->stop
= rtl8169_close
;
2025 dev
->tx_timeout
= rtl8169_tx_timeout
;
2026 dev
->set_multicast_list
= rtl_set_rx_mode
;
2027 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
2028 dev
->irq
= pdev
->irq
;
2029 dev
->base_addr
= (unsigned long) ioaddr
;
2030 dev
->change_mtu
= rtl8169_change_mtu
;
2031 dev
->set_mac_address
= rtl_set_mac_address
;
2033 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
2035 #ifdef CONFIG_R8169_VLAN
2036 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2037 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
2040 #ifdef CONFIG_NET_POLL_CONTROLLER
2041 dev
->poll_controller
= rtl8169_netpoll
;
2044 tp
->intr_mask
= 0xffff;
2045 tp
->mmio_addr
= ioaddr
;
2046 tp
->align
= cfg
->align
;
2047 tp
->hw_start
= cfg
->hw_start
;
2048 tp
->intr_event
= cfg
->intr_event
;
2049 tp
->napi_event
= cfg
->napi_event
;
2051 init_timer(&tp
->timer
);
2052 tp
->timer
.data
= (unsigned long) dev
;
2053 tp
->timer
.function
= rtl8169_phy_timer
;
2055 rc
= register_netdev(dev
);
2059 pci_set_drvdata(pdev
, dev
);
2061 if (netif_msg_probe(tp
)) {
2062 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
2064 printk(KERN_INFO
"%s: %s at 0x%lx, "
2065 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2066 "XID %08x IRQ %d\n",
2068 rtl_chip_info
[tp
->chipset
].name
,
2070 dev
->dev_addr
[0], dev
->dev_addr
[1],
2071 dev
->dev_addr
[2], dev
->dev_addr
[3],
2072 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2075 rtl8169_init_phy(dev
, tp
);
2076 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
2082 rtl_disable_msi(pdev
, tp
);
2085 pci_release_regions(pdev
);
2087 pci_clear_mwi(pdev
);
2089 pci_disable_device(pdev
);
2095 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2097 struct net_device
*dev
= pci_get_drvdata(pdev
);
2098 struct rtl8169_private
*tp
= netdev_priv(dev
);
2100 flush_scheduled_work();
2102 unregister_netdev(dev
);
2103 rtl_disable_msi(pdev
, tp
);
2104 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2105 pci_set_drvdata(pdev
, NULL
);
2108 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2109 struct net_device
*dev
)
2111 unsigned int mtu
= dev
->mtu
;
2113 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2116 static int rtl8169_open(struct net_device
*dev
)
2118 struct rtl8169_private
*tp
= netdev_priv(dev
);
2119 struct pci_dev
*pdev
= tp
->pci_dev
;
2120 int retval
= -ENOMEM
;
2123 rtl8169_set_rxbufsize(tp
, dev
);
2126 * Rx and Tx desscriptors needs 256 bytes alignment.
2127 * pci_alloc_consistent provides more.
2129 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2131 if (!tp
->TxDescArray
)
2134 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2136 if (!tp
->RxDescArray
)
2139 retval
= rtl8169_init_ring(dev
);
2143 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2147 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2148 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2151 goto err_release_ring_2
;
2153 napi_enable(&tp
->napi
);
2157 rtl8169_request_timer(dev
);
2159 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2164 rtl8169_rx_clear(tp
);
2166 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2169 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2174 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2176 /* Disable interrupts */
2177 rtl8169_irq_mask_and_ack(ioaddr
);
2179 /* Reset the chipset */
2180 RTL_W8(ChipCmd
, CmdReset
);
2186 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2188 void __iomem
*ioaddr
= tp
->mmio_addr
;
2189 u32 cfg
= rtl8169_rx_config
;
2191 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2192 RTL_W32(RxConfig
, cfg
);
2194 /* Set DMA burst size and Interframe Gap Time */
2195 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2196 (InterFrameGap
<< TxInterFrameGapShift
));
2199 static void rtl_hw_start(struct net_device
*dev
)
2201 struct rtl8169_private
*tp
= netdev_priv(dev
);
2202 void __iomem
*ioaddr
= tp
->mmio_addr
;
2205 /* Soft reset the chip. */
2206 RTL_W8(ChipCmd
, CmdReset
);
2208 /* Check that the chip has finished the reset. */
2209 for (i
= 0; i
< 100; i
++) {
2210 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2212 msleep_interruptible(1);
2217 netif_start_queue(dev
);
2221 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2222 void __iomem
*ioaddr
)
2225 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2226 * register to be written before TxDescAddrLow to work.
2227 * Switching from MMIO to I/O access fixes the issue as well.
2229 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2230 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
2231 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2232 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
2235 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2239 cmd
= RTL_R16(CPlusCmd
);
2240 RTL_W16(CPlusCmd
, cmd
);
2244 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
2246 /* Low hurts. Let's disable the filtering. */
2247 RTL_W16(RxMaxSize
, 16383);
2250 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2257 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2258 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2259 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2260 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2265 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2266 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2267 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2268 RTL_W32(0x7c, p
->val
);
2274 static void rtl_hw_start_8169(struct net_device
*dev
)
2276 struct rtl8169_private
*tp
= netdev_priv(dev
);
2277 void __iomem
*ioaddr
= tp
->mmio_addr
;
2278 struct pci_dev
*pdev
= tp
->pci_dev
;
2280 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2281 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2282 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2285 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2286 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2287 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2288 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2289 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2290 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2292 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2294 rtl_set_rx_max_size(ioaddr
);
2296 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2297 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2298 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2299 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2300 rtl_set_rx_tx_config_registers(tp
);
2302 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2304 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2305 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2306 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2307 "Bit-3 and bit-14 MUST be 1\n");
2308 tp
->cp_cmd
|= (1 << 14);
2311 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2313 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2316 * Undocumented corner. Supposedly:
2317 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2319 RTL_W16(IntrMitigate
, 0x0000);
2321 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2323 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2324 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2325 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2326 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2327 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2328 rtl_set_rx_tx_config_registers(tp
);
2331 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2333 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2336 RTL_W32(RxMissed
, 0);
2338 rtl_set_rx_mode(dev
);
2340 /* no early-rx interrupts */
2341 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2343 /* Enable all known interrupts by setting the interrupt mask. */
2344 RTL_W16(IntrMask
, tp
->intr_event
);
2347 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2349 struct net_device
*dev
= pci_get_drvdata(pdev
);
2350 struct rtl8169_private
*tp
= netdev_priv(dev
);
2351 int cap
= tp
->pcie_cap
;
2356 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2357 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2358 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2362 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2366 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2367 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2371 unsigned int offset
;
2376 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2381 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2382 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2387 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2389 rtl_tx_performance_tweak(pdev
,
2390 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
2393 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2395 rtl_hw_start_8168bb(ioaddr
, pdev
);
2398 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2400 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2403 static void rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2405 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2408 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2410 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2413 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2415 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2418 static void rtl_hw_start_8168(struct net_device
*dev
)
2420 struct rtl8169_private
*tp
= netdev_priv(dev
);
2421 void __iomem
*ioaddr
= tp
->mmio_addr
;
2422 struct pci_dev
*pdev
= tp
->pci_dev
;
2424 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2426 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2428 rtl_set_rx_max_size(ioaddr
);
2430 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2432 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2434 RTL_W16(IntrMitigate
, 0x5151);
2436 /* Work around for RxFIFO overflow. */
2437 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2438 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2439 tp
->intr_event
&= ~RxOverflow
;
2442 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2444 rtl_set_rx_mode(dev
);
2446 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2447 (InterFrameGap
<< TxInterFrameGapShift
));
2451 switch (tp
->mac_version
) {
2452 case RTL_GIGA_MAC_VER_11
:
2453 rtl_hw_start_8168bb(ioaddr
, pdev
);
2456 case RTL_GIGA_MAC_VER_12
:
2457 case RTL_GIGA_MAC_VER_17
:
2458 rtl_hw_start_8168bef(ioaddr
, pdev
);
2461 case RTL_GIGA_MAC_VER_18
:
2462 rtl_hw_start_8168cp(ioaddr
, pdev
);
2465 case RTL_GIGA_MAC_VER_19
:
2466 rtl_hw_start_8168c_1(ioaddr
, pdev
);
2469 case RTL_GIGA_MAC_VER_20
:
2470 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2474 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
2475 dev
->name
, tp
->mac_version
);
2479 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2481 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2483 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2485 RTL_W16(IntrMask
, tp
->intr_event
);
2488 #define R810X_CPCMD_QUIRK_MASK (\
2500 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2502 static struct ephy_info e_info_8102e_1
[] = {
2503 { 0x01, 0, 0x6e65 },
2504 { 0x02, 0, 0x091f },
2505 { 0x03, 0, 0xc2f9 },
2506 { 0x06, 0, 0xafb5 },
2507 { 0x07, 0, 0x0e00 },
2508 { 0x19, 0, 0xec80 },
2509 { 0x01, 0, 0x2e65 },
2514 rtl_csi_access_enable(ioaddr
);
2516 RTL_W8(DBG_REG
, FIX_NAK_1
);
2518 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2521 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2522 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2524 cfg1
= RTL_R8(Config1
);
2525 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2526 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2528 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2530 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2533 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2535 rtl_csi_access_enable(ioaddr
);
2537 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2539 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2540 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2542 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2545 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2547 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2549 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2552 static void rtl_hw_start_8101(struct net_device
*dev
)
2554 struct rtl8169_private
*tp
= netdev_priv(dev
);
2555 void __iomem
*ioaddr
= tp
->mmio_addr
;
2556 struct pci_dev
*pdev
= tp
->pci_dev
;
2558 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2559 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2560 int cap
= tp
->pcie_cap
;
2563 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2564 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2568 switch (tp
->mac_version
) {
2569 case RTL_GIGA_MAC_VER_07
:
2570 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2573 case RTL_GIGA_MAC_VER_08
:
2574 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2577 case RTL_GIGA_MAC_VER_09
:
2578 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2582 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2584 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2586 rtl_set_rx_max_size(ioaddr
);
2588 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2590 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2592 RTL_W16(IntrMitigate
, 0x0000);
2594 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2596 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2597 rtl_set_rx_tx_config_registers(tp
);
2599 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2603 rtl_set_rx_mode(dev
);
2605 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2607 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2609 RTL_W16(IntrMask
, tp
->intr_event
);
2612 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2614 struct rtl8169_private
*tp
= netdev_priv(dev
);
2617 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2622 if (!netif_running(dev
))
2627 rtl8169_set_rxbufsize(tp
, dev
);
2629 ret
= rtl8169_init_ring(dev
);
2633 napi_enable(&tp
->napi
);
2637 rtl8169_request_timer(dev
);
2643 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2645 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2646 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2649 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2650 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2652 struct pci_dev
*pdev
= tp
->pci_dev
;
2654 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2655 PCI_DMA_FROMDEVICE
);
2656 dev_kfree_skb(*sk_buff
);
2658 rtl8169_make_unusable_by_asic(desc
);
2661 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2663 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2665 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2668 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2671 desc
->addr
= cpu_to_le64(mapping
);
2673 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2676 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2677 struct net_device
*dev
,
2678 struct RxDesc
*desc
, int rx_buf_sz
,
2681 struct sk_buff
*skb
;
2685 pad
= align
? align
: NET_IP_ALIGN
;
2687 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2691 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2693 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2694 PCI_DMA_FROMDEVICE
);
2696 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2701 rtl8169_make_unusable_by_asic(desc
);
2705 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2709 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2710 if (tp
->Rx_skbuff
[i
]) {
2711 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2712 tp
->RxDescArray
+ i
);
2717 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2722 for (cur
= start
; end
- cur
!= 0; cur
++) {
2723 struct sk_buff
*skb
;
2724 unsigned int i
= cur
% NUM_RX_DESC
;
2726 WARN_ON((s32
)(end
- cur
) < 0);
2728 if (tp
->Rx_skbuff
[i
])
2731 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
2732 tp
->RxDescArray
+ i
,
2733 tp
->rx_buf_sz
, tp
->align
);
2737 tp
->Rx_skbuff
[i
] = skb
;
2742 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
2744 desc
->opts1
|= cpu_to_le32(RingEnd
);
2747 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
2749 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
2752 static int rtl8169_init_ring(struct net_device
*dev
)
2754 struct rtl8169_private
*tp
= netdev_priv(dev
);
2756 rtl8169_init_ring_indexes(tp
);
2758 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
2759 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
2761 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
2764 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
2769 rtl8169_rx_clear(tp
);
2773 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
2774 struct TxDesc
*desc
)
2776 unsigned int len
= tx_skb
->len
;
2778 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
2785 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
2789 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
2790 unsigned int entry
= i
% NUM_TX_DESC
;
2791 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
2792 unsigned int len
= tx_skb
->len
;
2795 struct sk_buff
*skb
= tx_skb
->skb
;
2797 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
2798 tp
->TxDescArray
+ entry
);
2803 tp
->dev
->stats
.tx_dropped
++;
2806 tp
->cur_tx
= tp
->dirty_tx
= 0;
2809 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
2811 struct rtl8169_private
*tp
= netdev_priv(dev
);
2813 PREPARE_DELAYED_WORK(&tp
->task
, task
);
2814 schedule_delayed_work(&tp
->task
, 4);
2817 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
2819 struct rtl8169_private
*tp
= netdev_priv(dev
);
2820 void __iomem
*ioaddr
= tp
->mmio_addr
;
2822 synchronize_irq(dev
->irq
);
2824 /* Wait for any pending NAPI task to complete */
2825 napi_disable(&tp
->napi
);
2827 rtl8169_irq_mask_and_ack(ioaddr
);
2829 tp
->intr_mask
= 0xffff;
2830 RTL_W16(IntrMask
, tp
->intr_event
);
2831 napi_enable(&tp
->napi
);
2834 static void rtl8169_reinit_task(struct work_struct
*work
)
2836 struct rtl8169_private
*tp
=
2837 container_of(work
, struct rtl8169_private
, task
.work
);
2838 struct net_device
*dev
= tp
->dev
;
2843 if (!netif_running(dev
))
2846 rtl8169_wait_for_quiescence(dev
);
2849 ret
= rtl8169_open(dev
);
2850 if (unlikely(ret
< 0)) {
2851 if (net_ratelimit() && netif_msg_drv(tp
)) {
2852 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
2853 " Rescheduling.\n", dev
->name
, ret
);
2855 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
2862 static void rtl8169_reset_task(struct work_struct
*work
)
2864 struct rtl8169_private
*tp
=
2865 container_of(work
, struct rtl8169_private
, task
.work
);
2866 struct net_device
*dev
= tp
->dev
;
2870 if (!netif_running(dev
))
2873 rtl8169_wait_for_quiescence(dev
);
2875 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
2876 rtl8169_tx_clear(tp
);
2878 if (tp
->dirty_rx
== tp
->cur_rx
) {
2879 rtl8169_init_ring_indexes(tp
);
2881 netif_wake_queue(dev
);
2882 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2884 if (net_ratelimit() && netif_msg_intr(tp
)) {
2885 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
2888 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2895 static void rtl8169_tx_timeout(struct net_device
*dev
)
2897 struct rtl8169_private
*tp
= netdev_priv(dev
);
2899 rtl8169_hw_reset(tp
->mmio_addr
);
2901 /* Let's wait a bit while any (async) irq lands on */
2902 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
2905 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
2908 struct skb_shared_info
*info
= skb_shinfo(skb
);
2909 unsigned int cur_frag
, entry
;
2910 struct TxDesc
* uninitialized_var(txd
);
2913 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
2914 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
2919 entry
= (entry
+ 1) % NUM_TX_DESC
;
2921 txd
= tp
->TxDescArray
+ entry
;
2923 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
2924 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
2926 /* anti gcc 2.95.3 bugware (sic) */
2927 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
2929 txd
->opts1
= cpu_to_le32(status
);
2930 txd
->addr
= cpu_to_le64(mapping
);
2932 tp
->tx_skb
[entry
].len
= len
;
2936 tp
->tx_skb
[entry
].skb
= skb
;
2937 txd
->opts1
|= cpu_to_le32(LastFrag
);
2943 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
2945 if (dev
->features
& NETIF_F_TSO
) {
2946 u32 mss
= skb_shinfo(skb
)->gso_size
;
2949 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
2951 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2952 const struct iphdr
*ip
= ip_hdr(skb
);
2954 if (ip
->protocol
== IPPROTO_TCP
)
2955 return IPCS
| TCPCS
;
2956 else if (ip
->protocol
== IPPROTO_UDP
)
2957 return IPCS
| UDPCS
;
2958 WARN_ON(1); /* we need a WARN() */
2963 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2965 struct rtl8169_private
*tp
= netdev_priv(dev
);
2966 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
2967 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
2968 void __iomem
*ioaddr
= tp
->mmio_addr
;
2972 int ret
= NETDEV_TX_OK
;
2974 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
2975 if (netif_msg_drv(tp
)) {
2977 "%s: BUG! Tx Ring full when queue awake!\n",
2983 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
2986 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
2988 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
2990 len
= skb_headlen(skb
);
2995 if (unlikely(len
< ETH_ZLEN
)) {
2996 if (skb_padto(skb
, ETH_ZLEN
))
2997 goto err_update_stats
;
3001 opts1
|= FirstFrag
| LastFrag
;
3002 tp
->tx_skb
[entry
].skb
= skb
;
3005 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3007 tp
->tx_skb
[entry
].len
= len
;
3008 txd
->addr
= cpu_to_le64(mapping
);
3009 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
3013 /* anti gcc 2.95.3 bugware (sic) */
3014 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3015 txd
->opts1
= cpu_to_le32(status
);
3017 dev
->trans_start
= jiffies
;
3019 tp
->cur_tx
+= frags
+ 1;
3023 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
3025 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
3026 netif_stop_queue(dev
);
3028 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
3029 netif_wake_queue(dev
);
3036 netif_stop_queue(dev
);
3037 ret
= NETDEV_TX_BUSY
;
3039 dev
->stats
.tx_dropped
++;
3043 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
3045 struct rtl8169_private
*tp
= netdev_priv(dev
);
3046 struct pci_dev
*pdev
= tp
->pci_dev
;
3047 void __iomem
*ioaddr
= tp
->mmio_addr
;
3048 u16 pci_status
, pci_cmd
;
3050 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3051 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3053 if (netif_msg_intr(tp
)) {
3055 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3056 dev
->name
, pci_cmd
, pci_status
);
3060 * The recovery sequence below admits a very elaborated explanation:
3061 * - it seems to work;
3062 * - I did not see what else could be done;
3063 * - it makes iop3xx happy.
3065 * Feel free to adjust to your needs.
3067 if (pdev
->broken_parity_status
)
3068 pci_cmd
&= ~PCI_COMMAND_PARITY
;
3070 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
3072 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
3074 pci_write_config_word(pdev
, PCI_STATUS
,
3075 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
3076 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
3077 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
3079 /* The infamous DAC f*ckup only happens at boot time */
3080 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
3081 if (netif_msg_intr(tp
))
3082 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
3083 tp
->cp_cmd
&= ~PCIDAC
;
3084 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3085 dev
->features
&= ~NETIF_F_HIGHDMA
;
3088 rtl8169_hw_reset(ioaddr
);
3090 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3093 static void rtl8169_tx_interrupt(struct net_device
*dev
,
3094 struct rtl8169_private
*tp
,
3095 void __iomem
*ioaddr
)
3097 unsigned int dirty_tx
, tx_left
;
3099 dirty_tx
= tp
->dirty_tx
;
3101 tx_left
= tp
->cur_tx
- dirty_tx
;
3103 while (tx_left
> 0) {
3104 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
3105 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3106 u32 len
= tx_skb
->len
;
3110 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
3111 if (status
& DescOwn
)
3114 dev
->stats
.tx_bytes
+= len
;
3115 dev
->stats
.tx_packets
++;
3117 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3119 if (status
& LastFrag
) {
3120 dev_kfree_skb_irq(tx_skb
->skb
);
3127 if (tp
->dirty_tx
!= dirty_tx
) {
3128 tp
->dirty_tx
= dirty_tx
;
3130 if (netif_queue_stopped(dev
) &&
3131 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3132 netif_wake_queue(dev
);
3135 * 8168 hack: TxPoll requests are lost when the Tx packets are
3136 * too close. Let's kick an extra TxPoll request when a burst
3137 * of start_xmit activity is detected (if it is not detected,
3138 * it is slow enough). -- FR
3141 if (tp
->cur_tx
!= dirty_tx
)
3142 RTL_W8(TxPoll
, NPQ
);
3146 static inline int rtl8169_fragmented_frame(u32 status
)
3148 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3151 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3153 u32 opts1
= le32_to_cpu(desc
->opts1
);
3154 u32 status
= opts1
& RxProtoMask
;
3156 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3157 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3158 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3159 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3161 skb
->ip_summed
= CHECKSUM_NONE
;
3164 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3165 struct rtl8169_private
*tp
, int pkt_size
,
3168 struct sk_buff
*skb
;
3171 if (pkt_size
>= rx_copybreak
)
3174 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3178 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3179 PCI_DMA_FROMDEVICE
);
3180 skb_reserve(skb
, NET_IP_ALIGN
);
3181 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3188 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3189 struct rtl8169_private
*tp
,
3190 void __iomem
*ioaddr
, u32 budget
)
3192 unsigned int cur_rx
, rx_left
;
3193 unsigned int delta
, count
;
3195 cur_rx
= tp
->cur_rx
;
3196 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3197 rx_left
= min(rx_left
, budget
);
3199 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3200 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3201 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3205 status
= le32_to_cpu(desc
->opts1
);
3207 if (status
& DescOwn
)
3209 if (unlikely(status
& RxRES
)) {
3210 if (netif_msg_rx_err(tp
)) {
3212 "%s: Rx ERROR. status = %08x\n",
3215 dev
->stats
.rx_errors
++;
3216 if (status
& (RxRWT
| RxRUNT
))
3217 dev
->stats
.rx_length_errors
++;
3219 dev
->stats
.rx_crc_errors
++;
3220 if (status
& RxFOVF
) {
3221 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3222 dev
->stats
.rx_fifo_errors
++;
3224 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3226 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3227 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3228 int pkt_size
= (status
& 0x00001FFF) - 4;
3229 struct pci_dev
*pdev
= tp
->pci_dev
;
3232 * The driver does not support incoming fragmented
3233 * frames. They are seen as a symptom of over-mtu
3236 if (unlikely(rtl8169_fragmented_frame(status
))) {
3237 dev
->stats
.rx_dropped
++;
3238 dev
->stats
.rx_length_errors
++;
3239 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3243 rtl8169_rx_csum(skb
, desc
);
3245 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3246 pci_dma_sync_single_for_device(pdev
, addr
,
3247 pkt_size
, PCI_DMA_FROMDEVICE
);
3248 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3250 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3251 PCI_DMA_FROMDEVICE
);
3252 tp
->Rx_skbuff
[entry
] = NULL
;
3255 skb_put(skb
, pkt_size
);
3256 skb
->protocol
= eth_type_trans(skb
, dev
);
3258 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3259 netif_receive_skb(skb
);
3261 dev
->last_rx
= jiffies
;
3262 dev
->stats
.rx_bytes
+= pkt_size
;
3263 dev
->stats
.rx_packets
++;
3266 /* Work around for AMD plateform. */
3267 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3268 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3274 count
= cur_rx
- tp
->cur_rx
;
3275 tp
->cur_rx
= cur_rx
;
3277 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3278 if (!delta
&& count
&& netif_msg_intr(tp
))
3279 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3280 tp
->dirty_rx
+= delta
;
3283 * FIXME: until there is periodic timer to try and refill the ring,
3284 * a temporary shortage may definitely kill the Rx process.
3285 * - disable the asic to try and avoid an overflow and kick it again
3287 * - how do others driver handle this condition (Uh oh...).
3289 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3290 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3295 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3297 struct net_device
*dev
= dev_instance
;
3298 struct rtl8169_private
*tp
= netdev_priv(dev
);
3299 void __iomem
*ioaddr
= tp
->mmio_addr
;
3303 status
= RTL_R16(IntrStatus
);
3305 /* hotplug/major error/no more work/shared irq */
3306 if ((status
== 0xffff) || !status
)
3311 if (unlikely(!netif_running(dev
))) {
3312 rtl8169_asic_down(ioaddr
);
3316 status
&= tp
->intr_mask
;
3318 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3320 if (!(status
& tp
->intr_event
))
3323 /* Work around for rx fifo overflow */
3324 if (unlikely(status
& RxFIFOOver
) &&
3325 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3326 netif_stop_queue(dev
);
3327 rtl8169_tx_timeout(dev
);
3331 if (unlikely(status
& SYSErr
)) {
3332 rtl8169_pcierr_interrupt(dev
);
3336 if (status
& LinkChg
)
3337 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3339 if (status
& tp
->napi_event
) {
3340 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3341 tp
->intr_mask
= ~tp
->napi_event
;
3343 if (likely(netif_rx_schedule_prep(dev
, &tp
->napi
)))
3344 __netif_rx_schedule(dev
, &tp
->napi
);
3345 else if (netif_msg_intr(tp
)) {
3346 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3351 return IRQ_RETVAL(handled
);
3354 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3356 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3357 struct net_device
*dev
= tp
->dev
;
3358 void __iomem
*ioaddr
= tp
->mmio_addr
;
3361 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3362 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3364 if (work_done
< budget
) {
3365 netif_rx_complete(dev
, napi
);
3366 tp
->intr_mask
= 0xffff;
3368 * 20040426: the barrier is not strictly required but the
3369 * behavior of the irq handler could be less predictable
3370 * without it. Btw, the lack of flush for the posted pci
3371 * write is safe - FR
3374 RTL_W16(IntrMask
, tp
->intr_event
);
3380 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3382 struct rtl8169_private
*tp
= netdev_priv(dev
);
3384 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3387 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3388 RTL_W32(RxMissed
, 0);
3391 static void rtl8169_down(struct net_device
*dev
)
3393 struct rtl8169_private
*tp
= netdev_priv(dev
);
3394 void __iomem
*ioaddr
= tp
->mmio_addr
;
3395 unsigned int intrmask
;
3397 rtl8169_delete_timer(dev
);
3399 netif_stop_queue(dev
);
3401 napi_disable(&tp
->napi
);
3404 spin_lock_irq(&tp
->lock
);
3406 rtl8169_asic_down(ioaddr
);
3408 rtl8169_rx_missed(dev
, ioaddr
);
3410 spin_unlock_irq(&tp
->lock
);
3412 synchronize_irq(dev
->irq
);
3414 /* Give a racing hard_start_xmit a few cycles to complete. */
3415 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3418 * And now for the 50k$ question: are IRQ disabled or not ?
3420 * Two paths lead here:
3422 * -> netif_running() is available to sync the current code and the
3423 * IRQ handler. See rtl8169_interrupt for details.
3424 * 2) dev->change_mtu
3425 * -> rtl8169_poll can not be issued again and re-enable the
3426 * interruptions. Let's simply issue the IRQ down sequence again.
3428 * No loop if hotpluged or major error (0xffff).
3430 intrmask
= RTL_R16(IntrMask
);
3431 if (intrmask
&& (intrmask
!= 0xffff))
3434 rtl8169_tx_clear(tp
);
3436 rtl8169_rx_clear(tp
);
3439 static int rtl8169_close(struct net_device
*dev
)
3441 struct rtl8169_private
*tp
= netdev_priv(dev
);
3442 struct pci_dev
*pdev
= tp
->pci_dev
;
3446 free_irq(dev
->irq
, dev
);
3448 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3450 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3452 tp
->TxDescArray
= NULL
;
3453 tp
->RxDescArray
= NULL
;
3458 static void rtl_set_rx_mode(struct net_device
*dev
)
3460 struct rtl8169_private
*tp
= netdev_priv(dev
);
3461 void __iomem
*ioaddr
= tp
->mmio_addr
;
3462 unsigned long flags
;
3463 u32 mc_filter
[2]; /* Multicast hash filter */
3467 if (dev
->flags
& IFF_PROMISC
) {
3468 /* Unconditionally log net taps. */
3469 if (netif_msg_link(tp
)) {
3470 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3474 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3476 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3477 } else if ((dev
->mc_count
> multicast_filter_limit
)
3478 || (dev
->flags
& IFF_ALLMULTI
)) {
3479 /* Too many to filter perfectly -- accept all multicasts. */
3480 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3481 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3483 struct dev_mc_list
*mclist
;
3486 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3487 mc_filter
[1] = mc_filter
[0] = 0;
3488 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3489 i
++, mclist
= mclist
->next
) {
3490 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3491 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3492 rx_mode
|= AcceptMulticast
;
3496 spin_lock_irqsave(&tp
->lock
, flags
);
3498 tmp
= rtl8169_rx_config
| rx_mode
|
3499 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3501 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3502 u32 data
= mc_filter
[0];
3504 mc_filter
[0] = swab32(mc_filter
[1]);
3505 mc_filter
[1] = swab32(data
);
3508 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3509 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3511 RTL_W32(RxConfig
, tmp
);
3513 spin_unlock_irqrestore(&tp
->lock
, flags
);
3517 * rtl8169_get_stats - Get rtl8169 read/write statistics
3518 * @dev: The Ethernet Device to get statistics for
3520 * Get TX/RX statistics for rtl8169
3522 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3524 struct rtl8169_private
*tp
= netdev_priv(dev
);
3525 void __iomem
*ioaddr
= tp
->mmio_addr
;
3526 unsigned long flags
;
3528 if (netif_running(dev
)) {
3529 spin_lock_irqsave(&tp
->lock
, flags
);
3530 rtl8169_rx_missed(dev
, ioaddr
);
3531 spin_unlock_irqrestore(&tp
->lock
, flags
);
3539 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3541 struct net_device
*dev
= pci_get_drvdata(pdev
);
3542 struct rtl8169_private
*tp
= netdev_priv(dev
);
3543 void __iomem
*ioaddr
= tp
->mmio_addr
;
3545 if (!netif_running(dev
))
3546 goto out_pci_suspend
;
3548 netif_device_detach(dev
);
3549 netif_stop_queue(dev
);
3551 spin_lock_irq(&tp
->lock
);
3553 rtl8169_asic_down(ioaddr
);
3555 rtl8169_rx_missed(dev
, ioaddr
);
3557 spin_unlock_irq(&tp
->lock
);
3560 pci_save_state(pdev
);
3561 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3562 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3563 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3568 static int rtl8169_resume(struct pci_dev
*pdev
)
3570 struct net_device
*dev
= pci_get_drvdata(pdev
);
3572 pci_set_power_state(pdev
, PCI_D0
);
3573 pci_restore_state(pdev
);
3574 pci_enable_wake(pdev
, PCI_D0
, 0);
3576 if (!netif_running(dev
))
3579 netif_device_attach(dev
);
3581 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3586 #endif /* CONFIG_PM */
3588 static struct pci_driver rtl8169_pci_driver
= {
3590 .id_table
= rtl8169_pci_tbl
,
3591 .probe
= rtl8169_init_one
,
3592 .remove
= __devexit_p(rtl8169_remove_one
),
3594 .suspend
= rtl8169_suspend
,
3595 .resume
= rtl8169_resume
,
3599 static int __init
rtl8169_init_module(void)
3601 return pci_register_driver(&rtl8169_pci_driver
);
3604 static void __exit
rtl8169_cleanup_module(void)
3606 pci_unregister_driver(&rtl8169_pci_driver
);
3609 module_init(rtl8169_init_module
);
3610 module_exit(rtl8169_cleanup_module
);